1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
3
4 #define pr_fmt(fmt) "mips-gic-timer: " fmt
5
6 #include <linux/clk.h>
7 #include <linux/clockchips.h>
8 #include <linux/cpu.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/notifier.h>
12 #include <linux/of_irq.h>
13 #include <linux/percpu.h>
14 #include <linux/sched_clock.h>
15 #include <linux/smp.h>
16 #include <linux/time.h>
17 #include <asm/mips-cps.h>
18
19 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
20 static int gic_timer_irq;
21 static unsigned int gic_frequency;
22 static bool __read_mostly gic_clock_unstable;
23
24 static void gic_clocksource_unstable(char *reason);
25
gic_read_count_2x32(void)26 static u64 notrace gic_read_count_2x32(void)
27 {
28 unsigned int hi, hi2, lo;
29
30 do {
31 hi = read_gic_counter_32h();
32 lo = read_gic_counter_32l();
33 hi2 = read_gic_counter_32h();
34 } while (hi2 != hi);
35
36 return (((u64) hi) << 32) + lo;
37 }
38
gic_read_count_64(void)39 static u64 notrace gic_read_count_64(void)
40 {
41 return read_gic_counter();
42 }
43
gic_read_count(void)44 static u64 notrace gic_read_count(void)
45 {
46 if (mips_cm_is64)
47 return gic_read_count_64();
48
49 return gic_read_count_2x32();
50 }
51
gic_next_event(unsigned long delta,struct clock_event_device * evt)52 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
53 {
54 int cpu = cpumask_first(evt->cpumask);
55 u64 cnt;
56 int res;
57
58 cnt = gic_read_count();
59 cnt += (u64)delta;
60 if (cpu == raw_smp_processor_id()) {
61 write_gic_vl_compare(cnt);
62 } else {
63 write_gic_vl_other(mips_cm_vp_id(cpu));
64 write_gic_vo_compare(cnt);
65 }
66 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
67 return res;
68 }
69
gic_compare_interrupt(int irq,void * dev_id)70 static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
71 {
72 struct clock_event_device *cd = dev_id;
73
74 write_gic_vl_compare(read_gic_vl_compare());
75 cd->event_handler(cd);
76 return IRQ_HANDLED;
77 }
78
79 static struct irqaction gic_compare_irqaction = {
80 .handler = gic_compare_interrupt,
81 .percpu_dev_id = &gic_clockevent_device,
82 .flags = IRQF_PERCPU | IRQF_TIMER,
83 .name = "timer",
84 };
85
gic_clockevent_cpu_init(unsigned int cpu,struct clock_event_device * cd)86 static void gic_clockevent_cpu_init(unsigned int cpu,
87 struct clock_event_device *cd)
88 {
89 cd->name = "MIPS GIC";
90 cd->features = CLOCK_EVT_FEAT_ONESHOT |
91 CLOCK_EVT_FEAT_C3STOP;
92
93 cd->rating = 350;
94 cd->irq = gic_timer_irq;
95 cd->cpumask = cpumask_of(cpu);
96 cd->set_next_event = gic_next_event;
97
98 clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
99
100 enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
101 }
102
gic_clockevent_cpu_exit(struct clock_event_device * cd)103 static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
104 {
105 disable_percpu_irq(gic_timer_irq);
106 }
107
gic_update_frequency(void * data)108 static void gic_update_frequency(void *data)
109 {
110 unsigned long rate = (unsigned long)data;
111
112 clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
113 }
114
gic_starting_cpu(unsigned int cpu)115 static int gic_starting_cpu(unsigned int cpu)
116 {
117 /* Ensure the GIC counter is running */
118 clear_gic_config(GIC_CONFIG_COUNTSTOP);
119
120 gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
121 return 0;
122 }
123
gic_clk_notifier(struct notifier_block * nb,unsigned long action,void * data)124 static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
125 void *data)
126 {
127 struct clk_notifier_data *cnd = data;
128
129 if (action == POST_RATE_CHANGE) {
130 gic_clocksource_unstable("ref clock rate change");
131 on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
132 }
133
134 return NOTIFY_OK;
135 }
136
gic_dying_cpu(unsigned int cpu)137 static int gic_dying_cpu(unsigned int cpu)
138 {
139 gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
140 return 0;
141 }
142
143 static struct notifier_block gic_clk_nb = {
144 .notifier_call = gic_clk_notifier,
145 };
146
gic_clockevent_init(void)147 static int gic_clockevent_init(void)
148 {
149 int ret;
150
151 if (!gic_frequency)
152 return -ENXIO;
153
154 ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
155 if (ret < 0) {
156 pr_err("IRQ %d setup failed (%d)\n", gic_timer_irq, ret);
157 return ret;
158 }
159
160 cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
161 "clockevents/mips/gic/timer:starting",
162 gic_starting_cpu, gic_dying_cpu);
163 return 0;
164 }
165
gic_hpt_read(struct clocksource * cs)166 static u64 gic_hpt_read(struct clocksource *cs)
167 {
168 return gic_read_count();
169 }
170
171 static struct clocksource gic_clocksource = {
172 .name = "GIC",
173 .read = gic_hpt_read,
174 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
175 .vdso_clock_mode = VDSO_CLOCKMODE_GIC,
176 };
177
gic_clocksource_unstable(char * reason)178 static void gic_clocksource_unstable(char *reason)
179 {
180 if (gic_clock_unstable)
181 return;
182
183 gic_clock_unstable = true;
184
185 pr_info("GIC timer is unstable due to %s\n", reason);
186
187 clocksource_mark_unstable(&gic_clocksource);
188 }
189
__gic_clocksource_init(void)190 static int __init __gic_clocksource_init(void)
191 {
192 unsigned int count_width;
193 int ret;
194
195 /* Set clocksource mask. */
196 count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
197 count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
198 count_width *= 4;
199 count_width += 32;
200 gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
201
202 /* Calculate a somewhat reasonable rating value. */
203 gic_clocksource.rating = 200 + gic_frequency / 10000000;
204
205 ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
206 if (ret < 0)
207 pr_warn("Unable to register clocksource\n");
208
209 return ret;
210 }
211
gic_clocksource_of_init(struct device_node * node)212 static int __init gic_clocksource_of_init(struct device_node *node)
213 {
214 struct clk *clk;
215 int ret;
216
217 if (!mips_gic_present() || !node->parent ||
218 !of_device_is_compatible(node->parent, "mti,gic")) {
219 pr_warn("No DT definition\n");
220 return -ENXIO;
221 }
222
223 clk = of_clk_get(node, 0);
224 if (!IS_ERR(clk)) {
225 ret = clk_prepare_enable(clk);
226 if (ret < 0) {
227 pr_err("Failed to enable clock\n");
228 clk_put(clk);
229 return ret;
230 }
231
232 gic_frequency = clk_get_rate(clk);
233 } else if (of_property_read_u32(node, "clock-frequency",
234 &gic_frequency)) {
235 pr_err("Frequency not specified\n");
236 return -EINVAL;
237 }
238 gic_timer_irq = irq_of_parse_and_map(node, 0);
239 if (!gic_timer_irq) {
240 pr_err("IRQ not specified\n");
241 return -EINVAL;
242 }
243
244 ret = __gic_clocksource_init();
245 if (ret)
246 return ret;
247
248 ret = gic_clockevent_init();
249 if (!ret && !IS_ERR(clk)) {
250 if (clk_notifier_register(clk, &gic_clk_nb) < 0)
251 pr_warn("Unable to register clock notifier\n");
252 }
253
254 /*
255 * It's safe to use the MIPS GIC timer as a sched clock source only if
256 * its ticks are stable, which is true on either the platforms with
257 * stable CPU frequency or on the platforms with CM3 and CPU frequency
258 * change performed by the CPC core clocks divider.
259 */
260 if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
261 sched_clock_register(mips_cm_is64 ?
262 gic_read_count_64 : gic_read_count_2x32,
263 64, gic_frequency);
264 }
265
266 return 0;
267 }
268 TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
269 gic_clocksource_of_init);
270