1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NXP FXLS8962AF/FXLS8964AF Accelerometer Core Driver
4 *
5 * Copyright 2021 Connected Cars A/S
6 *
7 * Datasheet:
8 * https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf
9 * https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf
10 *
11 * Errata:
12 * https://www.nxp.com/docs/en/errata/ES_FXLS8962AF.pdf
13 */
14
15 #include <linux/bits.h>
16 #include <linux/bitfield.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/of_irq.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/regmap.h>
23 #include <linux/units.h>
24
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/events.h>
27 #include <linux/iio/iio.h>
28 #include <linux/iio/kfifo_buf.h>
29 #include <linux/iio/sysfs.h>
30
31 #include "fxls8962af.h"
32
33 #define FXLS8962AF_INT_STATUS 0x00
34 #define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0)
35 #define FXLS8962AF_INT_STATUS_SRC_SDCD_OT BIT(4)
36 #define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5)
37 #define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7)
38 #define FXLS8962AF_TEMP_OUT 0x01
39 #define FXLS8962AF_VECM_LSB 0x02
40 #define FXLS8962AF_OUT_X_LSB 0x04
41 #define FXLS8962AF_OUT_Y_LSB 0x06
42 #define FXLS8962AF_OUT_Z_LSB 0x08
43 #define FXLS8962AF_BUF_STATUS 0x0b
44 #define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0)
45 #define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6)
46 #define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7)
47 #define FXLS8962AF_BUF_X_LSB 0x0c
48 #define FXLS8962AF_BUF_Y_LSB 0x0e
49 #define FXLS8962AF_BUF_Z_LSB 0x10
50
51 #define FXLS8962AF_PROD_REV 0x12
52 #define FXLS8962AF_WHO_AM_I 0x13
53
54 #define FXLS8962AF_SYS_MODE 0x14
55 #define FXLS8962AF_SENS_CONFIG1 0x15
56 #define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0)
57 #define FXLS8962AF_SENS_CONFIG1_RST BIT(7)
58 #define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1)
59 #define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x))
60 #define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x))
61
62 #define FXLS8962AF_SENS_CONFIG2 0x16
63 #define FXLS8962AF_SENS_CONFIG3 0x17
64 #define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4)
65 #define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x))
66 #define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x))
67 #define FXLS8962AF_SENS_CONFIG4 0x18
68 #define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1)
69 #define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x))
70 #define FXLS8962AF_SC4_INT_POL_MASK BIT(0)
71 #define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x))
72 #define FXLS8962AF_SENS_CONFIG5 0x19
73
74 #define FXLS8962AF_WAKE_IDLE_LSB 0x1b
75 #define FXLS8962AF_SLEEP_IDLE_LSB 0x1c
76 #define FXLS8962AF_ASLP_COUNT_LSB 0x1e
77
78 #define FXLS8962AF_INT_EN 0x20
79 #define FXLS8962AF_INT_EN_SDCD_OT_EN BIT(5)
80 #define FXLS8962AF_INT_EN_BUF_EN BIT(6)
81 #define FXLS8962AF_INT_PIN_SEL 0x21
82 #define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0)
83 #define FXLS8962AF_INT_PIN_SEL_INT1 0x00
84 #define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0)
85
86 #define FXLS8962AF_OFF_X 0x22
87 #define FXLS8962AF_OFF_Y 0x23
88 #define FXLS8962AF_OFF_Z 0x24
89
90 #define FXLS8962AF_BUF_CONFIG1 0x26
91 #define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5)
92 #define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x))
93 #define FXLS8962AF_BUF_CONFIG2 0x27
94 #define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0)
95
96 #define FXLS8962AF_ORIENT_STATUS 0x28
97 #define FXLS8962AF_ORIENT_CONFIG 0x29
98 #define FXLS8962AF_ORIENT_DBCOUNT 0x2a
99 #define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b
100 #define FXLS8962AF_ORIENT_THS_REG 0x2c
101
102 #define FXLS8962AF_SDCD_INT_SRC1 0x2d
103 #define FXLS8962AF_SDCD_INT_SRC1_X_OT BIT(5)
104 #define FXLS8962AF_SDCD_INT_SRC1_X_POL BIT(4)
105 #define FXLS8962AF_SDCD_INT_SRC1_Y_OT BIT(3)
106 #define FXLS8962AF_SDCD_INT_SRC1_Y_POL BIT(2)
107 #define FXLS8962AF_SDCD_INT_SRC1_Z_OT BIT(1)
108 #define FXLS8962AF_SDCD_INT_SRC1_Z_POL BIT(0)
109 #define FXLS8962AF_SDCD_INT_SRC2 0x2e
110 #define FXLS8962AF_SDCD_CONFIG1 0x2f
111 #define FXLS8962AF_SDCD_CONFIG1_Z_OT_EN BIT(3)
112 #define FXLS8962AF_SDCD_CONFIG1_Y_OT_EN BIT(4)
113 #define FXLS8962AF_SDCD_CONFIG1_X_OT_EN BIT(5)
114 #define FXLS8962AF_SDCD_CONFIG1_OT_ELE BIT(7)
115 #define FXLS8962AF_SDCD_CONFIG2 0x30
116 #define FXLS8962AF_SDCD_CONFIG2_SDCD_EN BIT(7)
117 #define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5)
118 #define FXLS8962AF_SDCD_OT_DBCNT 0x31
119 #define FXLS8962AF_SDCD_WT_DBCNT 0x32
120 #define FXLS8962AF_SDCD_LTHS_LSB 0x33
121 #define FXLS8962AF_SDCD_UTHS_LSB 0x35
122
123 #define FXLS8962AF_SELF_TEST_CONFIG1 0x37
124 #define FXLS8962AF_SELF_TEST_CONFIG2 0x38
125
126 #define FXLS8962AF_MAX_REG 0x38
127
128 #define FXLS8962AF_DEVICE_ID 0x62
129 #define FXLS8964AF_DEVICE_ID 0x84
130
131 /* Raw temp channel offset */
132 #define FXLS8962AF_TEMP_CENTER_VAL 25
133
134 #define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000
135
136 #define FXLS8962AF_FIFO_LENGTH 32
137 #define FXLS8962AF_SCALE_TABLE_LEN 4
138 #define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13
139
140 static const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = {
141 {0, IIO_G_TO_M_S_2(980000)},
142 {0, IIO_G_TO_M_S_2(1950000)},
143 {0, IIO_G_TO_M_S_2(3910000)},
144 {0, IIO_G_TO_M_S_2(7810000)},
145 };
146
147 static const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = {
148 {3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0},
149 {50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000},
150 {1, 563000}, {0, 781000},
151 };
152
153 struct fxls8962af_chip_info {
154 const char *name;
155 const struct iio_chan_spec *channels;
156 int num_channels;
157 u8 chip_id;
158 };
159
160 struct fxls8962af_data {
161 struct regmap *regmap;
162 const struct fxls8962af_chip_info *chip_info;
163 struct {
164 __le16 channels[3];
165 s64 ts __aligned(8);
166 } scan;
167 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
168 struct iio_mount_matrix orientation;
169 int irq;
170 u8 watermark;
171 u8 enable_event;
172 u16 lower_thres;
173 u16 upper_thres;
174 };
175
176 const struct regmap_config fxls8962af_i2c_regmap_conf = {
177 .reg_bits = 8,
178 .val_bits = 8,
179 .max_register = FXLS8962AF_MAX_REG,
180 };
181 EXPORT_SYMBOL_NS_GPL(fxls8962af_i2c_regmap_conf, IIO_FXLS8962AF);
182
183 const struct regmap_config fxls8962af_spi_regmap_conf = {
184 .reg_bits = 8,
185 .pad_bits = 8,
186 .val_bits = 8,
187 .max_register = FXLS8962AF_MAX_REG,
188 };
189 EXPORT_SYMBOL_NS_GPL(fxls8962af_spi_regmap_conf, IIO_FXLS8962AF);
190
191 enum {
192 fxls8962af_idx_x,
193 fxls8962af_idx_y,
194 fxls8962af_idx_z,
195 fxls8962af_idx_ts,
196 };
197
198 enum fxls8962af_int_pin {
199 FXLS8962AF_PIN_INT1,
200 FXLS8962AF_PIN_INT2,
201 };
202
fxls8962af_power_on(struct fxls8962af_data * data)203 static int fxls8962af_power_on(struct fxls8962af_data *data)
204 {
205 struct device *dev = regmap_get_device(data->regmap);
206 int ret;
207
208 ret = pm_runtime_resume_and_get(dev);
209 if (ret)
210 dev_err(dev, "failed to power on\n");
211
212 return ret;
213 }
214
fxls8962af_power_off(struct fxls8962af_data * data)215 static int fxls8962af_power_off(struct fxls8962af_data *data)
216 {
217 struct device *dev = regmap_get_device(data->regmap);
218 int ret;
219
220 pm_runtime_mark_last_busy(dev);
221 ret = pm_runtime_put_autosuspend(dev);
222 if (ret)
223 dev_err(dev, "failed to power off\n");
224
225 return ret;
226 }
227
fxls8962af_standby(struct fxls8962af_data * data)228 static int fxls8962af_standby(struct fxls8962af_data *data)
229 {
230 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,
231 FXLS8962AF_SENS_CONFIG1_ACTIVE, 0);
232 }
233
fxls8962af_active(struct fxls8962af_data * data)234 static int fxls8962af_active(struct fxls8962af_data *data)
235 {
236 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,
237 FXLS8962AF_SENS_CONFIG1_ACTIVE, 1);
238 }
239
fxls8962af_is_active(struct fxls8962af_data * data)240 static int fxls8962af_is_active(struct fxls8962af_data *data)
241 {
242 unsigned int reg;
243 int ret;
244
245 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®);
246 if (ret)
247 return ret;
248
249 return reg & FXLS8962AF_SENS_CONFIG1_ACTIVE;
250 }
251
fxls8962af_get_out(struct fxls8962af_data * data,struct iio_chan_spec const * chan,int * val)252 static int fxls8962af_get_out(struct fxls8962af_data *data,
253 struct iio_chan_spec const *chan, int *val)
254 {
255 struct device *dev = regmap_get_device(data->regmap);
256 __le16 raw_val;
257 int is_active;
258 int ret;
259
260 is_active = fxls8962af_is_active(data);
261 if (!is_active) {
262 ret = fxls8962af_power_on(data);
263 if (ret)
264 return ret;
265 }
266
267 ret = regmap_bulk_read(data->regmap, chan->address,
268 &raw_val, sizeof(data->lower_thres));
269
270 if (!is_active)
271 fxls8962af_power_off(data);
272
273 if (ret) {
274 dev_err(dev, "failed to get out reg 0x%lx\n", chan->address);
275 return ret;
276 }
277
278 *val = sign_extend32(le16_to_cpu(raw_val),
279 chan->scan_type.realbits - 1);
280
281 return IIO_VAL_INT;
282 }
283
fxls8962af_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)284 static int fxls8962af_read_avail(struct iio_dev *indio_dev,
285 struct iio_chan_spec const *chan,
286 const int **vals, int *type, int *length,
287 long mask)
288 {
289 switch (mask) {
290 case IIO_CHAN_INFO_SCALE:
291 *type = IIO_VAL_INT_PLUS_NANO;
292 *vals = (int *)fxls8962af_scale_table;
293 *length = ARRAY_SIZE(fxls8962af_scale_table) * 2;
294 return IIO_AVAIL_LIST;
295 case IIO_CHAN_INFO_SAMP_FREQ:
296 *type = IIO_VAL_INT_PLUS_MICRO;
297 *vals = (int *)fxls8962af_samp_freq_table;
298 *length = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2;
299 return IIO_AVAIL_LIST;
300 default:
301 return -EINVAL;
302 }
303 }
304
fxls8962af_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)305 static int fxls8962af_write_raw_get_fmt(struct iio_dev *indio_dev,
306 struct iio_chan_spec const *chan,
307 long mask)
308 {
309 switch (mask) {
310 case IIO_CHAN_INFO_SCALE:
311 return IIO_VAL_INT_PLUS_NANO;
312 case IIO_CHAN_INFO_SAMP_FREQ:
313 return IIO_VAL_INT_PLUS_MICRO;
314 default:
315 return IIO_VAL_INT_PLUS_NANO;
316 }
317 }
318
fxls8962af_update_config(struct fxls8962af_data * data,u8 reg,u8 mask,u8 val)319 static int fxls8962af_update_config(struct fxls8962af_data *data, u8 reg,
320 u8 mask, u8 val)
321 {
322 int ret;
323 int is_active;
324
325 is_active = fxls8962af_is_active(data);
326 if (is_active) {
327 ret = fxls8962af_standby(data);
328 if (ret)
329 return ret;
330 }
331
332 ret = regmap_update_bits(data->regmap, reg, mask, val);
333 if (ret)
334 return ret;
335
336 if (is_active) {
337 ret = fxls8962af_active(data);
338 if (ret)
339 return ret;
340 }
341
342 return 0;
343 }
344
fxls8962af_set_full_scale(struct fxls8962af_data * data,u32 scale)345 static int fxls8962af_set_full_scale(struct fxls8962af_data *data, u32 scale)
346 {
347 int i;
348
349 for (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++)
350 if (scale == fxls8962af_scale_table[i][1])
351 break;
352
353 if (i == ARRAY_SIZE(fxls8962af_scale_table))
354 return -EINVAL;
355
356 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1,
357 FXLS8962AF_SC1_FSR_MASK,
358 FXLS8962AF_SC1_FSR_PREP(i));
359 }
360
fxls8962af_read_full_scale(struct fxls8962af_data * data,int * val)361 static unsigned int fxls8962af_read_full_scale(struct fxls8962af_data *data,
362 int *val)
363 {
364 int ret;
365 unsigned int reg;
366 u8 range_idx;
367
368 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®);
369 if (ret)
370 return ret;
371
372 range_idx = FXLS8962AF_SC1_FSR_GET(reg);
373
374 *val = fxls8962af_scale_table[range_idx][1];
375
376 return IIO_VAL_INT_PLUS_NANO;
377 }
378
fxls8962af_set_samp_freq(struct fxls8962af_data * data,u32 val,u32 val2)379 static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val,
380 u32 val2)
381 {
382 int i;
383
384 for (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++)
385 if (val == fxls8962af_samp_freq_table[i][0] &&
386 val2 == fxls8962af_samp_freq_table[i][1])
387 break;
388
389 if (i == ARRAY_SIZE(fxls8962af_samp_freq_table))
390 return -EINVAL;
391
392 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3,
393 FXLS8962AF_SC3_WAKE_ODR_MASK,
394 FXLS8962AF_SC3_WAKE_ODR_PREP(i));
395 }
396
fxls8962af_read_samp_freq(struct fxls8962af_data * data,int * val,int * val2)397 static unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data *data,
398 int *val, int *val2)
399 {
400 int ret;
401 unsigned int reg;
402 u8 range_idx;
403
404 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, ®);
405 if (ret)
406 return ret;
407
408 range_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg);
409
410 *val = fxls8962af_samp_freq_table[range_idx][0];
411 *val2 = fxls8962af_samp_freq_table[range_idx][1];
412
413 return IIO_VAL_INT_PLUS_MICRO;
414 }
415
fxls8962af_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)416 static int fxls8962af_read_raw(struct iio_dev *indio_dev,
417 struct iio_chan_spec const *chan,
418 int *val, int *val2, long mask)
419 {
420 struct fxls8962af_data *data = iio_priv(indio_dev);
421
422 switch (mask) {
423 case IIO_CHAN_INFO_RAW:
424 switch (chan->type) {
425 case IIO_TEMP:
426 case IIO_ACCEL:
427 return fxls8962af_get_out(data, chan, val);
428 default:
429 return -EINVAL;
430 }
431 case IIO_CHAN_INFO_OFFSET:
432 if (chan->type != IIO_TEMP)
433 return -EINVAL;
434
435 *val = FXLS8962AF_TEMP_CENTER_VAL;
436 return IIO_VAL_INT;
437 case IIO_CHAN_INFO_SCALE:
438 switch (chan->type) {
439 case IIO_TEMP:
440 *val = MILLIDEGREE_PER_DEGREE;
441 return IIO_VAL_INT;
442 case IIO_ACCEL:
443 *val = 0;
444 return fxls8962af_read_full_scale(data, val2);
445 default:
446 return -EINVAL;
447 }
448 case IIO_CHAN_INFO_SAMP_FREQ:
449 return fxls8962af_read_samp_freq(data, val, val2);
450 default:
451 return -EINVAL;
452 }
453 }
454
fxls8962af_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)455 static int fxls8962af_write_raw(struct iio_dev *indio_dev,
456 struct iio_chan_spec const *chan,
457 int val, int val2, long mask)
458 {
459 struct fxls8962af_data *data = iio_priv(indio_dev);
460 int ret;
461
462 switch (mask) {
463 case IIO_CHAN_INFO_SCALE:
464 if (val != 0)
465 return -EINVAL;
466
467 ret = iio_device_claim_direct_mode(indio_dev);
468 if (ret)
469 return ret;
470
471 ret = fxls8962af_set_full_scale(data, val2);
472
473 iio_device_release_direct_mode(indio_dev);
474 return ret;
475 case IIO_CHAN_INFO_SAMP_FREQ:
476 ret = iio_device_claim_direct_mode(indio_dev);
477 if (ret)
478 return ret;
479
480 ret = fxls8962af_set_samp_freq(data, val, val2);
481
482 iio_device_release_direct_mode(indio_dev);
483 return ret;
484 default:
485 return -EINVAL;
486 }
487 }
488
fxls8962af_event_setup(struct fxls8962af_data * data,int state)489 static int fxls8962af_event_setup(struct fxls8962af_data *data, int state)
490 {
491 /* Enable wakeup interrupt */
492 int mask = FXLS8962AF_INT_EN_SDCD_OT_EN;
493 int value = state ? mask : 0;
494
495 return regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, mask, value);
496 }
497
fxls8962af_set_watermark(struct iio_dev * indio_dev,unsigned val)498 static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val)
499 {
500 struct fxls8962af_data *data = iio_priv(indio_dev);
501
502 if (val > FXLS8962AF_FIFO_LENGTH)
503 val = FXLS8962AF_FIFO_LENGTH;
504
505 data->watermark = val;
506
507 return 0;
508 }
509
__fxls8962af_set_thresholds(struct fxls8962af_data * data,const struct iio_chan_spec * chan,enum iio_event_direction dir,int val)510 static int __fxls8962af_set_thresholds(struct fxls8962af_data *data,
511 const struct iio_chan_spec *chan,
512 enum iio_event_direction dir,
513 int val)
514 {
515 switch (dir) {
516 case IIO_EV_DIR_FALLING:
517 data->lower_thres = val;
518 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_LTHS_LSB,
519 &data->lower_thres, sizeof(data->lower_thres));
520 case IIO_EV_DIR_RISING:
521 data->upper_thres = val;
522 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_UTHS_LSB,
523 &data->upper_thres, sizeof(data->upper_thres));
524 default:
525 return -EINVAL;
526 }
527 }
528
fxls8962af_read_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)529 static int fxls8962af_read_event(struct iio_dev *indio_dev,
530 const struct iio_chan_spec *chan,
531 enum iio_event_type type,
532 enum iio_event_direction dir,
533 enum iio_event_info info,
534 int *val, int *val2)
535 {
536 struct fxls8962af_data *data = iio_priv(indio_dev);
537 int ret;
538
539 if (type != IIO_EV_TYPE_THRESH)
540 return -EINVAL;
541
542 switch (dir) {
543 case IIO_EV_DIR_FALLING:
544 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_LTHS_LSB,
545 &data->lower_thres, sizeof(data->lower_thres));
546 if (ret)
547 return ret;
548
549 *val = sign_extend32(data->lower_thres, chan->scan_type.realbits - 1);
550 return IIO_VAL_INT;
551 case IIO_EV_DIR_RISING:
552 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_UTHS_LSB,
553 &data->upper_thres, sizeof(data->upper_thres));
554 if (ret)
555 return ret;
556
557 *val = sign_extend32(data->upper_thres, chan->scan_type.realbits - 1);
558 return IIO_VAL_INT;
559 default:
560 return -EINVAL;
561 }
562 }
563
fxls8962af_write_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)564 static int fxls8962af_write_event(struct iio_dev *indio_dev,
565 const struct iio_chan_spec *chan,
566 enum iio_event_type type,
567 enum iio_event_direction dir,
568 enum iio_event_info info,
569 int val, int val2)
570 {
571 struct fxls8962af_data *data = iio_priv(indio_dev);
572 int ret, val_masked;
573
574 if (type != IIO_EV_TYPE_THRESH)
575 return -EINVAL;
576
577 if (val < -2048 || val > 2047)
578 return -EINVAL;
579
580 if (data->enable_event)
581 return -EBUSY;
582
583 val_masked = val & GENMASK(11, 0);
584 if (fxls8962af_is_active(data)) {
585 ret = fxls8962af_standby(data);
586 if (ret)
587 return ret;
588
589 ret = __fxls8962af_set_thresholds(data, chan, dir, val_masked);
590 if (ret)
591 return ret;
592
593 return fxls8962af_active(data);
594 } else {
595 return __fxls8962af_set_thresholds(data, chan, dir, val_masked);
596 }
597 }
598
599 static int
fxls8962af_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)600 fxls8962af_read_event_config(struct iio_dev *indio_dev,
601 const struct iio_chan_spec *chan,
602 enum iio_event_type type,
603 enum iio_event_direction dir)
604 {
605 struct fxls8962af_data *data = iio_priv(indio_dev);
606
607 if (type != IIO_EV_TYPE_THRESH)
608 return -EINVAL;
609
610 switch (chan->channel2) {
611 case IIO_MOD_X:
612 return !!(FXLS8962AF_SDCD_CONFIG1_X_OT_EN & data->enable_event);
613 case IIO_MOD_Y:
614 return !!(FXLS8962AF_SDCD_CONFIG1_Y_OT_EN & data->enable_event);
615 case IIO_MOD_Z:
616 return !!(FXLS8962AF_SDCD_CONFIG1_Z_OT_EN & data->enable_event);
617 default:
618 return -EINVAL;
619 }
620 }
621
622 static int
fxls8962af_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)623 fxls8962af_write_event_config(struct iio_dev *indio_dev,
624 const struct iio_chan_spec *chan,
625 enum iio_event_type type,
626 enum iio_event_direction dir, int state)
627 {
628 struct fxls8962af_data *data = iio_priv(indio_dev);
629 u8 enable_event, enable_bits;
630 int ret, value;
631
632 if (type != IIO_EV_TYPE_THRESH)
633 return -EINVAL;
634
635 switch (chan->channel2) {
636 case IIO_MOD_X:
637 enable_bits = FXLS8962AF_SDCD_CONFIG1_X_OT_EN;
638 break;
639 case IIO_MOD_Y:
640 enable_bits = FXLS8962AF_SDCD_CONFIG1_Y_OT_EN;
641 break;
642 case IIO_MOD_Z:
643 enable_bits = FXLS8962AF_SDCD_CONFIG1_Z_OT_EN;
644 break;
645 default:
646 return -EINVAL;
647 }
648
649 if (state)
650 enable_event = data->enable_event | enable_bits;
651 else
652 enable_event = data->enable_event & ~enable_bits;
653
654 if (data->enable_event == enable_event)
655 return 0;
656
657 ret = fxls8962af_standby(data);
658 if (ret)
659 return ret;
660
661 /* Enable events */
662 value = enable_event | FXLS8962AF_SDCD_CONFIG1_OT_ELE;
663 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG1, value);
664 if (ret)
665 return ret;
666
667 /*
668 * Enable update of SDCD_REF_X/Y/Z values with the current decimated and
669 * trimmed X/Y/Z acceleration input data. This allows for acceleration
670 * slope detection with Data(n) to Data(n–1) always used as the input
671 * to the window comparator.
672 */
673 value = enable_event ?
674 FXLS8962AF_SDCD_CONFIG2_SDCD_EN | FXLS8962AF_SC2_REF_UPDM_AC :
675 0x00;
676 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG2, value);
677 if (ret)
678 return ret;
679
680 ret = fxls8962af_event_setup(data, state);
681 if (ret)
682 return ret;
683
684 data->enable_event = enable_event;
685
686 if (data->enable_event) {
687 fxls8962af_active(data);
688 ret = fxls8962af_power_on(data);
689 } else {
690 ret = iio_device_claim_direct_mode(indio_dev);
691 if (ret)
692 return ret;
693
694 /* Not in buffered mode so disable power */
695 ret = fxls8962af_power_off(data);
696
697 iio_device_release_direct_mode(indio_dev);
698 }
699
700 return ret;
701 }
702
703 static const struct iio_event_spec fxls8962af_event[] = {
704 {
705 .type = IIO_EV_TYPE_THRESH,
706 .dir = IIO_EV_DIR_EITHER,
707 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
708 },
709 {
710 .type = IIO_EV_TYPE_THRESH,
711 .dir = IIO_EV_DIR_FALLING,
712 .mask_separate = BIT(IIO_EV_INFO_VALUE),
713 },
714 {
715 .type = IIO_EV_TYPE_THRESH,
716 .dir = IIO_EV_DIR_RISING,
717 .mask_separate = BIT(IIO_EV_INFO_VALUE),
718 },
719 };
720
721 #define FXLS8962AF_CHANNEL(axis, reg, idx) { \
722 .type = IIO_ACCEL, \
723 .address = reg, \
724 .modified = 1, \
725 .channel2 = IIO_MOD_##axis, \
726 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
727 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
728 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
729 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \
730 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
731 .scan_index = idx, \
732 .scan_type = { \
733 .sign = 's', \
734 .realbits = 12, \
735 .storagebits = 16, \
736 .endianness = IIO_LE, \
737 }, \
738 .event_spec = fxls8962af_event, \
739 .num_event_specs = ARRAY_SIZE(fxls8962af_event), \
740 }
741
742 #define FXLS8962AF_TEMP_CHANNEL { \
743 .type = IIO_TEMP, \
744 .address = FXLS8962AF_TEMP_OUT, \
745 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
746 BIT(IIO_CHAN_INFO_SCALE) | \
747 BIT(IIO_CHAN_INFO_OFFSET),\
748 .scan_index = -1, \
749 .scan_type = { \
750 .sign = 's', \
751 .realbits = 8, \
752 .storagebits = 8, \
753 }, \
754 }
755
756 static const struct iio_chan_spec fxls8962af_channels[] = {
757 FXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x),
758 FXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y),
759 FXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z),
760 IIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts),
761 FXLS8962AF_TEMP_CHANNEL,
762 };
763
764 static const struct fxls8962af_chip_info fxls_chip_info_table[] = {
765 [fxls8962af] = {
766 .chip_id = FXLS8962AF_DEVICE_ID,
767 .name = "fxls8962af",
768 .channels = fxls8962af_channels,
769 .num_channels = ARRAY_SIZE(fxls8962af_channels),
770 },
771 [fxls8964af] = {
772 .chip_id = FXLS8964AF_DEVICE_ID,
773 .name = "fxls8964af",
774 .channels = fxls8962af_channels,
775 .num_channels = ARRAY_SIZE(fxls8962af_channels),
776 },
777 };
778
779 static const struct iio_info fxls8962af_info = {
780 .read_raw = &fxls8962af_read_raw,
781 .write_raw = &fxls8962af_write_raw,
782 .write_raw_get_fmt = fxls8962af_write_raw_get_fmt,
783 .read_event_value = fxls8962af_read_event,
784 .write_event_value = fxls8962af_write_event,
785 .read_event_config = fxls8962af_read_event_config,
786 .write_event_config = fxls8962af_write_event_config,
787 .read_avail = fxls8962af_read_avail,
788 .hwfifo_set_watermark = fxls8962af_set_watermark,
789 };
790
fxls8962af_reset(struct fxls8962af_data * data)791 static int fxls8962af_reset(struct fxls8962af_data *data)
792 {
793 struct device *dev = regmap_get_device(data->regmap);
794 unsigned int reg;
795 int ret;
796
797 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,
798 FXLS8962AF_SENS_CONFIG1_RST,
799 FXLS8962AF_SENS_CONFIG1_RST);
800 if (ret)
801 return ret;
802
803 /* TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms */
804 ret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg,
805 (reg & FXLS8962AF_INT_STATUS_SRC_BOOT),
806 1000, 18000);
807 if (ret == -ETIMEDOUT)
808 dev_err(dev, "reset timeout, int_status = 0x%x\n", reg);
809
810 return ret;
811 }
812
__fxls8962af_fifo_set_mode(struct fxls8962af_data * data,bool onoff)813 static int __fxls8962af_fifo_set_mode(struct fxls8962af_data *data, bool onoff)
814 {
815 int ret;
816
817 /* Enable watermark at max fifo size */
818 ret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2,
819 FXLS8962AF_BUF_CONFIG2_BUF_WMRK,
820 data->watermark);
821 if (ret)
822 return ret;
823
824 return regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1,
825 FXLS8962AF_BC1_BUF_MODE_MASK,
826 FXLS8962AF_BC1_BUF_MODE_PREP(onoff));
827 }
828
fxls8962af_buffer_preenable(struct iio_dev * indio_dev)829 static int fxls8962af_buffer_preenable(struct iio_dev *indio_dev)
830 {
831 return fxls8962af_power_on(iio_priv(indio_dev));
832 }
833
fxls8962af_buffer_postenable(struct iio_dev * indio_dev)834 static int fxls8962af_buffer_postenable(struct iio_dev *indio_dev)
835 {
836 struct fxls8962af_data *data = iio_priv(indio_dev);
837 int ret;
838
839 fxls8962af_standby(data);
840
841 /* Enable buffer interrupt */
842 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_EN,
843 FXLS8962AF_INT_EN_BUF_EN,
844 FXLS8962AF_INT_EN_BUF_EN);
845 if (ret)
846 return ret;
847
848 ret = __fxls8962af_fifo_set_mode(data, true);
849
850 fxls8962af_active(data);
851
852 return ret;
853 }
854
fxls8962af_buffer_predisable(struct iio_dev * indio_dev)855 static int fxls8962af_buffer_predisable(struct iio_dev *indio_dev)
856 {
857 struct fxls8962af_data *data = iio_priv(indio_dev);
858 int ret;
859
860 fxls8962af_standby(data);
861
862 /* Disable buffer interrupt */
863 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_EN,
864 FXLS8962AF_INT_EN_BUF_EN, 0);
865 if (ret)
866 return ret;
867
868 ret = __fxls8962af_fifo_set_mode(data, false);
869
870 if (data->enable_event)
871 fxls8962af_active(data);
872
873 return ret;
874 }
875
fxls8962af_buffer_postdisable(struct iio_dev * indio_dev)876 static int fxls8962af_buffer_postdisable(struct iio_dev *indio_dev)
877 {
878 struct fxls8962af_data *data = iio_priv(indio_dev);
879
880 if (!data->enable_event)
881 fxls8962af_power_off(data);
882
883 return 0;
884 }
885
886 static const struct iio_buffer_setup_ops fxls8962af_buffer_ops = {
887 .preenable = fxls8962af_buffer_preenable,
888 .postenable = fxls8962af_buffer_postenable,
889 .predisable = fxls8962af_buffer_predisable,
890 .postdisable = fxls8962af_buffer_postdisable,
891 };
892
fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data * data,u16 * buffer,int samples,int sample_length)893 static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data,
894 u16 *buffer, int samples,
895 int sample_length)
896 {
897 int i, ret;
898
899 for (i = 0; i < samples; i++) {
900 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB,
901 &buffer[i * 3], sample_length);
902 if (ret)
903 return ret;
904 }
905
906 return 0;
907 }
908
fxls8962af_fifo_transfer(struct fxls8962af_data * data,u16 * buffer,int samples)909 static int fxls8962af_fifo_transfer(struct fxls8962af_data *data,
910 u16 *buffer, int samples)
911 {
912 struct device *dev = regmap_get_device(data->regmap);
913 int sample_length = 3 * sizeof(*buffer);
914 int total_length = samples * sample_length;
915 int ret;
916
917 if (i2c_verify_client(dev) &&
918 data->chip_info->chip_id == FXLS8962AF_DEVICE_ID)
919 /*
920 * Due to errata bug (only applicable on fxls8962af):
921 * E3: FIFO burst read operation error using I2C interface
922 * We have to avoid burst reads on I2C..
923 */
924 ret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples,
925 sample_length);
926 else
927 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer,
928 total_length);
929
930 if (ret)
931 dev_err(dev, "Error transferring data from fifo: %d\n", ret);
932
933 return ret;
934 }
935
fxls8962af_fifo_flush(struct iio_dev * indio_dev)936 static int fxls8962af_fifo_flush(struct iio_dev *indio_dev)
937 {
938 struct fxls8962af_data *data = iio_priv(indio_dev);
939 struct device *dev = regmap_get_device(data->regmap);
940 u16 buffer[FXLS8962AF_FIFO_LENGTH * 3];
941 uint64_t sample_period;
942 unsigned int reg;
943 int64_t tstamp;
944 int ret, i;
945 u8 count;
946
947 ret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, ®);
948 if (ret)
949 return ret;
950
951 if (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) {
952 dev_err(dev, "Buffer overflow");
953 return -EOVERFLOW;
954 }
955
956 count = reg & FXLS8962AF_BUF_STATUS_BUF_CNT;
957 if (!count)
958 return 0;
959
960 data->old_timestamp = data->timestamp;
961 data->timestamp = iio_get_time_ns(indio_dev);
962
963 /*
964 * Approximate timestamps for each of the sample based on the sampling,
965 * frequency, timestamp for last sample and number of samples.
966 */
967 sample_period = (data->timestamp - data->old_timestamp);
968 do_div(sample_period, count);
969 tstamp = data->timestamp - (count - 1) * sample_period;
970
971 ret = fxls8962af_fifo_transfer(data, buffer, count);
972 if (ret)
973 return ret;
974
975 /* Demux hw FIFO into kfifo. */
976 for (i = 0; i < count; i++) {
977 int j, bit;
978
979 j = 0;
980 for_each_set_bit(bit, indio_dev->active_scan_mask,
981 indio_dev->masklength) {
982 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
983 sizeof(data->scan.channels[0]));
984 }
985
986 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
987 tstamp);
988
989 tstamp += sample_period;
990 }
991
992 return count;
993 }
994
fxls8962af_event_interrupt(struct iio_dev * indio_dev)995 static int fxls8962af_event_interrupt(struct iio_dev *indio_dev)
996 {
997 struct fxls8962af_data *data = iio_priv(indio_dev);
998 s64 ts = iio_get_time_ns(indio_dev);
999 unsigned int reg;
1000 u64 ev_code;
1001 int ret;
1002
1003 ret = regmap_read(data->regmap, FXLS8962AF_SDCD_INT_SRC1, ®);
1004 if (ret)
1005 return ret;
1006
1007 if (reg & FXLS8962AF_SDCD_INT_SRC1_X_OT) {
1008 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_X_POL ?
1009 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;
1010 iio_push_event(indio_dev,
1011 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1012 IIO_EV_TYPE_THRESH, ev_code), ts);
1013 }
1014
1015 if (reg & FXLS8962AF_SDCD_INT_SRC1_Y_OT) {
1016 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Y_POL ?
1017 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;
1018 iio_push_event(indio_dev,
1019 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1020 IIO_EV_TYPE_THRESH, ev_code), ts);
1021 }
1022
1023 if (reg & FXLS8962AF_SDCD_INT_SRC1_Z_OT) {
1024 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Z_POL ?
1025 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;
1026 iio_push_event(indio_dev,
1027 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1028 IIO_EV_TYPE_THRESH, ev_code), ts);
1029 }
1030
1031 return 0;
1032 }
1033
fxls8962af_interrupt(int irq,void * p)1034 static irqreturn_t fxls8962af_interrupt(int irq, void *p)
1035 {
1036 struct iio_dev *indio_dev = p;
1037 struct fxls8962af_data *data = iio_priv(indio_dev);
1038 unsigned int reg;
1039 int ret;
1040
1041 ret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, ®);
1042 if (ret)
1043 return IRQ_NONE;
1044
1045 if (reg & FXLS8962AF_INT_STATUS_SRC_BUF) {
1046 ret = fxls8962af_fifo_flush(indio_dev);
1047 if (ret < 0)
1048 return IRQ_NONE;
1049
1050 return IRQ_HANDLED;
1051 }
1052
1053 if (reg & FXLS8962AF_INT_STATUS_SRC_SDCD_OT) {
1054 ret = fxls8962af_event_interrupt(indio_dev);
1055 if (ret < 0)
1056 return IRQ_NONE;
1057
1058 return IRQ_HANDLED;
1059 }
1060
1061 return IRQ_NONE;
1062 }
1063
fxls8962af_pm_disable(void * dev_ptr)1064 static void fxls8962af_pm_disable(void *dev_ptr)
1065 {
1066 struct device *dev = dev_ptr;
1067 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1068
1069 pm_runtime_disable(dev);
1070 pm_runtime_set_suspended(dev);
1071 pm_runtime_put_noidle(dev);
1072
1073 fxls8962af_standby(iio_priv(indio_dev));
1074 }
1075
fxls8962af_get_irq(struct device_node * of_node,enum fxls8962af_int_pin * pin)1076 static void fxls8962af_get_irq(struct device_node *of_node,
1077 enum fxls8962af_int_pin *pin)
1078 {
1079 int irq;
1080
1081 irq = of_irq_get_byname(of_node, "INT2");
1082 if (irq > 0) {
1083 *pin = FXLS8962AF_PIN_INT2;
1084 return;
1085 }
1086
1087 *pin = FXLS8962AF_PIN_INT1;
1088 }
1089
fxls8962af_irq_setup(struct iio_dev * indio_dev,int irq)1090 static int fxls8962af_irq_setup(struct iio_dev *indio_dev, int irq)
1091 {
1092 struct fxls8962af_data *data = iio_priv(indio_dev);
1093 struct device *dev = regmap_get_device(data->regmap);
1094 unsigned long irq_type;
1095 bool irq_active_high;
1096 enum fxls8962af_int_pin int_pin;
1097 u8 int_pin_sel;
1098 int ret;
1099
1100 fxls8962af_get_irq(dev->of_node, &int_pin);
1101 switch (int_pin) {
1102 case FXLS8962AF_PIN_INT1:
1103 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1;
1104 break;
1105 case FXLS8962AF_PIN_INT2:
1106 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2;
1107 break;
1108 default:
1109 dev_err(dev, "unsupported int pin selected\n");
1110 return -EINVAL;
1111 }
1112
1113 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL,
1114 FXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel);
1115 if (ret)
1116 return ret;
1117
1118 irq_type = irqd_get_trigger_type(irq_get_irq_data(irq));
1119
1120 switch (irq_type) {
1121 case IRQF_TRIGGER_HIGH:
1122 case IRQF_TRIGGER_RISING:
1123 irq_active_high = true;
1124 break;
1125 case IRQF_TRIGGER_LOW:
1126 case IRQF_TRIGGER_FALLING:
1127 irq_active_high = false;
1128 break;
1129 default:
1130 dev_info(dev, "mode %lx unsupported\n", irq_type);
1131 return -EINVAL;
1132 }
1133
1134 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4,
1135 FXLS8962AF_SC4_INT_POL_MASK,
1136 FXLS8962AF_SC4_INT_POL_PREP(irq_active_high));
1137 if (ret)
1138 return ret;
1139
1140 if (device_property_read_bool(dev, "drive-open-drain")) {
1141 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4,
1142 FXLS8962AF_SC4_INT_PP_OD_MASK,
1143 FXLS8962AF_SC4_INT_PP_OD_PREP(1));
1144 if (ret)
1145 return ret;
1146
1147 irq_type |= IRQF_SHARED;
1148 }
1149
1150 return devm_request_threaded_irq(dev,
1151 irq,
1152 NULL, fxls8962af_interrupt,
1153 irq_type | IRQF_ONESHOT,
1154 indio_dev->name, indio_dev);
1155 }
1156
fxls8962af_core_probe(struct device * dev,struct regmap * regmap,int irq)1157 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq)
1158 {
1159 struct fxls8962af_data *data;
1160 struct iio_dev *indio_dev;
1161 unsigned int reg;
1162 int ret, i;
1163
1164 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1165 if (!indio_dev)
1166 return -ENOMEM;
1167
1168 data = iio_priv(indio_dev);
1169 dev_set_drvdata(dev, indio_dev);
1170 data->regmap = regmap;
1171 data->irq = irq;
1172
1173 ret = iio_read_mount_matrix(dev, &data->orientation);
1174 if (ret)
1175 return ret;
1176
1177 ret = devm_regulator_get_enable(dev, "vdd");
1178 if (ret)
1179 return dev_err_probe(dev, ret,
1180 "Failed to get vdd regulator\n");
1181
1182 ret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, ®);
1183 if (ret)
1184 return ret;
1185
1186 for (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) {
1187 if (fxls_chip_info_table[i].chip_id == reg) {
1188 data->chip_info = &fxls_chip_info_table[i];
1189 break;
1190 }
1191 }
1192 if (i == ARRAY_SIZE(fxls_chip_info_table)) {
1193 dev_err(dev, "failed to match device in table\n");
1194 return -ENXIO;
1195 }
1196
1197 indio_dev->channels = data->chip_info->channels;
1198 indio_dev->num_channels = data->chip_info->num_channels;
1199 indio_dev->name = data->chip_info->name;
1200 indio_dev->info = &fxls8962af_info;
1201 indio_dev->modes = INDIO_DIRECT_MODE;
1202
1203 ret = fxls8962af_reset(data);
1204 if (ret)
1205 return ret;
1206
1207 if (irq) {
1208 ret = fxls8962af_irq_setup(indio_dev, irq);
1209 if (ret)
1210 return ret;
1211
1212 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev,
1213 &fxls8962af_buffer_ops);
1214 if (ret)
1215 return ret;
1216 }
1217
1218 ret = pm_runtime_set_active(dev);
1219 if (ret)
1220 return ret;
1221
1222 pm_runtime_enable(dev);
1223 pm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS);
1224 pm_runtime_use_autosuspend(dev);
1225
1226 ret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev);
1227 if (ret)
1228 return ret;
1229
1230 if (device_property_read_bool(dev, "wakeup-source"))
1231 device_init_wakeup(dev, true);
1232
1233 return devm_iio_device_register(dev, indio_dev);
1234 }
1235 EXPORT_SYMBOL_NS_GPL(fxls8962af_core_probe, IIO_FXLS8962AF);
1236
fxls8962af_runtime_suspend(struct device * dev)1237 static int fxls8962af_runtime_suspend(struct device *dev)
1238 {
1239 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev));
1240 int ret;
1241
1242 ret = fxls8962af_standby(data);
1243 if (ret) {
1244 dev_err(dev, "powering off device failed\n");
1245 return ret;
1246 }
1247
1248 return 0;
1249 }
1250
fxls8962af_runtime_resume(struct device * dev)1251 static int fxls8962af_runtime_resume(struct device *dev)
1252 {
1253 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev));
1254
1255 return fxls8962af_active(data);
1256 }
1257
fxls8962af_suspend(struct device * dev)1258 static int fxls8962af_suspend(struct device *dev)
1259 {
1260 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1261 struct fxls8962af_data *data = iio_priv(indio_dev);
1262
1263 if (device_may_wakeup(dev) && data->enable_event) {
1264 enable_irq_wake(data->irq);
1265
1266 /*
1267 * Disable buffer, as the buffer is so small the device will wake
1268 * almost immediately.
1269 */
1270 if (iio_buffer_enabled(indio_dev))
1271 fxls8962af_buffer_predisable(indio_dev);
1272 } else {
1273 fxls8962af_runtime_suspend(dev);
1274 }
1275
1276 return 0;
1277 }
1278
fxls8962af_resume(struct device * dev)1279 static int fxls8962af_resume(struct device *dev)
1280 {
1281 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1282 struct fxls8962af_data *data = iio_priv(indio_dev);
1283
1284 if (device_may_wakeup(dev) && data->enable_event) {
1285 disable_irq_wake(data->irq);
1286
1287 if (iio_buffer_enabled(indio_dev))
1288 fxls8962af_buffer_postenable(indio_dev);
1289 } else {
1290 fxls8962af_runtime_resume(dev);
1291 }
1292
1293 return 0;
1294 }
1295
1296 EXPORT_NS_GPL_DEV_PM_OPS(fxls8962af_pm_ops, IIO_FXLS8962AF) = {
1297 SYSTEM_SLEEP_PM_OPS(fxls8962af_suspend, fxls8962af_resume)
1298 RUNTIME_PM_OPS(fxls8962af_runtime_suspend, fxls8962af_runtime_resume, NULL)
1299 };
1300
1301 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.com>");
1302 MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer driver");
1303 MODULE_LICENSE("GPL v2");
1304