1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/acpi.h>
34 #include <linux/etherdevice.h>
35 #include <linux/interrupt.h>
36 #include <linux/iopoll.h>
37 #include <linux/kernel.h>
38 #include <linux/types.h>
39 #include <net/addrconf.h>
40 #include <rdma/ib_addr.h>
41 #include <rdma/ib_cache.h>
42 #include <rdma/ib_umem.h>
43 #include <rdma/uverbs_ioctl.h>
44
45 #include "hns_roce_common.h"
46 #include "hns_roce_device.h"
47 #include "hns_roce_cmd.h"
48 #include "hns_roce_hem.h"
49 #include "hns_roce_hw_v2.h"
50
51 enum {
52 CMD_RST_PRC_OTHERS,
53 CMD_RST_PRC_SUCCESS,
54 CMD_RST_PRC_EBUSY,
55 };
56
57 enum ecc_resource_type {
58 ECC_RESOURCE_QPC,
59 ECC_RESOURCE_CQC,
60 ECC_RESOURCE_MPT,
61 ECC_RESOURCE_SRQC,
62 ECC_RESOURCE_GMV,
63 ECC_RESOURCE_QPC_TIMER,
64 ECC_RESOURCE_CQC_TIMER,
65 ECC_RESOURCE_SCCC,
66 ECC_RESOURCE_COUNT,
67 };
68
69 static const struct {
70 const char *name;
71 u8 read_bt0_op;
72 u8 write_bt0_op;
73 } fmea_ram_res[] = {
74 { "ECC_RESOURCE_QPC",
75 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 },
76 { "ECC_RESOURCE_CQC",
77 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 },
78 { "ECC_RESOURCE_MPT",
79 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 },
80 { "ECC_RESOURCE_SRQC",
81 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 },
82 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */
83 { "ECC_RESOURCE_GMV",
84 0, 0 },
85 { "ECC_RESOURCE_QPC_TIMER",
86 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 },
87 { "ECC_RESOURCE_CQC_TIMER",
88 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 },
89 { "ECC_RESOURCE_SCCC",
90 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 },
91 };
92
set_data_seg_v2(struct hns_roce_v2_wqe_data_seg * dseg,struct ib_sge * sg)93 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
94 struct ib_sge *sg)
95 {
96 dseg->lkey = cpu_to_le32(sg->lkey);
97 dseg->addr = cpu_to_le64(sg->addr);
98 dseg->len = cpu_to_le32(sg->length);
99 }
100
101 /*
102 * mapped-value = 1 + real-value
103 * The hns wr opcode real value is start from 0, In order to distinguish between
104 * initialized and uninitialized map values, we plus 1 to the actual value when
105 * defining the mapping, so that the validity can be identified by checking the
106 * mapped value is greater than 0.
107 */
108 #define HR_OPC_MAP(ib_key, hr_key) \
109 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
110
111 static const u32 hns_roce_op_code[] = {
112 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
113 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
114 HR_OPC_MAP(SEND, SEND),
115 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
116 HR_OPC_MAP(RDMA_READ, RDMA_READ),
117 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
118 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
119 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
120 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
121 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
122 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
123 };
124
to_hr_opcode(u32 ib_opcode)125 static u32 to_hr_opcode(u32 ib_opcode)
126 {
127 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
128 return HNS_ROCE_V2_WQE_OP_MASK;
129
130 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
131 HNS_ROCE_V2_WQE_OP_MASK;
132 }
133
set_frmr_seg(struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_reg_wr * wr)134 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
135 const struct ib_reg_wr *wr)
136 {
137 struct hns_roce_wqe_frmr_seg *fseg =
138 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
139 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
140 u64 pbl_ba;
141
142 /* use ib_access_flags */
143 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND);
144 hr_reg_write_bool(fseg, FRMR_ATOMIC,
145 wr->access & IB_ACCESS_REMOTE_ATOMIC);
146 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
147 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
148 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
149
150 /* Data structure reuse may lead to confusion */
151 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
152 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
153 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
154
155 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
156 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
157 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
158 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
159
160 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
161 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
162 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
163 hr_reg_clear(fseg, FRMR_BLK_MODE);
164 }
165
set_atomic_seg(const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int valid_num_sge)166 static void set_atomic_seg(const struct ib_send_wr *wr,
167 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
168 unsigned int valid_num_sge)
169 {
170 struct hns_roce_v2_wqe_data_seg *dseg =
171 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
172 struct hns_roce_wqe_atomic_seg *aseg =
173 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
174
175 set_data_seg_v2(dseg, wr->sg_list);
176
177 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
178 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
179 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
180 } else {
181 aseg->fetchadd_swap_data =
182 cpu_to_le64(atomic_wr(wr)->compare_add);
183 aseg->cmp_data = 0;
184 }
185
186 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
187 }
188
fill_ext_sge_inl_data(struct hns_roce_qp * qp,const struct ib_send_wr * wr,unsigned int * sge_idx,u32 msg_len)189 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
190 const struct ib_send_wr *wr,
191 unsigned int *sge_idx, u32 msg_len)
192 {
193 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
194 unsigned int left_len_in_pg;
195 unsigned int idx = *sge_idx;
196 unsigned int i = 0;
197 unsigned int len;
198 void *addr;
199 void *dseg;
200
201 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) {
202 ibdev_err(ibdev,
203 "no enough extended sge space for inline data.\n");
204 return -EINVAL;
205 }
206
207 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
208 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
209 len = wr->sg_list[0].length;
210 addr = (void *)(unsigned long)(wr->sg_list[0].addr);
211
212 /* When copying data to extended sge space, the left length in page may
213 * not long enough for current user's sge. So the data should be
214 * splited into several parts, one in the first page, and the others in
215 * the subsequent pages.
216 */
217 while (1) {
218 if (len <= left_len_in_pg) {
219 memcpy(dseg, addr, len);
220
221 idx += len / HNS_ROCE_SGE_SIZE;
222
223 i++;
224 if (i >= wr->num_sge)
225 break;
226
227 left_len_in_pg -= len;
228 len = wr->sg_list[i].length;
229 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
230 dseg += len;
231 } else {
232 memcpy(dseg, addr, left_len_in_pg);
233
234 len -= left_len_in_pg;
235 addr += left_len_in_pg;
236 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
237 dseg = hns_roce_get_extend_sge(qp,
238 idx & (qp->sge.sge_cnt - 1));
239 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
240 }
241 }
242
243 *sge_idx = idx;
244
245 return 0;
246 }
247
set_extend_sge(struct hns_roce_qp * qp,struct ib_sge * sge,unsigned int * sge_ind,unsigned int cnt)248 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
249 unsigned int *sge_ind, unsigned int cnt)
250 {
251 struct hns_roce_v2_wqe_data_seg *dseg;
252 unsigned int idx = *sge_ind;
253
254 while (cnt > 0) {
255 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
256 if (likely(sge->length)) {
257 set_data_seg_v2(dseg, sge);
258 idx++;
259 cnt--;
260 }
261 sge++;
262 }
263
264 *sge_ind = idx;
265 }
266
check_inl_data_len(struct hns_roce_qp * qp,unsigned int len)267 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
268 {
269 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
270 int mtu = ib_mtu_enum_to_int(qp->path_mtu);
271
272 if (mtu < 0 || len > qp->max_inline_data || len > mtu) {
273 ibdev_err(&hr_dev->ib_dev,
274 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
275 len, qp->max_inline_data, mtu);
276 return false;
277 }
278
279 return true;
280 }
281
set_rc_inl(struct hns_roce_qp * qp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_idx)282 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
283 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
284 unsigned int *sge_idx)
285 {
286 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
287 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
288 struct ib_device *ibdev = &hr_dev->ib_dev;
289 unsigned int curr_idx = *sge_idx;
290 void *dseg = rc_sq_wqe;
291 unsigned int i;
292 int ret;
293
294 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
295 ibdev_err(ibdev, "invalid inline parameters!\n");
296 return -EINVAL;
297 }
298
299 if (!check_inl_data_len(qp, msg_len))
300 return -EINVAL;
301
302 dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
303
304 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
305 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
306
307 for (i = 0; i < wr->num_sge; i++) {
308 memcpy(dseg, ((void *)wr->sg_list[i].addr),
309 wr->sg_list[i].length);
310 dseg += wr->sg_list[i].length;
311 }
312 } else {
313 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
314
315 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
316 if (ret)
317 return ret;
318
319 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx);
320 }
321
322 *sge_idx = curr_idx;
323
324 return 0;
325 }
326
set_rwqe_data_seg(struct ib_qp * ibqp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_ind,unsigned int valid_num_sge)327 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
328 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
329 unsigned int *sge_ind,
330 unsigned int valid_num_sge)
331 {
332 struct hns_roce_v2_wqe_data_seg *dseg =
333 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
334 struct hns_roce_qp *qp = to_hr_qp(ibqp);
335 int j = 0;
336 int i;
337
338 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX,
339 (*sge_ind) & (qp->sge.sge_cnt - 1));
340
341 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE,
342 !!(wr->send_flags & IB_SEND_INLINE));
343 if (wr->send_flags & IB_SEND_INLINE)
344 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
345
346 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
347 for (i = 0; i < wr->num_sge; i++) {
348 if (likely(wr->sg_list[i].length)) {
349 set_data_seg_v2(dseg, wr->sg_list + i);
350 dseg++;
351 }
352 }
353 } else {
354 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
355 if (likely(wr->sg_list[i].length)) {
356 set_data_seg_v2(dseg, wr->sg_list + i);
357 dseg++;
358 j++;
359 }
360 }
361
362 set_extend_sge(qp, wr->sg_list + i, sge_ind,
363 valid_num_sge - HNS_ROCE_SGE_IN_WQE);
364 }
365
366 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
367
368 return 0;
369 }
370
check_send_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)371 static int check_send_valid(struct hns_roce_dev *hr_dev,
372 struct hns_roce_qp *hr_qp)
373 {
374 if (unlikely(hr_qp->state == IB_QPS_RESET ||
375 hr_qp->state == IB_QPS_INIT ||
376 hr_qp->state == IB_QPS_RTR))
377 return -EINVAL;
378 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
379 return -EIO;
380
381 return 0;
382 }
383
calc_wr_sge_num(const struct ib_send_wr * wr,unsigned int * sge_len)384 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
385 unsigned int *sge_len)
386 {
387 unsigned int valid_num = 0;
388 unsigned int len = 0;
389 int i;
390
391 for (i = 0; i < wr->num_sge; i++) {
392 if (likely(wr->sg_list[i].length)) {
393 len += wr->sg_list[i].length;
394 valid_num++;
395 }
396 }
397
398 *sge_len = len;
399 return valid_num;
400 }
401
get_immtdata(const struct ib_send_wr * wr)402 static __le32 get_immtdata(const struct ib_send_wr *wr)
403 {
404 switch (wr->opcode) {
405 case IB_WR_SEND_WITH_IMM:
406 case IB_WR_RDMA_WRITE_WITH_IMM:
407 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
408 default:
409 return 0;
410 }
411 }
412
set_ud_opcode(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,const struct ib_send_wr * wr)413 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
414 const struct ib_send_wr *wr)
415 {
416 u32 ib_op = wr->opcode;
417
418 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
419 return -EINVAL;
420
421 ud_sq_wqe->immtdata = get_immtdata(wr);
422
423 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
424
425 return 0;
426 }
427
fill_ud_av(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,struct hns_roce_ah * ah)428 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
429 struct hns_roce_ah *ah)
430 {
431 struct ib_device *ib_dev = ah->ibah.device;
432 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
433
434 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport);
435 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit);
436 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass);
437 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel);
438
439 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL))
440 return -EINVAL;
441
442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl);
443
444 ud_sq_wqe->sgid_index = ah->av.gid_index;
445
446 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
447 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
448
449 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
450 return 0;
451
452 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en);
453 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id);
454
455 return 0;
456 }
457
set_ud_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)458 static inline int set_ud_wqe(struct hns_roce_qp *qp,
459 const struct ib_send_wr *wr,
460 void *wqe, unsigned int *sge_idx,
461 unsigned int owner_bit)
462 {
463 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
464 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
465 unsigned int curr_idx = *sge_idx;
466 unsigned int valid_num_sge;
467 u32 msg_len = 0;
468 int ret;
469
470 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
471
472 ret = set_ud_opcode(ud_sq_wqe, wr);
473 if (WARN_ON_ONCE(ret))
474 return ret;
475
476 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
477
478 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE,
479 !!(wr->send_flags & IB_SEND_SIGNALED));
480 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE,
481 !!(wr->send_flags & IB_SEND_SOLICITED));
482
483 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn);
484 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge);
485 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX,
486 curr_idx & (qp->sge.sge_cnt - 1));
487
488 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
489 qp->qkey : ud_wr(wr)->remote_qkey);
490 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn);
491
492 ret = fill_ud_av(ud_sq_wqe, ah);
493 if (ret)
494 return ret;
495
496 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
497
498 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
499
500 /*
501 * The pipeline can sequentially post all valid WQEs into WQ buffer,
502 * including new WQEs waiting for the doorbell to update the PI again.
503 * Therefore, the owner bit of WQE MUST be updated after all fields
504 * and extSGEs have been written into DDR instead of cache.
505 */
506 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
507 dma_wmb();
508
509 *sge_idx = curr_idx;
510 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit);
511
512 return 0;
513 }
514
set_rc_opcode(struct hns_roce_dev * hr_dev,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_send_wr * wr)515 static int set_rc_opcode(struct hns_roce_dev *hr_dev,
516 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
517 const struct ib_send_wr *wr)
518 {
519 u32 ib_op = wr->opcode;
520 int ret = 0;
521
522 rc_sq_wqe->immtdata = get_immtdata(wr);
523
524 switch (ib_op) {
525 case IB_WR_RDMA_READ:
526 case IB_WR_RDMA_WRITE:
527 case IB_WR_RDMA_WRITE_WITH_IMM:
528 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
529 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
530 break;
531 case IB_WR_SEND:
532 case IB_WR_SEND_WITH_IMM:
533 break;
534 case IB_WR_ATOMIC_CMP_AND_SWP:
535 case IB_WR_ATOMIC_FETCH_AND_ADD:
536 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
537 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
538 break;
539 case IB_WR_REG_MR:
540 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
541 set_frmr_seg(rc_sq_wqe, reg_wr(wr));
542 else
543 ret = -EOPNOTSUPP;
544 break;
545 case IB_WR_SEND_WITH_INV:
546 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
547 break;
548 default:
549 ret = -EINVAL;
550 }
551
552 if (unlikely(ret))
553 return ret;
554
555 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
556
557 return ret;
558 }
559
set_rc_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)560 static inline int set_rc_wqe(struct hns_roce_qp *qp,
561 const struct ib_send_wr *wr,
562 void *wqe, unsigned int *sge_idx,
563 unsigned int owner_bit)
564 {
565 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
566 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
567 unsigned int curr_idx = *sge_idx;
568 unsigned int valid_num_sge;
569 u32 msg_len = 0;
570 int ret;
571
572 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
573
574 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
575
576 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
577 if (WARN_ON_ONCE(ret))
578 return ret;
579
580 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO,
581 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
582
583 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE,
584 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
585
586 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE,
587 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
588
589 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
590 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
591 if (msg_len != ATOMIC_WR_LEN)
592 return -EINVAL;
593 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
594 } else if (wr->opcode != IB_WR_REG_MR) {
595 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
596 &curr_idx, valid_num_sge);
597 if (ret)
598 return ret;
599 }
600
601 /*
602 * The pipeline can sequentially post all valid WQEs into WQ buffer,
603 * including new WQEs waiting for the doorbell to update the PI again.
604 * Therefore, the owner bit of WQE MUST be updated after all fields
605 * and extSGEs have been written into DDR instead of cache.
606 */
607 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
608 dma_wmb();
609
610 *sge_idx = curr_idx;
611 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit);
612
613 return ret;
614 }
615
update_sq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)616 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
617 struct hns_roce_qp *qp)
618 {
619 if (unlikely(qp->state == IB_QPS_ERR)) {
620 flush_cqe(hr_dev, qp);
621 } else {
622 struct hns_roce_v2_db sq_db = {};
623
624 hr_reg_write(&sq_db, DB_TAG, qp->qpn);
625 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
626 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
627 hr_reg_write(&sq_db, DB_SL, qp->sl);
628
629 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
630 }
631 }
632
update_rq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)633 static inline void update_rq_db(struct hns_roce_dev *hr_dev,
634 struct hns_roce_qp *qp)
635 {
636 if (unlikely(qp->state == IB_QPS_ERR)) {
637 flush_cqe(hr_dev, qp);
638 } else {
639 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
640 *qp->rdb.db_record =
641 qp->rq.head & V2_DB_PRODUCER_IDX_M;
642 } else {
643 struct hns_roce_v2_db rq_db = {};
644
645 hr_reg_write(&rq_db, DB_TAG, qp->qpn);
646 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
647 hr_reg_write(&rq_db, DB_PI, qp->rq.head);
648
649 hns_roce_write64(hr_dev, (__le32 *)&rq_db,
650 qp->rq.db_reg);
651 }
652 }
653 }
654
hns_roce_write512(struct hns_roce_dev * hr_dev,u64 * val,u64 __iomem * dest)655 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
656 u64 __iomem *dest)
657 {
658 #define HNS_ROCE_WRITE_TIMES 8
659 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
660 struct hnae3_handle *handle = priv->handle;
661 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
662 int i;
663
664 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
665 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
666 writeq_relaxed(*(val + i), dest + i);
667 }
668
write_dwqe(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,void * wqe)669 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
670 void *wqe)
671 {
672 #define HNS_ROCE_SL_SHIFT 2
673 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
674
675 if (unlikely(qp->state == IB_QPS_ERR)) {
676 flush_cqe(hr_dev, qp);
677 return;
678 }
679 /* All kinds of DirectWQE have the same header field layout */
680 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG);
681 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl);
682 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H,
683 qp->sl >> HNS_ROCE_SL_SHIFT);
684 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head);
685
686 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
687 }
688
hns_roce_v2_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)689 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
690 const struct ib_send_wr *wr,
691 const struct ib_send_wr **bad_wr)
692 {
693 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
694 struct ib_device *ibdev = &hr_dev->ib_dev;
695 struct hns_roce_qp *qp = to_hr_qp(ibqp);
696 unsigned long flags = 0;
697 unsigned int owner_bit;
698 unsigned int sge_idx;
699 unsigned int wqe_idx;
700 void *wqe = NULL;
701 u32 nreq;
702 int ret;
703
704 spin_lock_irqsave(&qp->sq.lock, flags);
705
706 ret = check_send_valid(hr_dev, qp);
707 if (unlikely(ret)) {
708 *bad_wr = wr;
709 nreq = 0;
710 goto out;
711 }
712
713 sge_idx = qp->next_sge;
714
715 for (nreq = 0; wr; ++nreq, wr = wr->next) {
716 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
717 ret = -ENOMEM;
718 *bad_wr = wr;
719 goto out;
720 }
721
722 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
723
724 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
725 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
726 wr->num_sge, qp->sq.max_gs);
727 ret = -EINVAL;
728 *bad_wr = wr;
729 goto out;
730 }
731
732 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
733 qp->sq.wrid[wqe_idx] = wr->wr_id;
734 owner_bit =
735 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
736
737 /* Corresponding to the QP type, wqe process separately */
738 if (ibqp->qp_type == IB_QPT_RC)
739 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
740 else
741 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
742
743 if (unlikely(ret)) {
744 *bad_wr = wr;
745 goto out;
746 }
747 }
748
749 out:
750 if (likely(nreq)) {
751 qp->sq.head += nreq;
752 qp->next_sge = sge_idx;
753
754 if (nreq == 1 && !ret &&
755 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
756 write_dwqe(hr_dev, qp, wqe);
757 else
758 update_sq_db(hr_dev, qp);
759 }
760
761 spin_unlock_irqrestore(&qp->sq.lock, flags);
762
763 return ret;
764 }
765
check_recv_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)766 static int check_recv_valid(struct hns_roce_dev *hr_dev,
767 struct hns_roce_qp *hr_qp)
768 {
769 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
770 return -EIO;
771
772 if (hr_qp->state == IB_QPS_RESET)
773 return -EINVAL;
774
775 return 0;
776 }
777
fill_recv_sge_to_wqe(const struct ib_recv_wr * wr,void * wqe,u32 max_sge,bool rsv)778 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
779 u32 max_sge, bool rsv)
780 {
781 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
782 u32 i, cnt;
783
784 for (i = 0, cnt = 0; i < wr->num_sge; i++) {
785 /* Skip zero-length sge */
786 if (!wr->sg_list[i].length)
787 continue;
788 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
789 cnt++;
790 }
791
792 /* Fill a reserved sge to make hw stop reading remaining segments */
793 if (rsv) {
794 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
795 dseg[cnt].addr = 0;
796 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
797 } else {
798 /* Clear remaining segments to make ROCEE ignore sges */
799 if (cnt < max_sge)
800 memset(dseg + cnt, 0,
801 (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
802 }
803 }
804
fill_rq_wqe(struct hns_roce_qp * hr_qp,const struct ib_recv_wr * wr,u32 wqe_idx,u32 max_sge)805 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
806 u32 wqe_idx, u32 max_sge)
807 {
808 void *wqe = NULL;
809
810 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
811 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
812 }
813
hns_roce_v2_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)814 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
815 const struct ib_recv_wr *wr,
816 const struct ib_recv_wr **bad_wr)
817 {
818 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
819 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
820 struct ib_device *ibdev = &hr_dev->ib_dev;
821 u32 wqe_idx, nreq, max_sge;
822 unsigned long flags;
823 int ret;
824
825 spin_lock_irqsave(&hr_qp->rq.lock, flags);
826
827 ret = check_recv_valid(hr_dev, hr_qp);
828 if (unlikely(ret)) {
829 *bad_wr = wr;
830 nreq = 0;
831 goto out;
832 }
833
834 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
835 for (nreq = 0; wr; ++nreq, wr = wr->next) {
836 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
837 hr_qp->ibqp.recv_cq))) {
838 ret = -ENOMEM;
839 *bad_wr = wr;
840 goto out;
841 }
842
843 if (unlikely(wr->num_sge > max_sge)) {
844 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
845 wr->num_sge, max_sge);
846 ret = -EINVAL;
847 *bad_wr = wr;
848 goto out;
849 }
850
851 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
852 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
853 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
854 }
855
856 out:
857 if (likely(nreq)) {
858 hr_qp->rq.head += nreq;
859
860 update_rq_db(hr_dev, hr_qp);
861 }
862 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
863
864 return ret;
865 }
866
get_srq_wqe_buf(struct hns_roce_srq * srq,u32 n)867 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
868 {
869 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
870 }
871
get_idx_buf(struct hns_roce_idx_que * idx_que,u32 n)872 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
873 {
874 return hns_roce_buf_offset(idx_que->mtr.kmem,
875 n << idx_que->entry_shift);
876 }
877
hns_roce_free_srq_wqe(struct hns_roce_srq * srq,u32 wqe_index)878 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
879 {
880 /* always called with interrupts disabled. */
881 spin_lock(&srq->lock);
882
883 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
884 srq->idx_que.tail++;
885
886 spin_unlock(&srq->lock);
887 }
888
hns_roce_srqwq_overflow(struct hns_roce_srq * srq)889 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
890 {
891 struct hns_roce_idx_que *idx_que = &srq->idx_que;
892
893 return idx_que->head - idx_que->tail >= srq->wqe_cnt;
894 }
895
check_post_srq_valid(struct hns_roce_srq * srq,u32 max_sge,const struct ib_recv_wr * wr)896 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
897 const struct ib_recv_wr *wr)
898 {
899 struct ib_device *ib_dev = srq->ibsrq.device;
900
901 if (unlikely(wr->num_sge > max_sge)) {
902 ibdev_err(ib_dev,
903 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
904 wr->num_sge, max_sge);
905 return -EINVAL;
906 }
907
908 if (unlikely(hns_roce_srqwq_overflow(srq))) {
909 ibdev_err(ib_dev,
910 "failed to check srqwq status, srqwq is full.\n");
911 return -ENOMEM;
912 }
913
914 return 0;
915 }
916
get_srq_wqe_idx(struct hns_roce_srq * srq,u32 * wqe_idx)917 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
918 {
919 struct hns_roce_idx_que *idx_que = &srq->idx_que;
920 u32 pos;
921
922 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
923 if (unlikely(pos == srq->wqe_cnt))
924 return -ENOSPC;
925
926 bitmap_set(idx_que->bitmap, pos, 1);
927 *wqe_idx = pos;
928 return 0;
929 }
930
fill_wqe_idx(struct hns_roce_srq * srq,unsigned int wqe_idx)931 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
932 {
933 struct hns_roce_idx_que *idx_que = &srq->idx_que;
934 unsigned int head;
935 __le32 *buf;
936
937 head = idx_que->head & (srq->wqe_cnt - 1);
938
939 buf = get_idx_buf(idx_que, head);
940 *buf = cpu_to_le32(wqe_idx);
941
942 idx_que->head++;
943 }
944
update_srq_db(struct hns_roce_v2_db * db,struct hns_roce_srq * srq)945 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq)
946 {
947 hr_reg_write(db, DB_TAG, srq->srqn);
948 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
949 hr_reg_write(db, DB_PI, srq->idx_que.head);
950 }
951
hns_roce_v2_post_srq_recv(struct ib_srq * ibsrq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)952 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
953 const struct ib_recv_wr *wr,
954 const struct ib_recv_wr **bad_wr)
955 {
956 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
957 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
958 struct hns_roce_v2_db srq_db;
959 unsigned long flags;
960 int ret = 0;
961 u32 max_sge;
962 u32 wqe_idx;
963 void *wqe;
964 u32 nreq;
965
966 spin_lock_irqsave(&srq->lock, flags);
967
968 max_sge = srq->max_gs - srq->rsv_sge;
969 for (nreq = 0; wr; ++nreq, wr = wr->next) {
970 ret = check_post_srq_valid(srq, max_sge, wr);
971 if (ret) {
972 *bad_wr = wr;
973 break;
974 }
975
976 ret = get_srq_wqe_idx(srq, &wqe_idx);
977 if (unlikely(ret)) {
978 *bad_wr = wr;
979 break;
980 }
981
982 wqe = get_srq_wqe_buf(srq, wqe_idx);
983 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
984 fill_wqe_idx(srq, wqe_idx);
985 srq->wrid[wqe_idx] = wr->wr_id;
986 }
987
988 if (likely(nreq)) {
989 update_srq_db(&srq_db, srq);
990
991 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg);
992 }
993
994 spin_unlock_irqrestore(&srq->lock, flags);
995
996 return ret;
997 }
998
hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)999 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1000 unsigned long instance_stage,
1001 unsigned long reset_stage)
1002 {
1003 /* When hardware reset has been completed once or more, we should stop
1004 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1005 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1006 * stage of soft reset process, we should exit with error, and then
1007 * HNAE3_INIT_CLIENT related process can rollback the operation like
1008 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1009 * process will exit with error to notify NIC driver to reschedule soft
1010 * reset process once again.
1011 */
1012 hr_dev->is_reset = true;
1013 hr_dev->dis_db = true;
1014
1015 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1016 instance_stage == HNS_ROCE_STATE_INIT)
1017 return CMD_RST_PRC_EBUSY;
1018
1019 return CMD_RST_PRC_SUCCESS;
1020 }
1021
hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)1022 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1023 unsigned long instance_stage,
1024 unsigned long reset_stage)
1025 {
1026 #define HW_RESET_TIMEOUT_US 1000000
1027 #define HW_RESET_SLEEP_US 1000
1028
1029 struct hns_roce_v2_priv *priv = hr_dev->priv;
1030 struct hnae3_handle *handle = priv->handle;
1031 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1032 unsigned long val;
1033 int ret;
1034
1035 /* When hardware reset is detected, we should stop sending mailbox&cmq&
1036 * doorbell to hardware. If now in .init_instance() function, we should
1037 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1038 * process, we should exit with error, and then HNAE3_INIT_CLIENT
1039 * related process can rollback the operation like notifing hardware to
1040 * free resources, HNAE3_INIT_CLIENT related process will exit with
1041 * error to notify NIC driver to reschedule soft reset process once
1042 * again.
1043 */
1044 hr_dev->dis_db = true;
1045
1046 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
1047 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
1048 HW_RESET_TIMEOUT_US, false, handle);
1049 if (!ret)
1050 hr_dev->is_reset = true;
1051
1052 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1053 instance_stage == HNS_ROCE_STATE_INIT)
1054 return CMD_RST_PRC_EBUSY;
1055
1056 return CMD_RST_PRC_SUCCESS;
1057 }
1058
hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev * hr_dev)1059 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1060 {
1061 struct hns_roce_v2_priv *priv = hr_dev->priv;
1062 struct hnae3_handle *handle = priv->handle;
1063 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1064
1065 /* When software reset is detected at .init_instance() function, we
1066 * should stop sending mailbox&cmq&doorbell to hardware, and exit
1067 * with error.
1068 */
1069 hr_dev->dis_db = true;
1070 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1071 hr_dev->is_reset = true;
1072
1073 return CMD_RST_PRC_EBUSY;
1074 }
1075
check_aedev_reset_status(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1076 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1077 struct hnae3_handle *handle)
1078 {
1079 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1080 unsigned long instance_stage; /* the current instance stage */
1081 unsigned long reset_stage; /* the current reset stage */
1082 unsigned long reset_cnt;
1083 bool sw_resetting;
1084 bool hw_resetting;
1085
1086 /* Get information about reset from NIC driver or RoCE driver itself,
1087 * the meaning of the following variables from NIC driver are described
1088 * as below:
1089 * reset_cnt -- The count value of completed hardware reset.
1090 * hw_resetting -- Whether hardware device is resetting now.
1091 * sw_resetting -- Whether NIC's software reset process is running now.
1092 */
1093 instance_stage = handle->rinfo.instance_state;
1094 reset_stage = handle->rinfo.reset_state;
1095 reset_cnt = ops->ae_dev_reset_cnt(handle);
1096 if (reset_cnt != hr_dev->reset_cnt)
1097 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1098 reset_stage);
1099
1100 hw_resetting = ops->get_cmdq_stat(handle);
1101 if (hw_resetting)
1102 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1103 reset_stage);
1104
1105 sw_resetting = ops->ae_dev_resetting(handle);
1106 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1107 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1108
1109 return CMD_RST_PRC_OTHERS;
1110 }
1111
check_device_is_in_reset(struct hns_roce_dev * hr_dev)1112 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1113 {
1114 struct hns_roce_v2_priv *priv = hr_dev->priv;
1115 struct hnae3_handle *handle = priv->handle;
1116 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1117
1118 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1119 return true;
1120
1121 if (ops->get_hw_reset_stat(handle))
1122 return true;
1123
1124 if (ops->ae_dev_resetting(handle))
1125 return true;
1126
1127 return false;
1128 }
1129
v2_chk_mbox_is_avail(struct hns_roce_dev * hr_dev,bool * busy)1130 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1131 {
1132 struct hns_roce_v2_priv *priv = hr_dev->priv;
1133 u32 status;
1134
1135 if (hr_dev->is_reset)
1136 status = CMD_RST_PRC_SUCCESS;
1137 else
1138 status = check_aedev_reset_status(hr_dev, priv->handle);
1139
1140 *busy = (status == CMD_RST_PRC_EBUSY);
1141
1142 return status == CMD_RST_PRC_OTHERS;
1143 }
1144
hns_roce_alloc_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1145 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1146 struct hns_roce_v2_cmq_ring *ring)
1147 {
1148 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1149
1150 ring->desc = dma_alloc_coherent(hr_dev->dev, size,
1151 &ring->desc_dma_addr, GFP_KERNEL);
1152 if (!ring->desc)
1153 return -ENOMEM;
1154
1155 return 0;
1156 }
1157
hns_roce_free_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1158 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1159 struct hns_roce_v2_cmq_ring *ring)
1160 {
1161 dma_free_coherent(hr_dev->dev,
1162 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1163 ring->desc, ring->desc_dma_addr);
1164
1165 ring->desc_dma_addr = 0;
1166 }
1167
init_csq(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * csq)1168 static int init_csq(struct hns_roce_dev *hr_dev,
1169 struct hns_roce_v2_cmq_ring *csq)
1170 {
1171 dma_addr_t dma;
1172 int ret;
1173
1174 csq->desc_num = CMD_CSQ_DESC_NUM;
1175 spin_lock_init(&csq->lock);
1176 csq->flag = TYPE_CSQ;
1177 csq->head = 0;
1178
1179 ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1180 if (ret)
1181 return ret;
1182
1183 dma = csq->desc_dma_addr;
1184 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1185 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1186 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1187 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1188
1189 /* Make sure to write CI first and then PI */
1190 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1191 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1192
1193 return 0;
1194 }
1195
hns_roce_v2_cmq_init(struct hns_roce_dev * hr_dev)1196 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1197 {
1198 struct hns_roce_v2_priv *priv = hr_dev->priv;
1199 int ret;
1200
1201 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1202
1203 ret = init_csq(hr_dev, &priv->cmq.csq);
1204 if (ret)
1205 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1206
1207 return ret;
1208 }
1209
hns_roce_v2_cmq_exit(struct hns_roce_dev * hr_dev)1210 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1211 {
1212 struct hns_roce_v2_priv *priv = hr_dev->priv;
1213
1214 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1215 }
1216
hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc * desc,enum hns_roce_opcode_type opcode,bool is_read)1217 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1218 enum hns_roce_opcode_type opcode,
1219 bool is_read)
1220 {
1221 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1222 desc->opcode = cpu_to_le16(opcode);
1223 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1224 if (is_read)
1225 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1226 else
1227 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1228 }
1229
hns_roce_cmq_csq_done(struct hns_roce_dev * hr_dev)1230 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1231 {
1232 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1233 struct hns_roce_v2_priv *priv = hr_dev->priv;
1234
1235 return tail == priv->cmq.csq.head;
1236 }
1237
update_cmdq_status(struct hns_roce_dev * hr_dev)1238 static void update_cmdq_status(struct hns_roce_dev *hr_dev)
1239 {
1240 struct hns_roce_v2_priv *priv = hr_dev->priv;
1241 struct hnae3_handle *handle = priv->handle;
1242
1243 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
1244 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT)
1245 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR;
1246 }
1247
hns_roce_cmd_err_convert_errno(u16 desc_ret)1248 static int hns_roce_cmd_err_convert_errno(u16 desc_ret)
1249 {
1250 struct hns_roce_cmd_errcode errcode_table[] = {
1251 {CMD_EXEC_SUCCESS, 0},
1252 {CMD_NO_AUTH, -EPERM},
1253 {CMD_NOT_EXIST, -EOPNOTSUPP},
1254 {CMD_CRQ_FULL, -EXFULL},
1255 {CMD_NEXT_ERR, -ENOSR},
1256 {CMD_NOT_EXEC, -ENOTBLK},
1257 {CMD_PARA_ERR, -EINVAL},
1258 {CMD_RESULT_ERR, -ERANGE},
1259 {CMD_TIMEOUT, -ETIME},
1260 {CMD_HILINK_ERR, -ENOLINK},
1261 {CMD_INFO_ILLEGAL, -ENXIO},
1262 {CMD_INVALID, -EBADR},
1263 };
1264 u16 i;
1265
1266 for (i = 0; i < ARRAY_SIZE(errcode_table); i++)
1267 if (desc_ret == errcode_table[i].return_status)
1268 return errcode_table[i].errno;
1269 return -EIO;
1270 }
1271
__hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1272 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1273 struct hns_roce_cmq_desc *desc, int num)
1274 {
1275 struct hns_roce_v2_priv *priv = hr_dev->priv;
1276 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1277 u32 timeout = 0;
1278 u16 desc_ret;
1279 u32 tail;
1280 int ret;
1281 int i;
1282
1283 spin_lock_bh(&csq->lock);
1284
1285 tail = csq->head;
1286
1287 for (i = 0; i < num; i++) {
1288 csq->desc[csq->head++] = desc[i];
1289 if (csq->head == csq->desc_num)
1290 csq->head = 0;
1291 }
1292
1293 /* Write to hardware */
1294 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1295
1296 do {
1297 if (hns_roce_cmq_csq_done(hr_dev))
1298 break;
1299 udelay(1);
1300 } while (++timeout < priv->cmq.tx_timeout);
1301
1302 if (hns_roce_cmq_csq_done(hr_dev)) {
1303 ret = 0;
1304 for (i = 0; i < num; i++) {
1305 /* check the result of hardware write back */
1306 desc[i] = csq->desc[tail++];
1307 if (tail == csq->desc_num)
1308 tail = 0;
1309
1310 desc_ret = le16_to_cpu(desc[i].retval);
1311 if (likely(desc_ret == CMD_EXEC_SUCCESS))
1312 continue;
1313
1314 dev_err_ratelimited(hr_dev->dev,
1315 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n",
1316 desc->opcode, desc_ret);
1317 ret = hns_roce_cmd_err_convert_errno(desc_ret);
1318 }
1319 } else {
1320 /* FW/HW reset or incorrect number of desc */
1321 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1322 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
1323 csq->head, tail);
1324 csq->head = tail;
1325
1326 update_cmdq_status(hr_dev);
1327
1328 ret = -EAGAIN;
1329 }
1330
1331 spin_unlock_bh(&csq->lock);
1332
1333 return ret;
1334 }
1335
hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1336 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1337 struct hns_roce_cmq_desc *desc, int num)
1338 {
1339 bool busy;
1340 int ret;
1341
1342 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1343 return -EIO;
1344
1345 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1346 return busy ? -EBUSY : 0;
1347
1348 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1349 if (ret) {
1350 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1351 return busy ? -EBUSY : 0;
1352 }
1353
1354 return ret;
1355 }
1356
config_hem_ba_to_hw(struct hns_roce_dev * hr_dev,dma_addr_t base_addr,u8 cmd,unsigned long tag)1357 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1358 dma_addr_t base_addr, u8 cmd, unsigned long tag)
1359 {
1360 struct hns_roce_cmd_mailbox *mbox;
1361 int ret;
1362
1363 mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1364 if (IS_ERR(mbox))
1365 return PTR_ERR(mbox);
1366
1367 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1368 hns_roce_free_cmd_mailbox(hr_dev, mbox);
1369 return ret;
1370 }
1371
hns_roce_cmq_query_hw_info(struct hns_roce_dev * hr_dev)1372 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1373 {
1374 struct hns_roce_query_version *resp;
1375 struct hns_roce_cmq_desc desc;
1376 int ret;
1377
1378 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1379 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1380 if (ret)
1381 return ret;
1382
1383 resp = (struct hns_roce_query_version *)desc.data;
1384 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1385 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1386
1387 return 0;
1388 }
1389
func_clr_hw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1390 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1391 struct hnae3_handle *handle)
1392 {
1393 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1394 unsigned long end;
1395
1396 hr_dev->dis_db = true;
1397
1398 dev_warn(hr_dev->dev,
1399 "func clear is pending, device in resetting state.\n");
1400 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1401 while (end) {
1402 if (!ops->get_hw_reset_stat(handle)) {
1403 hr_dev->is_reset = true;
1404 dev_info(hr_dev->dev,
1405 "func clear success after reset.\n");
1406 return;
1407 }
1408 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1409 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1410 }
1411
1412 dev_warn(hr_dev->dev, "func clear failed.\n");
1413 }
1414
func_clr_sw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1415 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1416 struct hnae3_handle *handle)
1417 {
1418 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1419 unsigned long end;
1420
1421 hr_dev->dis_db = true;
1422
1423 dev_warn(hr_dev->dev,
1424 "func clear is pending, device in resetting state.\n");
1425 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1426 while (end) {
1427 if (ops->ae_dev_reset_cnt(handle) !=
1428 hr_dev->reset_cnt) {
1429 hr_dev->is_reset = true;
1430 dev_info(hr_dev->dev,
1431 "func clear success after sw reset\n");
1432 return;
1433 }
1434 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1435 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1436 }
1437
1438 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n");
1439 }
1440
hns_roce_func_clr_rst_proc(struct hns_roce_dev * hr_dev,int retval,int flag)1441 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1442 int flag)
1443 {
1444 struct hns_roce_v2_priv *priv = hr_dev->priv;
1445 struct hnae3_handle *handle = priv->handle;
1446 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1447
1448 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1449 hr_dev->dis_db = true;
1450 hr_dev->is_reset = true;
1451 dev_info(hr_dev->dev, "func clear success after reset.\n");
1452 return;
1453 }
1454
1455 if (ops->get_hw_reset_stat(handle)) {
1456 func_clr_hw_resetting_state(hr_dev, handle);
1457 return;
1458 }
1459
1460 if (ops->ae_dev_resetting(handle) &&
1461 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1462 func_clr_sw_resetting_state(hr_dev, handle);
1463 return;
1464 }
1465
1466 if (retval && !flag)
1467 dev_warn(hr_dev->dev,
1468 "func clear read failed, ret = %d.\n", retval);
1469
1470 dev_warn(hr_dev->dev, "func clear failed.\n");
1471 }
1472
__hns_roce_function_clear(struct hns_roce_dev * hr_dev,int vf_id)1473 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1474 {
1475 bool fclr_write_fail_flag = false;
1476 struct hns_roce_func_clear *resp;
1477 struct hns_roce_cmq_desc desc;
1478 unsigned long end;
1479 int ret = 0;
1480
1481 if (check_device_is_in_reset(hr_dev))
1482 goto out;
1483
1484 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1485 resp = (struct hns_roce_func_clear *)desc.data;
1486 resp->rst_funcid_en = cpu_to_le32(vf_id);
1487
1488 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1489 if (ret) {
1490 fclr_write_fail_flag = true;
1491 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n",
1492 ret);
1493 goto out;
1494 }
1495
1496 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1497 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1498 while (end) {
1499 if (check_device_is_in_reset(hr_dev))
1500 goto out;
1501 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1502 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1503
1504 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1505 true);
1506
1507 resp->rst_funcid_en = cpu_to_le32(vf_id);
1508 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1509 if (ret)
1510 continue;
1511
1512 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
1513 if (vf_id == 0)
1514 hr_dev->is_reset = true;
1515 return;
1516 }
1517 }
1518
1519 out:
1520 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1521 }
1522
hns_roce_free_vf_resource(struct hns_roce_dev * hr_dev,int vf_id)1523 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1524 {
1525 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1526 struct hns_roce_cmq_desc desc[2];
1527 struct hns_roce_cmq_req *req_a;
1528
1529 req_a = (struct hns_roce_cmq_req *)desc[0].data;
1530 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1531 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1532 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1533 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1534
1535 return hns_roce_cmq_send(hr_dev, desc, 2);
1536 }
1537
hns_roce_function_clear(struct hns_roce_dev * hr_dev)1538 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1539 {
1540 int ret;
1541 int i;
1542
1543 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1544 return;
1545
1546 for (i = hr_dev->func_num - 1; i >= 0; i--) {
1547 __hns_roce_function_clear(hr_dev, i);
1548
1549 if (i == 0)
1550 continue;
1551
1552 ret = hns_roce_free_vf_resource(hr_dev, i);
1553 if (ret)
1554 ibdev_err(&hr_dev->ib_dev,
1555 "failed to free vf resource, vf_id = %d, ret = %d.\n",
1556 i, ret);
1557 }
1558 }
1559
hns_roce_clear_extdb_list_info(struct hns_roce_dev * hr_dev)1560 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1561 {
1562 struct hns_roce_cmq_desc desc;
1563 int ret;
1564
1565 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1566 false);
1567 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1568 if (ret)
1569 ibdev_err(&hr_dev->ib_dev,
1570 "failed to clear extended doorbell info, ret = %d.\n",
1571 ret);
1572
1573 return ret;
1574 }
1575
hns_roce_query_fw_ver(struct hns_roce_dev * hr_dev)1576 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1577 {
1578 struct hns_roce_query_fw_info *resp;
1579 struct hns_roce_cmq_desc desc;
1580 int ret;
1581
1582 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1583 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1584 if (ret)
1585 return ret;
1586
1587 resp = (struct hns_roce_query_fw_info *)desc.data;
1588 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1589
1590 return 0;
1591 }
1592
hns_roce_query_func_info(struct hns_roce_dev * hr_dev)1593 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1594 {
1595 struct hns_roce_cmq_desc desc;
1596 int ret;
1597
1598 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
1599 hr_dev->func_num = 1;
1600 return 0;
1601 }
1602
1603 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1604 true);
1605 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1606 if (ret) {
1607 hr_dev->func_num = 1;
1608 return ret;
1609 }
1610
1611 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1612 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1613
1614 return 0;
1615 }
1616
hns_roce_hw_v2_query_counter(struct hns_roce_dev * hr_dev,u64 * stats,u32 port,int * num_counters)1617 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev,
1618 u64 *stats, u32 port, int *num_counters)
1619 {
1620 #define CNT_PER_DESC 3
1621 struct hns_roce_cmq_desc *desc;
1622 int bd_idx, cnt_idx;
1623 __le64 *cnt_data;
1624 int desc_num;
1625 int ret;
1626 int i;
1627
1628 if (port > hr_dev->caps.num_ports)
1629 return -EINVAL;
1630
1631 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC);
1632 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL);
1633 if (!desc)
1634 return -ENOMEM;
1635
1636 for (i = 0; i < desc_num; i++) {
1637 hns_roce_cmq_setup_basic_desc(&desc[i],
1638 HNS_ROCE_OPC_QUERY_COUNTER, true);
1639 if (i != desc_num - 1)
1640 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1641 }
1642
1643 ret = hns_roce_cmq_send(hr_dev, desc, desc_num);
1644 if (ret) {
1645 ibdev_err(&hr_dev->ib_dev,
1646 "failed to get counter, ret = %d.\n", ret);
1647 goto err_out;
1648 }
1649
1650 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) {
1651 bd_idx = i / CNT_PER_DESC;
1652 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC &&
1653 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT)))
1654 break;
1655
1656 cnt_data = (__le64 *)&desc[bd_idx].data[0];
1657 cnt_idx = i % CNT_PER_DESC;
1658 stats[i] = le64_to_cpu(cnt_data[cnt_idx]);
1659 }
1660 *num_counters = i;
1661
1662 err_out:
1663 kfree(desc);
1664 return ret;
1665 }
1666
hns_roce_config_global_param(struct hns_roce_dev * hr_dev)1667 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1668 {
1669 struct hns_roce_cmq_desc desc;
1670 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1671 u32 clock_cycles_of_1us;
1672
1673 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1674 false);
1675
1676 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
1677 clock_cycles_of_1us = HNS_ROCE_1NS_CFG;
1678 else
1679 clock_cycles_of_1us = HNS_ROCE_1US_CFG;
1680
1681 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us);
1682 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1683
1684 return hns_roce_cmq_send(hr_dev, &desc, 1);
1685 }
1686
load_func_res_caps(struct hns_roce_dev * hr_dev,bool is_vf)1687 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1688 {
1689 struct hns_roce_cmq_desc desc[2];
1690 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1691 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1692 struct hns_roce_caps *caps = &hr_dev->caps;
1693 enum hns_roce_opcode_type opcode;
1694 u32 func_num;
1695 int ret;
1696
1697 if (is_vf) {
1698 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1699 func_num = 1;
1700 } else {
1701 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1702 func_num = hr_dev->func_num;
1703 }
1704
1705 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1706 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1707 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1708
1709 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1710 if (ret)
1711 return ret;
1712
1713 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1714 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1715 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1716 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1717 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1718 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1719 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1720 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1721
1722 if (is_vf) {
1723 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1724 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1725 func_num;
1726 } else {
1727 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1728 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1729 func_num;
1730 }
1731
1732 return 0;
1733 }
1734
load_pf_timer_res_caps(struct hns_roce_dev * hr_dev)1735 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1736 {
1737 struct hns_roce_cmq_desc desc;
1738 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1739 struct hns_roce_caps *caps = &hr_dev->caps;
1740 int ret;
1741
1742 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1743 true);
1744
1745 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1746 if (ret)
1747 return ret;
1748
1749 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1750 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1751
1752 return 0;
1753 }
1754
hns_roce_query_pf_resource(struct hns_roce_dev * hr_dev)1755 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1756 {
1757 struct device *dev = hr_dev->dev;
1758 int ret;
1759
1760 ret = load_func_res_caps(hr_dev, false);
1761 if (ret) {
1762 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret);
1763 return ret;
1764 }
1765
1766 ret = load_pf_timer_res_caps(hr_dev);
1767 if (ret)
1768 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1769 ret);
1770
1771 return ret;
1772 }
1773
hns_roce_query_vf_resource(struct hns_roce_dev * hr_dev)1774 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1775 {
1776 struct device *dev = hr_dev->dev;
1777 int ret;
1778
1779 ret = load_func_res_caps(hr_dev, true);
1780 if (ret)
1781 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret);
1782
1783 return ret;
1784 }
1785
__hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev,u32 vf_id)1786 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1787 u32 vf_id)
1788 {
1789 struct hns_roce_vf_switch *swt;
1790 struct hns_roce_cmq_desc desc;
1791 int ret;
1792
1793 swt = (struct hns_roce_vf_switch *)desc.data;
1794 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1795 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1796 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id);
1797 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1798 if (ret)
1799 return ret;
1800
1801 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1802 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1803 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK);
1804 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK);
1805 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD);
1806
1807 return hns_roce_cmq_send(hr_dev, &desc, 1);
1808 }
1809
hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev)1810 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1811 {
1812 u32 vf_id;
1813 int ret;
1814
1815 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1816 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1817 if (ret)
1818 return ret;
1819 }
1820 return 0;
1821 }
1822
config_vf_hem_resource(struct hns_roce_dev * hr_dev,int vf_id)1823 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1824 {
1825 struct hns_roce_cmq_desc desc[2];
1826 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1827 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1828 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1829 struct hns_roce_caps *caps = &hr_dev->caps;
1830
1831 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1832 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1833 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1834
1835 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1836
1837 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1838 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1839 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1840 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1841 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1842 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1843 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1844 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
1845 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
1846 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
1847 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
1848 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
1849 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
1850 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
1851
1852 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1853 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
1854 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
1855 vf_id * caps->gmv_bt_num);
1856 } else {
1857 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
1858 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
1859 vf_id * caps->sgid_bt_num);
1860 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
1861 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
1862 vf_id * caps->smac_bt_num);
1863 }
1864
1865 return hns_roce_cmq_send(hr_dev, desc, 2);
1866 }
1867
hns_roce_alloc_vf_resource(struct hns_roce_dev * hr_dev)1868 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1869 {
1870 u32 func_num = max_t(u32, 1, hr_dev->func_num);
1871 u32 vf_id;
1872 int ret;
1873
1874 for (vf_id = 0; vf_id < func_num; vf_id++) {
1875 ret = config_vf_hem_resource(hr_dev, vf_id);
1876 if (ret) {
1877 dev_err(hr_dev->dev,
1878 "failed to config vf-%u hem res, ret = %d.\n",
1879 vf_id, ret);
1880 return ret;
1881 }
1882 }
1883
1884 return 0;
1885 }
1886
hns_roce_v2_set_bt(struct hns_roce_dev * hr_dev)1887 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1888 {
1889 struct hns_roce_cmq_desc desc;
1890 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1891 struct hns_roce_caps *caps = &hr_dev->caps;
1892
1893 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1894
1895 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
1896 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1897 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
1898 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1899 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
1900 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
1901
1902 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
1903 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1904 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
1905 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1906 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
1907 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
1908
1909 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
1910 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1911 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
1912 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1913 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
1914 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
1915
1916 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
1917 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1918 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
1919 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1920 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
1921 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
1922
1923 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
1924 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1925 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
1926 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1927 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
1928 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
1929
1930 return hns_roce_cmq_send(hr_dev, &desc, 1);
1931 }
1932
calc_pg_sz(u32 obj_num,u32 obj_size,u32 hop_num,u32 ctx_bt_num,u32 * buf_page_size,u32 * bt_page_size,u32 hem_type)1933 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
1934 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
1935 {
1936 u64 obj_per_chunk;
1937 u64 bt_chunk_size = PAGE_SIZE;
1938 u64 buf_chunk_size = PAGE_SIZE;
1939 u64 obj_per_chunk_default = buf_chunk_size / obj_size;
1940
1941 *buf_page_size = 0;
1942 *bt_page_size = 0;
1943
1944 switch (hop_num) {
1945 case 3:
1946 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1947 (bt_chunk_size / BA_BYTE_LEN) *
1948 (bt_chunk_size / BA_BYTE_LEN) *
1949 obj_per_chunk_default;
1950 break;
1951 case 2:
1952 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1953 (bt_chunk_size / BA_BYTE_LEN) *
1954 obj_per_chunk_default;
1955 break;
1956 case 1:
1957 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1958 obj_per_chunk_default;
1959 break;
1960 case HNS_ROCE_HOP_NUM_0:
1961 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
1962 break;
1963 default:
1964 pr_err("table %u not support hop_num = %u!\n", hem_type,
1965 hop_num);
1966 return;
1967 }
1968
1969 if (hem_type >= HEM_TYPE_MTT)
1970 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1971 else
1972 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1973 }
1974
set_hem_page_size(struct hns_roce_dev * hr_dev)1975 static void set_hem_page_size(struct hns_roce_dev *hr_dev)
1976 {
1977 struct hns_roce_caps *caps = &hr_dev->caps;
1978
1979 /* EQ */
1980 caps->eqe_ba_pg_sz = 0;
1981 caps->eqe_buf_pg_sz = 0;
1982
1983 /* Link Table */
1984 caps->llm_buf_pg_sz = 0;
1985
1986 /* MR */
1987 caps->mpt_ba_pg_sz = 0;
1988 caps->mpt_buf_pg_sz = 0;
1989 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
1990 caps->pbl_buf_pg_sz = 0;
1991 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
1992 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
1993 HEM_TYPE_MTPT);
1994
1995 /* QP */
1996 caps->qpc_ba_pg_sz = 0;
1997 caps->qpc_buf_pg_sz = 0;
1998 caps->qpc_timer_ba_pg_sz = 0;
1999 caps->qpc_timer_buf_pg_sz = 0;
2000 caps->sccc_ba_pg_sz = 0;
2001 caps->sccc_buf_pg_sz = 0;
2002 caps->mtt_ba_pg_sz = 0;
2003 caps->mtt_buf_pg_sz = 0;
2004 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2005 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2006 HEM_TYPE_QPC);
2007
2008 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2009 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2010 caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2011 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2012
2013 /* CQ */
2014 caps->cqc_ba_pg_sz = 0;
2015 caps->cqc_buf_pg_sz = 0;
2016 caps->cqc_timer_ba_pg_sz = 0;
2017 caps->cqc_timer_buf_pg_sz = 0;
2018 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2019 caps->cqe_buf_pg_sz = 0;
2020 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2021 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2022 HEM_TYPE_CQC);
2023 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2024 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2025
2026 /* SRQ */
2027 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2028 caps->srqc_ba_pg_sz = 0;
2029 caps->srqc_buf_pg_sz = 0;
2030 caps->srqwqe_ba_pg_sz = 0;
2031 caps->srqwqe_buf_pg_sz = 0;
2032 caps->idx_ba_pg_sz = 0;
2033 caps->idx_buf_pg_sz = 0;
2034 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2035 caps->srqc_hop_num, caps->srqc_bt_num,
2036 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2037 HEM_TYPE_SRQC);
2038 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2039 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2040 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2041 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2042 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2043 &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2044 }
2045
2046 /* GMV */
2047 caps->gmv_ba_pg_sz = 0;
2048 caps->gmv_buf_pg_sz = 0;
2049 }
2050
2051 /* Apply all loaded caps before setting to hardware */
apply_func_caps(struct hns_roce_dev * hr_dev)2052 static void apply_func_caps(struct hns_roce_dev *hr_dev)
2053 {
2054 struct hns_roce_caps *caps = &hr_dev->caps;
2055 struct hns_roce_v2_priv *priv = hr_dev->priv;
2056
2057 /* The following configurations don't need to be got from firmware. */
2058 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2059 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2060 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2061
2062 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2063 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2064 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2065
2066 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2067 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2068
2069 if (!caps->num_comp_vectors)
2070 caps->num_comp_vectors =
2071 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM,
2072 (u32)priv->handle->rinfo.num_vectors -
2073 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));
2074
2075 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2076 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
2077 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2078 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2079
2080 /* The following configurations will be overwritten */
2081 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2082 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2083 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2084
2085 /* The following configurations are not got from firmware */
2086 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2087
2088 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2089 caps->gid_table_len[0] = caps->gmv_bt_num *
2090 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz);
2091
2092 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE /
2093 caps->gmv_entry_sz);
2094 } else {
2095 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2096
2097 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
2098 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2099 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2100 caps->gid_table_len[0] /= func_num;
2101 }
2102
2103 if (hr_dev->is_vf) {
2104 caps->default_aeq_arm_st = 0x3;
2105 caps->default_ceq_arm_st = 0x3;
2106 caps->default_ceq_max_cnt = 0x1;
2107 caps->default_ceq_period = 0x10;
2108 caps->default_aeq_max_cnt = 0x1;
2109 caps->default_aeq_period = 0x10;
2110 }
2111
2112 set_hem_page_size(hr_dev);
2113 }
2114
hns_roce_query_caps(struct hns_roce_dev * hr_dev)2115 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev)
2116 {
2117 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
2118 struct hns_roce_caps *caps = &hr_dev->caps;
2119 struct hns_roce_query_pf_caps_a *resp_a;
2120 struct hns_roce_query_pf_caps_b *resp_b;
2121 struct hns_roce_query_pf_caps_c *resp_c;
2122 struct hns_roce_query_pf_caps_d *resp_d;
2123 struct hns_roce_query_pf_caps_e *resp_e;
2124 enum hns_roce_opcode_type cmd;
2125 int ctx_hop_num;
2126 int pbl_hop_num;
2127 int ret;
2128 int i;
2129
2130 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM :
2131 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM;
2132
2133 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
2134 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true);
2135 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
2136 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2137 else
2138 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2139 }
2140
2141 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
2142 if (ret)
2143 return ret;
2144
2145 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2146 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2147 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2148 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2149 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2150
2151 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
2152 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
2153 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
2154 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
2155 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2156 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
2157 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2158 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
2159 caps->num_other_vectors = resp_a->num_other_vectors;
2160 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
2161 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
2162
2163 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
2164 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
2165 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
2166 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
2167 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
2168 caps->idx_entry_sz = resp_b->idx_entry_sz;
2169 caps->sccc_sz = resp_b->sccc_sz;
2170 caps->max_mtu = resp_b->max_mtu;
2171 caps->min_cqes = resp_b->min_cqes;
2172 caps->min_wqes = resp_b->min_wqes;
2173 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
2174 caps->pkey_table_len[0] = resp_b->pkey_table_len;
2175 caps->phy_num_uars = resp_b->phy_num_uars;
2176 ctx_hop_num = resp_b->ctx_hop_num;
2177 pbl_hop_num = resp_b->pbl_hop_num;
2178
2179 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
2180
2181 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
2182 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2183 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2184
2185 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
2186 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
2187 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
2188 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS);
2189 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
2190 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
2191 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
2192 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2193 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2194
2195 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
2196 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE);
2197 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2198 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
2199 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
2200 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
2201 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
2202 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
2203 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
2204 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
2205
2206 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
2207 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
2208 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
2209 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS);
2210 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
2211 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
2212
2213 caps->qpc_hop_num = ctx_hop_num;
2214 caps->sccc_hop_num = ctx_hop_num;
2215 caps->srqc_hop_num = ctx_hop_num;
2216 caps->cqc_hop_num = ctx_hop_num;
2217 caps->mpt_hop_num = ctx_hop_num;
2218 caps->mtt_hop_num = pbl_hop_num;
2219 caps->cqe_hop_num = pbl_hop_num;
2220 caps->srqwqe_hop_num = pbl_hop_num;
2221 caps->idx_hop_num = pbl_hop_num;
2222 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
2223 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
2224 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
2225
2226 if (!(caps->page_size_cap & PAGE_SIZE))
2227 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
2228
2229 if (!hr_dev->is_vf) {
2230 caps->cqe_sz = resp_a->cqe_sz;
2231 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz);
2232 caps->default_aeq_arm_st =
2233 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
2234 caps->default_ceq_arm_st =
2235 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
2236 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2237 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2238 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2239 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2240 }
2241
2242 return 0;
2243 }
2244
config_hem_entry_size(struct hns_roce_dev * hr_dev,u32 type,u32 val)2245 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2246 {
2247 struct hns_roce_cmq_desc desc;
2248 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2249
2250 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2251 false);
2252
2253 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2254 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2255
2256 return hns_roce_cmq_send(hr_dev, &desc, 1);
2257 }
2258
hns_roce_config_entry_size(struct hns_roce_dev * hr_dev)2259 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2260 {
2261 struct hns_roce_caps *caps = &hr_dev->caps;
2262 int ret;
2263
2264 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2265 return 0;
2266
2267 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2268 caps->qpc_sz);
2269 if (ret) {
2270 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2271 return ret;
2272 }
2273
2274 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2275 caps->sccc_sz);
2276 if (ret)
2277 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2278
2279 return ret;
2280 }
2281
hns_roce_v2_vf_profile(struct hns_roce_dev * hr_dev)2282 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2283 {
2284 struct device *dev = hr_dev->dev;
2285 int ret;
2286
2287 hr_dev->func_num = 1;
2288
2289 ret = hns_roce_query_caps(hr_dev);
2290 if (ret) {
2291 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret);
2292 return ret;
2293 }
2294
2295 ret = hns_roce_query_vf_resource(hr_dev);
2296 if (ret) {
2297 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2298 return ret;
2299 }
2300
2301 apply_func_caps(hr_dev);
2302
2303 ret = hns_roce_v2_set_bt(hr_dev);
2304 if (ret)
2305 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2306
2307 return ret;
2308 }
2309
hns_roce_v2_pf_profile(struct hns_roce_dev * hr_dev)2310 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2311 {
2312 struct device *dev = hr_dev->dev;
2313 int ret;
2314
2315 ret = hns_roce_query_func_info(hr_dev);
2316 if (ret) {
2317 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2318 return ret;
2319 }
2320
2321 ret = hns_roce_config_global_param(hr_dev);
2322 if (ret) {
2323 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2324 return ret;
2325 }
2326
2327 ret = hns_roce_set_vf_switch_param(hr_dev);
2328 if (ret) {
2329 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2330 return ret;
2331 }
2332
2333 ret = hns_roce_query_caps(hr_dev);
2334 if (ret) {
2335 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret);
2336 return ret;
2337 }
2338
2339 ret = hns_roce_query_pf_resource(hr_dev);
2340 if (ret) {
2341 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2342 return ret;
2343 }
2344
2345 apply_func_caps(hr_dev);
2346
2347 ret = hns_roce_alloc_vf_resource(hr_dev);
2348 if (ret) {
2349 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2350 return ret;
2351 }
2352
2353 ret = hns_roce_v2_set_bt(hr_dev);
2354 if (ret) {
2355 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2356 return ret;
2357 }
2358
2359 /* Configure the size of QPC, SCCC, etc. */
2360 return hns_roce_config_entry_size(hr_dev);
2361 }
2362
hns_roce_v2_profile(struct hns_roce_dev * hr_dev)2363 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2364 {
2365 struct device *dev = hr_dev->dev;
2366 int ret;
2367
2368 ret = hns_roce_cmq_query_hw_info(hr_dev);
2369 if (ret) {
2370 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2371 return ret;
2372 }
2373
2374 ret = hns_roce_query_fw_ver(hr_dev);
2375 if (ret) {
2376 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2377 return ret;
2378 }
2379
2380 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2381 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2382
2383 if (hr_dev->is_vf)
2384 return hns_roce_v2_vf_profile(hr_dev);
2385 else
2386 return hns_roce_v2_pf_profile(hr_dev);
2387 }
2388
config_llm_table(struct hns_roce_buf * data_buf,void * cfg_buf)2389 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2390 {
2391 u32 i, next_ptr, page_num;
2392 __le64 *entry = cfg_buf;
2393 dma_addr_t addr;
2394 u64 val;
2395
2396 page_num = data_buf->npages;
2397 for (i = 0; i < page_num; i++) {
2398 addr = hns_roce_buf_page(data_buf, i);
2399 if (i == (page_num - 1))
2400 next_ptr = 0;
2401 else
2402 next_ptr = i + 1;
2403
2404 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2405 entry[i] = cpu_to_le64(val);
2406 }
2407 }
2408
set_llm_cfg_to_hw(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * table)2409 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2410 struct hns_roce_link_table *table)
2411 {
2412 struct hns_roce_cmq_desc desc[2];
2413 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2414 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2415 struct hns_roce_buf *buf = table->buf;
2416 enum hns_roce_opcode_type opcode;
2417 dma_addr_t addr;
2418
2419 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2420 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2421 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2422 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2423
2424 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2425 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2426 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2427 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2428 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2429
2430 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2431 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2432 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2433 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2434 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2435
2436 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2437 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2438 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2439 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2440
2441 return hns_roce_cmq_send(hr_dev, desc, 2);
2442 }
2443
2444 static struct hns_roce_link_table *
alloc_link_table_buf(struct hns_roce_dev * hr_dev)2445 alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2446 {
2447 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num;
2448 struct hns_roce_v2_priv *priv = hr_dev->priv;
2449 struct hns_roce_link_table *link_tbl;
2450 u32 pg_shift, size, min_size;
2451
2452 link_tbl = &priv->ext_llm;
2453 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2454 size = hr_dev->caps.num_qps * hr_dev->func_num *
2455 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2456 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift;
2457
2458 /* Alloc data table */
2459 size = max(size, min_size);
2460 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2461 if (IS_ERR(link_tbl->buf))
2462 return ERR_PTR(-ENOMEM);
2463
2464 /* Alloc config table */
2465 size = link_tbl->buf->npages * sizeof(u64);
2466 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2467 &link_tbl->table.map,
2468 GFP_KERNEL);
2469 if (!link_tbl->table.buf) {
2470 hns_roce_buf_free(hr_dev, link_tbl->buf);
2471 return ERR_PTR(-ENOMEM);
2472 }
2473
2474 return link_tbl;
2475 }
2476
free_link_table_buf(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * tbl)2477 static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2478 struct hns_roce_link_table *tbl)
2479 {
2480 if (tbl->buf) {
2481 u32 size = tbl->buf->npages * sizeof(u64);
2482
2483 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2484 tbl->table.map);
2485 }
2486
2487 hns_roce_buf_free(hr_dev, tbl->buf);
2488 }
2489
hns_roce_init_link_table(struct hns_roce_dev * hr_dev)2490 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2491 {
2492 struct hns_roce_link_table *link_tbl;
2493 int ret;
2494
2495 link_tbl = alloc_link_table_buf(hr_dev);
2496 if (IS_ERR(link_tbl))
2497 return -ENOMEM;
2498
2499 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2500 ret = -EINVAL;
2501 goto err_alloc;
2502 }
2503
2504 config_llm_table(link_tbl->buf, link_tbl->table.buf);
2505 ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2506 if (ret)
2507 goto err_alloc;
2508
2509 return 0;
2510
2511 err_alloc:
2512 free_link_table_buf(hr_dev, link_tbl);
2513 return ret;
2514 }
2515
hns_roce_free_link_table(struct hns_roce_dev * hr_dev)2516 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2517 {
2518 struct hns_roce_v2_priv *priv = hr_dev->priv;
2519
2520 free_link_table_buf(hr_dev, &priv->ext_llm);
2521 }
2522
free_dip_list(struct hns_roce_dev * hr_dev)2523 static void free_dip_list(struct hns_roce_dev *hr_dev)
2524 {
2525 struct hns_roce_dip *hr_dip;
2526 struct hns_roce_dip *tmp;
2527 unsigned long flags;
2528
2529 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
2530
2531 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) {
2532 list_del(&hr_dip->node);
2533 kfree(hr_dip);
2534 }
2535
2536 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
2537 }
2538
free_mr_init_pd(struct hns_roce_dev * hr_dev)2539 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev)
2540 {
2541 struct hns_roce_v2_priv *priv = hr_dev->priv;
2542 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2543 struct ib_device *ibdev = &hr_dev->ib_dev;
2544 struct hns_roce_pd *hr_pd;
2545 struct ib_pd *pd;
2546
2547 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL);
2548 if (ZERO_OR_NULL_PTR(hr_pd))
2549 return NULL;
2550 pd = &hr_pd->ibpd;
2551 pd->device = ibdev;
2552
2553 if (hns_roce_alloc_pd(pd, NULL)) {
2554 ibdev_err(ibdev, "failed to create pd for free mr.\n");
2555 kfree(hr_pd);
2556 return NULL;
2557 }
2558 free_mr->rsv_pd = to_hr_pd(pd);
2559 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev;
2560 free_mr->rsv_pd->ibpd.uobject = NULL;
2561 free_mr->rsv_pd->ibpd.__internal_mr = NULL;
2562 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0);
2563
2564 return pd;
2565 }
2566
free_mr_init_cq(struct hns_roce_dev * hr_dev)2567 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev)
2568 {
2569 struct hns_roce_v2_priv *priv = hr_dev->priv;
2570 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2571 struct ib_device *ibdev = &hr_dev->ib_dev;
2572 struct ib_cq_init_attr cq_init_attr = {};
2573 struct hns_roce_cq *hr_cq;
2574 struct ib_cq *cq;
2575
2576 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
2577
2578 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL);
2579 if (ZERO_OR_NULL_PTR(hr_cq))
2580 return NULL;
2581
2582 cq = &hr_cq->ib_cq;
2583 cq->device = ibdev;
2584
2585 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) {
2586 ibdev_err(ibdev, "failed to create cq for free mr.\n");
2587 kfree(hr_cq);
2588 return NULL;
2589 }
2590 free_mr->rsv_cq = to_hr_cq(cq);
2591 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev;
2592 free_mr->rsv_cq->ib_cq.uobject = NULL;
2593 free_mr->rsv_cq->ib_cq.comp_handler = NULL;
2594 free_mr->rsv_cq->ib_cq.event_handler = NULL;
2595 free_mr->rsv_cq->ib_cq.cq_context = NULL;
2596 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0);
2597
2598 return cq;
2599 }
2600
free_mr_init_qp(struct hns_roce_dev * hr_dev,struct ib_cq * cq,struct ib_qp_init_attr * init_attr,int i)2601 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq,
2602 struct ib_qp_init_attr *init_attr, int i)
2603 {
2604 struct hns_roce_v2_priv *priv = hr_dev->priv;
2605 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2606 struct ib_device *ibdev = &hr_dev->ib_dev;
2607 struct hns_roce_qp *hr_qp;
2608 struct ib_qp *qp;
2609 int ret;
2610
2611 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
2612 if (ZERO_OR_NULL_PTR(hr_qp))
2613 return -ENOMEM;
2614
2615 qp = &hr_qp->ibqp;
2616 qp->device = ibdev;
2617
2618 ret = hns_roce_create_qp(qp, init_attr, NULL);
2619 if (ret) {
2620 ibdev_err(ibdev, "failed to create qp for free mr.\n");
2621 kfree(hr_qp);
2622 return ret;
2623 }
2624
2625 free_mr->rsv_qp[i] = hr_qp;
2626 free_mr->rsv_qp[i]->ibqp.recv_cq = cq;
2627 free_mr->rsv_qp[i]->ibqp.send_cq = cq;
2628
2629 return 0;
2630 }
2631
free_mr_exit(struct hns_roce_dev * hr_dev)2632 static void free_mr_exit(struct hns_roce_dev *hr_dev)
2633 {
2634 struct hns_roce_v2_priv *priv = hr_dev->priv;
2635 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2636 struct ib_qp *qp;
2637 int i;
2638
2639 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2640 if (free_mr->rsv_qp[i]) {
2641 qp = &free_mr->rsv_qp[i]->ibqp;
2642 hns_roce_v2_destroy_qp(qp, NULL);
2643 kfree(free_mr->rsv_qp[i]);
2644 free_mr->rsv_qp[i] = NULL;
2645 }
2646 }
2647
2648 if (free_mr->rsv_cq) {
2649 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL);
2650 kfree(free_mr->rsv_cq);
2651 free_mr->rsv_cq = NULL;
2652 }
2653
2654 if (free_mr->rsv_pd) {
2655 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL);
2656 kfree(free_mr->rsv_pd);
2657 free_mr->rsv_pd = NULL;
2658 }
2659 }
2660
free_mr_alloc_res(struct hns_roce_dev * hr_dev)2661 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
2662 {
2663 struct hns_roce_v2_priv *priv = hr_dev->priv;
2664 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2665 struct ib_qp_init_attr qp_init_attr = {};
2666 struct ib_pd *pd;
2667 struct ib_cq *cq;
2668 int ret;
2669 int i;
2670
2671 pd = free_mr_init_pd(hr_dev);
2672 if (!pd)
2673 return -ENOMEM;
2674
2675 cq = free_mr_init_cq(hr_dev);
2676 if (!cq) {
2677 ret = -ENOMEM;
2678 goto create_failed_cq;
2679 }
2680
2681 qp_init_attr.qp_type = IB_QPT_RC;
2682 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
2683 qp_init_attr.send_cq = cq;
2684 qp_init_attr.recv_cq = cq;
2685 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2686 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
2687 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
2688 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
2689 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
2690
2691 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i);
2692 if (ret)
2693 goto create_failed_qp;
2694 }
2695
2696 return 0;
2697
2698 create_failed_qp:
2699 for (i--; i >= 0; i--) {
2700 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL);
2701 kfree(free_mr->rsv_qp[i]);
2702 }
2703 hns_roce_destroy_cq(cq, NULL);
2704 kfree(cq);
2705
2706 create_failed_cq:
2707 hns_roce_dealloc_pd(pd, NULL);
2708 kfree(pd);
2709
2710 return ret;
2711 }
2712
free_mr_modify_rsv_qp(struct hns_roce_dev * hr_dev,struct ib_qp_attr * attr,int sl_num)2713 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
2714 struct ib_qp_attr *attr, int sl_num)
2715 {
2716 struct hns_roce_v2_priv *priv = hr_dev->priv;
2717 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2718 struct ib_device *ibdev = &hr_dev->ib_dev;
2719 struct hns_roce_qp *hr_qp;
2720 int loopback;
2721 int mask;
2722 int ret;
2723
2724 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp);
2725 hr_qp->free_mr_en = 1;
2726 hr_qp->ibqp.device = ibdev;
2727 hr_qp->ibqp.qp_type = IB_QPT_RC;
2728
2729 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS;
2730 attr->qp_state = IB_QPS_INIT;
2731 attr->port_num = 1;
2732 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
2733 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2734 IB_QPS_INIT, NULL);
2735 if (ret) {
2736 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n",
2737 ret);
2738 return ret;
2739 }
2740
2741 loopback = hr_dev->loop_idc;
2742 /* Set qpc lbi = 1 incidate loopback IO */
2743 hr_dev->loop_idc = 1;
2744
2745 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN |
2746 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
2747 attr->qp_state = IB_QPS_RTR;
2748 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2749 attr->path_mtu = IB_MTU_256;
2750 attr->dest_qp_num = hr_qp->qpn;
2751 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2752
2753 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
2754
2755 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2756 IB_QPS_RTR, NULL);
2757 hr_dev->loop_idc = loopback;
2758 if (ret) {
2759 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
2760 ret);
2761 return ret;
2762 }
2763
2764 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT |
2765 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC;
2766 attr->qp_state = IB_QPS_RTS;
2767 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2768 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
2769 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
2770 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR,
2771 IB_QPS_RTS, NULL);
2772 if (ret)
2773 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
2774 ret);
2775
2776 return ret;
2777 }
2778
free_mr_modify_qp(struct hns_roce_dev * hr_dev)2779 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
2780 {
2781 struct hns_roce_v2_priv *priv = hr_dev->priv;
2782 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2783 struct ib_qp_attr attr = {};
2784 int ret;
2785 int i;
2786
2787 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
2788 rdma_ah_set_static_rate(&attr.ah_attr, 3);
2789 rdma_ah_set_port_num(&attr.ah_attr, 1);
2790
2791 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2792 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
2793 if (ret)
2794 return ret;
2795 }
2796
2797 return 0;
2798 }
2799
free_mr_init(struct hns_roce_dev * hr_dev)2800 static int free_mr_init(struct hns_roce_dev *hr_dev)
2801 {
2802 struct hns_roce_v2_priv *priv = hr_dev->priv;
2803 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2804 int ret;
2805
2806 mutex_init(&free_mr->mutex);
2807
2808 ret = free_mr_alloc_res(hr_dev);
2809 if (ret)
2810 return ret;
2811
2812 ret = free_mr_modify_qp(hr_dev);
2813 if (ret)
2814 goto err_modify_qp;
2815
2816 return 0;
2817
2818 err_modify_qp:
2819 free_mr_exit(hr_dev);
2820
2821 return ret;
2822 }
2823
get_hem_table(struct hns_roce_dev * hr_dev)2824 static int get_hem_table(struct hns_roce_dev *hr_dev)
2825 {
2826 unsigned int qpc_count;
2827 unsigned int cqc_count;
2828 unsigned int gmv_count;
2829 int ret;
2830 int i;
2831
2832 /* Alloc memory for source address table buffer space chunk */
2833 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
2834 gmv_count++) {
2835 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
2836 if (ret)
2837 goto err_gmv_failed;
2838 }
2839
2840 if (hr_dev->is_vf)
2841 return 0;
2842
2843 /* Alloc memory for QPC Timer buffer space chunk */
2844 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2845 qpc_count++) {
2846 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2847 qpc_count);
2848 if (ret) {
2849 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2850 goto err_qpc_timer_failed;
2851 }
2852 }
2853
2854 /* Alloc memory for CQC Timer buffer space chunk */
2855 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2856 cqc_count++) {
2857 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2858 cqc_count);
2859 if (ret) {
2860 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2861 goto err_cqc_timer_failed;
2862 }
2863 }
2864
2865 return 0;
2866
2867 err_cqc_timer_failed:
2868 for (i = 0; i < cqc_count; i++)
2869 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2870
2871 err_qpc_timer_failed:
2872 for (i = 0; i < qpc_count; i++)
2873 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2874
2875 err_gmv_failed:
2876 for (i = 0; i < gmv_count; i++)
2877 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2878
2879 return ret;
2880 }
2881
put_hem_table(struct hns_roce_dev * hr_dev)2882 static void put_hem_table(struct hns_roce_dev *hr_dev)
2883 {
2884 int i;
2885
2886 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
2887 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2888
2889 if (hr_dev->is_vf)
2890 return;
2891
2892 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
2893 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2894
2895 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
2896 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2897 }
2898
hns_roce_v2_init(struct hns_roce_dev * hr_dev)2899 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2900 {
2901 int ret;
2902
2903 /* The hns ROCEE requires the extdb info to be cleared before using */
2904 ret = hns_roce_clear_extdb_list_info(hr_dev);
2905 if (ret)
2906 return ret;
2907
2908 ret = get_hem_table(hr_dev);
2909 if (ret)
2910 return ret;
2911
2912 if (hr_dev->is_vf)
2913 return 0;
2914
2915 ret = hns_roce_init_link_table(hr_dev);
2916 if (ret) {
2917 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
2918 goto err_llm_init_failed;
2919 }
2920
2921 return 0;
2922
2923 err_llm_init_failed:
2924 put_hem_table(hr_dev);
2925
2926 return ret;
2927 }
2928
hns_roce_v2_exit(struct hns_roce_dev * hr_dev)2929 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2930 {
2931 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2932 free_mr_exit(hr_dev);
2933
2934 hns_roce_function_clear(hr_dev);
2935
2936 if (!hr_dev->is_vf)
2937 hns_roce_free_link_table(hr_dev);
2938
2939 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09)
2940 free_dip_list(hr_dev);
2941 }
2942
hns_roce_mbox_post(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)2943 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
2944 struct hns_roce_mbox_msg *mbox_msg)
2945 {
2946 struct hns_roce_cmq_desc desc;
2947 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2948
2949 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2950
2951 mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
2952 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
2953 mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
2954 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
2955 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd);
2956 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 |
2957 mbox_msg->token);
2958
2959 return hns_roce_cmq_send(hr_dev, &desc, 1);
2960 }
2961
v2_wait_mbox_complete(struct hns_roce_dev * hr_dev,u32 timeout,u8 * complete_status)2962 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
2963 u8 *complete_status)
2964 {
2965 struct hns_roce_mbox_status *mb_st;
2966 struct hns_roce_cmq_desc desc;
2967 unsigned long end;
2968 int ret = -EBUSY;
2969 u32 status;
2970 bool busy;
2971
2972 mb_st = (struct hns_roce_mbox_status *)desc.data;
2973 end = msecs_to_jiffies(timeout) + jiffies;
2974 while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
2975 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
2976 return -EIO;
2977
2978 status = 0;
2979 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
2980 true);
2981 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
2982 if (!ret) {
2983 status = le32_to_cpu(mb_st->mb_status_hw_run);
2984 /* No pending message exists in ROCEE mbox. */
2985 if (!(status & MB_ST_HW_RUN_M))
2986 break;
2987 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
2988 break;
2989 }
2990
2991 if (time_after(jiffies, end)) {
2992 dev_err_ratelimited(hr_dev->dev,
2993 "failed to wait mbox status 0x%x\n",
2994 status);
2995 return -ETIMEDOUT;
2996 }
2997
2998 cond_resched();
2999 ret = -EBUSY;
3000 }
3001
3002 if (!ret) {
3003 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
3004 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3005 /* Ignore all errors if the mbox is unavailable. */
3006 ret = 0;
3007 *complete_status = MB_ST_COMPLETE_M;
3008 }
3009
3010 return ret;
3011 }
3012
v2_post_mbox(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)3013 static int v2_post_mbox(struct hns_roce_dev *hr_dev,
3014 struct hns_roce_mbox_msg *mbox_msg)
3015 {
3016 u8 status = 0;
3017 int ret;
3018
3019 /* Waiting for the mbox to be idle */
3020 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
3021 &status);
3022 if (unlikely(ret)) {
3023 dev_err_ratelimited(hr_dev->dev,
3024 "failed to check post mbox status = 0x%x, ret = %d.\n",
3025 status, ret);
3026 return ret;
3027 }
3028
3029 /* Post new message to mbox */
3030 ret = hns_roce_mbox_post(hr_dev, mbox_msg);
3031 if (ret)
3032 dev_err_ratelimited(hr_dev->dev,
3033 "failed to post mailbox, ret = %d.\n", ret);
3034
3035 return ret;
3036 }
3037
v2_poll_mbox_done(struct hns_roce_dev * hr_dev)3038 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
3039 {
3040 u8 status = 0;
3041 int ret;
3042
3043 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
3044 &status);
3045 if (!ret) {
3046 if (status != MB_ST_COMPLETE_SUCC)
3047 return -EBUSY;
3048 } else {
3049 dev_err_ratelimited(hr_dev->dev,
3050 "failed to check mbox status = 0x%x, ret = %d.\n",
3051 status, ret);
3052 }
3053
3054 return ret;
3055 }
3056
copy_gid(void * dest,const union ib_gid * gid)3057 static void copy_gid(void *dest, const union ib_gid *gid)
3058 {
3059 #define GID_SIZE 4
3060 const union ib_gid *src = gid;
3061 __le32 (*p)[GID_SIZE] = dest;
3062 int i;
3063
3064 if (!gid)
3065 src = &zgid;
3066
3067 for (i = 0; i < GID_SIZE; i++)
3068 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
3069 }
3070
config_sgid_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type)3071 static int config_sgid_table(struct hns_roce_dev *hr_dev,
3072 int gid_index, const union ib_gid *gid,
3073 enum hns_roce_sgid_type sgid_type)
3074 {
3075 struct hns_roce_cmq_desc desc;
3076 struct hns_roce_cfg_sgid_tb *sgid_tb =
3077 (struct hns_roce_cfg_sgid_tb *)desc.data;
3078
3079 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
3080
3081 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index);
3082 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type);
3083
3084 copy_gid(&sgid_tb->vf_sgid_l, gid);
3085
3086 return hns_roce_cmq_send(hr_dev, &desc, 1);
3087 }
3088
config_gmv_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type,const struct ib_gid_attr * attr)3089 static int config_gmv_table(struct hns_roce_dev *hr_dev,
3090 int gid_index, const union ib_gid *gid,
3091 enum hns_roce_sgid_type sgid_type,
3092 const struct ib_gid_attr *attr)
3093 {
3094 struct hns_roce_cmq_desc desc[2];
3095 struct hns_roce_cfg_gmv_tb_a *tb_a =
3096 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
3097 struct hns_roce_cfg_gmv_tb_b *tb_b =
3098 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
3099
3100 u16 vlan_id = VLAN_CFI_MASK;
3101 u8 mac[ETH_ALEN] = {};
3102 int ret;
3103
3104 if (gid) {
3105 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
3106 if (ret)
3107 return ret;
3108 }
3109
3110 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3111 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
3112
3113 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3114
3115 copy_gid(&tb_a->vf_sgid_l, gid);
3116
3117 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type);
3118 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK);
3119 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id);
3120
3121 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
3122
3123 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]);
3124 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index);
3125
3126 return hns_roce_cmq_send(hr_dev, desc, 2);
3127 }
3128
hns_roce_v2_set_gid(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,const struct ib_gid_attr * attr)3129 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
3130 const union ib_gid *gid,
3131 const struct ib_gid_attr *attr)
3132 {
3133 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
3134 int ret;
3135
3136 if (gid) {
3137 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
3138 if (ipv6_addr_v4mapped((void *)gid))
3139 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3140 else
3141 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3142 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3143 sgid_type = GID_TYPE_FLAG_ROCE_V1;
3144 }
3145 }
3146
3147 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3148 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3149 else
3150 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3151
3152 if (ret)
3153 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3154 ret);
3155
3156 return ret;
3157 }
3158
hns_roce_v2_set_mac(struct hns_roce_dev * hr_dev,u8 phy_port,const u8 * addr)3159 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3160 const u8 *addr)
3161 {
3162 struct hns_roce_cmq_desc desc;
3163 struct hns_roce_cfg_smac_tb *smac_tb =
3164 (struct hns_roce_cfg_smac_tb *)desc.data;
3165 u16 reg_smac_h;
3166 u32 reg_smac_l;
3167
3168 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3169
3170 reg_smac_l = *(u32 *)(&addr[0]);
3171 reg_smac_h = *(u16 *)(&addr[4]);
3172
3173 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port);
3174 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h);
3175 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3176
3177 return hns_roce_cmq_send(hr_dev, &desc, 1);
3178 }
3179
set_mtpt_pbl(struct hns_roce_dev * hr_dev,struct hns_roce_v2_mpt_entry * mpt_entry,struct hns_roce_mr * mr)3180 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3181 struct hns_roce_v2_mpt_entry *mpt_entry,
3182 struct hns_roce_mr *mr)
3183 {
3184 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3185 struct ib_device *ibdev = &hr_dev->ib_dev;
3186 dma_addr_t pbl_ba;
3187 int ret;
3188 int i;
3189
3190 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3191 min_t(int, ARRAY_SIZE(pages), mr->npages));
3192 if (ret) {
3193 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret);
3194 return ret;
3195 }
3196
3197 /* Aligned to the hardware address access unit */
3198 for (i = 0; i < ARRAY_SIZE(pages); i++)
3199 pages[i] >>= 6;
3200
3201 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr);
3202
3203 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3204 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
3205 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3206
3207 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3208 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
3209
3210 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3211 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1]));
3212 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3213 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3214
3215 return 0;
3216 }
3217
hns_roce_v2_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr)3218 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3219 void *mb_buf, struct hns_roce_mr *mr)
3220 {
3221 struct hns_roce_v2_mpt_entry *mpt_entry;
3222
3223 mpt_entry = mb_buf;
3224 memset(mpt_entry, 0, sizeof(*mpt_entry));
3225
3226 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3227 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3228
3229 hr_reg_write_bool(mpt_entry, MPT_BIND_EN,
3230 mr->access & IB_ACCESS_MW_BIND);
3231 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3232 mr->access & IB_ACCESS_REMOTE_ATOMIC);
3233 hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3234 mr->access & IB_ACCESS_REMOTE_READ);
3235 hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3236 mr->access & IB_ACCESS_REMOTE_WRITE);
3237 hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3238 mr->access & IB_ACCESS_LOCAL_WRITE);
3239
3240 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3241 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3242 mpt_entry->lkey = cpu_to_le32(mr->key);
3243 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3244 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3245
3246 if (mr->type != MR_TYPE_MR)
3247 hr_reg_enable(mpt_entry, MPT_PA);
3248
3249 if (mr->type == MR_TYPE_DMA)
3250 return 0;
3251
3252 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3253 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3254
3255 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3256 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3257 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3258
3259 return set_mtpt_pbl(hr_dev, mpt_entry, mr);
3260 }
3261
hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev * hr_dev,struct hns_roce_mr * mr,int flags,void * mb_buf)3262 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3263 struct hns_roce_mr *mr, int flags,
3264 void *mb_buf)
3265 {
3266 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3267 u32 mr_access_flags = mr->access;
3268 int ret = 0;
3269
3270 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3271 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3272
3273 if (flags & IB_MR_REREG_ACCESS) {
3274 hr_reg_write(mpt_entry, MPT_BIND_EN,
3275 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
3276 hr_reg_write(mpt_entry, MPT_ATOMIC_EN,
3277 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3278 hr_reg_write(mpt_entry, MPT_RR_EN,
3279 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3280 hr_reg_write(mpt_entry, MPT_RW_EN,
3281 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3282 hr_reg_write(mpt_entry, MPT_LW_EN,
3283 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3284 }
3285
3286 if (flags & IB_MR_REREG_TRANS) {
3287 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3288 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3289 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3290 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3291
3292 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3293 }
3294
3295 return ret;
3296 }
3297
hns_roce_v2_frmr_write_mtpt(void * mb_buf,struct hns_roce_mr * mr)3298 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
3299 {
3300 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr);
3301 struct hns_roce_v2_mpt_entry *mpt_entry;
3302
3303 mpt_entry = mb_buf;
3304 memset(mpt_entry, 0, sizeof(*mpt_entry));
3305
3306 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3307 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3308
3309 hr_reg_enable(mpt_entry, MPT_RA_EN);
3310 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3311
3312 hr_reg_enable(mpt_entry, MPT_FRE);
3313 hr_reg_clear(mpt_entry, MPT_MR_MW);
3314 hr_reg_enable(mpt_entry, MPT_BPD);
3315 hr_reg_clear(mpt_entry, MPT_PA);
3316
3317 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1);
3318 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3319 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3320 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3321 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3322
3323 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3324
3325 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
3326 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3327
3328 return 0;
3329 }
3330
hns_roce_v2_mw_write_mtpt(void * mb_buf,struct hns_roce_mw * mw)3331 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
3332 {
3333 struct hns_roce_v2_mpt_entry *mpt_entry;
3334
3335 mpt_entry = mb_buf;
3336 memset(mpt_entry, 0, sizeof(*mpt_entry));
3337
3338 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3339 hr_reg_write(mpt_entry, MPT_PD, mw->pdn);
3340
3341 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3342 hr_reg_enable(mpt_entry, MPT_LW_EN);
3343
3344 hr_reg_enable(mpt_entry, MPT_MR_MW);
3345 hr_reg_enable(mpt_entry, MPT_BPD);
3346 hr_reg_clear(mpt_entry, MPT_PA);
3347 hr_reg_write(mpt_entry, MPT_BQP,
3348 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
3349
3350 mpt_entry->lkey = cpu_to_le32(mw->rkey);
3351
3352 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM,
3353 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
3354 mw->pbl_hop_num);
3355 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3356 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3357 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3358 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3359
3360 return 0;
3361 }
3362
free_mr_post_send_lp_wqe(struct hns_roce_qp * hr_qp)3363 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
3364 {
3365 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
3366 struct ib_device *ibdev = &hr_dev->ib_dev;
3367 const struct ib_send_wr *bad_wr;
3368 struct ib_rdma_wr rdma_wr = {};
3369 struct ib_send_wr *send_wr;
3370 int ret;
3371
3372 send_wr = &rdma_wr.wr;
3373 send_wr->opcode = IB_WR_RDMA_WRITE;
3374
3375 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
3376 if (ret) {
3377 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n",
3378 ret);
3379 return ret;
3380 }
3381
3382 return 0;
3383 }
3384
3385 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3386 struct ib_wc *wc);
3387
free_mr_send_cmd_to_hw(struct hns_roce_dev * hr_dev)3388 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
3389 {
3390 struct hns_roce_v2_priv *priv = hr_dev->priv;
3391 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
3392 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
3393 struct ib_device *ibdev = &hr_dev->ib_dev;
3394 struct hns_roce_qp *hr_qp;
3395 unsigned long end;
3396 int cqe_cnt = 0;
3397 int npolled;
3398 int ret;
3399 int i;
3400
3401 /*
3402 * If the device initialization is not complete or in the uninstall
3403 * process, then there is no need to execute free mr.
3404 */
3405 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
3406 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT ||
3407 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
3408 return;
3409
3410 mutex_lock(&free_mr->mutex);
3411
3412 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
3413 hr_qp = free_mr->rsv_qp[i];
3414
3415 ret = free_mr_post_send_lp_wqe(hr_qp);
3416 if (ret) {
3417 ibdev_err_ratelimited(ibdev,
3418 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
3419 hr_qp->qpn, ret);
3420 break;
3421 }
3422
3423 cqe_cnt++;
3424 }
3425
3426 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
3427 while (cqe_cnt) {
3428 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc);
3429 if (npolled < 0) {
3430 ibdev_err_ratelimited(ibdev,
3431 "failed to poll cqe for free mr, remain %d cqe.\n",
3432 cqe_cnt);
3433 goto out;
3434 }
3435
3436 if (time_after(jiffies, end)) {
3437 ibdev_err_ratelimited(ibdev,
3438 "failed to poll cqe for free mr and timeout, remain %d cqe.\n",
3439 cqe_cnt);
3440 goto out;
3441 }
3442 cqe_cnt -= npolled;
3443 }
3444
3445 out:
3446 mutex_unlock(&free_mr->mutex);
3447 }
3448
hns_roce_v2_dereg_mr(struct hns_roce_dev * hr_dev)3449 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
3450 {
3451 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3452 free_mr_send_cmd_to_hw(hr_dev);
3453 }
3454
get_cqe_v2(struct hns_roce_cq * hr_cq,int n)3455 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3456 {
3457 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3458 }
3459
get_sw_cqe_v2(struct hns_roce_cq * hr_cq,unsigned int n)3460 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3461 {
3462 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3463
3464 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3465 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3466 NULL;
3467 }
3468
update_cq_db(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq)3469 static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3470 struct hns_roce_cq *hr_cq)
3471 {
3472 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3473 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3474 } else {
3475 struct hns_roce_v2_db cq_db = {};
3476
3477 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3478 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3479 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3480 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3481
3482 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3483 }
3484 }
3485
__hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3486 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3487 struct hns_roce_srq *srq)
3488 {
3489 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3490 struct hns_roce_v2_cqe *cqe, *dest;
3491 u32 prod_index;
3492 int nfreed = 0;
3493 int wqe_index;
3494 u8 owner_bit;
3495
3496 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3497 ++prod_index) {
3498 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3499 break;
3500 }
3501
3502 /*
3503 * Now backwards through the CQ, removing CQ entries
3504 * that match our QP by overwriting them with next entries.
3505 */
3506 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3507 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3508 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3509 if (srq && hr_reg_read(cqe, CQE_S_R)) {
3510 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3511 hns_roce_free_srq_wqe(srq, wqe_index);
3512 }
3513 ++nfreed;
3514 } else if (nfreed) {
3515 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3516 hr_cq->ib_cq.cqe);
3517 owner_bit = hr_reg_read(dest, CQE_OWNER);
3518 memcpy(dest, cqe, hr_cq->cqe_size);
3519 hr_reg_write(dest, CQE_OWNER, owner_bit);
3520 }
3521 }
3522
3523 if (nfreed) {
3524 hr_cq->cons_index += nfreed;
3525 update_cq_db(hr_dev, hr_cq);
3526 }
3527 }
3528
hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3529 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3530 struct hns_roce_srq *srq)
3531 {
3532 spin_lock_irq(&hr_cq->lock);
3533 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3534 spin_unlock_irq(&hr_cq->lock);
3535 }
3536
hns_roce_v2_write_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,void * mb_buf,u64 * mtts,dma_addr_t dma_handle)3537 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3538 struct hns_roce_cq *hr_cq, void *mb_buf,
3539 u64 *mtts, dma_addr_t dma_handle)
3540 {
3541 struct hns_roce_v2_cq_context *cq_context;
3542
3543 cq_context = mb_buf;
3544 memset(cq_context, 0, sizeof(*cq_context));
3545
3546 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3547 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED);
3548 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3549 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3550 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3551
3552 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3553 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3554
3555 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3556 hr_reg_enable(cq_context, CQC_STASH);
3557
3558 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3559 to_hr_hw_page_addr(mtts[0]));
3560 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3561 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3562 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3563 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3564 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3565 to_hr_hw_page_addr(mtts[1]));
3566 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3567 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3568 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3569 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3570 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3571 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3572 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3);
3573 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3)));
3574 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3575 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3576 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3577 ((u32)hr_cq->db.dma) >> 1);
3578 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3579 hr_cq->db.dma >> 32);
3580 hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3581 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3582 hr_reg_write(cq_context, CQC_CQ_PERIOD,
3583 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3584 }
3585
hns_roce_v2_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)3586 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3587 enum ib_cq_notify_flags flags)
3588 {
3589 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3590 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3591 struct hns_roce_v2_db cq_db = {};
3592 u32 notify_flag;
3593
3594 /*
3595 * flags = 0, then notify_flag : next
3596 * flags = 1, then notify flag : solocited
3597 */
3598 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3599 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3600
3601 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3602 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3603 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3604 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3605 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3606
3607 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3608
3609 return 0;
3610 }
3611
sw_comp(struct hns_roce_qp * hr_qp,struct hns_roce_wq * wq,int num_entries,struct ib_wc * wc)3612 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3613 int num_entries, struct ib_wc *wc)
3614 {
3615 unsigned int left;
3616 int npolled = 0;
3617
3618 left = wq->head - wq->tail;
3619 if (left == 0)
3620 return 0;
3621
3622 left = min_t(unsigned int, (unsigned int)num_entries, left);
3623 while (npolled < left) {
3624 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3625 wc->status = IB_WC_WR_FLUSH_ERR;
3626 wc->vendor_err = 0;
3627 wc->qp = &hr_qp->ibqp;
3628
3629 wq->tail++;
3630 wc++;
3631 npolled++;
3632 }
3633
3634 return npolled;
3635 }
3636
hns_roce_v2_sw_poll_cq(struct hns_roce_cq * hr_cq,int num_entries,struct ib_wc * wc)3637 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3638 struct ib_wc *wc)
3639 {
3640 struct hns_roce_qp *hr_qp;
3641 int npolled = 0;
3642
3643 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3644 npolled += sw_comp(hr_qp, &hr_qp->sq,
3645 num_entries - npolled, wc + npolled);
3646 if (npolled >= num_entries)
3647 goto out;
3648 }
3649
3650 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3651 npolled += sw_comp(hr_qp, &hr_qp->rq,
3652 num_entries - npolled, wc + npolled);
3653 if (npolled >= num_entries)
3654 goto out;
3655 }
3656
3657 out:
3658 return npolled;
3659 }
3660
get_cqe_status(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,struct hns_roce_cq * cq,struct hns_roce_v2_cqe * cqe,struct ib_wc * wc)3661 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3662 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3663 struct ib_wc *wc)
3664 {
3665 static const struct {
3666 u32 cqe_status;
3667 enum ib_wc_status wc_status;
3668 } map[] = {
3669 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3670 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3671 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3672 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3673 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3674 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3675 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3676 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3677 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3678 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3679 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3680 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3681 IB_WC_RETRY_EXC_ERR },
3682 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3683 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3684 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3685 };
3686
3687 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3688 int i;
3689
3690 wc->status = IB_WC_GENERAL_ERR;
3691 for (i = 0; i < ARRAY_SIZE(map); i++)
3692 if (cqe_status == map[i].cqe_status) {
3693 wc->status = map[i].wc_status;
3694 break;
3695 }
3696
3697 if (likely(wc->status == IB_WC_SUCCESS ||
3698 wc->status == IB_WC_WR_FLUSH_ERR))
3699 return;
3700
3701 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n",
3702 cqe_status);
3703 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3704 cq->cqe_size, false);
3705 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
3706
3707 /*
3708 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3709 * the standard protocol, the driver must ignore it and needn't to set
3710 * the QP to an error state.
3711 */
3712 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3713 return;
3714
3715 flush_cqe(hr_dev, qp);
3716 }
3717
get_cur_qp(struct hns_roce_cq * hr_cq,struct hns_roce_v2_cqe * cqe,struct hns_roce_qp ** cur_qp)3718 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3719 struct hns_roce_qp **cur_qp)
3720 {
3721 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3722 struct hns_roce_qp *hr_qp = *cur_qp;
3723 u32 qpn;
3724
3725 qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3726
3727 if (!hr_qp || qpn != hr_qp->qpn) {
3728 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3729 if (unlikely(!hr_qp)) {
3730 ibdev_err(&hr_dev->ib_dev,
3731 "CQ %06lx with entry for unknown QPN %06x\n",
3732 hr_cq->cqn, qpn);
3733 return -EINVAL;
3734 }
3735 *cur_qp = hr_qp;
3736 }
3737
3738 return 0;
3739 }
3740
3741 /*
3742 * mapped-value = 1 + real-value
3743 * The ib wc opcode's real value is start from 0, In order to distinguish
3744 * between initialized and uninitialized map values, we plus 1 to the actual
3745 * value when defining the mapping, so that the validity can be identified by
3746 * checking whether the mapped value is greater than 0.
3747 */
3748 #define HR_WC_OP_MAP(hr_key, ib_key) \
3749 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3750
3751 static const u32 wc_send_op_map[] = {
3752 HR_WC_OP_MAP(SEND, SEND),
3753 HR_WC_OP_MAP(SEND_WITH_INV, SEND),
3754 HR_WC_OP_MAP(SEND_WITH_IMM, SEND),
3755 HR_WC_OP_MAP(RDMA_READ, RDMA_READ),
3756 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE),
3757 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE),
3758 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP),
3759 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD),
3760 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP),
3761 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD),
3762 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR),
3763 HR_WC_OP_MAP(BIND_MW, REG_MR),
3764 };
3765
to_ib_wc_send_op(u32 hr_opcode)3766 static int to_ib_wc_send_op(u32 hr_opcode)
3767 {
3768 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3769 return -EINVAL;
3770
3771 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3772 -EINVAL;
3773 }
3774
3775 static const u32 wc_recv_op_map[] = {
3776 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM),
3777 HR_WC_OP_MAP(SEND, RECV),
3778 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM),
3779 HR_WC_OP_MAP(SEND_WITH_INV, RECV),
3780 };
3781
to_ib_wc_recv_op(u32 hr_opcode)3782 static int to_ib_wc_recv_op(u32 hr_opcode)
3783 {
3784 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3785 return -EINVAL;
3786
3787 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3788 -EINVAL;
3789 }
3790
fill_send_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3791 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3792 {
3793 u32 hr_opcode;
3794 int ib_opcode;
3795
3796 wc->wc_flags = 0;
3797
3798 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3799 switch (hr_opcode) {
3800 case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3801 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3802 break;
3803 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3804 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3805 wc->wc_flags |= IB_WC_WITH_IMM;
3806 break;
3807 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3808 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3809 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3810 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3811 wc->byte_len = 8;
3812 break;
3813 default:
3814 break;
3815 }
3816
3817 ib_opcode = to_ib_wc_send_op(hr_opcode);
3818 if (ib_opcode < 0)
3819 wc->status = IB_WC_GENERAL_ERR;
3820 else
3821 wc->opcode = ib_opcode;
3822 }
3823
fill_recv_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3824 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3825 {
3826 u32 hr_opcode;
3827 int ib_opcode;
3828
3829 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3830
3831 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3832 switch (hr_opcode) {
3833 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3834 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3835 wc->wc_flags = IB_WC_WITH_IMM;
3836 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3837 break;
3838 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3839 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3840 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3841 break;
3842 default:
3843 wc->wc_flags = 0;
3844 }
3845
3846 ib_opcode = to_ib_wc_recv_op(hr_opcode);
3847 if (ib_opcode < 0)
3848 wc->status = IB_WC_GENERAL_ERR;
3849 else
3850 wc->opcode = ib_opcode;
3851
3852 wc->sl = hr_reg_read(cqe, CQE_SL);
3853 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
3854 wc->slid = 0;
3855 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
3856 wc->port_num = hr_reg_read(cqe, CQE_PORTN);
3857 wc->pkey_index = 0;
3858
3859 if (hr_reg_read(cqe, CQE_VID_VLD)) {
3860 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
3861 wc->wc_flags |= IB_WC_WITH_VLAN;
3862 } else {
3863 wc->vlan_id = 0xffff;
3864 }
3865
3866 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
3867
3868 return 0;
3869 }
3870
hns_roce_v2_poll_one(struct hns_roce_cq * hr_cq,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)3871 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3872 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3873 {
3874 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3875 struct hns_roce_qp *qp = *cur_qp;
3876 struct hns_roce_srq *srq = NULL;
3877 struct hns_roce_v2_cqe *cqe;
3878 struct hns_roce_wq *wq;
3879 int is_send;
3880 u16 wqe_idx;
3881 int ret;
3882
3883 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
3884 if (!cqe)
3885 return -EAGAIN;
3886
3887 ++hr_cq->cons_index;
3888 /* Memory barrier */
3889 rmb();
3890
3891 ret = get_cur_qp(hr_cq, cqe, &qp);
3892 if (ret)
3893 return ret;
3894
3895 wc->qp = &qp->ibqp;
3896 wc->vendor_err = 0;
3897
3898 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
3899
3900 is_send = !hr_reg_read(cqe, CQE_S_R);
3901 if (is_send) {
3902 wq = &qp->sq;
3903
3904 /* If sg_signal_bit is set, tail pointer will be updated to
3905 * the WQE corresponding to the current CQE.
3906 */
3907 if (qp->sq_signal_bits)
3908 wq->tail += (wqe_idx - (u16)wq->tail) &
3909 (wq->wqe_cnt - 1);
3910
3911 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3912 ++wq->tail;
3913
3914 fill_send_wc(wc, cqe);
3915 } else {
3916 if (qp->ibqp.srq) {
3917 srq = to_hr_srq(qp->ibqp.srq);
3918 wc->wr_id = srq->wrid[wqe_idx];
3919 hns_roce_free_srq_wqe(srq, wqe_idx);
3920 } else {
3921 wq = &qp->rq;
3922 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3923 ++wq->tail;
3924 }
3925
3926 ret = fill_recv_wc(wc, cqe);
3927 }
3928
3929 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
3930 if (unlikely(wc->status != IB_WC_SUCCESS))
3931 return 0;
3932
3933 return ret;
3934 }
3935
hns_roce_v2_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)3936 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3937 struct ib_wc *wc)
3938 {
3939 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3940 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3941 struct hns_roce_qp *cur_qp = NULL;
3942 unsigned long flags;
3943 int npolled;
3944
3945 spin_lock_irqsave(&hr_cq->lock, flags);
3946
3947 /*
3948 * When the device starts to reset, the state is RST_DOWN. At this time,
3949 * there may still be some valid CQEs in the hardware that are not
3950 * polled. Therefore, it is not allowed to switch to the software mode
3951 * immediately. When the state changes to UNINIT, CQE no longer exists
3952 * in the hardware, and then switch to software mode.
3953 */
3954 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3955 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3956 goto out;
3957 }
3958
3959 for (npolled = 0; npolled < num_entries; ++npolled) {
3960 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3961 break;
3962 }
3963
3964 if (npolled)
3965 update_cq_db(hr_dev, hr_cq);
3966
3967 out:
3968 spin_unlock_irqrestore(&hr_cq->lock, flags);
3969
3970 return npolled;
3971 }
3972
get_op_for_set_hem(struct hns_roce_dev * hr_dev,u32 type,u32 step_idx,u8 * mbox_cmd)3973 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3974 u32 step_idx, u8 *mbox_cmd)
3975 {
3976 u8 cmd;
3977
3978 switch (type) {
3979 case HEM_TYPE_QPC:
3980 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
3981 break;
3982 case HEM_TYPE_MTPT:
3983 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
3984 break;
3985 case HEM_TYPE_CQC:
3986 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
3987 break;
3988 case HEM_TYPE_SRQC:
3989 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
3990 break;
3991 case HEM_TYPE_SCCC:
3992 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
3993 break;
3994 case HEM_TYPE_QPC_TIMER:
3995 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
3996 break;
3997 case HEM_TYPE_CQC_TIMER:
3998 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
3999 break;
4000 default:
4001 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
4002 return -EINVAL;
4003 }
4004
4005 *mbox_cmd = cmd + step_idx;
4006
4007 return 0;
4008 }
4009
config_gmv_ba_to_hw(struct hns_roce_dev * hr_dev,unsigned long obj,dma_addr_t base_addr)4010 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
4011 dma_addr_t base_addr)
4012 {
4013 struct hns_roce_cmq_desc desc;
4014 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
4015 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
4016 u64 addr = to_hr_hw_page_addr(base_addr);
4017
4018 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
4019
4020 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
4021 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
4022 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
4023
4024 return hns_roce_cmq_send(hr_dev, &desc, 1);
4025 }
4026
set_hem_to_hw(struct hns_roce_dev * hr_dev,int obj,dma_addr_t base_addr,u32 hem_type,u32 step_idx)4027 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
4028 dma_addr_t base_addr, u32 hem_type, u32 step_idx)
4029 {
4030 int ret;
4031 u8 cmd;
4032
4033 if (unlikely(hem_type == HEM_TYPE_GMV))
4034 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
4035
4036 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
4037 return 0;
4038
4039 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
4040 if (ret < 0)
4041 return ret;
4042
4043 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
4044 }
4045
hns_roce_v2_set_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,u32 step_idx)4046 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
4047 struct hns_roce_hem_table *table, int obj,
4048 u32 step_idx)
4049 {
4050 struct hns_roce_hem_iter iter;
4051 struct hns_roce_hem_mhop mhop;
4052 struct hns_roce_hem *hem;
4053 unsigned long mhop_obj = obj;
4054 int i, j, k;
4055 int ret = 0;
4056 u64 hem_idx = 0;
4057 u64 l1_idx = 0;
4058 u64 bt_ba = 0;
4059 u32 chunk_ba_num;
4060 u32 hop_num;
4061
4062 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4063 return 0;
4064
4065 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
4066 i = mhop.l0_idx;
4067 j = mhop.l1_idx;
4068 k = mhop.l2_idx;
4069 hop_num = mhop.hop_num;
4070 chunk_ba_num = mhop.bt_chunk_size / 8;
4071
4072 if (hop_num == 2) {
4073 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
4074 k;
4075 l1_idx = i * chunk_ba_num + j;
4076 } else if (hop_num == 1) {
4077 hem_idx = i * chunk_ba_num + j;
4078 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
4079 hem_idx = i;
4080 }
4081
4082 if (table->type == HEM_TYPE_SCCC)
4083 obj = mhop.l0_idx;
4084
4085 if (check_whether_last_step(hop_num, step_idx)) {
4086 hem = table->hem[hem_idx];
4087 for (hns_roce_hem_first(hem, &iter);
4088 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
4089 bt_ba = hns_roce_hem_addr(&iter);
4090 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
4091 step_idx);
4092 }
4093 } else {
4094 if (step_idx == 0)
4095 bt_ba = table->bt_l0_dma_addr[i];
4096 else if (step_idx == 1 && hop_num == 2)
4097 bt_ba = table->bt_l1_dma_addr[l1_idx];
4098
4099 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
4100 }
4101
4102 return ret;
4103 }
4104
hns_roce_v2_clear_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int tag,u32 step_idx)4105 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
4106 struct hns_roce_hem_table *table,
4107 int tag, u32 step_idx)
4108 {
4109 struct hns_roce_cmd_mailbox *mailbox;
4110 struct device *dev = hr_dev->dev;
4111 u8 cmd = 0xff;
4112 int ret;
4113
4114 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4115 return 0;
4116
4117 switch (table->type) {
4118 case HEM_TYPE_QPC:
4119 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
4120 break;
4121 case HEM_TYPE_MTPT:
4122 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
4123 break;
4124 case HEM_TYPE_CQC:
4125 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
4126 break;
4127 case HEM_TYPE_SRQC:
4128 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4129 break;
4130 case HEM_TYPE_SCCC:
4131 case HEM_TYPE_QPC_TIMER:
4132 case HEM_TYPE_CQC_TIMER:
4133 case HEM_TYPE_GMV:
4134 return 0;
4135 default:
4136 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4137 table->type);
4138 return 0;
4139 }
4140
4141 cmd += step_idx;
4142
4143 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4144 if (IS_ERR(mailbox))
4145 return PTR_ERR(mailbox);
4146
4147 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
4148
4149 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4150 return ret;
4151 }
4152
hns_roce_v2_qp_modify(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct hns_roce_qp * hr_qp)4153 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4154 struct hns_roce_v2_qp_context *context,
4155 struct hns_roce_v2_qp_context *qpc_mask,
4156 struct hns_roce_qp *hr_qp)
4157 {
4158 struct hns_roce_cmd_mailbox *mailbox;
4159 int qpc_size;
4160 int ret;
4161
4162 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4163 if (IS_ERR(mailbox))
4164 return PTR_ERR(mailbox);
4165
4166 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4167 qpc_size = hr_dev->caps.qpc_sz;
4168 memcpy(mailbox->buf, context, qpc_size);
4169 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4170
4171 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4172 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4173
4174 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4175
4176 return ret;
4177 }
4178
set_access_flags(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,const struct ib_qp_attr * attr,int attr_mask)4179 static void set_access_flags(struct hns_roce_qp *hr_qp,
4180 struct hns_roce_v2_qp_context *context,
4181 struct hns_roce_v2_qp_context *qpc_mask,
4182 const struct ib_qp_attr *attr, int attr_mask)
4183 {
4184 u8 dest_rd_atomic;
4185 u32 access_flags;
4186
4187 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4188 attr->max_dest_rd_atomic : hr_qp->resp_depth;
4189
4190 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4191 attr->qp_access_flags : hr_qp->atomic_rd_en;
4192
4193 if (!dest_rd_atomic)
4194 access_flags &= IB_ACCESS_REMOTE_WRITE;
4195
4196 hr_reg_write_bool(context, QPC_RRE,
4197 access_flags & IB_ACCESS_REMOTE_READ);
4198 hr_reg_clear(qpc_mask, QPC_RRE);
4199
4200 hr_reg_write_bool(context, QPC_RWE,
4201 access_flags & IB_ACCESS_REMOTE_WRITE);
4202 hr_reg_clear(qpc_mask, QPC_RWE);
4203
4204 hr_reg_write_bool(context, QPC_ATE,
4205 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4206 hr_reg_clear(qpc_mask, QPC_ATE);
4207 hr_reg_write_bool(context, QPC_EXT_ATE,
4208 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4209 hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4210 }
4211
set_qpc_wqe_cnt(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context)4212 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4213 struct hns_roce_v2_qp_context *context)
4214 {
4215 hr_reg_write(context, QPC_SGE_SHIFT,
4216 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4217 hr_qp->sge.sge_shift));
4218
4219 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4220
4221 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4222 }
4223
get_cqn(struct ib_cq * ib_cq)4224 static inline int get_cqn(struct ib_cq *ib_cq)
4225 {
4226 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4227 }
4228
get_pdn(struct ib_pd * ib_pd)4229 static inline int get_pdn(struct ib_pd *ib_pd)
4230 {
4231 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4232 }
4233
modify_qp_reset_to_init(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4234 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4235 struct hns_roce_v2_qp_context *context,
4236 struct hns_roce_v2_qp_context *qpc_mask)
4237 {
4238 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4239 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4240
4241 /*
4242 * In v2 engine, software pass context and context mask to hardware
4243 * when modifying qp. If software need modify some fields in context,
4244 * we should set all bits of the relevant fields in context mask to
4245 * 0 at the same time, else set them to 0x1.
4246 */
4247 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4248
4249 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4250
4251 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4252
4253 set_qpc_wqe_cnt(hr_qp, context);
4254
4255 /* No VLAN need to set 0xFFF */
4256 hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4257
4258 if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4259 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4260
4261 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4262 }
4263
4264 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4265 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4266
4267 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
4268 hr_reg_enable(context, QPC_OWNER_MODE);
4269
4270 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4271 lower_32_bits(hr_qp->rdb.dma) >> 1);
4272 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4273 upper_32_bits(hr_qp->rdb.dma));
4274
4275 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4276
4277 if (ibqp->srq) {
4278 hr_reg_enable(context, QPC_SRQ_EN);
4279 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4280 }
4281
4282 hr_reg_enable(context, QPC_FRE);
4283
4284 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4285
4286 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4287 return;
4288
4289 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4290 hr_reg_enable(&context->ext, QPCEX_STASH);
4291 }
4292
modify_qp_init_to_init(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4293 static void modify_qp_init_to_init(struct ib_qp *ibqp,
4294 struct hns_roce_v2_qp_context *context,
4295 struct hns_roce_v2_qp_context *qpc_mask)
4296 {
4297 /*
4298 * In v2 engine, software pass context and context mask to hardware
4299 * when modifying qp. If software need modify some fields in context,
4300 * we should set all bits of the relevant fields in context mask to
4301 * 0 at the same time, else set them to 0x1.
4302 */
4303 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4304 hr_reg_clear(qpc_mask, QPC_TST);
4305
4306 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4307 hr_reg_clear(qpc_mask, QPC_PD);
4308
4309 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4310 hr_reg_clear(qpc_mask, QPC_RX_CQN);
4311
4312 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4313 hr_reg_clear(qpc_mask, QPC_TX_CQN);
4314
4315 if (ibqp->srq) {
4316 hr_reg_enable(context, QPC_SRQ_EN);
4317 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4318 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4319 hr_reg_clear(qpc_mask, QPC_SRQN);
4320 }
4321 }
4322
config_qp_rq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4323 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4324 struct hns_roce_qp *hr_qp,
4325 struct hns_roce_v2_qp_context *context,
4326 struct hns_roce_v2_qp_context *qpc_mask)
4327 {
4328 u64 mtts[MTT_MIN_COUNT] = { 0 };
4329 u64 wqe_sge_ba;
4330 int ret;
4331
4332 /* Search qp buf's mtts */
4333 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4334 MTT_MIN_COUNT);
4335 if (hr_qp->rq.wqe_cnt && ret) {
4336 ibdev_err(&hr_dev->ib_dev,
4337 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n",
4338 hr_qp->qpn, ret);
4339 return ret;
4340 }
4341
4342 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr);
4343
4344 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4345 qpc_mask->wqe_sge_ba = 0;
4346
4347 /*
4348 * In v2 engine, software pass context and context mask to hardware
4349 * when modifying qp. If software need modify some fields in context,
4350 * we should set all bits of the relevant fields in context mask to
4351 * 0 at the same time, else set them to 0x1.
4352 */
4353 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4354 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4355
4356 hr_reg_write(context, QPC_SQ_HOP_NUM,
4357 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4358 hr_qp->sq.wqe_cnt));
4359 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4360
4361 hr_reg_write(context, QPC_SGE_HOP_NUM,
4362 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4363 hr_qp->sge.sge_cnt));
4364 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4365
4366 hr_reg_write(context, QPC_RQ_HOP_NUM,
4367 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4368 hr_qp->rq.wqe_cnt));
4369
4370 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4371
4372 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4373 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4374 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4375
4376 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4377 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4378 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4379
4380 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4381 qpc_mask->rq_cur_blk_addr = 0;
4382
4383 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4384 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4385 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4386
4387 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4388 context->rq_nxt_blk_addr =
4389 cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4390 qpc_mask->rq_nxt_blk_addr = 0;
4391 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4392 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4393 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4394 }
4395
4396 return 0;
4397 }
4398
config_qp_sq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4399 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4400 struct hns_roce_qp *hr_qp,
4401 struct hns_roce_v2_qp_context *context,
4402 struct hns_roce_v2_qp_context *qpc_mask)
4403 {
4404 struct ib_device *ibdev = &hr_dev->ib_dev;
4405 u64 sge_cur_blk = 0;
4406 u64 sq_cur_blk = 0;
4407 int ret;
4408
4409 /* search qp buf's mtts */
4410 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset,
4411 &sq_cur_blk, 1);
4412 if (ret) {
4413 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n",
4414 hr_qp->qpn, ret);
4415 return ret;
4416 }
4417 if (hr_qp->sge.sge_cnt > 0) {
4418 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4419 hr_qp->sge.offset, &sge_cur_blk, 1);
4420 if (ret) {
4421 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n",
4422 hr_qp->qpn, ret);
4423 return ret;
4424 }
4425 }
4426
4427 /*
4428 * In v2 engine, software pass context and context mask to hardware
4429 * when modifying qp. If software need modify some fields in context,
4430 * we should set all bits of the relevant fields in context mask to
4431 * 0 at the same time, else set them to 0x1.
4432 */
4433 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4434 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4435 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4436 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4437 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4438 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4439
4440 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4441 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4442 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4443 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4444 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4445 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4446
4447 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4448 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4449 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4450 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4451 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4452 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4453
4454 return 0;
4455 }
4456
get_mtu(struct ib_qp * ibqp,const struct ib_qp_attr * attr)4457 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4458 const struct ib_qp_attr *attr)
4459 {
4460 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4461 return IB_MTU_4096;
4462
4463 return attr->path_mtu;
4464 }
4465
modify_qp_init_to_rtr(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)4466 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4467 const struct ib_qp_attr *attr, int attr_mask,
4468 struct hns_roce_v2_qp_context *context,
4469 struct hns_roce_v2_qp_context *qpc_mask,
4470 struct ib_udata *udata)
4471 {
4472 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata,
4473 struct hns_roce_ucontext, ibucontext);
4474 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4475 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4476 struct ib_device *ibdev = &hr_dev->ib_dev;
4477 dma_addr_t trrl_ba;
4478 dma_addr_t irrl_ba;
4479 enum ib_mtu ib_mtu;
4480 const u8 *smac;
4481 u8 lp_pktn_ini;
4482 u64 *mtts;
4483 u8 *dmac;
4484 u32 port;
4485 int mtu;
4486 int ret;
4487
4488 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4489 if (ret) {
4490 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4491 return ret;
4492 }
4493
4494 /* Search IRRL's mtts */
4495 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4496 hr_qp->qpn, &irrl_ba);
4497 if (!mtts) {
4498 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4499 return -EINVAL;
4500 }
4501
4502 /* Search TRRL's mtts */
4503 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4504 hr_qp->qpn, &trrl_ba);
4505 if (!mtts) {
4506 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4507 return -EINVAL;
4508 }
4509
4510 if (attr_mask & IB_QP_ALT_PATH) {
4511 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4512 attr_mask);
4513 return -EINVAL;
4514 }
4515
4516 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4);
4517 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4518 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
4519 qpc_mask->trrl_ba = 0;
4520 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4));
4521 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4522
4523 context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
4524 qpc_mask->irrl_ba = 0;
4525 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6));
4526 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4527
4528 hr_reg_enable(context, QPC_RMT_E2E);
4529 hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4530
4531 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4532 hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4533
4534 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4535
4536 smac = (const u8 *)hr_dev->dev_addr[port];
4537 dmac = (u8 *)attr->ah_attr.roce.dmac;
4538 /* when dmac equals smac or loop_idc is 1, it should loopback */
4539 if (ether_addr_equal_unaligned(dmac, smac) ||
4540 hr_dev->loop_idc == 0x1) {
4541 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4542 hr_reg_clear(qpc_mask, QPC_LBI);
4543 }
4544
4545 if (attr_mask & IB_QP_DEST_QPN) {
4546 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4547 hr_reg_clear(qpc_mask, QPC_DQPN);
4548 }
4549
4550 memcpy(&context->dmac, dmac, sizeof(u32));
4551 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4552 qpc_mask->dmac = 0;
4553 hr_reg_clear(qpc_mask, QPC_DMAC_H);
4554
4555 ib_mtu = get_mtu(ibqp, attr);
4556 hr_qp->path_mtu = ib_mtu;
4557
4558 mtu = ib_mtu_enum_to_int(ib_mtu);
4559 if (WARN_ON(mtu <= 0))
4560 return -EINVAL;
4561 #define MIN_LP_MSG_LEN 1024
4562 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */
4563 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu);
4564
4565 if (attr_mask & IB_QP_PATH_MTU) {
4566 hr_reg_write(context, QPC_MTU, ib_mtu);
4567 hr_reg_clear(qpc_mask, QPC_MTU);
4568 }
4569
4570 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4571 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4572
4573 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */
4574 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini);
4575 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4576
4577 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4578 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4579 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4580
4581 context->rq_rnr_timer = 0;
4582 qpc_mask->rq_rnr_timer = 0;
4583
4584 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4585 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4586
4587 /* rocee send 2^lp_sgen_ini segs every time */
4588 hr_reg_write(context, QPC_LP_SGEN_INI, 3);
4589 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4590
4591 if (udata && ibqp->qp_type == IB_QPT_RC &&
4592 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) {
4593 hr_reg_write_bool(context, QPC_RQIE,
4594 hr_dev->caps.flags &
4595 HNS_ROCE_CAP_FLAG_RQ_INLINE);
4596 hr_reg_clear(qpc_mask, QPC_RQIE);
4597 }
4598
4599 if (udata &&
4600 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) &&
4601 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) {
4602 hr_reg_write_bool(context, QPC_CQEIE,
4603 hr_dev->caps.flags &
4604 HNS_ROCE_CAP_FLAG_CQE_INLINE);
4605 hr_reg_clear(qpc_mask, QPC_CQEIE);
4606
4607 hr_reg_write(context, QPC_CQEIS, 0);
4608 hr_reg_clear(qpc_mask, QPC_CQEIS);
4609 }
4610
4611 return 0;
4612 }
4613
modify_qp_rtr_to_rts(struct ib_qp * ibqp,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4614 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask,
4615 struct hns_roce_v2_qp_context *context,
4616 struct hns_roce_v2_qp_context *qpc_mask)
4617 {
4618 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4619 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4620 struct ib_device *ibdev = &hr_dev->ib_dev;
4621 int ret;
4622
4623 /* Not support alternate path and path migration */
4624 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4625 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4626 return -EINVAL;
4627 }
4628
4629 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4630 if (ret) {
4631 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4632 return ret;
4633 }
4634
4635 /*
4636 * Set some fields in context to zero, Because the default values
4637 * of all fields in context are zero, we need not set them to 0 again.
4638 * but we should set the relevant fields of context mask to 0.
4639 */
4640 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4641
4642 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4643
4644 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4645 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4646 hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4647
4648 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4649
4650 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4651
4652 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4653
4654 hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4655
4656 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4657
4658 return 0;
4659 }
4660
get_dip_ctx_idx(struct ib_qp * ibqp,const struct ib_qp_attr * attr,u32 * dip_idx)4661 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4662 u32 *dip_idx)
4663 {
4664 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4665 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4666 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx;
4667 u32 *head = &hr_dev->qp_table.idx_table.head;
4668 u32 *tail = &hr_dev->qp_table.idx_table.tail;
4669 struct hns_roce_dip *hr_dip;
4670 unsigned long flags;
4671 int ret = 0;
4672
4673 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
4674
4675 spare_idx[*tail] = ibqp->qp_num;
4676 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1);
4677
4678 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) {
4679 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) {
4680 *dip_idx = hr_dip->dip_idx;
4681 goto out;
4682 }
4683 }
4684
4685 /* If no dgid is found, a new dip and a mapping between dgid and
4686 * dip_idx will be created.
4687 */
4688 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC);
4689 if (!hr_dip) {
4690 ret = -ENOMEM;
4691 goto out;
4692 }
4693
4694 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4695 hr_dip->dip_idx = *dip_idx = spare_idx[*head];
4696 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1);
4697 list_add_tail(&hr_dip->node, &hr_dev->dip_list);
4698
4699 out:
4700 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
4701 return ret;
4702 }
4703
4704 enum {
4705 CONG_DCQCN,
4706 CONG_WINDOW,
4707 };
4708
4709 enum {
4710 UNSUPPORT_CONG_LEVEL,
4711 SUPPORT_CONG_LEVEL,
4712 };
4713
4714 enum {
4715 CONG_LDCP,
4716 CONG_HC3,
4717 };
4718
4719 enum {
4720 DIP_INVALID,
4721 DIP_VALID,
4722 };
4723
4724 enum {
4725 WND_LIMIT,
4726 WND_UNLIMIT,
4727 };
4728
check_cong_type(struct ib_qp * ibqp,struct hns_roce_congestion_algorithm * cong_alg)4729 static int check_cong_type(struct ib_qp *ibqp,
4730 struct hns_roce_congestion_algorithm *cong_alg)
4731 {
4732 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4733 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4734
4735 if (ibqp->qp_type == IB_QPT_UD || ibqp->qp_type == IB_QPT_GSI)
4736 hr_qp->cong_type = CONG_TYPE_DCQCN;
4737 else
4738 hr_qp->cong_type = hr_dev->caps.cong_type;
4739
4740 /* different congestion types match different configurations */
4741 switch (hr_qp->cong_type) {
4742 case CONG_TYPE_DCQCN:
4743 cong_alg->alg_sel = CONG_DCQCN;
4744 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4745 cong_alg->dip_vld = DIP_INVALID;
4746 cong_alg->wnd_mode_sel = WND_LIMIT;
4747 break;
4748 case CONG_TYPE_LDCP:
4749 cong_alg->alg_sel = CONG_WINDOW;
4750 cong_alg->alg_sub_sel = CONG_LDCP;
4751 cong_alg->dip_vld = DIP_INVALID;
4752 cong_alg->wnd_mode_sel = WND_UNLIMIT;
4753 break;
4754 case CONG_TYPE_HC3:
4755 cong_alg->alg_sel = CONG_WINDOW;
4756 cong_alg->alg_sub_sel = CONG_HC3;
4757 cong_alg->dip_vld = DIP_INVALID;
4758 cong_alg->wnd_mode_sel = WND_LIMIT;
4759 break;
4760 case CONG_TYPE_DIP:
4761 cong_alg->alg_sel = CONG_DCQCN;
4762 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4763 cong_alg->dip_vld = DIP_VALID;
4764 cong_alg->wnd_mode_sel = WND_LIMIT;
4765 break;
4766 default:
4767 ibdev_warn(&hr_dev->ib_dev,
4768 "invalid type(%u) for congestion selection.\n",
4769 hr_qp->cong_type);
4770 hr_qp->cong_type = CONG_TYPE_DCQCN;
4771 cong_alg->alg_sel = CONG_DCQCN;
4772 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4773 cong_alg->dip_vld = DIP_INVALID;
4774 cong_alg->wnd_mode_sel = WND_LIMIT;
4775 break;
4776 }
4777
4778 return 0;
4779 }
4780
fill_cong_field(struct ib_qp * ibqp,const struct ib_qp_attr * attr,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4781 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4782 struct hns_roce_v2_qp_context *context,
4783 struct hns_roce_v2_qp_context *qpc_mask)
4784 {
4785 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4786 struct hns_roce_congestion_algorithm cong_field;
4787 struct ib_device *ibdev = ibqp->device;
4788 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4789 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4790 u32 dip_idx = 0;
4791 int ret;
4792
4793 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4794 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4795 return 0;
4796
4797 ret = check_cong_type(ibqp, &cong_field);
4798 if (ret)
4799 return ret;
4800
4801 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4802 hr_qp->cong_type * HNS_ROCE_CONG_SIZE);
4803 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4804 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4805 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4806 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4807 cong_field.alg_sub_sel);
4808 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4809 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4810 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4811 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN,
4812 cong_field.wnd_mode_sel);
4813 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN);
4814
4815 /* if dip is disabled, there is no need to set dip idx */
4816 if (cong_field.dip_vld == 0)
4817 return 0;
4818
4819 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
4820 if (ret) {
4821 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
4822 return ret;
4823 }
4824
4825 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
4826 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
4827
4828 return 0;
4829 }
4830
hns_roce_v2_set_path(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4831 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4832 const struct ib_qp_attr *attr,
4833 int attr_mask,
4834 struct hns_roce_v2_qp_context *context,
4835 struct hns_roce_v2_qp_context *qpc_mask)
4836 {
4837 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4838 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4839 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4840 struct ib_device *ibdev = &hr_dev->ib_dev;
4841 const struct ib_gid_attr *gid_attr = NULL;
4842 u8 sl = rdma_ah_get_sl(&attr->ah_attr);
4843 int is_roce_protocol;
4844 u16 vlan_id = 0xffff;
4845 bool is_udp = false;
4846 u32 max_sl;
4847 u8 ib_port;
4848 u8 hr_port;
4849 int ret;
4850
4851 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1);
4852 if (unlikely(sl > max_sl)) {
4853 ibdev_err_ratelimited(ibdev,
4854 "failed to fill QPC, sl (%u) shouldn't be larger than %u.\n",
4855 sl, max_sl);
4856 return -EINVAL;
4857 }
4858
4859 /*
4860 * If free_mr_en of qp is set, it means that this qp comes from
4861 * free mr. This qp will perform the loopback operation.
4862 * In the loopback scenario, only sl needs to be set.
4863 */
4864 if (hr_qp->free_mr_en) {
4865 hr_reg_write(context, QPC_SL, sl);
4866 hr_reg_clear(qpc_mask, QPC_SL);
4867 hr_qp->sl = sl;
4868 return 0;
4869 }
4870
4871 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4872 hr_port = ib_port - 1;
4873 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4874 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4875
4876 if (is_roce_protocol) {
4877 gid_attr = attr->ah_attr.grh.sgid_attr;
4878 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
4879 if (ret)
4880 return ret;
4881
4882 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
4883 }
4884
4885 /* Only HIP08 needs to set the vlan_en bits in QPC */
4886 if (vlan_id < VLAN_N_VID &&
4887 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4888 hr_reg_enable(context, QPC_RQ_VLAN_EN);
4889 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
4890 hr_reg_enable(context, QPC_SQ_VLAN_EN);
4891 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
4892 }
4893
4894 hr_reg_write(context, QPC_VLAN_ID, vlan_id);
4895 hr_reg_clear(qpc_mask, QPC_VLAN_ID);
4896
4897 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4898 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4899 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
4900 return -EINVAL;
4901 }
4902
4903 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4904 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
4905 return -EINVAL;
4906 }
4907
4908 hr_reg_write(context, QPC_UDPSPN,
4909 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
4910 attr->dest_qp_num) :
4911 0);
4912
4913 hr_reg_clear(qpc_mask, QPC_UDPSPN);
4914
4915 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
4916
4917 hr_reg_clear(qpc_mask, QPC_GMV_IDX);
4918
4919 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
4920 hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
4921
4922 ret = fill_cong_field(ibqp, attr, context, qpc_mask);
4923 if (ret)
4924 return ret;
4925
4926 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
4927 hr_reg_clear(qpc_mask, QPC_TC);
4928
4929 hr_reg_write(context, QPC_FL, grh->flow_label);
4930 hr_reg_clear(qpc_mask, QPC_FL);
4931 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4932 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4933
4934 hr_qp->sl = sl;
4935 hr_reg_write(context, QPC_SL, hr_qp->sl);
4936 hr_reg_clear(qpc_mask, QPC_SL);
4937
4938 return 0;
4939 }
4940
check_qp_state(enum ib_qp_state cur_state,enum ib_qp_state new_state)4941 static bool check_qp_state(enum ib_qp_state cur_state,
4942 enum ib_qp_state new_state)
4943 {
4944 static const bool sm[][IB_QPS_ERR + 1] = {
4945 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4946 [IB_QPS_INIT] = true },
4947 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4948 [IB_QPS_INIT] = true,
4949 [IB_QPS_RTR] = true,
4950 [IB_QPS_ERR] = true },
4951 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4952 [IB_QPS_RTS] = true,
4953 [IB_QPS_ERR] = true },
4954 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
4955 [IB_QPS_RTS] = true,
4956 [IB_QPS_ERR] = true },
4957 [IB_QPS_SQD] = {},
4958 [IB_QPS_SQE] = {},
4959 [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
4960 [IB_QPS_ERR] = true }
4961 };
4962
4963 return sm[cur_state][new_state];
4964 }
4965
hns_roce_v2_set_abs_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)4966 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4967 const struct ib_qp_attr *attr,
4968 int attr_mask,
4969 enum ib_qp_state cur_state,
4970 enum ib_qp_state new_state,
4971 struct hns_roce_v2_qp_context *context,
4972 struct hns_roce_v2_qp_context *qpc_mask,
4973 struct ib_udata *udata)
4974 {
4975 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4976 int ret = 0;
4977
4978 if (!check_qp_state(cur_state, new_state))
4979 return -EINVAL;
4980
4981 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4982 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
4983 modify_qp_reset_to_init(ibqp, context, qpc_mask);
4984 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4985 modify_qp_init_to_init(ibqp, context, qpc_mask);
4986 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4987 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
4988 qpc_mask, udata);
4989 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4990 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask);
4991 }
4992
4993 return ret;
4994 }
4995
check_qp_timeout_cfg_range(struct hns_roce_dev * hr_dev,u8 * timeout)4996 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)
4997 {
4998 #define QP_ACK_TIMEOUT_MAX_HIP08 20
4999 #define QP_ACK_TIMEOUT_MAX 31
5000
5001 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5002 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) {
5003 ibdev_warn(&hr_dev->ib_dev,
5004 "local ACK timeout shall be 0 to 20.\n");
5005 return false;
5006 }
5007 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5008 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {
5009 if (*timeout > QP_ACK_TIMEOUT_MAX) {
5010 ibdev_warn(&hr_dev->ib_dev,
5011 "local ACK timeout shall be 0 to 31.\n");
5012 return false;
5013 }
5014 }
5015
5016 return true;
5017 }
5018
hns_roce_v2_set_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5019 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
5020 const struct ib_qp_attr *attr,
5021 int attr_mask,
5022 struct hns_roce_v2_qp_context *context,
5023 struct hns_roce_v2_qp_context *qpc_mask)
5024 {
5025 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5026 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5027 int ret = 0;
5028 u8 timeout;
5029
5030 if (attr_mask & IB_QP_AV) {
5031 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
5032 qpc_mask);
5033 if (ret)
5034 return ret;
5035 }
5036
5037 if (attr_mask & IB_QP_TIMEOUT) {
5038 timeout = attr->timeout;
5039 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) {
5040 hr_reg_write(context, QPC_AT, timeout);
5041 hr_reg_clear(qpc_mask, QPC_AT);
5042 }
5043 }
5044
5045 if (attr_mask & IB_QP_RETRY_CNT) {
5046 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
5047 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
5048
5049 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
5050 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
5051 }
5052
5053 if (attr_mask & IB_QP_RNR_RETRY) {
5054 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
5055 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
5056
5057 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
5058 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
5059 }
5060
5061 if (attr_mask & IB_QP_SQ_PSN) {
5062 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
5063 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
5064
5065 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
5066 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
5067
5068 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
5069 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
5070
5071 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
5072 attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
5073 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
5074
5075 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
5076 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
5077
5078 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
5079 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
5080 }
5081
5082 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
5083 attr->max_dest_rd_atomic) {
5084 hr_reg_write(context, QPC_RR_MAX,
5085 fls(attr->max_dest_rd_atomic - 1));
5086 hr_reg_clear(qpc_mask, QPC_RR_MAX);
5087 }
5088
5089 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
5090 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
5091 hr_reg_clear(qpc_mask, QPC_SR_MAX);
5092 }
5093
5094 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
5095 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
5096
5097 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
5098 hr_reg_write(context, QPC_MIN_RNR_TIME,
5099 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
5100 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer);
5101 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
5102 }
5103
5104 if (attr_mask & IB_QP_RQ_PSN) {
5105 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
5106 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
5107
5108 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
5109 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
5110 }
5111
5112 if (attr_mask & IB_QP_QKEY) {
5113 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5114 qpc_mask->qkey_xrcd = 0;
5115 hr_qp->qkey = attr->qkey;
5116 }
5117
5118 return ret;
5119 }
5120
hns_roce_v2_record_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask)5121 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
5122 const struct ib_qp_attr *attr,
5123 int attr_mask)
5124 {
5125 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5126 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5127
5128 if (attr_mask & IB_QP_ACCESS_FLAGS)
5129 hr_qp->atomic_rd_en = attr->qp_access_flags;
5130
5131 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
5132 hr_qp->resp_depth = attr->max_dest_rd_atomic;
5133 if (attr_mask & IB_QP_PORT) {
5134 hr_qp->port = attr->port_num - 1;
5135 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
5136 }
5137 }
5138
clear_qp(struct hns_roce_qp * hr_qp)5139 static void clear_qp(struct hns_roce_qp *hr_qp)
5140 {
5141 struct ib_qp *ibqp = &hr_qp->ibqp;
5142
5143 if (ibqp->send_cq)
5144 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
5145 hr_qp->qpn, NULL);
5146
5147 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq)
5148 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
5149 hr_qp->qpn, ibqp->srq ?
5150 to_hr_srq(ibqp->srq) : NULL);
5151
5152 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
5153 *hr_qp->rdb.db_record = 0;
5154
5155 hr_qp->rq.head = 0;
5156 hr_qp->rq.tail = 0;
5157 hr_qp->sq.head = 0;
5158 hr_qp->sq.tail = 0;
5159 hr_qp->next_sge = 0;
5160 }
5161
v2_set_flushed_fields(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5162 static void v2_set_flushed_fields(struct ib_qp *ibqp,
5163 struct hns_roce_v2_qp_context *context,
5164 struct hns_roce_v2_qp_context *qpc_mask)
5165 {
5166 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5167 unsigned long sq_flag = 0;
5168 unsigned long rq_flag = 0;
5169
5170 if (ibqp->qp_type == IB_QPT_XRC_TGT)
5171 return;
5172
5173 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
5174 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
5175 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
5176 hr_qp->state = IB_QPS_ERR;
5177 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
5178
5179 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
5180 return;
5181
5182 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
5183 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
5184 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
5185 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
5186 }
5187
hns_roce_v2_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct ib_udata * udata)5188 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
5189 const struct ib_qp_attr *attr,
5190 int attr_mask, enum ib_qp_state cur_state,
5191 enum ib_qp_state new_state, struct ib_udata *udata)
5192 {
5193 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5194 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5195 struct hns_roce_v2_qp_context ctx[2];
5196 struct hns_roce_v2_qp_context *context = ctx;
5197 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
5198 struct ib_device *ibdev = &hr_dev->ib_dev;
5199 int ret;
5200
5201 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5202 return -EOPNOTSUPP;
5203
5204 /*
5205 * In v2 engine, software pass context and context mask to hardware
5206 * when modifying qp. If software need modify some fields in context,
5207 * we should set all bits of the relevant fields in context mask to
5208 * 0 at the same time, else set them to 0x1.
5209 */
5210 memset(context, 0, hr_dev->caps.qpc_sz);
5211 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5212
5213 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5214 new_state, context, qpc_mask, udata);
5215 if (ret)
5216 goto out;
5217
5218 /* When QP state is err, SQ and RQ WQE should be flushed */
5219 if (new_state == IB_QPS_ERR)
5220 v2_set_flushed_fields(ibqp, context, qpc_mask);
5221
5222 /* Configure the optional fields */
5223 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5224 qpc_mask);
5225 if (ret)
5226 goto out;
5227
5228 hr_reg_write_bool(context, QPC_INV_CREDIT,
5229 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5230 ibqp->srq);
5231 hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5232
5233 /* Every status migrate must change state */
5234 hr_reg_write(context, QPC_QP_ST, new_state);
5235 hr_reg_clear(qpc_mask, QPC_QP_ST);
5236
5237 /* SW pass context to HW */
5238 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5239 if (ret) {
5240 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret);
5241 goto out;
5242 }
5243
5244 hr_qp->state = new_state;
5245
5246 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5247
5248 if (new_state == IB_QPS_RESET && !ibqp->uobject)
5249 clear_qp(hr_qp);
5250
5251 out:
5252 return ret;
5253 }
5254
to_ib_qp_st(enum hns_roce_v2_qp_state state)5255 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5256 {
5257 static const enum ib_qp_state map[] = {
5258 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5259 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5260 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5261 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5262 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5263 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5264 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5265 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5266 };
5267
5268 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5269 }
5270
hns_roce_v2_query_qpc(struct hns_roce_dev * hr_dev,u32 qpn,void * buffer)5271 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn,
5272 void *buffer)
5273 {
5274 struct hns_roce_cmd_mailbox *mailbox;
5275 int ret;
5276
5277 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5278 if (IS_ERR(mailbox))
5279 return PTR_ERR(mailbox);
5280
5281 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5282 qpn);
5283 if (ret)
5284 goto out;
5285
5286 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz);
5287
5288 out:
5289 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5290 return ret;
5291 }
5292
get_qp_timeout_attr(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context)5293 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev,
5294 struct hns_roce_v2_qp_context *context)
5295 {
5296 u8 timeout;
5297
5298 timeout = (u8)hr_reg_read(context, QPC_AT);
5299 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
5300 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5301
5302 return timeout;
5303 }
5304
hns_roce_v2_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)5305 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5306 int qp_attr_mask,
5307 struct ib_qp_init_attr *qp_init_attr)
5308 {
5309 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5310 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5311 struct hns_roce_v2_qp_context context = {};
5312 struct ib_device *ibdev = &hr_dev->ib_dev;
5313 int tmp_qp_state;
5314 int state;
5315 int ret;
5316
5317 memset(qp_attr, 0, sizeof(*qp_attr));
5318 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5319
5320 mutex_lock(&hr_qp->mutex);
5321
5322 if (hr_qp->state == IB_QPS_RESET) {
5323 qp_attr->qp_state = IB_QPS_RESET;
5324 ret = 0;
5325 goto done;
5326 }
5327
5328 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context);
5329 if (ret) {
5330 ibdev_err_ratelimited(ibdev,
5331 "failed to query QPC, ret = %d.\n",
5332 ret);
5333 ret = -EINVAL;
5334 goto out;
5335 }
5336
5337 state = hr_reg_read(&context, QPC_QP_ST);
5338 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5339 if (tmp_qp_state == -1) {
5340 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n");
5341 ret = -EINVAL;
5342 goto out;
5343 }
5344 hr_qp->state = (u8)tmp_qp_state;
5345 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5346 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5347 qp_attr->path_mig_state = IB_MIG_ARMED;
5348 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5349 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5350 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5351
5352 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5353 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5354 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
5355 qp_attr->qp_access_flags =
5356 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5357 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5358 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5359
5360 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5361 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5362 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5363 struct ib_global_route *grh =
5364 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5365
5366 rdma_ah_set_sl(&qp_attr->ah_attr,
5367 hr_reg_read(&context, QPC_SL));
5368 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1);
5369 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
5370 grh->flow_label = hr_reg_read(&context, QPC_FL);
5371 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5372 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5373 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5374
5375 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5376 }
5377
5378 qp_attr->port_num = hr_qp->port + 1;
5379 qp_attr->sq_draining = 0;
5380 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5381 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5382
5383 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5384 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context);
5385 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5386 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5387
5388 done:
5389 qp_attr->cur_qp_state = qp_attr->qp_state;
5390 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5391 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5392 qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5393
5394 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5395 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5396
5397 qp_init_attr->qp_context = ibqp->qp_context;
5398 qp_init_attr->qp_type = ibqp->qp_type;
5399 qp_init_attr->recv_cq = ibqp->recv_cq;
5400 qp_init_attr->send_cq = ibqp->send_cq;
5401 qp_init_attr->srq = ibqp->srq;
5402 qp_init_attr->cap = qp_attr->cap;
5403 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5404
5405 out:
5406 mutex_unlock(&hr_qp->mutex);
5407 return ret;
5408 }
5409
modify_qp_is_ok(struct hns_roce_qp * hr_qp)5410 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5411 {
5412 return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5413 hr_qp->ibqp.qp_type == IB_QPT_UD ||
5414 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5415 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5416 hr_qp->state != IB_QPS_RESET);
5417 }
5418
hns_roce_v2_destroy_qp_common(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct ib_udata * udata)5419 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5420 struct hns_roce_qp *hr_qp,
5421 struct ib_udata *udata)
5422 {
5423 struct ib_device *ibdev = &hr_dev->ib_dev;
5424 struct hns_roce_cq *send_cq, *recv_cq;
5425 unsigned long flags;
5426 int ret = 0;
5427
5428 if (modify_qp_is_ok(hr_qp)) {
5429 /* Modify qp to reset before destroying qp */
5430 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5431 hr_qp->state, IB_QPS_RESET, udata);
5432 if (ret)
5433 ibdev_err_ratelimited(ibdev,
5434 "failed to modify QP to RST, ret = %d.\n",
5435 ret);
5436 }
5437
5438 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5439 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5440
5441 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5442 hns_roce_lock_cqs(send_cq, recv_cq);
5443
5444 if (!udata) {
5445 if (recv_cq)
5446 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5447 (hr_qp->ibqp.srq ?
5448 to_hr_srq(hr_qp->ibqp.srq) :
5449 NULL));
5450
5451 if (send_cq && send_cq != recv_cq)
5452 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5453 }
5454
5455 hns_roce_qp_remove(hr_dev, hr_qp);
5456
5457 hns_roce_unlock_cqs(send_cq, recv_cq);
5458 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5459
5460 return ret;
5461 }
5462
hns_roce_v2_destroy_qp(struct ib_qp * ibqp,struct ib_udata * udata)5463 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5464 {
5465 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5466 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5467 int ret;
5468
5469 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5470 if (ret)
5471 ibdev_err_ratelimited(&hr_dev->ib_dev,
5472 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5473 hr_qp->qpn, ret);
5474
5475 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5476
5477 return 0;
5478 }
5479
hns_roce_v2_qp_flow_control_init(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)5480 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5481 struct hns_roce_qp *hr_qp)
5482 {
5483 struct ib_device *ibdev = &hr_dev->ib_dev;
5484 struct hns_roce_sccc_clr_done *resp;
5485 struct hns_roce_sccc_clr *clr;
5486 struct hns_roce_cmq_desc desc;
5487 int ret, i;
5488
5489 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5490 return 0;
5491
5492 mutex_lock(&hr_dev->qp_table.scc_mutex);
5493
5494 /* set scc ctx clear done flag */
5495 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5496 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5497 if (ret) {
5498 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5499 goto out;
5500 }
5501
5502 /* clear scc context */
5503 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5504 clr = (struct hns_roce_sccc_clr *)desc.data;
5505 clr->qpn = cpu_to_le32(hr_qp->qpn);
5506 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5507 if (ret) {
5508 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5509 goto out;
5510 }
5511
5512 /* query scc context clear is done or not */
5513 resp = (struct hns_roce_sccc_clr_done *)desc.data;
5514 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5515 hns_roce_cmq_setup_basic_desc(&desc,
5516 HNS_ROCE_OPC_QUERY_SCCC, true);
5517 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5518 if (ret) {
5519 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5520 ret);
5521 goto out;
5522 }
5523
5524 if (resp->clr_done)
5525 goto out;
5526
5527 msleep(20);
5528 }
5529
5530 ibdev_err(ibdev, "query SCC clr done flag overtime.\n");
5531 ret = -ETIMEDOUT;
5532
5533 out:
5534 mutex_unlock(&hr_dev->qp_table.scc_mutex);
5535 return ret;
5536 }
5537
5538 #define DMA_IDX_SHIFT 3
5539 #define DMA_WQE_SHIFT 3
5540
hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq * srq,struct hns_roce_srq_context * ctx)5541 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5542 struct hns_roce_srq_context *ctx)
5543 {
5544 struct hns_roce_idx_que *idx_que = &srq->idx_que;
5545 struct ib_device *ibdev = srq->ibsrq.device;
5546 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5547 u64 mtts_idx[MTT_MIN_COUNT] = {};
5548 dma_addr_t dma_handle_idx;
5549 int ret;
5550
5551 /* Get physical address of idx que buf */
5552 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5553 ARRAY_SIZE(mtts_idx));
5554 if (ret) {
5555 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5556 ret);
5557 return ret;
5558 }
5559
5560 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr);
5561
5562 hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5563 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5564
5565 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5566 hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5567 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5568
5569 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5570 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5571 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5572 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5573
5574 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5575 to_hr_hw_page_addr(mtts_idx[0]));
5576 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5577 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5578
5579 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5580 to_hr_hw_page_addr(mtts_idx[1]));
5581 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5582 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5583
5584 return 0;
5585 }
5586
hns_roce_v2_write_srqc(struct hns_roce_srq * srq,void * mb_buf)5587 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5588 {
5589 struct ib_device *ibdev = srq->ibsrq.device;
5590 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5591 struct hns_roce_srq_context *ctx = mb_buf;
5592 u64 mtts_wqe[MTT_MIN_COUNT] = {};
5593 dma_addr_t dma_handle_wqe;
5594 int ret;
5595
5596 memset(ctx, 0, sizeof(*ctx));
5597
5598 /* Get the physical address of srq buf */
5599 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5600 ARRAY_SIZE(mtts_wqe));
5601 if (ret) {
5602 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5603 ret);
5604 return ret;
5605 }
5606
5607 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr);
5608
5609 hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5610 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5611 srq->ibsrq.srq_type == IB_SRQT_XRC);
5612 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5613 hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5614 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5615 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5616 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5617 hr_reg_write(ctx, SRQC_RQWS,
5618 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5619
5620 hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5621 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5622 srq->wqe_cnt));
5623
5624 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5625 hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5626 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5627
5628 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5629 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5630 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5631 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5632
5633 return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5634 }
5635
hns_roce_v2_modify_srq(struct ib_srq * ibsrq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)5636 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5637 struct ib_srq_attr *srq_attr,
5638 enum ib_srq_attr_mask srq_attr_mask,
5639 struct ib_udata *udata)
5640 {
5641 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5642 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5643 struct hns_roce_srq_context *srq_context;
5644 struct hns_roce_srq_context *srqc_mask;
5645 struct hns_roce_cmd_mailbox *mailbox;
5646 int ret;
5647
5648 /* Resizing SRQs is not supported yet */
5649 if (srq_attr_mask & IB_SRQ_MAX_WR)
5650 return -EOPNOTSUPP;
5651
5652 if (srq_attr_mask & IB_SRQ_LIMIT) {
5653 if (srq_attr->srq_limit > srq->wqe_cnt)
5654 return -EINVAL;
5655
5656 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5657 if (IS_ERR(mailbox))
5658 return PTR_ERR(mailbox);
5659
5660 srq_context = mailbox->buf;
5661 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5662
5663 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5664
5665 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5666 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5667
5668 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5669 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
5670 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5671 if (ret) {
5672 ibdev_err(&hr_dev->ib_dev,
5673 "failed to handle cmd of modifying SRQ, ret = %d.\n",
5674 ret);
5675 return ret;
5676 }
5677 }
5678
5679 return 0;
5680 }
5681
hns_roce_v2_query_srq(struct ib_srq * ibsrq,struct ib_srq_attr * attr)5682 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5683 {
5684 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5685 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5686 struct hns_roce_srq_context *srq_context;
5687 struct hns_roce_cmd_mailbox *mailbox;
5688 int ret;
5689
5690 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5691 if (IS_ERR(mailbox))
5692 return PTR_ERR(mailbox);
5693
5694 srq_context = mailbox->buf;
5695 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5696 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
5697 if (ret) {
5698 ibdev_err(&hr_dev->ib_dev,
5699 "failed to process cmd of querying SRQ, ret = %d.\n",
5700 ret);
5701 goto out;
5702 }
5703
5704 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
5705 attr->max_wr = srq->wqe_cnt;
5706 attr->max_sge = srq->max_gs - srq->rsv_sge;
5707
5708 out:
5709 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5710 return ret;
5711 }
5712
hns_roce_v2_modify_cq(struct ib_cq * cq,u16 cq_count,u16 cq_period)5713 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5714 {
5715 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5716 struct hns_roce_v2_cq_context *cq_context;
5717 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5718 struct hns_roce_v2_cq_context *cqc_mask;
5719 struct hns_roce_cmd_mailbox *mailbox;
5720 int ret;
5721
5722 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5723 if (IS_ERR(mailbox))
5724 return PTR_ERR(mailbox);
5725
5726 cq_context = mailbox->buf;
5727 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5728
5729 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5730
5731 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
5732 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
5733
5734 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5735 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
5736 dev_info(hr_dev->dev,
5737 "cq_period(%u) reached the upper limit, adjusted to 65.\n",
5738 cq_period);
5739 cq_period = HNS_ROCE_MAX_CQ_PERIOD;
5740 }
5741 cq_period *= HNS_ROCE_CLOCK_ADJUST;
5742 }
5743 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
5744 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
5745
5746 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5747 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
5748 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5749 if (ret)
5750 ibdev_err_ratelimited(&hr_dev->ib_dev,
5751 "failed to process cmd when modifying CQ, ret = %d.\n",
5752 ret);
5753
5754 return ret;
5755 }
5756
hns_roce_v2_query_cqc(struct hns_roce_dev * hr_dev,u32 cqn,void * buffer)5757 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn,
5758 void *buffer)
5759 {
5760 struct hns_roce_v2_cq_context *context;
5761 struct hns_roce_cmd_mailbox *mailbox;
5762 int ret;
5763
5764 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5765 if (IS_ERR(mailbox))
5766 return PTR_ERR(mailbox);
5767
5768 context = mailbox->buf;
5769 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5770 HNS_ROCE_CMD_QUERY_CQC, cqn);
5771 if (ret) {
5772 ibdev_err_ratelimited(&hr_dev->ib_dev,
5773 "failed to process cmd when querying CQ, ret = %d.\n",
5774 ret);
5775 goto err_mailbox;
5776 }
5777
5778 memcpy(buffer, context, sizeof(*context));
5779
5780 err_mailbox:
5781 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5782
5783 return ret;
5784 }
5785
hns_roce_v2_query_mpt(struct hns_roce_dev * hr_dev,u32 key,void * buffer)5786 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key,
5787 void *buffer)
5788 {
5789 struct hns_roce_v2_mpt_entry *context;
5790 struct hns_roce_cmd_mailbox *mailbox;
5791 int ret;
5792
5793 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5794 if (IS_ERR(mailbox))
5795 return PTR_ERR(mailbox);
5796
5797 context = mailbox->buf;
5798 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
5799 key_to_hw_index(key));
5800 if (ret) {
5801 ibdev_err(&hr_dev->ib_dev,
5802 "failed to process cmd when querying MPT, ret = %d.\n",
5803 ret);
5804 goto err_mailbox;
5805 }
5806
5807 memcpy(buffer, context, sizeof(*context));
5808
5809 err_mailbox:
5810 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5811
5812 return ret;
5813 }
5814
dump_aeqe_log(struct hns_roce_work * irq_work)5815 static void dump_aeqe_log(struct hns_roce_work *irq_work)
5816 {
5817 struct hns_roce_dev *hr_dev = irq_work->hr_dev;
5818 struct ib_device *ibdev = &hr_dev->ib_dev;
5819
5820 switch (irq_work->event_type) {
5821 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5822 ibdev_info(ibdev, "path migrated succeeded.\n");
5823 break;
5824 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5825 ibdev_warn(ibdev, "path migration failed.\n");
5826 break;
5827 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5828 break;
5829 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5830 ibdev_dbg(ibdev, "send queue drained.\n");
5831 break;
5832 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5833 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n",
5834 irq_work->queue_num, irq_work->sub_type);
5835 break;
5836 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5837 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n",
5838 irq_work->queue_num);
5839 break;
5840 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5841 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n",
5842 irq_work->queue_num, irq_work->sub_type);
5843 break;
5844 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5845 ibdev_dbg(ibdev, "SRQ limit reach.\n");
5846 break;
5847 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5848 ibdev_dbg(ibdev, "SRQ last wqe reach.\n");
5849 break;
5850 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5851 ibdev_err(ibdev, "SRQ catas error.\n");
5852 break;
5853 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5854 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
5855 break;
5856 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5857 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
5858 break;
5859 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5860 ibdev_warn(ibdev, "DB overflow.\n");
5861 break;
5862 case HNS_ROCE_EVENT_TYPE_MB:
5863 break;
5864 case HNS_ROCE_EVENT_TYPE_FLR:
5865 ibdev_warn(ibdev, "function level reset.\n");
5866 break;
5867 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5868 ibdev_err(ibdev, "xrc domain violation error.\n");
5869 break;
5870 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5871 ibdev_err(ibdev, "invalid xrceth error.\n");
5872 break;
5873 default:
5874 ibdev_info(ibdev, "Undefined event %d.\n",
5875 irq_work->event_type);
5876 break;
5877 }
5878 }
5879
hns_roce_irq_work_handle(struct work_struct * work)5880 static void hns_roce_irq_work_handle(struct work_struct *work)
5881 {
5882 struct hns_roce_work *irq_work =
5883 container_of(work, struct hns_roce_work, work);
5884 struct hns_roce_dev *hr_dev = irq_work->hr_dev;
5885 int event_type = irq_work->event_type;
5886 u32 queue_num = irq_work->queue_num;
5887
5888 switch (event_type) {
5889 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5890 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5891 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5892 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5893 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5894 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5895 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5896 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5897 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5898 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5899 hns_roce_qp_event(hr_dev, queue_num, event_type);
5900 break;
5901 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5902 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5903 hns_roce_srq_event(hr_dev, queue_num, event_type);
5904 break;
5905 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5906 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5907 hns_roce_cq_event(hr_dev, queue_num, event_type);
5908 break;
5909 default:
5910 break;
5911 }
5912
5913 dump_aeqe_log(irq_work);
5914
5915 kfree(irq_work);
5916 }
5917
hns_roce_v2_init_irq_work(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u32 queue_num)5918 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
5919 struct hns_roce_eq *eq, u32 queue_num)
5920 {
5921 struct hns_roce_work *irq_work;
5922
5923 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5924 if (!irq_work)
5925 return;
5926
5927 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle);
5928 irq_work->hr_dev = hr_dev;
5929 irq_work->event_type = eq->event_type;
5930 irq_work->sub_type = eq->sub_type;
5931 irq_work->queue_num = queue_num;
5932 queue_work(hr_dev->irq_workq, &irq_work->work);
5933 }
5934
update_eq_db(struct hns_roce_eq * eq)5935 static void update_eq_db(struct hns_roce_eq *eq)
5936 {
5937 struct hns_roce_dev *hr_dev = eq->hr_dev;
5938 struct hns_roce_v2_db eq_db = {};
5939
5940 if (eq->type_flag == HNS_ROCE_AEQ) {
5941 hr_reg_write(&eq_db, EQ_DB_CMD,
5942 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5943 HNS_ROCE_EQ_DB_CMD_AEQ :
5944 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5945 } else {
5946 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
5947
5948 hr_reg_write(&eq_db, EQ_DB_CMD,
5949 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5950 HNS_ROCE_EQ_DB_CMD_CEQ :
5951 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5952 }
5953
5954 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
5955
5956 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
5957 }
5958
next_aeqe_sw_v2(struct hns_roce_eq * eq)5959 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5960 {
5961 struct hns_roce_aeqe *aeqe;
5962
5963 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
5964 (eq->cons_index & (eq->entries - 1)) *
5965 eq->eqe_size);
5966
5967 return (hr_reg_read(aeqe, AEQE_OWNER) ^
5968 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5969 }
5970
hns_roce_v2_aeq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)5971 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5972 struct hns_roce_eq *eq)
5973 {
5974 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
5975 irqreturn_t aeqe_found = IRQ_NONE;
5976 int num_aeqes = 0;
5977 int event_type;
5978 u32 queue_num;
5979 int sub_type;
5980
5981 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) {
5982 /* Make sure we read AEQ entry after we have checked the
5983 * ownership bit
5984 */
5985 dma_rmb();
5986
5987 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
5988 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
5989 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
5990
5991 switch (event_type) {
5992 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5993 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5994 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5995 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5996 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5997 hns_roce_flush_cqe(hr_dev, queue_num);
5998 break;
5999 case HNS_ROCE_EVENT_TYPE_MB:
6000 hns_roce_cmd_event(hr_dev,
6001 le16_to_cpu(aeqe->event.cmd.token),
6002 aeqe->event.cmd.status,
6003 le64_to_cpu(aeqe->event.cmd.out_param));
6004 break;
6005 default:
6006 break;
6007 }
6008
6009 eq->event_type = event_type;
6010 eq->sub_type = sub_type;
6011 ++eq->cons_index;
6012 aeqe_found = IRQ_HANDLED;
6013
6014 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
6015
6016 aeqe = next_aeqe_sw_v2(eq);
6017 ++num_aeqes;
6018 }
6019
6020 update_eq_db(eq);
6021
6022 return IRQ_RETVAL(aeqe_found);
6023 }
6024
next_ceqe_sw_v2(struct hns_roce_eq * eq)6025 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
6026 {
6027 struct hns_roce_ceqe *ceqe;
6028
6029 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
6030 (eq->cons_index & (eq->entries - 1)) *
6031 eq->eqe_size);
6032
6033 return (hr_reg_read(ceqe, CEQE_OWNER) ^
6034 !!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6035 }
6036
hns_roce_v2_ceq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6037 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
6038 struct hns_roce_eq *eq)
6039 {
6040 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6041 irqreturn_t ceqe_found = IRQ_NONE;
6042 u32 cqn;
6043
6044 while (ceqe) {
6045 /* Make sure we read CEQ entry after we have checked the
6046 * ownership bit
6047 */
6048 dma_rmb();
6049
6050 cqn = hr_reg_read(ceqe, CEQE_CQN);
6051
6052 hns_roce_cq_completion(hr_dev, cqn);
6053
6054 ++eq->cons_index;
6055 ceqe_found = IRQ_HANDLED;
6056
6057 ceqe = next_ceqe_sw_v2(eq);
6058 }
6059
6060 update_eq_db(eq);
6061
6062 return IRQ_RETVAL(ceqe_found);
6063 }
6064
hns_roce_v2_msix_interrupt_eq(int irq,void * eq_ptr)6065 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
6066 {
6067 struct hns_roce_eq *eq = eq_ptr;
6068 struct hns_roce_dev *hr_dev = eq->hr_dev;
6069 irqreturn_t int_work;
6070
6071 if (eq->type_flag == HNS_ROCE_CEQ)
6072 /* Completion event interrupt */
6073 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
6074 else
6075 /* Asynchronous event interrupt */
6076 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
6077
6078 return IRQ_RETVAL(int_work);
6079 }
6080
abnormal_interrupt_basic(struct hns_roce_dev * hr_dev,u32 int_st)6081 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,
6082 u32 int_st)
6083 {
6084 struct pci_dev *pdev = hr_dev->pci_dev;
6085 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
6086 const struct hnae3_ae_ops *ops = ae_dev->ops;
6087 enum hnae3_reset_type reset_type;
6088 irqreturn_t int_work = IRQ_NONE;
6089 u32 int_en;
6090
6091 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
6092
6093 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
6094 dev_err(hr_dev->dev, "AEQ overflow!\n");
6095
6096 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
6097 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
6098
6099 reset_type = hr_dev->is_vf ?
6100 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET;
6101
6102 /* Set reset level for reset_event() */
6103 if (ops->set_default_reset_request)
6104 ops->set_default_reset_request(ae_dev, reset_type);
6105 if (ops->reset_event)
6106 ops->reset_event(pdev, NULL);
6107
6108 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
6109 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
6110
6111 int_work = IRQ_HANDLED;
6112 } else {
6113 dev_err(hr_dev->dev, "there is no basic abn irq found.\n");
6114 }
6115
6116 return IRQ_RETVAL(int_work);
6117 }
6118
fmea_ram_ecc_query(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6119 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev,
6120 struct fmea_ram_ecc *ecc_info)
6121 {
6122 struct hns_roce_cmq_desc desc;
6123 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6124 int ret;
6125
6126 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true);
6127 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6128 if (ret)
6129 return ret;
6130
6131 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
6132 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
6133 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
6134
6135 return 0;
6136 }
6137
fmea_recover_gmv(struct hns_roce_dev * hr_dev,u32 idx)6138 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx)
6139 {
6140 struct hns_roce_cmq_desc desc;
6141 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6142 u32 addr_upper;
6143 u32 addr_low;
6144 int ret;
6145
6146 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true);
6147 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6148
6149 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6150 if (ret) {
6151 dev_err(hr_dev->dev,
6152 "failed to execute cmd to read gmv, ret = %d.\n", ret);
6153 return ret;
6154 }
6155
6156 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L);
6157 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
6158
6159 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
6160 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low);
6161 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper);
6162 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6163
6164 return hns_roce_cmq_send(hr_dev, &desc, 1);
6165 }
6166
fmea_get_ram_res_addr(u32 res_type,__le64 * data)6167 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data)
6168 {
6169 if (res_type == ECC_RESOURCE_QPC_TIMER ||
6170 res_type == ECC_RESOURCE_CQC_TIMER ||
6171 res_type == ECC_RESOURCE_SCCC)
6172 return le64_to_cpu(*data);
6173
6174 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT;
6175 }
6176
fmea_recover_others(struct hns_roce_dev * hr_dev,u32 res_type,u32 index)6177 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type,
6178 u32 index)
6179 {
6180 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op;
6181 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op;
6182 struct hns_roce_cmd_mailbox *mailbox;
6183 u64 addr;
6184 int ret;
6185
6186 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6187 if (IS_ERR(mailbox))
6188 return PTR_ERR(mailbox);
6189
6190 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index);
6191 if (ret) {
6192 dev_err(hr_dev->dev,
6193 "failed to execute cmd to read fmea ram, ret = %d.\n",
6194 ret);
6195 goto out;
6196 }
6197
6198 addr = fmea_get_ram_res_addr(res_type, mailbox->buf);
6199
6200 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index);
6201 if (ret)
6202 dev_err(hr_dev->dev,
6203 "failed to execute cmd to write fmea ram, ret = %d.\n",
6204 ret);
6205
6206 out:
6207 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6208 return ret;
6209 }
6210
fmea_ram_ecc_recover(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6211 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev,
6212 struct fmea_ram_ecc *ecc_info)
6213 {
6214 u32 res_type = ecc_info->res_type;
6215 u32 index = ecc_info->index;
6216 int ret;
6217
6218 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT);
6219
6220 if (res_type >= ECC_RESOURCE_COUNT) {
6221 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n",
6222 res_type);
6223 return;
6224 }
6225
6226 if (res_type == ECC_RESOURCE_GMV)
6227 ret = fmea_recover_gmv(hr_dev, index);
6228 else
6229 ret = fmea_recover_others(hr_dev, res_type, index);
6230 if (ret)
6231 dev_err(hr_dev->dev,
6232 "failed to recover %s, index = %u, ret = %d.\n",
6233 fmea_ram_res[res_type].name, index, ret);
6234 }
6235
fmea_ram_ecc_work(struct work_struct * ecc_work)6236 static void fmea_ram_ecc_work(struct work_struct *ecc_work)
6237 {
6238 struct hns_roce_dev *hr_dev =
6239 container_of(ecc_work, struct hns_roce_dev, ecc_work);
6240 struct fmea_ram_ecc ecc_info = {};
6241
6242 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) {
6243 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n");
6244 return;
6245 }
6246
6247 if (!ecc_info.is_ecc_err) {
6248 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n");
6249 return;
6250 }
6251
6252 fmea_ram_ecc_recover(hr_dev, &ecc_info);
6253 }
6254
hns_roce_v2_msix_interrupt_abn(int irq,void * dev_id)6255 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
6256 {
6257 struct hns_roce_dev *hr_dev = dev_id;
6258 irqreturn_t int_work = IRQ_NONE;
6259 u32 int_st;
6260
6261 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
6262
6263 if (int_st) {
6264 int_work = abnormal_interrupt_basic(hr_dev, int_st);
6265 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
6266 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work);
6267 int_work = IRQ_HANDLED;
6268 } else {
6269 dev_err(hr_dev->dev, "there is no abnormal irq found.\n");
6270 }
6271
6272 return IRQ_RETVAL(int_work);
6273 }
6274
hns_roce_v2_int_mask_enable(struct hns_roce_dev * hr_dev,int eq_num,u32 enable_flag)6275 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
6276 int eq_num, u32 enable_flag)
6277 {
6278 int i;
6279
6280 for (i = 0; i < eq_num; i++)
6281 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
6282 i * EQ_REG_OFFSET, enable_flag);
6283
6284 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
6285 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6286 }
6287
free_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6288 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6289 {
6290 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6291 }
6292
hns_roce_v2_destroy_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6293 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev,
6294 struct hns_roce_eq *eq)
6295 {
6296 struct device *dev = hr_dev->dev;
6297 int eqn = eq->eqn;
6298 int ret;
6299 u8 cmd;
6300
6301 if (eqn < hr_dev->caps.num_comp_vectors)
6302 cmd = HNS_ROCE_CMD_DESTROY_CEQC;
6303 else
6304 cmd = HNS_ROCE_CMD_DESTROY_AEQC;
6305
6306 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6307 if (ret)
6308 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
6309
6310 free_eq_buf(hr_dev, eq);
6311 }
6312
init_eq_config(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6313 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6314 {
6315 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
6316 eq->cons_index = 0;
6317 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
6318 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
6319 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
6320 eq->shift = ilog2((unsigned int)eq->entries);
6321 }
6322
config_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,void * mb_buf)6323 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
6324 void *mb_buf)
6325 {
6326 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
6327 struct hns_roce_eq_context *eqc;
6328 u64 bt_ba = 0;
6329 int ret;
6330
6331 eqc = mb_buf;
6332 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
6333
6334 init_eq_config(hr_dev, eq);
6335
6336 /* if not multi-hop, eqe buffer only use one trunk */
6337 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba,
6338 ARRAY_SIZE(eqe_ba));
6339 if (ret) {
6340 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret);
6341 return ret;
6342 }
6343
6344 bt_ba = hns_roce_get_mtr_ba(&eq->mtr);
6345
6346 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
6347 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
6348 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
6349 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
6350 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
6351 hr_reg_write(eqc, EQC_EQN, eq->eqn);
6352 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
6353 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
6354 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
6355 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
6356 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
6357 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
6358 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
6359
6360 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6361 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6362 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n",
6363 eq->eq_period);
6364 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD;
6365 }
6366 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST;
6367 }
6368
6369 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
6370 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
6371 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
6372 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
6373 hr_reg_write(eqc, EQC_SHIFT, eq->shift);
6374 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
6375 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
6376 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
6377 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
6378 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
6379 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
6380 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
6381 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
6382
6383 return 0;
6384 }
6385
alloc_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6386 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6387 {
6388 struct hns_roce_buf_attr buf_attr = {};
6389 int err;
6390
6391 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
6392 eq->hop_num = 0;
6393 else
6394 eq->hop_num = hr_dev->caps.eqe_hop_num;
6395
6396 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
6397 buf_attr.region[0].size = eq->entries * eq->eqe_size;
6398 buf_attr.region[0].hopnum = eq->hop_num;
6399 buf_attr.region_count = 1;
6400
6401 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
6402 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
6403 0);
6404 if (err)
6405 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err);
6406
6407 return err;
6408 }
6409
hns_roce_v2_create_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u8 eq_cmd)6410 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
6411 struct hns_roce_eq *eq, u8 eq_cmd)
6412 {
6413 struct hns_roce_cmd_mailbox *mailbox;
6414 int ret;
6415
6416 /* Allocate mailbox memory */
6417 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6418 if (IS_ERR(mailbox))
6419 return PTR_ERR(mailbox);
6420
6421 ret = alloc_eq_buf(hr_dev, eq);
6422 if (ret)
6423 goto free_cmd_mbox;
6424
6425 ret = config_eqc(hr_dev, eq, mailbox->buf);
6426 if (ret)
6427 goto err_cmd_mbox;
6428
6429 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6430 if (ret) {
6431 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6432 goto err_cmd_mbox;
6433 }
6434
6435 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6436
6437 return 0;
6438
6439 err_cmd_mbox:
6440 free_eq_buf(hr_dev, eq);
6441
6442 free_cmd_mbox:
6443 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6444
6445 return ret;
6446 }
6447
__hns_roce_request_irq(struct hns_roce_dev * hr_dev,int irq_num,int comp_num,int aeq_num,int other_num)6448 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6449 int comp_num, int aeq_num, int other_num)
6450 {
6451 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6452 int i, j;
6453 int ret;
6454
6455 for (i = 0; i < irq_num; i++) {
6456 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6457 GFP_KERNEL);
6458 if (!hr_dev->irq_names[i]) {
6459 ret = -ENOMEM;
6460 goto err_kzalloc_failed;
6461 }
6462 }
6463
6464 /* irq contains: abnormal + AEQ + CEQ */
6465 for (j = 0; j < other_num; j++)
6466 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6467 "hns-abn-%d", j);
6468
6469 for (j = other_num; j < (other_num + aeq_num); j++)
6470 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6471 "hns-aeq-%d", j - other_num);
6472
6473 for (j = (other_num + aeq_num); j < irq_num; j++)
6474 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6475 "hns-ceq-%d", j - other_num - aeq_num);
6476
6477 for (j = 0; j < irq_num; j++) {
6478 if (j < other_num)
6479 ret = request_irq(hr_dev->irq[j],
6480 hns_roce_v2_msix_interrupt_abn,
6481 0, hr_dev->irq_names[j], hr_dev);
6482
6483 else if (j < (other_num + comp_num))
6484 ret = request_irq(eq_table->eq[j - other_num].irq,
6485 hns_roce_v2_msix_interrupt_eq,
6486 0, hr_dev->irq_names[j + aeq_num],
6487 &eq_table->eq[j - other_num]);
6488 else
6489 ret = request_irq(eq_table->eq[j - other_num].irq,
6490 hns_roce_v2_msix_interrupt_eq,
6491 0, hr_dev->irq_names[j - comp_num],
6492 &eq_table->eq[j - other_num]);
6493 if (ret) {
6494 dev_err(hr_dev->dev, "request irq error!\n");
6495 goto err_request_failed;
6496 }
6497 }
6498
6499 return 0;
6500
6501 err_request_failed:
6502 for (j -= 1; j >= 0; j--)
6503 if (j < other_num)
6504 free_irq(hr_dev->irq[j], hr_dev);
6505 else
6506 free_irq(eq_table->eq[j - other_num].irq,
6507 &eq_table->eq[j - other_num]);
6508
6509 err_kzalloc_failed:
6510 for (i -= 1; i >= 0; i--)
6511 kfree(hr_dev->irq_names[i]);
6512
6513 return ret;
6514 }
6515
__hns_roce_free_irq(struct hns_roce_dev * hr_dev)6516 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6517 {
6518 int irq_num;
6519 int eq_num;
6520 int i;
6521
6522 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6523 irq_num = eq_num + hr_dev->caps.num_other_vectors;
6524
6525 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6526 free_irq(hr_dev->irq[i], hr_dev);
6527
6528 for (i = 0; i < eq_num; i++)
6529 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6530
6531 for (i = 0; i < irq_num; i++)
6532 kfree(hr_dev->irq_names[i]);
6533 }
6534
hns_roce_v2_init_eq_table(struct hns_roce_dev * hr_dev)6535 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6536 {
6537 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6538 struct device *dev = hr_dev->dev;
6539 struct hns_roce_eq *eq;
6540 int other_num;
6541 int comp_num;
6542 int aeq_num;
6543 int irq_num;
6544 int eq_num;
6545 u8 eq_cmd;
6546 int ret;
6547 int i;
6548
6549 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET)
6550 return -EINVAL;
6551
6552 other_num = hr_dev->caps.num_other_vectors;
6553 comp_num = hr_dev->caps.num_comp_vectors;
6554 aeq_num = hr_dev->caps.num_aeq_vectors;
6555
6556 eq_num = comp_num + aeq_num;
6557 irq_num = eq_num + other_num;
6558
6559 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6560 if (!eq_table->eq)
6561 return -ENOMEM;
6562
6563 /* create eq */
6564 for (i = 0; i < eq_num; i++) {
6565 eq = &eq_table->eq[i];
6566 eq->hr_dev = hr_dev;
6567 eq->eqn = i;
6568 if (i < comp_num) {
6569 /* CEQ */
6570 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6571 eq->type_flag = HNS_ROCE_CEQ;
6572 eq->entries = hr_dev->caps.ceqe_depth;
6573 eq->eqe_size = hr_dev->caps.ceqe_size;
6574 eq->irq = hr_dev->irq[i + other_num + aeq_num];
6575 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6576 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6577 } else {
6578 /* AEQ */
6579 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6580 eq->type_flag = HNS_ROCE_AEQ;
6581 eq->entries = hr_dev->caps.aeqe_depth;
6582 eq->eqe_size = hr_dev->caps.aeqe_size;
6583 eq->irq = hr_dev->irq[i - comp_num + other_num];
6584 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6585 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6586 }
6587
6588 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6589 if (ret) {
6590 dev_err(dev, "failed to create eq.\n");
6591 goto err_create_eq_fail;
6592 }
6593 }
6594
6595 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work);
6596
6597 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6598 if (!hr_dev->irq_workq) {
6599 dev_err(dev, "failed to create irq workqueue.\n");
6600 ret = -ENOMEM;
6601 goto err_create_eq_fail;
6602 }
6603
6604 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num,
6605 other_num);
6606 if (ret) {
6607 dev_err(dev, "failed to request irq.\n");
6608 goto err_request_irq_fail;
6609 }
6610
6611 /* enable irq */
6612 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6613
6614 return 0;
6615
6616 err_request_irq_fail:
6617 destroy_workqueue(hr_dev->irq_workq);
6618
6619 err_create_eq_fail:
6620 for (i -= 1; i >= 0; i--)
6621 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6622 kfree(eq_table->eq);
6623
6624 return ret;
6625 }
6626
hns_roce_v2_cleanup_eq_table(struct hns_roce_dev * hr_dev)6627 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6628 {
6629 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6630 int eq_num;
6631 int i;
6632
6633 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6634
6635 /* Disable irq */
6636 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6637
6638 __hns_roce_free_irq(hr_dev);
6639 destroy_workqueue(hr_dev->irq_workq);
6640
6641 for (i = 0; i < eq_num; i++)
6642 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6643
6644 kfree(eq_table->eq);
6645 }
6646
6647 static const struct ib_device_ops hns_roce_v2_dev_ops = {
6648 .destroy_qp = hns_roce_v2_destroy_qp,
6649 .modify_cq = hns_roce_v2_modify_cq,
6650 .poll_cq = hns_roce_v2_poll_cq,
6651 .post_recv = hns_roce_v2_post_recv,
6652 .post_send = hns_roce_v2_post_send,
6653 .query_qp = hns_roce_v2_query_qp,
6654 .req_notify_cq = hns_roce_v2_req_notify_cq,
6655 };
6656
6657 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6658 .modify_srq = hns_roce_v2_modify_srq,
6659 .post_srq_recv = hns_roce_v2_post_srq_recv,
6660 .query_srq = hns_roce_v2_query_srq,
6661 };
6662
6663 static const struct hns_roce_hw hns_roce_hw_v2 = {
6664 .cmq_init = hns_roce_v2_cmq_init,
6665 .cmq_exit = hns_roce_v2_cmq_exit,
6666 .hw_profile = hns_roce_v2_profile,
6667 .hw_init = hns_roce_v2_init,
6668 .hw_exit = hns_roce_v2_exit,
6669 .post_mbox = v2_post_mbox,
6670 .poll_mbox_done = v2_poll_mbox_done,
6671 .chk_mbox_avail = v2_chk_mbox_is_avail,
6672 .set_gid = hns_roce_v2_set_gid,
6673 .set_mac = hns_roce_v2_set_mac,
6674 .write_mtpt = hns_roce_v2_write_mtpt,
6675 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6676 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6677 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6678 .write_cqc = hns_roce_v2_write_cqc,
6679 .set_hem = hns_roce_v2_set_hem,
6680 .clear_hem = hns_roce_v2_clear_hem,
6681 .modify_qp = hns_roce_v2_modify_qp,
6682 .dereg_mr = hns_roce_v2_dereg_mr,
6683 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6684 .init_eq = hns_roce_v2_init_eq_table,
6685 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6686 .write_srqc = hns_roce_v2_write_srqc,
6687 .query_cqc = hns_roce_v2_query_cqc,
6688 .query_qpc = hns_roce_v2_query_qpc,
6689 .query_mpt = hns_roce_v2_query_mpt,
6690 .query_hw_counter = hns_roce_hw_v2_query_counter,
6691 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6692 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6693 };
6694
6695 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6696 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6697 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
6698 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6699 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
6700 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6701 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
6702 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
6703 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
6704 /* required last entry */
6705 {0, }
6706 };
6707
6708 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6709
hns_roce_hw_v2_get_cfg(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)6710 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6711 struct hnae3_handle *handle)
6712 {
6713 struct hns_roce_v2_priv *priv = hr_dev->priv;
6714 const struct pci_device_id *id;
6715 int i;
6716
6717 hr_dev->pci_dev = handle->pdev;
6718 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
6719 hr_dev->is_vf = id->driver_data;
6720 hr_dev->dev = &handle->pdev->dev;
6721 hr_dev->hw = &hns_roce_hw_v2;
6722 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6723 hr_dev->odb_offset = hr_dev->sdb_offset;
6724
6725 /* Get info from NIC driver. */
6726 hr_dev->reg_base = handle->rinfo.roce_io_base;
6727 hr_dev->mem_base = handle->rinfo.roce_mem_base;
6728 hr_dev->caps.num_ports = 1;
6729 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6730 hr_dev->iboe.phy_port[0] = 0;
6731
6732 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6733 hr_dev->iboe.netdevs[0]->dev_addr);
6734
6735 for (i = 0; i < handle->rinfo.num_vectors; i++)
6736 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6737 i + handle->rinfo.base_vector);
6738
6739 /* cmd issue mode: 0 is poll, 1 is event */
6740 hr_dev->cmd_mod = 1;
6741 hr_dev->loop_idc = 0;
6742
6743 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6744 priv->handle = handle;
6745 }
6746
__hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)6747 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6748 {
6749 struct hns_roce_dev *hr_dev;
6750 int ret;
6751
6752 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
6753 if (!hr_dev)
6754 return -ENOMEM;
6755
6756 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6757 if (!hr_dev->priv) {
6758 ret = -ENOMEM;
6759 goto error_failed_kzalloc;
6760 }
6761
6762 hns_roce_hw_v2_get_cfg(hr_dev, handle);
6763
6764 ret = hns_roce_init(hr_dev);
6765 if (ret) {
6766 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6767 goto error_failed_roce_init;
6768 }
6769
6770 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6771 ret = free_mr_init(hr_dev);
6772 if (ret) {
6773 dev_err(hr_dev->dev, "failed to init free mr!\n");
6774 goto error_failed_free_mr_init;
6775 }
6776 }
6777
6778 handle->priv = hr_dev;
6779
6780 return 0;
6781
6782 error_failed_free_mr_init:
6783 hns_roce_exit(hr_dev);
6784
6785 error_failed_roce_init:
6786 kfree(hr_dev->priv);
6787
6788 error_failed_kzalloc:
6789 ib_dealloc_device(&hr_dev->ib_dev);
6790
6791 return ret;
6792 }
6793
__hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)6794 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6795 bool reset)
6796 {
6797 struct hns_roce_dev *hr_dev = handle->priv;
6798
6799 if (!hr_dev)
6800 return;
6801
6802 handle->priv = NULL;
6803
6804 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6805 hns_roce_handle_device_err(hr_dev);
6806
6807 hns_roce_exit(hr_dev);
6808 kfree(hr_dev->priv);
6809 ib_dealloc_device(&hr_dev->ib_dev);
6810 }
6811
hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)6812 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6813 {
6814 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6815 const struct pci_device_id *id;
6816 struct device *dev = &handle->pdev->dev;
6817 int ret;
6818
6819 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6820
6821 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6822 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6823 goto reset_chk_err;
6824 }
6825
6826 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6827 if (!id)
6828 return 0;
6829
6830 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
6831 return 0;
6832
6833 ret = __hns_roce_hw_v2_init_instance(handle);
6834 if (ret) {
6835 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6836 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6837 if (ops->ae_dev_resetting(handle) ||
6838 ops->get_hw_reset_stat(handle))
6839 goto reset_chk_err;
6840 else
6841 return ret;
6842 }
6843
6844 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6845
6846 return 0;
6847
6848 reset_chk_err:
6849 dev_err(dev, "Device is busy in resetting state.\n"
6850 "please retry later.\n");
6851
6852 return -EBUSY;
6853 }
6854
hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)6855 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6856 bool reset)
6857 {
6858 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6859 return;
6860
6861 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6862
6863 __hns_roce_hw_v2_uninit_instance(handle, reset);
6864
6865 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6866 }
hns_roce_hw_v2_reset_notify_down(struct hnae3_handle * handle)6867 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6868 {
6869 struct hns_roce_dev *hr_dev;
6870
6871 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6872 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6873 return 0;
6874 }
6875
6876 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6877 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6878
6879 hr_dev = handle->priv;
6880 if (!hr_dev)
6881 return 0;
6882
6883 hr_dev->active = false;
6884 hr_dev->dis_db = true;
6885 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
6886
6887 return 0;
6888 }
6889
hns_roce_hw_v2_reset_notify_init(struct hnae3_handle * handle)6890 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6891 {
6892 struct device *dev = &handle->pdev->dev;
6893 int ret;
6894
6895 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6896 &handle->rinfo.state)) {
6897 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6898 return 0;
6899 }
6900
6901 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6902
6903 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6904 ret = __hns_roce_hw_v2_init_instance(handle);
6905 if (ret) {
6906 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6907 * callback function, RoCE Engine reinitialize. If RoCE reinit
6908 * failed, we should inform NIC driver.
6909 */
6910 handle->priv = NULL;
6911 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6912 } else {
6913 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6914 dev_info(dev, "reset done, RoCE client reinit finished.\n");
6915 }
6916
6917 return ret;
6918 }
6919
hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle * handle)6920 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6921 {
6922 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6923 return 0;
6924
6925 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6926 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
6927 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
6928 __hns_roce_hw_v2_uninit_instance(handle, false);
6929
6930 return 0;
6931 }
6932
hns_roce_hw_v2_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)6933 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6934 enum hnae3_reset_notify_type type)
6935 {
6936 int ret = 0;
6937
6938 switch (type) {
6939 case HNAE3_DOWN_CLIENT:
6940 ret = hns_roce_hw_v2_reset_notify_down(handle);
6941 break;
6942 case HNAE3_INIT_CLIENT:
6943 ret = hns_roce_hw_v2_reset_notify_init(handle);
6944 break;
6945 case HNAE3_UNINIT_CLIENT:
6946 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6947 break;
6948 default:
6949 break;
6950 }
6951
6952 return ret;
6953 }
6954
6955 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6956 .init_instance = hns_roce_hw_v2_init_instance,
6957 .uninit_instance = hns_roce_hw_v2_uninit_instance,
6958 .reset_notify = hns_roce_hw_v2_reset_notify,
6959 };
6960
6961 static struct hnae3_client hns_roce_hw_v2_client = {
6962 .name = "hns_roce_hw_v2",
6963 .type = HNAE3_CLIENT_ROCE,
6964 .ops = &hns_roce_hw_v2_ops,
6965 };
6966
hns_roce_hw_v2_init(void)6967 static int __init hns_roce_hw_v2_init(void)
6968 {
6969 return hnae3_register_client(&hns_roce_hw_v2_client);
6970 }
6971
hns_roce_hw_v2_exit(void)6972 static void __exit hns_roce_hw_v2_exit(void)
6973 {
6974 hnae3_unregister_client(&hns_roce_hw_v2_client);
6975 }
6976
6977 module_init(hns_roce_hw_v2_init);
6978 module_exit(hns_roce_hw_v2_exit);
6979
6980 MODULE_LICENSE("Dual BSD/GPL");
6981 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6982 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6983 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6984 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
6985