xref: /openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1  /*
2   * Copyright 2017 Advanced Micro Devices, Inc.
3   *
4   * Permission is hereby granted, free of charge, to any person obtaining a
5   * copy of this software and associated documentation files (the "Software"),
6   * to deal in the Software without restriction, including without limitation
7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8   * and/or sell copies of the Software, and to permit persons to whom the
9   * Software is furnished to do so, subject to the following conditions:
10   *
11   * The above copyright notice and this permission notice shall be included in
12   * all copies or substantial portions of the Software.
13   *
14   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17   * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18   * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19   * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20   * OTHER DEALINGS IN THE SOFTWARE.
21   *
22   */
23  /*
24   * link_encoder.h
25   *
26   *  Created on: Oct 6, 2015
27   *      Author: yonsun
28   */
29  
30  #ifndef LINK_ENCODER_H_
31  #define LINK_ENCODER_H_
32  
33  #include "grph_object_defs.h"
34  #include "signal_types.h"
35  #include "dc_types.h"
36  
37  struct dc_context;
38  struct encoder_set_dp_phy_pattern_param;
39  struct link_mst_stream_allocation_table;
40  struct dc_link_settings;
41  struct link_training_settings;
42  struct pipe_ctx;
43  
44  struct encoder_init_data {
45  	enum channel_id channel;
46  	struct graphics_object_id connector;
47  	enum hpd_source_id hpd_source;
48  	/* TODO: in DAL2, here was pointer to EventManagerInterface */
49  	struct graphics_object_id encoder;
50  	struct dc_context *ctx;
51  	enum transmitter transmitter;
52  };
53  
54  struct encoder_feature_support {
55  	union {
56  		struct {
57  			uint32_t IS_HBR2_CAPABLE:1;
58  			uint32_t IS_HBR3_CAPABLE:1;
59  			uint32_t IS_TPS3_CAPABLE:1;
60  			uint32_t IS_TPS4_CAPABLE:1;
61  			uint32_t HDMI_6GB_EN:1;
62  			uint32_t IS_DP2_CAPABLE:1;
63  			uint32_t IS_UHBR10_CAPABLE:1;
64  			uint32_t IS_UHBR13_5_CAPABLE:1;
65  			uint32_t IS_UHBR20_CAPABLE:1;
66  			uint32_t DP_IS_USB_C:1;
67  		} bits;
68  		uint32_t raw;
69  	} flags;
70  
71  	enum dc_color_depth max_hdmi_deep_color;
72  	unsigned int max_hdmi_pixel_clock;
73  	bool hdmi_ycbcr420_supported;
74  	bool dp_ycbcr420_supported;
75  	bool fec_supported;
76  };
77  
78  struct link_encoder {
79  	const struct link_encoder_funcs *funcs;
80  	int32_t aux_channel_offset;
81  	struct dc_context *ctx;
82  	struct graphics_object_id id;
83  	struct graphics_object_id connector;
84  	uint32_t output_signals;
85  	enum engine_id preferred_engine;
86  	struct encoder_feature_support features;
87  	enum transmitter transmitter;
88  	enum hpd_source_id hpd_source;
89  	bool usbc_combo_phy;
90  };
91  
92  struct link_enc_state {
93  
94  		uint32_t dphy_fec_en;
95  		uint32_t dphy_fec_ready_shadow;
96  		uint32_t dphy_fec_active_status;
97  		uint32_t dp_link_training_complete;
98  
99  };
100  
101  enum encoder_type_select {
102  	ENCODER_TYPE_DIG = 0,
103  	ENCODER_TYPE_HDMI_FRL = 1,
104  	ENCODER_TYPE_DP_128B132B = 2
105  };
106  
107  struct link_encoder_funcs {
108  	void (*read_state)(
109  			struct link_encoder *enc, struct link_enc_state *s);
110  	bool (*validate_output_with_stream)(
111  		struct link_encoder *enc, const struct dc_stream_state *stream);
112  	void (*hw_init)(struct link_encoder *enc);
113  	void (*setup)(struct link_encoder *enc,
114  		enum signal_type signal);
115  	void (*enable_tmds_output)(struct link_encoder *enc,
116  		enum clock_source_id clock_source,
117  		enum dc_color_depth color_depth,
118  		enum signal_type signal,
119  		uint32_t pixel_clock);
120  	void (*enable_dp_output)(struct link_encoder *enc,
121  		const struct dc_link_settings *link_settings,
122  		enum clock_source_id clock_source);
123  	void (*enable_dp_mst_output)(struct link_encoder *enc,
124  		const struct dc_link_settings *link_settings,
125  		enum clock_source_id clock_source);
126  	void (*enable_lvds_output)(struct link_encoder *enc,
127  		enum clock_source_id clock_source,
128  		uint32_t pixel_clock);
129  	void (*disable_output)(struct link_encoder *link_enc,
130  		enum signal_type signal);
131  	void (*dp_set_lane_settings)(struct link_encoder *enc,
132  		const struct dc_link_settings *link_settings,
133  		const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
134  	void (*dp_set_phy_pattern)(struct link_encoder *enc,
135  		const struct encoder_set_dp_phy_pattern_param *para);
136  	void (*update_mst_stream_allocation_table)(
137  		struct link_encoder *enc,
138  		const struct link_mst_stream_allocation_table *table);
139  	void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc,
140  			bool exit_link_training_required);
141  	void (*psr_program_secondary_packet)(struct link_encoder *enc,
142  				unsigned int sdp_transmit_line_num_deadline);
143  	void (*connect_dig_be_to_fe)(struct link_encoder *enc,
144  		enum engine_id engine,
145  		bool connect);
146  	void (*enable_hpd)(struct link_encoder *enc);
147  	void (*disable_hpd)(struct link_encoder *enc);
148  	bool (*is_dig_enabled)(struct link_encoder *enc);
149  	unsigned int (*get_dig_frontend)(struct link_encoder *enc);
150  	void (*destroy)(struct link_encoder **enc);
151  
152  	void (*fec_set_enable)(struct link_encoder *enc,
153  		bool enable);
154  
155  	void (*fec_set_ready)(struct link_encoder *enc,
156  		bool ready);
157  
158  	bool (*fec_is_active)(struct link_encoder *enc);
159  	bool (*is_in_alt_mode) (struct link_encoder *enc);
160  
161  	void (*get_max_link_cap)(struct link_encoder *enc,
162  		struct dc_link_settings *link_settings);
163  
164  	enum signal_type (*get_dig_mode)(
165  		struct link_encoder *enc);
166  	void (*set_dio_phy_mux)(
167  		struct link_encoder *enc,
168  		enum encoder_type_select sel,
169  		uint32_t hpo_inst);
170  	void (*set_dig_output_mode)(
171  			struct link_encoder *enc, uint8_t pix_per_container);
172  };
173  
174  /*
175   * Used to track assignments of links (display endpoints) to link encoders.
176   *
177   * Entry in link_enc_assignments table in struct resource_context.
178   * Entries only marked valid once encoder assigned to a link and invalidated once unassigned.
179   * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint.
180   */
181  struct link_enc_assignment {
182  	bool valid;
183  	struct display_endpoint_id ep_id;
184  	enum engine_id eng_id;
185  	struct dc_stream_state *stream;
186  };
187  
188  enum link_enc_cfg_mode {
189  	LINK_ENC_CFG_STEADY, /* Normal operation - use current_state. */
190  	LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */
191  };
192  
193  enum dp2_link_mode {
194  	DP2_LINK_TRAINING_TPS1,
195  	DP2_LINK_TRAINING_TPS2,
196  	DP2_LINK_ACTIVE,
197  	DP2_TEST_PATTERN
198  };
199  
200  enum dp2_phy_tp_select {
201  	DP_DPHY_TP_SELECT_TPS1,
202  	DP_DPHY_TP_SELECT_TPS2,
203  	DP_DPHY_TP_SELECT_PRBS,
204  	DP_DPHY_TP_SELECT_CUSTOM,
205  	DP_DPHY_TP_SELECT_SQUARE
206  };
207  
208  enum dp2_phy_tp_prbs {
209  	DP_DPHY_TP_PRBS7,
210  	DP_DPHY_TP_PRBS9,
211  	DP_DPHY_TP_PRBS11,
212  	DP_DPHY_TP_PRBS15,
213  	DP_DPHY_TP_PRBS23,
214  	DP_DPHY_TP_PRBS31
215  };
216  
217  struct hpo_dp_link_enc_state {
218  	uint32_t   link_enc_enabled;
219  	uint32_t   link_mode;
220  	uint32_t   lane_count;
221  	uint32_t   slot_count[4];
222  	uint32_t   stream_src[4];
223  	uint32_t   vc_rate_x[4];
224  	uint32_t   vc_rate_y[4];
225  };
226  
227  struct hpo_dp_link_encoder {
228  	const struct hpo_dp_link_encoder_funcs *funcs;
229  	struct dc_context *ctx;
230  	int inst;
231  	enum engine_id preferred_engine;
232  	enum transmitter transmitter;
233  	enum hpd_source_id hpd_source;
234  };
235  
236  struct hpo_dp_link_encoder_funcs {
237  
238  	void (*enable_link_phy)(struct hpo_dp_link_encoder *enc,
239  		const struct dc_link_settings *link_settings,
240  		enum transmitter transmitter,
241  		enum hpd_source_id hpd_source);
242  
243  	void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc,
244  		enum signal_type signal);
245  
246  	void (*link_enable)(
247  			struct hpo_dp_link_encoder *enc,
248  			enum dc_lane_count num_lanes);
249  
250  	void (*link_disable)(
251  			struct hpo_dp_link_encoder *enc);
252  
253  	void (*set_link_test_pattern)(
254  			struct hpo_dp_link_encoder *enc,
255  			struct encoder_set_dp_phy_pattern_param *tp_params);
256  
257  	void (*update_stream_allocation_table)(
258  			struct hpo_dp_link_encoder *enc,
259  			const struct link_mst_stream_allocation_table *table);
260  
261  	void (*set_throttled_vcp_size)(
262  			struct hpo_dp_link_encoder *enc,
263  			uint32_t stream_encoder_inst,
264  			struct fixed31_32 avg_time_slots_per_mtp);
265  
266  	bool (*is_in_alt_mode) (
267  			struct hpo_dp_link_encoder *enc);
268  
269  	void (*read_state)(
270  			struct hpo_dp_link_encoder *enc,
271  			struct hpo_dp_link_enc_state *state);
272  
273  	void (*set_ffe)(
274  		struct hpo_dp_link_encoder *enc,
275  		const struct dc_link_settings *link_settings,
276  		uint8_t ffe_preset);
277  };
278  
279  #endif /* LINK_ENCODER_H_ */
280