xref: /openbmc/linux/drivers/net/ethernet/freescale/fec_main.c (revision 4d75f5c664195b970e1cd2fd25b65b5eff257a0a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5  *
6  * Right now, I am very wasteful with the buffers.  I allocate memory
7  * pages and then divide them into 2K frame buffers.  This way I know I
8  * have buffers large enough to hold one frame within one buffer descriptor.
9  * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10  * will be much more memory efficient and will easily handle lots of
11  * small packets.
12  *
13  * Much better multiple PHY support by Magnus Damm.
14  * Copyright (c) 2000 Ericsson Radio Systems AB.
15  *
16  * Support for FEC controller of ColdFire processors.
17  * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18  *
19  * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20  * Copyright (c) 2004-2006 Macq Electronique SA.
21  *
22  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23  */
24 
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/in.h>
39 #include <linux/ip.h>
40 #include <net/ip.h>
41 #include <net/page_pool/helpers.h>
42 #include <net/selftests.h>
43 #include <net/tso.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/icmp.h>
47 #include <linux/spinlock.h>
48 #include <linux/workqueue.h>
49 #include <linux/bitops.h>
50 #include <linux/io.h>
51 #include <linux/irq.h>
52 #include <linux/clk.h>
53 #include <linux/crc32.h>
54 #include <linux/platform_device.h>
55 #include <linux/mdio.h>
56 #include <linux/phy.h>
57 #include <linux/fec.h>
58 #include <linux/of.h>
59 #include <linux/of_device.h>
60 #include <linux/of_mdio.h>
61 #include <linux/of_net.h>
62 #include <linux/regulator/consumer.h>
63 #include <linux/if_vlan.h>
64 #include <linux/pinctrl/consumer.h>
65 #include <linux/gpio/consumer.h>
66 #include <linux/prefetch.h>
67 #include <linux/mfd/syscon.h>
68 #include <linux/regmap.h>
69 #include <soc/imx/cpuidle.h>
70 #include <linux/filter.h>
71 #include <linux/bpf.h>
72 #include <linux/bpf_trace.h>
73 
74 #include <asm/cacheflush.h>
75 
76 #include "fec.h"
77 
78 static void set_multicast_list(struct net_device *ndev);
79 static void fec_enet_itr_coal_set(struct net_device *ndev);
80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
81 				int cpu, struct xdp_buff *xdp,
82 				u32 dma_sync_len);
83 
84 #define DRIVER_NAME	"fec"
85 
86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
87 
88 /* Pause frame feild and FIFO threshold */
89 #define FEC_ENET_FCE	(1 << 5)
90 #define FEC_ENET_RSEM_V	0x84
91 #define FEC_ENET_RSFL_V	16
92 #define FEC_ENET_RAEM_V	0x8
93 #define FEC_ENET_RAFL_V	0x8
94 #define FEC_ENET_OPD_V	0xFFF0
95 #define FEC_MDIO_PM_TIMEOUT  100 /* ms */
96 
97 #define FEC_ENET_XDP_PASS          0
98 #define FEC_ENET_XDP_CONSUMED      BIT(0)
99 #define FEC_ENET_XDP_TX            BIT(1)
100 #define FEC_ENET_XDP_REDIR         BIT(2)
101 
102 struct fec_devinfo {
103 	u32 quirks;
104 };
105 
106 static const struct fec_devinfo fec_imx25_info = {
107 	.quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
108 		  FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45,
109 };
110 
111 static const struct fec_devinfo fec_imx27_info = {
112 	.quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG |
113 		  FEC_QUIRK_HAS_MDIO_C45,
114 };
115 
116 static const struct fec_devinfo fec_imx28_info = {
117 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
118 		  FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
119 		  FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
120 		  FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45,
121 };
122 
123 static const struct fec_devinfo fec_imx6q_info = {
124 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
125 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
126 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
127 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII |
128 		  FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45,
129 };
130 
131 static const struct fec_devinfo fec_mvf600_info = {
132 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC |
133 		  FEC_QUIRK_HAS_MDIO_C45,
134 };
135 
136 static const struct fec_devinfo fec_imx6x_info = {
137 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
138 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
139 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
140 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
141 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
142 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
143 		  FEC_QUIRK_HAS_MDIO_C45,
144 };
145 
146 static const struct fec_devinfo fec_imx6ul_info = {
147 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
148 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
149 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
150 		  FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
151 		  FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII |
152 		  FEC_QUIRK_HAS_MDIO_C45,
153 };
154 
155 static const struct fec_devinfo fec_imx8mq_info = {
156 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
157 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
158 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
159 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
160 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
161 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
162 		  FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 |
163 		  FEC_QUIRK_HAS_MDIO_C45,
164 };
165 
166 static const struct fec_devinfo fec_imx8qm_info = {
167 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
168 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
169 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
170 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
171 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
172 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
173 		  FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45,
174 };
175 
176 static const struct fec_devinfo fec_s32v234_info = {
177 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
178 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
179 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
180 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
181 		  FEC_QUIRK_HAS_MDIO_C45,
182 };
183 
184 static struct platform_device_id fec_devtype[] = {
185 	{
186 		/* keep it for coldfire */
187 		.name = DRIVER_NAME,
188 		.driver_data = 0,
189 	}, {
190 		.name = "imx25-fec",
191 		.driver_data = (kernel_ulong_t)&fec_imx25_info,
192 	}, {
193 		.name = "imx27-fec",
194 		.driver_data = (kernel_ulong_t)&fec_imx27_info,
195 	}, {
196 		.name = "imx28-fec",
197 		.driver_data = (kernel_ulong_t)&fec_imx28_info,
198 	}, {
199 		.name = "imx6q-fec",
200 		.driver_data = (kernel_ulong_t)&fec_imx6q_info,
201 	}, {
202 		.name = "mvf600-fec",
203 		.driver_data = (kernel_ulong_t)&fec_mvf600_info,
204 	}, {
205 		.name = "imx6sx-fec",
206 		.driver_data = (kernel_ulong_t)&fec_imx6x_info,
207 	}, {
208 		.name = "imx6ul-fec",
209 		.driver_data = (kernel_ulong_t)&fec_imx6ul_info,
210 	}, {
211 		.name = "imx8mq-fec",
212 		.driver_data = (kernel_ulong_t)&fec_imx8mq_info,
213 	}, {
214 		.name = "imx8qm-fec",
215 		.driver_data = (kernel_ulong_t)&fec_imx8qm_info,
216 	}, {
217 		.name = "s32v234-fec",
218 		.driver_data = (kernel_ulong_t)&fec_s32v234_info,
219 	}, {
220 		/* sentinel */
221 	}
222 };
223 MODULE_DEVICE_TABLE(platform, fec_devtype);
224 
225 enum imx_fec_type {
226 	IMX25_FEC = 1,	/* runs on i.mx25/50/53 */
227 	IMX27_FEC,	/* runs on i.mx27/35/51 */
228 	IMX28_FEC,
229 	IMX6Q_FEC,
230 	MVF600_FEC,
231 	IMX6SX_FEC,
232 	IMX6UL_FEC,
233 	IMX8MQ_FEC,
234 	IMX8QM_FEC,
235 	S32V234_FEC,
236 };
237 
238 static const struct of_device_id fec_dt_ids[] = {
239 	{ .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
240 	{ .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
241 	{ .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
242 	{ .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
243 	{ .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
244 	{ .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
245 	{ .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
246 	{ .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
247 	{ .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
248 	{ .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], },
249 	{ /* sentinel */ }
250 };
251 MODULE_DEVICE_TABLE(of, fec_dt_ids);
252 
253 static unsigned char macaddr[ETH_ALEN];
254 module_param_array(macaddr, byte, NULL, 0);
255 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
256 
257 #if defined(CONFIG_M5272)
258 /*
259  * Some hardware gets it MAC address out of local flash memory.
260  * if this is non-zero then assume it is the address to get MAC from.
261  */
262 #if defined(CONFIG_NETtel)
263 #define	FEC_FLASHMAC	0xf0006006
264 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
265 #define	FEC_FLASHMAC	0xf0006000
266 #elif defined(CONFIG_CANCam)
267 #define	FEC_FLASHMAC	0xf0020000
268 #elif defined (CONFIG_M5272C3)
269 #define	FEC_FLASHMAC	(0xffe04000 + 4)
270 #elif defined(CONFIG_MOD5272)
271 #define FEC_FLASHMAC	0xffc0406b
272 #else
273 #define	FEC_FLASHMAC	0
274 #endif
275 #endif /* CONFIG_M5272 */
276 
277 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
278  *
279  * 2048 byte skbufs are allocated. However, alignment requirements
280  * varies between FEC variants. Worst case is 64, so round down by 64.
281  */
282 #define PKT_MAXBUF_SIZE		(round_down(2048 - 64, 64))
283 #define PKT_MINBUF_SIZE		64
284 
285 /* FEC receive acceleration */
286 #define FEC_RACC_IPDIS		BIT(1)
287 #define FEC_RACC_PRODIS		BIT(2)
288 #define FEC_RACC_SHIFT16	BIT(7)
289 #define FEC_RACC_OPTIONS	(FEC_RACC_IPDIS | FEC_RACC_PRODIS)
290 
291 /* MIB Control Register */
292 #define FEC_MIB_CTRLSTAT_DISABLE	BIT(31)
293 
294 /*
295  * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
296  * size bits. Other FEC hardware does not, so we need to take that into
297  * account when setting it.
298  */
299 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
300     defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
301     defined(CONFIG_ARM64)
302 #define	OPT_FRAME_SIZE	(PKT_MAXBUF_SIZE << 16)
303 #else
304 #define	OPT_FRAME_SIZE	0
305 #endif
306 
307 /* FEC MII MMFR bits definition */
308 #define FEC_MMFR_ST		(1 << 30)
309 #define FEC_MMFR_ST_C45		(0)
310 #define FEC_MMFR_OP_READ	(2 << 28)
311 #define FEC_MMFR_OP_READ_C45	(3 << 28)
312 #define FEC_MMFR_OP_WRITE	(1 << 28)
313 #define FEC_MMFR_OP_ADDR_WRITE	(0)
314 #define FEC_MMFR_PA(v)		((v & 0x1f) << 23)
315 #define FEC_MMFR_RA(v)		((v & 0x1f) << 18)
316 #define FEC_MMFR_TA		(2 << 16)
317 #define FEC_MMFR_DATA(v)	(v & 0xffff)
318 /* FEC ECR bits definition */
319 #define FEC_ECR_RESET           BIT(0)
320 #define FEC_ECR_ETHEREN         BIT(1)
321 #define FEC_ECR_MAGICEN         BIT(2)
322 #define FEC_ECR_SLEEP           BIT(3)
323 #define FEC_ECR_EN1588          BIT(4)
324 #define FEC_ECR_BYTESWP         BIT(8)
325 /* FEC RCR bits definition */
326 #define FEC_RCR_LOOP            BIT(0)
327 #define FEC_RCR_HALFDPX         BIT(1)
328 #define FEC_RCR_MII             BIT(2)
329 #define FEC_RCR_PROMISC         BIT(3)
330 #define FEC_RCR_BC_REJ          BIT(4)
331 #define FEC_RCR_FLOWCTL         BIT(5)
332 #define FEC_RCR_RMII            BIT(8)
333 #define FEC_RCR_10BASET         BIT(9)
334 /* TX WMARK bits */
335 #define FEC_TXWMRK_STRFWD       BIT(8)
336 
337 #define FEC_MII_TIMEOUT		30000 /* us */
338 
339 /* Transmitter timeout */
340 #define TX_TIMEOUT (2 * HZ)
341 
342 #define FEC_PAUSE_FLAG_AUTONEG	0x1
343 #define FEC_PAUSE_FLAG_ENABLE	0x2
344 #define FEC_WOL_HAS_MAGIC_PACKET	(0x1 << 0)
345 #define FEC_WOL_FLAG_ENABLE		(0x1 << 1)
346 #define FEC_WOL_FLAG_SLEEP_ON		(0x1 << 2)
347 
348 /* Max number of allowed TCP segments for software TSO */
349 #define FEC_MAX_TSO_SEGS	100
350 #define FEC_MAX_SKB_DESCS	(FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
351 
352 #define IS_TSO_HEADER(txq, addr) \
353 	((addr >= txq->tso_hdrs_dma) && \
354 	(addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
355 
356 static int mii_cnt;
357 
fec_enet_get_nextdesc(struct bufdesc * bdp,struct bufdesc_prop * bd)358 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
359 					     struct bufdesc_prop *bd)
360 {
361 	return (bdp >= bd->last) ? bd->base
362 			: (struct bufdesc *)(((void *)bdp) + bd->dsize);
363 }
364 
fec_enet_get_prevdesc(struct bufdesc * bdp,struct bufdesc_prop * bd)365 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
366 					     struct bufdesc_prop *bd)
367 {
368 	return (bdp <= bd->base) ? bd->last
369 			: (struct bufdesc *)(((void *)bdp) - bd->dsize);
370 }
371 
fec_enet_get_bd_index(struct bufdesc * bdp,struct bufdesc_prop * bd)372 static int fec_enet_get_bd_index(struct bufdesc *bdp,
373 				 struct bufdesc_prop *bd)
374 {
375 	return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
376 }
377 
fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q * txq)378 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
379 {
380 	int entries;
381 
382 	entries = (((const char *)txq->dirty_tx -
383 			(const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
384 
385 	return entries >= 0 ? entries : entries + txq->bd.ring_size;
386 }
387 
swap_buffer(void * bufaddr,int len)388 static void swap_buffer(void *bufaddr, int len)
389 {
390 	int i;
391 	unsigned int *buf = bufaddr;
392 
393 	for (i = 0; i < len; i += 4, buf++)
394 		swab32s(buf);
395 }
396 
fec_dump(struct net_device * ndev)397 static void fec_dump(struct net_device *ndev)
398 {
399 	struct fec_enet_private *fep = netdev_priv(ndev);
400 	struct bufdesc *bdp;
401 	struct fec_enet_priv_tx_q *txq;
402 	int index = 0;
403 
404 	netdev_info(ndev, "TX ring dump\n");
405 	pr_info("Nr     SC     addr       len  SKB\n");
406 
407 	txq = fep->tx_queue[0];
408 	bdp = txq->bd.base;
409 
410 	do {
411 		pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
412 			index,
413 			bdp == txq->bd.cur ? 'S' : ' ',
414 			bdp == txq->dirty_tx ? 'H' : ' ',
415 			fec16_to_cpu(bdp->cbd_sc),
416 			fec32_to_cpu(bdp->cbd_bufaddr),
417 			fec16_to_cpu(bdp->cbd_datlen),
418 			txq->tx_buf[index].buf_p);
419 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
420 		index++;
421 	} while (bdp != txq->bd.base);
422 }
423 
is_ipv4_pkt(struct sk_buff * skb)424 static inline bool is_ipv4_pkt(struct sk_buff *skb)
425 {
426 	return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
427 }
428 
429 static int
fec_enet_clear_csum(struct sk_buff * skb,struct net_device * ndev)430 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
431 {
432 	/* Only run for packets requiring a checksum. */
433 	if (skb->ip_summed != CHECKSUM_PARTIAL)
434 		return 0;
435 
436 	if (unlikely(skb_cow_head(skb, 0)))
437 		return -1;
438 
439 	if (is_ipv4_pkt(skb))
440 		ip_hdr(skb)->check = 0;
441 	*(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
442 
443 	return 0;
444 }
445 
446 static int
fec_enet_create_page_pool(struct fec_enet_private * fep,struct fec_enet_priv_rx_q * rxq,int size)447 fec_enet_create_page_pool(struct fec_enet_private *fep,
448 			  struct fec_enet_priv_rx_q *rxq, int size)
449 {
450 	struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
451 	struct page_pool_params pp_params = {
452 		.order = 0,
453 		.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
454 		.pool_size = size,
455 		.nid = dev_to_node(&fep->pdev->dev),
456 		.dev = &fep->pdev->dev,
457 		.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
458 		.offset = FEC_ENET_XDP_HEADROOM,
459 		.max_len = FEC_ENET_RX_FRSIZE,
460 	};
461 	int err;
462 
463 	rxq->page_pool = page_pool_create(&pp_params);
464 	if (IS_ERR(rxq->page_pool)) {
465 		err = PTR_ERR(rxq->page_pool);
466 		rxq->page_pool = NULL;
467 		return err;
468 	}
469 
470 	err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0);
471 	if (err < 0)
472 		goto err_free_pp;
473 
474 	err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
475 					 rxq->page_pool);
476 	if (err)
477 		goto err_unregister_rxq;
478 
479 	return 0;
480 
481 err_unregister_rxq:
482 	xdp_rxq_info_unreg(&rxq->xdp_rxq);
483 err_free_pp:
484 	page_pool_destroy(rxq->page_pool);
485 	rxq->page_pool = NULL;
486 	return err;
487 }
488 
489 static struct bufdesc *
fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)490 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
491 			     struct sk_buff *skb,
492 			     struct net_device *ndev)
493 {
494 	struct fec_enet_private *fep = netdev_priv(ndev);
495 	struct bufdesc *bdp = txq->bd.cur;
496 	struct bufdesc_ex *ebdp;
497 	int nr_frags = skb_shinfo(skb)->nr_frags;
498 	int frag, frag_len;
499 	unsigned short status;
500 	unsigned int estatus = 0;
501 	skb_frag_t *this_frag;
502 	unsigned int index;
503 	void *bufaddr;
504 	dma_addr_t addr;
505 	int i;
506 
507 	for (frag = 0; frag < nr_frags; frag++) {
508 		this_frag = &skb_shinfo(skb)->frags[frag];
509 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
510 		ebdp = (struct bufdesc_ex *)bdp;
511 
512 		status = fec16_to_cpu(bdp->cbd_sc);
513 		status &= ~BD_ENET_TX_STATS;
514 		status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
515 		frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
516 
517 		/* Handle the last BD specially */
518 		if (frag == nr_frags - 1) {
519 			status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
520 			if (fep->bufdesc_ex) {
521 				estatus |= BD_ENET_TX_INT;
522 				if (unlikely(skb_shinfo(skb)->tx_flags &
523 					SKBTX_HW_TSTAMP && fep->hwts_tx_en))
524 					estatus |= BD_ENET_TX_TS;
525 			}
526 		}
527 
528 		if (fep->bufdesc_ex) {
529 			if (fep->quirks & FEC_QUIRK_HAS_AVB)
530 				estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
531 			if (skb->ip_summed == CHECKSUM_PARTIAL)
532 				estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
533 
534 			ebdp->cbd_bdu = 0;
535 			ebdp->cbd_esc = cpu_to_fec32(estatus);
536 		}
537 
538 		bufaddr = skb_frag_address(this_frag);
539 
540 		index = fec_enet_get_bd_index(bdp, &txq->bd);
541 		if (((unsigned long) bufaddr) & fep->tx_align ||
542 			fep->quirks & FEC_QUIRK_SWAP_FRAME) {
543 			memcpy(txq->tx_bounce[index], bufaddr, frag_len);
544 			bufaddr = txq->tx_bounce[index];
545 
546 			if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
547 				swap_buffer(bufaddr, frag_len);
548 		}
549 
550 		addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
551 				      DMA_TO_DEVICE);
552 		if (dma_mapping_error(&fep->pdev->dev, addr)) {
553 			if (net_ratelimit())
554 				netdev_err(ndev, "Tx DMA memory map failed\n");
555 			goto dma_mapping_error;
556 		}
557 
558 		bdp->cbd_bufaddr = cpu_to_fec32(addr);
559 		bdp->cbd_datlen = cpu_to_fec16(frag_len);
560 		/* Make sure the updates to rest of the descriptor are
561 		 * performed before transferring ownership.
562 		 */
563 		wmb();
564 		bdp->cbd_sc = cpu_to_fec16(status);
565 	}
566 
567 	return bdp;
568 dma_mapping_error:
569 	bdp = txq->bd.cur;
570 	for (i = 0; i < frag; i++) {
571 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
572 		dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
573 				 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
574 	}
575 	return ERR_PTR(-ENOMEM);
576 }
577 
fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)578 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
579 				   struct sk_buff *skb, struct net_device *ndev)
580 {
581 	struct fec_enet_private *fep = netdev_priv(ndev);
582 	int nr_frags = skb_shinfo(skb)->nr_frags;
583 	struct bufdesc *bdp, *last_bdp;
584 	void *bufaddr;
585 	dma_addr_t addr;
586 	unsigned short status;
587 	unsigned short buflen;
588 	unsigned int estatus = 0;
589 	unsigned int index;
590 	int entries_free;
591 
592 	entries_free = fec_enet_get_free_txdesc_num(txq);
593 	if (entries_free < MAX_SKB_FRAGS + 1) {
594 		dev_kfree_skb_any(skb);
595 		if (net_ratelimit())
596 			netdev_err(ndev, "NOT enough BD for SG!\n");
597 		return NETDEV_TX_OK;
598 	}
599 
600 	/* Protocol checksum off-load for TCP and UDP. */
601 	if (fec_enet_clear_csum(skb, ndev)) {
602 		dev_kfree_skb_any(skb);
603 		return NETDEV_TX_OK;
604 	}
605 
606 	/* Fill in a Tx ring entry */
607 	bdp = txq->bd.cur;
608 	last_bdp = bdp;
609 	status = fec16_to_cpu(bdp->cbd_sc);
610 	status &= ~BD_ENET_TX_STATS;
611 
612 	/* Set buffer length and buffer pointer */
613 	bufaddr = skb->data;
614 	buflen = skb_headlen(skb);
615 
616 	index = fec_enet_get_bd_index(bdp, &txq->bd);
617 	if (((unsigned long) bufaddr) & fep->tx_align ||
618 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
619 		memcpy(txq->tx_bounce[index], skb->data, buflen);
620 		bufaddr = txq->tx_bounce[index];
621 
622 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
623 			swap_buffer(bufaddr, buflen);
624 	}
625 
626 	/* Push the data cache so the CPM does not get stale memory data. */
627 	addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
628 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
629 		dev_kfree_skb_any(skb);
630 		if (net_ratelimit())
631 			netdev_err(ndev, "Tx DMA memory map failed\n");
632 		return NETDEV_TX_OK;
633 	}
634 
635 	if (nr_frags) {
636 		last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
637 		if (IS_ERR(last_bdp)) {
638 			dma_unmap_single(&fep->pdev->dev, addr,
639 					 buflen, DMA_TO_DEVICE);
640 			dev_kfree_skb_any(skb);
641 			return NETDEV_TX_OK;
642 		}
643 	} else {
644 		status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
645 		if (fep->bufdesc_ex) {
646 			estatus = BD_ENET_TX_INT;
647 			if (unlikely(skb_shinfo(skb)->tx_flags &
648 				SKBTX_HW_TSTAMP && fep->hwts_tx_en))
649 				estatus |= BD_ENET_TX_TS;
650 		}
651 	}
652 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
653 	bdp->cbd_datlen = cpu_to_fec16(buflen);
654 
655 	if (fep->bufdesc_ex) {
656 
657 		struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
658 
659 		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
660 			fep->hwts_tx_en))
661 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
662 
663 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
664 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
665 
666 		if (skb->ip_summed == CHECKSUM_PARTIAL)
667 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
668 
669 		ebdp->cbd_bdu = 0;
670 		ebdp->cbd_esc = cpu_to_fec32(estatus);
671 	}
672 
673 	index = fec_enet_get_bd_index(last_bdp, &txq->bd);
674 	/* Save skb pointer */
675 	txq->tx_buf[index].buf_p = skb;
676 
677 	/* Make sure the updates to rest of the descriptor are performed before
678 	 * transferring ownership.
679 	 */
680 	wmb();
681 
682 	/* Send it on its way.  Tell FEC it's ready, interrupt when done,
683 	 * it's the last BD of the frame, and to put the CRC on the end.
684 	 */
685 	status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
686 	bdp->cbd_sc = cpu_to_fec16(status);
687 
688 	/* If this was the last BD in the ring, start at the beginning again. */
689 	bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
690 
691 	skb_tx_timestamp(skb);
692 
693 	/* Make sure the update to bdp is performed before txq->bd.cur. */
694 	wmb();
695 	txq->bd.cur = bdp;
696 
697 	/* Trigger transmission start */
698 	if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
699 	    !readl(txq->bd.reg_desc_active) ||
700 	    !readl(txq->bd.reg_desc_active) ||
701 	    !readl(txq->bd.reg_desc_active) ||
702 	    !readl(txq->bd.reg_desc_active))
703 		writel(0, txq->bd.reg_desc_active);
704 
705 	return 0;
706 }
707 
708 static int
fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev,struct bufdesc * bdp,int index,char * data,int size,bool last_tcp,bool is_last)709 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
710 			  struct net_device *ndev,
711 			  struct bufdesc *bdp, int index, char *data,
712 			  int size, bool last_tcp, bool is_last)
713 {
714 	struct fec_enet_private *fep = netdev_priv(ndev);
715 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
716 	unsigned short status;
717 	unsigned int estatus = 0;
718 	dma_addr_t addr;
719 
720 	status = fec16_to_cpu(bdp->cbd_sc);
721 	status &= ~BD_ENET_TX_STATS;
722 
723 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
724 
725 	if (((unsigned long) data) & fep->tx_align ||
726 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
727 		memcpy(txq->tx_bounce[index], data, size);
728 		data = txq->tx_bounce[index];
729 
730 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
731 			swap_buffer(data, size);
732 	}
733 
734 	addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
735 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
736 		dev_kfree_skb_any(skb);
737 		if (net_ratelimit())
738 			netdev_err(ndev, "Tx DMA memory map failed\n");
739 		return NETDEV_TX_OK;
740 	}
741 
742 	bdp->cbd_datlen = cpu_to_fec16(size);
743 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
744 
745 	if (fep->bufdesc_ex) {
746 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
747 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
748 		if (skb->ip_summed == CHECKSUM_PARTIAL)
749 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
750 		ebdp->cbd_bdu = 0;
751 		ebdp->cbd_esc = cpu_to_fec32(estatus);
752 	}
753 
754 	/* Handle the last BD specially */
755 	if (last_tcp)
756 		status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
757 	if (is_last) {
758 		status |= BD_ENET_TX_INTR;
759 		if (fep->bufdesc_ex)
760 			ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
761 	}
762 
763 	bdp->cbd_sc = cpu_to_fec16(status);
764 
765 	return 0;
766 }
767 
768 static int
fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev,struct bufdesc * bdp,int index)769 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
770 			 struct sk_buff *skb, struct net_device *ndev,
771 			 struct bufdesc *bdp, int index)
772 {
773 	struct fec_enet_private *fep = netdev_priv(ndev);
774 	int hdr_len = skb_tcp_all_headers(skb);
775 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
776 	void *bufaddr;
777 	unsigned long dmabuf;
778 	unsigned short status;
779 	unsigned int estatus = 0;
780 
781 	status = fec16_to_cpu(bdp->cbd_sc);
782 	status &= ~BD_ENET_TX_STATS;
783 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
784 
785 	bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
786 	dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
787 	if (((unsigned long)bufaddr) & fep->tx_align ||
788 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
789 		memcpy(txq->tx_bounce[index], skb->data, hdr_len);
790 		bufaddr = txq->tx_bounce[index];
791 
792 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
793 			swap_buffer(bufaddr, hdr_len);
794 
795 		dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
796 					hdr_len, DMA_TO_DEVICE);
797 		if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
798 			dev_kfree_skb_any(skb);
799 			if (net_ratelimit())
800 				netdev_err(ndev, "Tx DMA memory map failed\n");
801 			return NETDEV_TX_OK;
802 		}
803 	}
804 
805 	bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
806 	bdp->cbd_datlen = cpu_to_fec16(hdr_len);
807 
808 	if (fep->bufdesc_ex) {
809 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
810 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
811 		if (skb->ip_summed == CHECKSUM_PARTIAL)
812 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
813 		ebdp->cbd_bdu = 0;
814 		ebdp->cbd_esc = cpu_to_fec32(estatus);
815 	}
816 
817 	bdp->cbd_sc = cpu_to_fec16(status);
818 
819 	return 0;
820 }
821 
fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)822 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
823 				   struct sk_buff *skb,
824 				   struct net_device *ndev)
825 {
826 	struct fec_enet_private *fep = netdev_priv(ndev);
827 	int hdr_len, total_len, data_left;
828 	struct bufdesc *bdp = txq->bd.cur;
829 	struct bufdesc *tmp_bdp;
830 	struct bufdesc_ex *ebdp;
831 	struct tso_t tso;
832 	unsigned int index = 0;
833 	int ret;
834 
835 	if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
836 		dev_kfree_skb_any(skb);
837 		if (net_ratelimit())
838 			netdev_err(ndev, "NOT enough BD for TSO!\n");
839 		return NETDEV_TX_OK;
840 	}
841 
842 	/* Protocol checksum off-load for TCP and UDP. */
843 	if (fec_enet_clear_csum(skb, ndev)) {
844 		dev_kfree_skb_any(skb);
845 		return NETDEV_TX_OK;
846 	}
847 
848 	/* Initialize the TSO handler, and prepare the first payload */
849 	hdr_len = tso_start(skb, &tso);
850 
851 	total_len = skb->len - hdr_len;
852 	while (total_len > 0) {
853 		char *hdr;
854 
855 		index = fec_enet_get_bd_index(bdp, &txq->bd);
856 		data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
857 		total_len -= data_left;
858 
859 		/* prepare packet headers: MAC + IP + TCP */
860 		hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
861 		tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
862 		ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
863 		if (ret)
864 			goto err_release;
865 
866 		while (data_left > 0) {
867 			int size;
868 
869 			size = min_t(int, tso.size, data_left);
870 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
871 			index = fec_enet_get_bd_index(bdp, &txq->bd);
872 			ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
873 							bdp, index,
874 							tso.data, size,
875 							size == data_left,
876 							total_len == 0);
877 			if (ret)
878 				goto err_release;
879 
880 			data_left -= size;
881 			tso_build_data(skb, &tso, size);
882 		}
883 
884 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
885 	}
886 
887 	/* Save skb pointer */
888 	txq->tx_buf[index].buf_p = skb;
889 
890 	skb_tx_timestamp(skb);
891 	txq->bd.cur = bdp;
892 
893 	/* Trigger transmission start */
894 	if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
895 	    !readl(txq->bd.reg_desc_active) ||
896 	    !readl(txq->bd.reg_desc_active) ||
897 	    !readl(txq->bd.reg_desc_active) ||
898 	    !readl(txq->bd.reg_desc_active))
899 		writel(0, txq->bd.reg_desc_active);
900 
901 	return 0;
902 
903 err_release:
904 	/* Release all used data descriptors for TSO */
905 	tmp_bdp = txq->bd.cur;
906 
907 	while (tmp_bdp != bdp) {
908 		/* Unmap data buffers */
909 		if (tmp_bdp->cbd_bufaddr &&
910 		    !IS_TSO_HEADER(txq, fec32_to_cpu(tmp_bdp->cbd_bufaddr)))
911 			dma_unmap_single(&fep->pdev->dev,
912 					 fec32_to_cpu(tmp_bdp->cbd_bufaddr),
913 					 fec16_to_cpu(tmp_bdp->cbd_datlen),
914 					 DMA_TO_DEVICE);
915 
916 		/* Clear standard buffer descriptor fields */
917 		tmp_bdp->cbd_sc = 0;
918 		tmp_bdp->cbd_datlen = 0;
919 		tmp_bdp->cbd_bufaddr = 0;
920 
921 		/* Handle extended descriptor if enabled */
922 		if (fep->bufdesc_ex) {
923 			ebdp = (struct bufdesc_ex *)tmp_bdp;
924 			ebdp->cbd_esc = 0;
925 		}
926 
927 		tmp_bdp = fec_enet_get_nextdesc(tmp_bdp, &txq->bd);
928 	}
929 
930 	dev_kfree_skb_any(skb);
931 
932 	return ret;
933 }
934 
935 static netdev_tx_t
fec_enet_start_xmit(struct sk_buff * skb,struct net_device * ndev)936 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
937 {
938 	struct fec_enet_private *fep = netdev_priv(ndev);
939 	int entries_free;
940 	unsigned short queue;
941 	struct fec_enet_priv_tx_q *txq;
942 	struct netdev_queue *nq;
943 	int ret;
944 
945 	queue = skb_get_queue_mapping(skb);
946 	txq = fep->tx_queue[queue];
947 	nq = netdev_get_tx_queue(ndev, queue);
948 
949 	if (skb_is_gso(skb))
950 		ret = fec_enet_txq_submit_tso(txq, skb, ndev);
951 	else
952 		ret = fec_enet_txq_submit_skb(txq, skb, ndev);
953 	if (ret)
954 		return ret;
955 
956 	entries_free = fec_enet_get_free_txdesc_num(txq);
957 	if (entries_free <= txq->tx_stop_threshold)
958 		netif_tx_stop_queue(nq);
959 
960 	return NETDEV_TX_OK;
961 }
962 
963 /* Init RX & TX buffer descriptors
964  */
fec_enet_bd_init(struct net_device * dev)965 static void fec_enet_bd_init(struct net_device *dev)
966 {
967 	struct fec_enet_private *fep = netdev_priv(dev);
968 	struct fec_enet_priv_tx_q *txq;
969 	struct fec_enet_priv_rx_q *rxq;
970 	struct bufdesc *bdp;
971 	unsigned int i;
972 	unsigned int q;
973 
974 	for (q = 0; q < fep->num_rx_queues; q++) {
975 		/* Initialize the receive buffer descriptors. */
976 		rxq = fep->rx_queue[q];
977 		bdp = rxq->bd.base;
978 
979 		for (i = 0; i < rxq->bd.ring_size; i++) {
980 
981 			/* Initialize the BD for every fragment in the page. */
982 			if (bdp->cbd_bufaddr)
983 				bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
984 			else
985 				bdp->cbd_sc = cpu_to_fec16(0);
986 			bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
987 		}
988 
989 		/* Set the last buffer to wrap */
990 		bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
991 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
992 
993 		rxq->bd.cur = rxq->bd.base;
994 	}
995 
996 	for (q = 0; q < fep->num_tx_queues; q++) {
997 		/* ...and the same for transmit */
998 		txq = fep->tx_queue[q];
999 		bdp = txq->bd.base;
1000 		txq->bd.cur = bdp;
1001 
1002 		for (i = 0; i < txq->bd.ring_size; i++) {
1003 			/* Initialize the BD for every fragment in the page. */
1004 			bdp->cbd_sc = cpu_to_fec16(0);
1005 			if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
1006 				if (bdp->cbd_bufaddr &&
1007 				    !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1008 					dma_unmap_single(&fep->pdev->dev,
1009 							 fec32_to_cpu(bdp->cbd_bufaddr),
1010 							 fec16_to_cpu(bdp->cbd_datlen),
1011 							 DMA_TO_DEVICE);
1012 				if (txq->tx_buf[i].buf_p)
1013 					dev_kfree_skb_any(txq->tx_buf[i].buf_p);
1014 			} else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
1015 				if (bdp->cbd_bufaddr)
1016 					dma_unmap_single(&fep->pdev->dev,
1017 							 fec32_to_cpu(bdp->cbd_bufaddr),
1018 							 fec16_to_cpu(bdp->cbd_datlen),
1019 							 DMA_TO_DEVICE);
1020 
1021 				if (txq->tx_buf[i].buf_p)
1022 					xdp_return_frame(txq->tx_buf[i].buf_p);
1023 			} else {
1024 				struct page *page = txq->tx_buf[i].buf_p;
1025 
1026 				if (page)
1027 					page_pool_put_page(page->pp, page, 0, false);
1028 			}
1029 
1030 			txq->tx_buf[i].buf_p = NULL;
1031 			/* restore default tx buffer type: FEC_TXBUF_T_SKB */
1032 			txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
1033 			bdp->cbd_bufaddr = cpu_to_fec32(0);
1034 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1035 		}
1036 
1037 		/* Set the last buffer to wrap */
1038 		bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
1039 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
1040 		txq->dirty_tx = bdp;
1041 	}
1042 }
1043 
fec_enet_active_rxring(struct net_device * ndev)1044 static void fec_enet_active_rxring(struct net_device *ndev)
1045 {
1046 	struct fec_enet_private *fep = netdev_priv(ndev);
1047 	int i;
1048 
1049 	for (i = 0; i < fep->num_rx_queues; i++)
1050 		writel(0, fep->rx_queue[i]->bd.reg_desc_active);
1051 }
1052 
fec_enet_enable_ring(struct net_device * ndev)1053 static void fec_enet_enable_ring(struct net_device *ndev)
1054 {
1055 	struct fec_enet_private *fep = netdev_priv(ndev);
1056 	struct fec_enet_priv_tx_q *txq;
1057 	struct fec_enet_priv_rx_q *rxq;
1058 	int i;
1059 
1060 	for (i = 0; i < fep->num_rx_queues; i++) {
1061 		rxq = fep->rx_queue[i];
1062 		writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
1063 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
1064 
1065 		/* enable DMA1/2 */
1066 		if (i)
1067 			writel(RCMR_MATCHEN | RCMR_CMP(i),
1068 			       fep->hwp + FEC_RCMR(i));
1069 	}
1070 
1071 	for (i = 0; i < fep->num_tx_queues; i++) {
1072 		txq = fep->tx_queue[i];
1073 		writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
1074 
1075 		/* enable DMA1/2 */
1076 		if (i)
1077 			writel(DMA_CLASS_EN | IDLE_SLOPE(i),
1078 			       fep->hwp + FEC_DMA_CFG(i));
1079 	}
1080 }
1081 
1082 /* Whack a reset.  We should wait for this.
1083  * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1084  * instead of reset MAC itself.
1085  */
fec_ctrl_reset(struct fec_enet_private * fep,bool allow_wol)1086 static void fec_ctrl_reset(struct fec_enet_private *fep, bool allow_wol)
1087 {
1088 	u32 val;
1089 
1090 	if (!allow_wol || !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1091 		if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES ||
1092 		    ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) {
1093 			writel(0, fep->hwp + FEC_ECNTRL);
1094 		} else {
1095 			writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL);
1096 			udelay(10);
1097 		}
1098 	} else {
1099 		val = readl(fep->hwp + FEC_ECNTRL);
1100 		val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1101 		writel(val, fep->hwp + FEC_ECNTRL);
1102 	}
1103 }
1104 
1105 /*
1106  * This function is called to start or restart the FEC during a link
1107  * change, transmit timeout, or to reconfigure the FEC.  The network
1108  * packet processing for this device must be stopped before this call.
1109  */
1110 static void
fec_restart(struct net_device * ndev)1111 fec_restart(struct net_device *ndev)
1112 {
1113 	struct fec_enet_private *fep = netdev_priv(ndev);
1114 	u32 temp_mac[2];
1115 	u32 rcntl = OPT_FRAME_SIZE | 0x04;
1116 	u32 ecntl = FEC_ECR_ETHEREN;
1117 
1118 	if (fep->bufdesc_ex)
1119 		fec_ptp_save_state(fep);
1120 
1121 	fec_ctrl_reset(fep, false);
1122 
1123 	/*
1124 	 * enet-mac reset will reset mac address registers too,
1125 	 * so need to reconfigure it.
1126 	 */
1127 	memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1128 	writel((__force u32)cpu_to_be32(temp_mac[0]),
1129 	       fep->hwp + FEC_ADDR_LOW);
1130 	writel((__force u32)cpu_to_be32(temp_mac[1]),
1131 	       fep->hwp + FEC_ADDR_HIGH);
1132 
1133 	/* Clear any outstanding interrupt, except MDIO. */
1134 	writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
1135 
1136 	fec_enet_bd_init(ndev);
1137 
1138 	fec_enet_enable_ring(ndev);
1139 
1140 	/* Enable MII mode */
1141 	if (fep->full_duplex == DUPLEX_FULL) {
1142 		/* FD enable */
1143 		writel(0x04, fep->hwp + FEC_X_CNTRL);
1144 	} else {
1145 		/* No Rcv on Xmit */
1146 		rcntl |= 0x02;
1147 		writel(0x0, fep->hwp + FEC_X_CNTRL);
1148 	}
1149 
1150 	/* Set MII speed */
1151 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1152 
1153 #if !defined(CONFIG_M5272)
1154 	if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1155 		u32 val = readl(fep->hwp + FEC_RACC);
1156 
1157 		/* align IP header */
1158 		val |= FEC_RACC_SHIFT16;
1159 		if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1160 			/* set RX checksum */
1161 			val |= FEC_RACC_OPTIONS;
1162 		else
1163 			val &= ~FEC_RACC_OPTIONS;
1164 		writel(val, fep->hwp + FEC_RACC);
1165 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1166 	}
1167 #endif
1168 
1169 	/*
1170 	 * The phy interface and speed need to get configured
1171 	 * differently on enet-mac.
1172 	 */
1173 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1174 		/* Enable flow control and length check */
1175 		rcntl |= 0x40000000 | 0x00000020;
1176 
1177 		/* RGMII, RMII or MII */
1178 		if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1179 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1180 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1181 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1182 			rcntl |= (1 << 6);
1183 		else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1184 			rcntl |= FEC_RCR_RMII;
1185 		else
1186 			rcntl &= ~FEC_RCR_RMII;
1187 
1188 		/* 1G, 100M or 10M */
1189 		if (ndev->phydev) {
1190 			if (ndev->phydev->speed == SPEED_1000)
1191 				ecntl |= (1 << 5);
1192 			else if (ndev->phydev->speed == SPEED_100)
1193 				rcntl &= ~FEC_RCR_10BASET;
1194 			else
1195 				rcntl |= FEC_RCR_10BASET;
1196 		}
1197 	} else {
1198 #ifdef FEC_MIIGSK_ENR
1199 		if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1200 			u32 cfgr;
1201 			/* disable the gasket and wait */
1202 			writel(0, fep->hwp + FEC_MIIGSK_ENR);
1203 			while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1204 				udelay(1);
1205 
1206 			/*
1207 			 * configure the gasket:
1208 			 *   RMII, 50 MHz, no loopback, no echo
1209 			 *   MII, 25 MHz, no loopback, no echo
1210 			 */
1211 			cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1212 				? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1213 			if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1214 				cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1215 			writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1216 
1217 			/* re-enable the gasket */
1218 			writel(2, fep->hwp + FEC_MIIGSK_ENR);
1219 		}
1220 #endif
1221 	}
1222 
1223 #if !defined(CONFIG_M5272)
1224 	/* enable pause frame*/
1225 	if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1226 	    ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1227 	     ndev->phydev && ndev->phydev->pause)) {
1228 		rcntl |= FEC_ENET_FCE;
1229 
1230 		/* set FIFO threshold parameter to reduce overrun */
1231 		writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1232 		writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1233 		writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1234 		writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1235 
1236 		/* OPD */
1237 		writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1238 	} else {
1239 		rcntl &= ~FEC_ENET_FCE;
1240 	}
1241 #endif /* !defined(CONFIG_M5272) */
1242 
1243 	writel(rcntl, fep->hwp + FEC_R_CNTRL);
1244 
1245 	/* Setup multicast filter. */
1246 	set_multicast_list(ndev);
1247 #ifndef CONFIG_M5272
1248 	writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1249 	writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1250 #endif
1251 
1252 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1253 		/* enable ENET endian swap */
1254 		ecntl |= FEC_ECR_BYTESWP;
1255 		/* enable ENET store and forward mode */
1256 		writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK);
1257 	}
1258 
1259 	if (fep->bufdesc_ex)
1260 		ecntl |= FEC_ECR_EN1588;
1261 
1262 	if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1263 	    fep->rgmii_txc_dly)
1264 		ecntl |= FEC_ENET_TXC_DLY;
1265 	if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1266 	    fep->rgmii_rxc_dly)
1267 		ecntl |= FEC_ENET_RXC_DLY;
1268 
1269 #ifndef CONFIG_M5272
1270 	/* Enable the MIB statistic event counters */
1271 	writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1272 #endif
1273 
1274 	/* And last, enable the transmit and receive processing */
1275 	writel(ecntl, fep->hwp + FEC_ECNTRL);
1276 	fec_enet_active_rxring(ndev);
1277 
1278 	if (fep->bufdesc_ex) {
1279 		fec_ptp_start_cyclecounter(ndev);
1280 		fec_ptp_restore_state(fep);
1281 	}
1282 
1283 	/* Enable interrupts we wish to service */
1284 	if (fep->link)
1285 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1286 	else
1287 		writel(0, fep->hwp + FEC_IMASK);
1288 
1289 	/* Init the interrupt coalescing */
1290 	if (fep->quirks & FEC_QUIRK_HAS_COALESCE)
1291 		fec_enet_itr_coal_set(ndev);
1292 }
1293 
fec_enet_ipc_handle_init(struct fec_enet_private * fep)1294 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep)
1295 {
1296 	if (!(of_machine_is_compatible("fsl,imx8qm") ||
1297 	      of_machine_is_compatible("fsl,imx8qxp") ||
1298 	      of_machine_is_compatible("fsl,imx8dxl")))
1299 		return 0;
1300 
1301 	return imx_scu_get_handle(&fep->ipc_handle);
1302 }
1303 
fec_enet_ipg_stop_set(struct fec_enet_private * fep,bool enabled)1304 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled)
1305 {
1306 	struct device_node *np = fep->pdev->dev.of_node;
1307 	u32 rsrc_id, val;
1308 	int idx;
1309 
1310 	if (!np || !fep->ipc_handle)
1311 		return;
1312 
1313 	idx = of_alias_get_id(np, "ethernet");
1314 	if (idx < 0)
1315 		idx = 0;
1316 	rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0;
1317 
1318 	val = enabled ? 1 : 0;
1319 	imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val);
1320 }
1321 
fec_enet_stop_mode(struct fec_enet_private * fep,bool enabled)1322 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1323 {
1324 	struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1325 	struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1326 
1327 	if (stop_gpr->gpr) {
1328 		if (enabled)
1329 			regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1330 					   BIT(stop_gpr->bit),
1331 					   BIT(stop_gpr->bit));
1332 		else
1333 			regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1334 					   BIT(stop_gpr->bit), 0);
1335 	} else if (pdata && pdata->sleep_mode_enable) {
1336 		pdata->sleep_mode_enable(enabled);
1337 	} else {
1338 		fec_enet_ipg_stop_set(fep, enabled);
1339 	}
1340 }
1341 
fec_irqs_disable(struct net_device * ndev)1342 static void fec_irqs_disable(struct net_device *ndev)
1343 {
1344 	struct fec_enet_private *fep = netdev_priv(ndev);
1345 
1346 	writel(0, fep->hwp + FEC_IMASK);
1347 }
1348 
fec_irqs_disable_except_wakeup(struct net_device * ndev)1349 static void fec_irqs_disable_except_wakeup(struct net_device *ndev)
1350 {
1351 	struct fec_enet_private *fep = netdev_priv(ndev);
1352 
1353 	writel(0, fep->hwp + FEC_IMASK);
1354 	writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1355 }
1356 
1357 static void
fec_stop(struct net_device * ndev)1358 fec_stop(struct net_device *ndev)
1359 {
1360 	struct fec_enet_private *fep = netdev_priv(ndev);
1361 	u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII;
1362 	u32 val;
1363 
1364 	/* We cannot expect a graceful transmit stop without link !!! */
1365 	if (fep->link) {
1366 		writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1367 		udelay(10);
1368 		if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1369 			netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1370 	}
1371 
1372 	if (fep->bufdesc_ex)
1373 		fec_ptp_save_state(fep);
1374 
1375 	fec_ctrl_reset(fep, true);
1376 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1377 	writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1378 
1379 	/* We have to keep ENET enabled to have MII interrupt stay working */
1380 	if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1381 		!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1382 		writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL);
1383 		writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1384 	}
1385 
1386 	if (fep->bufdesc_ex) {
1387 		val = readl(fep->hwp + FEC_ECNTRL);
1388 		val |= FEC_ECR_EN1588;
1389 		writel(val, fep->hwp + FEC_ECNTRL);
1390 
1391 		fec_ptp_start_cyclecounter(ndev);
1392 		fec_ptp_restore_state(fep);
1393 	}
1394 }
1395 
1396 static void
fec_timeout(struct net_device * ndev,unsigned int txqueue)1397 fec_timeout(struct net_device *ndev, unsigned int txqueue)
1398 {
1399 	struct fec_enet_private *fep = netdev_priv(ndev);
1400 
1401 	fec_dump(ndev);
1402 
1403 	ndev->stats.tx_errors++;
1404 
1405 	schedule_work(&fep->tx_timeout_work);
1406 }
1407 
fec_enet_timeout_work(struct work_struct * work)1408 static void fec_enet_timeout_work(struct work_struct *work)
1409 {
1410 	struct fec_enet_private *fep =
1411 		container_of(work, struct fec_enet_private, tx_timeout_work);
1412 	struct net_device *ndev = fep->netdev;
1413 
1414 	rtnl_lock();
1415 	if (netif_device_present(ndev) || netif_running(ndev)) {
1416 		napi_disable(&fep->napi);
1417 		netif_tx_lock_bh(ndev);
1418 		fec_restart(ndev);
1419 		netif_tx_wake_all_queues(ndev);
1420 		netif_tx_unlock_bh(ndev);
1421 		napi_enable(&fep->napi);
1422 	}
1423 	rtnl_unlock();
1424 }
1425 
1426 static void
fec_enet_hwtstamp(struct fec_enet_private * fep,unsigned ts,struct skb_shared_hwtstamps * hwtstamps)1427 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1428 	struct skb_shared_hwtstamps *hwtstamps)
1429 {
1430 	unsigned long flags;
1431 	u64 ns;
1432 
1433 	spin_lock_irqsave(&fep->tmreg_lock, flags);
1434 	ns = timecounter_cyc2time(&fep->tc, ts);
1435 	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1436 
1437 	memset(hwtstamps, 0, sizeof(*hwtstamps));
1438 	hwtstamps->hwtstamp = ns_to_ktime(ns);
1439 }
1440 
1441 static void
fec_enet_tx_queue(struct net_device * ndev,u16 queue_id,int budget)1442 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget)
1443 {
1444 	struct	fec_enet_private *fep;
1445 	struct xdp_frame *xdpf;
1446 	struct bufdesc *bdp;
1447 	unsigned short status;
1448 	struct	sk_buff	*skb;
1449 	struct fec_enet_priv_tx_q *txq;
1450 	struct netdev_queue *nq;
1451 	int	index = 0;
1452 	int	entries_free;
1453 	struct page *page;
1454 	int frame_len;
1455 
1456 	fep = netdev_priv(ndev);
1457 
1458 	txq = fep->tx_queue[queue_id];
1459 	/* get next bdp of dirty_tx */
1460 	nq = netdev_get_tx_queue(ndev, queue_id);
1461 	bdp = txq->dirty_tx;
1462 
1463 	/* get next bdp of dirty_tx */
1464 	bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1465 
1466 	while (bdp != READ_ONCE(txq->bd.cur)) {
1467 		/* Order the load of bd.cur and cbd_sc */
1468 		rmb();
1469 		status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1470 		if (status & BD_ENET_TX_READY)
1471 			break;
1472 
1473 		index = fec_enet_get_bd_index(bdp, &txq->bd);
1474 
1475 		if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1476 			skb = txq->tx_buf[index].buf_p;
1477 			if (bdp->cbd_bufaddr &&
1478 			    !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1479 				dma_unmap_single(&fep->pdev->dev,
1480 						 fec32_to_cpu(bdp->cbd_bufaddr),
1481 						 fec16_to_cpu(bdp->cbd_datlen),
1482 						 DMA_TO_DEVICE);
1483 			bdp->cbd_bufaddr = cpu_to_fec32(0);
1484 			if (!skb)
1485 				goto tx_buf_done;
1486 		} else {
1487 			/* Tx processing cannot call any XDP (or page pool) APIs if
1488 			 * the "budget" is 0. Because NAPI is called with budget of
1489 			 * 0 (such as netpoll) indicates we may be in an IRQ context,
1490 			 * however, we can't use the page pool from IRQ context.
1491 			 */
1492 			if (unlikely(!budget))
1493 				break;
1494 
1495 			if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1496 				xdpf = txq->tx_buf[index].buf_p;
1497 				if (bdp->cbd_bufaddr)
1498 					dma_unmap_single(&fep->pdev->dev,
1499 							 fec32_to_cpu(bdp->cbd_bufaddr),
1500 							 fec16_to_cpu(bdp->cbd_datlen),
1501 							 DMA_TO_DEVICE);
1502 			} else {
1503 				page = txq->tx_buf[index].buf_p;
1504 			}
1505 
1506 			bdp->cbd_bufaddr = cpu_to_fec32(0);
1507 			if (unlikely(!txq->tx_buf[index].buf_p)) {
1508 				txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1509 				goto tx_buf_done;
1510 			}
1511 
1512 			frame_len = fec16_to_cpu(bdp->cbd_datlen);
1513 		}
1514 
1515 		/* Check for errors. */
1516 		if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1517 				   BD_ENET_TX_RL | BD_ENET_TX_UN |
1518 				   BD_ENET_TX_CSL)) {
1519 			ndev->stats.tx_errors++;
1520 			if (status & BD_ENET_TX_HB)  /* No heartbeat */
1521 				ndev->stats.tx_heartbeat_errors++;
1522 			if (status & BD_ENET_TX_LC)  /* Late collision */
1523 				ndev->stats.tx_window_errors++;
1524 			if (status & BD_ENET_TX_RL)  /* Retrans limit */
1525 				ndev->stats.tx_aborted_errors++;
1526 			if (status & BD_ENET_TX_UN)  /* Underrun */
1527 				ndev->stats.tx_fifo_errors++;
1528 			if (status & BD_ENET_TX_CSL) /* Carrier lost */
1529 				ndev->stats.tx_carrier_errors++;
1530 		} else {
1531 			ndev->stats.tx_packets++;
1532 
1533 			if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB)
1534 				ndev->stats.tx_bytes += skb->len;
1535 			else
1536 				ndev->stats.tx_bytes += frame_len;
1537 		}
1538 
1539 		/* Deferred means some collisions occurred during transmit,
1540 		 * but we eventually sent the packet OK.
1541 		 */
1542 		if (status & BD_ENET_TX_DEF)
1543 			ndev->stats.collisions++;
1544 
1545 		if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1546 			/* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1547 			 * are to time stamp the packet, so we still need to check time
1548 			 * stamping enabled flag.
1549 			 */
1550 			if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1551 				     fep->hwts_tx_en) && fep->bufdesc_ex) {
1552 				struct skb_shared_hwtstamps shhwtstamps;
1553 				struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1554 
1555 				fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1556 				skb_tstamp_tx(skb, &shhwtstamps);
1557 			}
1558 
1559 			/* Free the sk buffer associated with this last transmit */
1560 			napi_consume_skb(skb, budget);
1561 		} else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1562 			xdp_return_frame_rx_napi(xdpf);
1563 		} else { /* recycle pages of XDP_TX frames */
1564 			/* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */
1565 			page_pool_put_page(page->pp, page, 0, true);
1566 		}
1567 
1568 		txq->tx_buf[index].buf_p = NULL;
1569 		/* restore default tx buffer type: FEC_TXBUF_T_SKB */
1570 		txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1571 
1572 tx_buf_done:
1573 		/* Make sure the update to bdp and tx_buf are performed
1574 		 * before dirty_tx
1575 		 */
1576 		wmb();
1577 		txq->dirty_tx = bdp;
1578 
1579 		/* Update pointer to next buffer descriptor to be transmitted */
1580 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1581 
1582 		/* Since we have freed up a buffer, the ring is no longer full
1583 		 */
1584 		if (netif_tx_queue_stopped(nq)) {
1585 			entries_free = fec_enet_get_free_txdesc_num(txq);
1586 			if (entries_free >= txq->tx_wake_threshold)
1587 				netif_tx_wake_queue(nq);
1588 		}
1589 	}
1590 
1591 	/* ERR006358: Keep the transmitter going */
1592 	if (bdp != txq->bd.cur &&
1593 	    readl(txq->bd.reg_desc_active) == 0)
1594 		writel(0, txq->bd.reg_desc_active);
1595 }
1596 
fec_enet_tx(struct net_device * ndev,int budget)1597 static void fec_enet_tx(struct net_device *ndev, int budget)
1598 {
1599 	struct fec_enet_private *fep = netdev_priv(ndev);
1600 	int i;
1601 
1602 	/* Make sure that AVB queues are processed first. */
1603 	for (i = fep->num_tx_queues - 1; i >= 0; i--)
1604 		fec_enet_tx_queue(ndev, i, budget);
1605 }
1606 
fec_enet_update_cbd(struct fec_enet_priv_rx_q * rxq,struct bufdesc * bdp,int index)1607 static int fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq,
1608 				struct bufdesc *bdp, int index)
1609 {
1610 	struct page *new_page;
1611 	dma_addr_t phys_addr;
1612 
1613 	new_page = page_pool_dev_alloc_pages(rxq->page_pool);
1614 	if (unlikely(!new_page))
1615 		return -ENOMEM;
1616 
1617 	rxq->rx_skb_info[index].page = new_page;
1618 	rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM;
1619 	phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM;
1620 	bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
1621 
1622 	return 0;
1623 }
1624 
1625 static u32
fec_enet_run_xdp(struct fec_enet_private * fep,struct bpf_prog * prog,struct xdp_buff * xdp,struct fec_enet_priv_rx_q * rxq,int cpu)1626 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog,
1627 		 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu)
1628 {
1629 	unsigned int sync, len = xdp->data_end - xdp->data;
1630 	u32 ret = FEC_ENET_XDP_PASS;
1631 	struct page *page;
1632 	int err;
1633 	u32 act;
1634 
1635 	act = bpf_prog_run_xdp(prog, xdp);
1636 
1637 	/* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover
1638 	 * max len CPU touch
1639 	 */
1640 	sync = xdp->data_end - xdp->data;
1641 	sync = max(sync, len);
1642 
1643 	switch (act) {
1644 	case XDP_PASS:
1645 		rxq->stats[RX_XDP_PASS]++;
1646 		ret = FEC_ENET_XDP_PASS;
1647 		break;
1648 
1649 	case XDP_REDIRECT:
1650 		rxq->stats[RX_XDP_REDIRECT]++;
1651 		err = xdp_do_redirect(fep->netdev, xdp, prog);
1652 		if (unlikely(err))
1653 			goto xdp_err;
1654 
1655 		ret = FEC_ENET_XDP_REDIR;
1656 		break;
1657 
1658 	case XDP_TX:
1659 		rxq->stats[RX_XDP_TX]++;
1660 		err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync);
1661 		if (unlikely(err)) {
1662 			rxq->stats[RX_XDP_TX_ERRORS]++;
1663 			goto xdp_err;
1664 		}
1665 
1666 		ret = FEC_ENET_XDP_TX;
1667 		break;
1668 
1669 	default:
1670 		bpf_warn_invalid_xdp_action(fep->netdev, prog, act);
1671 		fallthrough;
1672 
1673 	case XDP_ABORTED:
1674 		fallthrough;    /* handle aborts by dropping packet */
1675 
1676 	case XDP_DROP:
1677 		rxq->stats[RX_XDP_DROP]++;
1678 xdp_err:
1679 		ret = FEC_ENET_XDP_CONSUMED;
1680 		page = virt_to_head_page(xdp->data);
1681 		page_pool_put_page(rxq->page_pool, page, sync, true);
1682 		if (act != XDP_DROP)
1683 			trace_xdp_exception(fep->netdev, prog, act);
1684 		break;
1685 	}
1686 
1687 	return ret;
1688 }
1689 
1690 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1691  * When we update through the ring, if the next incoming buffer has
1692  * not been given to the system, we just set the empty indicator,
1693  * effectively tossing the packet.
1694  */
1695 static int
fec_enet_rx_queue(struct net_device * ndev,int budget,u16 queue_id)1696 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1697 {
1698 	struct fec_enet_private *fep = netdev_priv(ndev);
1699 	struct fec_enet_priv_rx_q *rxq;
1700 	struct bufdesc *bdp;
1701 	unsigned short status;
1702 	struct  sk_buff *skb;
1703 	ushort	pkt_len;
1704 	__u8 *data;
1705 	int	pkt_received = 0;
1706 	struct	bufdesc_ex *ebdp = NULL;
1707 	bool	vlan_packet_rcvd = false;
1708 	u16	vlan_tag;
1709 	int	index = 0;
1710 	bool	need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1711 	struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
1712 	u32 ret, xdp_result = FEC_ENET_XDP_PASS;
1713 	u32 data_start = FEC_ENET_XDP_HEADROOM;
1714 	int cpu = smp_processor_id();
1715 	struct xdp_buff xdp;
1716 	struct page *page;
1717 	__fec32 cbd_bufaddr;
1718 	u32 sub_len = 4;
1719 
1720 #if !defined(CONFIG_M5272)
1721 	/*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of
1722 	 * FEC_RACC_SHIFT16 is set by default in the probe function.
1723 	 */
1724 	if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1725 		data_start += 2;
1726 		sub_len += 2;
1727 	}
1728 #endif
1729 
1730 #ifdef CONFIG_M532x
1731 	flush_cache_all();
1732 #endif
1733 	rxq = fep->rx_queue[queue_id];
1734 
1735 	/* First, grab all of the stats for the incoming packet.
1736 	 * These get messed up if we get called due to a busy condition.
1737 	 */
1738 	bdp = rxq->bd.cur;
1739 	xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq);
1740 
1741 	while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1742 
1743 		if (pkt_received >= budget)
1744 			break;
1745 		pkt_received++;
1746 
1747 		writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1748 
1749 		/* Check for errors. */
1750 		status ^= BD_ENET_RX_LAST;
1751 		if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1752 			   BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1753 			   BD_ENET_RX_CL)) {
1754 			ndev->stats.rx_errors++;
1755 			if (status & BD_ENET_RX_OV) {
1756 				/* FIFO overrun */
1757 				ndev->stats.rx_fifo_errors++;
1758 				goto rx_processing_done;
1759 			}
1760 			if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1761 						| BD_ENET_RX_LAST)) {
1762 				/* Frame too long or too short. */
1763 				ndev->stats.rx_length_errors++;
1764 				if (status & BD_ENET_RX_LAST)
1765 					netdev_err(ndev, "rcv is not +last\n");
1766 			}
1767 			if (status & BD_ENET_RX_CR)	/* CRC Error */
1768 				ndev->stats.rx_crc_errors++;
1769 			/* Report late collisions as a frame error. */
1770 			if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1771 				ndev->stats.rx_frame_errors++;
1772 			goto rx_processing_done;
1773 		}
1774 
1775 		/* Process the incoming frame. */
1776 		ndev->stats.rx_packets++;
1777 		pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1778 		ndev->stats.rx_bytes += pkt_len;
1779 
1780 		index = fec_enet_get_bd_index(bdp, &rxq->bd);
1781 		page = rxq->rx_skb_info[index].page;
1782 		cbd_bufaddr = bdp->cbd_bufaddr;
1783 		if (fec_enet_update_cbd(rxq, bdp, index)) {
1784 			ndev->stats.rx_dropped++;
1785 			goto rx_processing_done;
1786 		}
1787 
1788 		dma_sync_single_for_cpu(&fep->pdev->dev,
1789 					fec32_to_cpu(cbd_bufaddr),
1790 					pkt_len,
1791 					DMA_FROM_DEVICE);
1792 		prefetch(page_address(page));
1793 
1794 		if (xdp_prog) {
1795 			xdp_buff_clear_frags_flag(&xdp);
1796 			/* subtract 16bit shift and FCS */
1797 			xdp_prepare_buff(&xdp, page_address(page),
1798 					 data_start, pkt_len - sub_len, false);
1799 			ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu);
1800 			xdp_result |= ret;
1801 			if (ret != FEC_ENET_XDP_PASS)
1802 				goto rx_processing_done;
1803 		}
1804 
1805 		/* The packet length includes FCS, but we don't want to
1806 		 * include that when passing upstream as it messes up
1807 		 * bridging applications.
1808 		 */
1809 		skb = build_skb(page_address(page), PAGE_SIZE);
1810 		if (unlikely(!skb)) {
1811 			page_pool_recycle_direct(rxq->page_pool, page);
1812 			ndev->stats.rx_dropped++;
1813 
1814 			netdev_err_once(ndev, "build_skb failed!\n");
1815 			goto rx_processing_done;
1816 		}
1817 
1818 		skb_reserve(skb, data_start);
1819 		skb_put(skb, pkt_len - sub_len);
1820 		skb_mark_for_recycle(skb);
1821 
1822 		if (unlikely(need_swap)) {
1823 			data = page_address(page) + FEC_ENET_XDP_HEADROOM;
1824 			swap_buffer(data, pkt_len);
1825 		}
1826 		data = skb->data;
1827 
1828 		/* Extract the enhanced buffer descriptor */
1829 		ebdp = NULL;
1830 		if (fep->bufdesc_ex)
1831 			ebdp = (struct bufdesc_ex *)bdp;
1832 
1833 		/* If this is a VLAN packet remove the VLAN Tag */
1834 		vlan_packet_rcvd = false;
1835 		if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1836 		    fep->bufdesc_ex &&
1837 		    (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1838 			/* Push and remove the vlan tag */
1839 			struct vlan_hdr *vlan_header =
1840 					(struct vlan_hdr *) (data + ETH_HLEN);
1841 			vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1842 
1843 			vlan_packet_rcvd = true;
1844 
1845 			memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1846 			skb_pull(skb, VLAN_HLEN);
1847 		}
1848 
1849 		skb->protocol = eth_type_trans(skb, ndev);
1850 
1851 		/* Get receive timestamp from the skb */
1852 		if (fep->hwts_rx_en && fep->bufdesc_ex)
1853 			fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1854 					  skb_hwtstamps(skb));
1855 
1856 		if (fep->bufdesc_ex &&
1857 		    (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1858 			if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1859 				/* don't check it */
1860 				skb->ip_summed = CHECKSUM_UNNECESSARY;
1861 			} else {
1862 				skb_checksum_none_assert(skb);
1863 			}
1864 		}
1865 
1866 		/* Handle received VLAN packets */
1867 		if (vlan_packet_rcvd)
1868 			__vlan_hwaccel_put_tag(skb,
1869 					       htons(ETH_P_8021Q),
1870 					       vlan_tag);
1871 
1872 		skb_record_rx_queue(skb, queue_id);
1873 		napi_gro_receive(&fep->napi, skb);
1874 
1875 rx_processing_done:
1876 		/* Clear the status flags for this buffer */
1877 		status &= ~BD_ENET_RX_STATS;
1878 
1879 		/* Mark the buffer empty */
1880 		status |= BD_ENET_RX_EMPTY;
1881 
1882 		if (fep->bufdesc_ex) {
1883 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1884 
1885 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1886 			ebdp->cbd_prot = 0;
1887 			ebdp->cbd_bdu = 0;
1888 		}
1889 		/* Make sure the updates to rest of the descriptor are
1890 		 * performed before transferring ownership.
1891 		 */
1892 		wmb();
1893 		bdp->cbd_sc = cpu_to_fec16(status);
1894 
1895 		/* Update BD pointer to next entry */
1896 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1897 
1898 		/* Doing this here will keep the FEC running while we process
1899 		 * incoming frames.  On a heavily loaded network, we should be
1900 		 * able to keep up at the expense of system resources.
1901 		 */
1902 		writel(0, rxq->bd.reg_desc_active);
1903 	}
1904 	rxq->bd.cur = bdp;
1905 
1906 	if (xdp_result & FEC_ENET_XDP_REDIR)
1907 		xdp_do_flush_map();
1908 
1909 	return pkt_received;
1910 }
1911 
fec_enet_rx(struct net_device * ndev,int budget)1912 static int fec_enet_rx(struct net_device *ndev, int budget)
1913 {
1914 	struct fec_enet_private *fep = netdev_priv(ndev);
1915 	int i, done = 0;
1916 
1917 	/* Make sure that AVB queues are processed first. */
1918 	for (i = fep->num_rx_queues - 1; i >= 0; i--)
1919 		done += fec_enet_rx_queue(ndev, budget - done, i);
1920 
1921 	return done;
1922 }
1923 
fec_enet_collect_events(struct fec_enet_private * fep)1924 static bool fec_enet_collect_events(struct fec_enet_private *fep)
1925 {
1926 	uint int_events;
1927 
1928 	int_events = readl(fep->hwp + FEC_IEVENT);
1929 
1930 	/* Don't clear MDIO events, we poll for those */
1931 	int_events &= ~FEC_ENET_MII;
1932 
1933 	writel(int_events, fep->hwp + FEC_IEVENT);
1934 
1935 	return int_events != 0;
1936 }
1937 
1938 static irqreturn_t
fec_enet_interrupt(int irq,void * dev_id)1939 fec_enet_interrupt(int irq, void *dev_id)
1940 {
1941 	struct net_device *ndev = dev_id;
1942 	struct fec_enet_private *fep = netdev_priv(ndev);
1943 	irqreturn_t ret = IRQ_NONE;
1944 
1945 	if (fec_enet_collect_events(fep) && fep->link) {
1946 		ret = IRQ_HANDLED;
1947 
1948 		if (napi_schedule_prep(&fep->napi)) {
1949 			/* Disable interrupts */
1950 			writel(0, fep->hwp + FEC_IMASK);
1951 			__napi_schedule(&fep->napi);
1952 		}
1953 	}
1954 
1955 	return ret;
1956 }
1957 
fec_enet_rx_napi(struct napi_struct * napi,int budget)1958 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1959 {
1960 	struct net_device *ndev = napi->dev;
1961 	struct fec_enet_private *fep = netdev_priv(ndev);
1962 	int done = 0;
1963 
1964 	do {
1965 		done += fec_enet_rx(ndev, budget - done);
1966 		fec_enet_tx(ndev, budget);
1967 	} while ((done < budget) && fec_enet_collect_events(fep));
1968 
1969 	if (done < budget) {
1970 		napi_complete_done(napi, done);
1971 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1972 	}
1973 
1974 	return done;
1975 }
1976 
1977 /* ------------------------------------------------------------------------- */
fec_get_mac(struct net_device * ndev)1978 static int fec_get_mac(struct net_device *ndev)
1979 {
1980 	struct fec_enet_private *fep = netdev_priv(ndev);
1981 	unsigned char *iap, tmpaddr[ETH_ALEN];
1982 	int ret;
1983 
1984 	/*
1985 	 * try to get mac address in following order:
1986 	 *
1987 	 * 1) module parameter via kernel command line in form
1988 	 *    fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1989 	 */
1990 	iap = macaddr;
1991 
1992 	/*
1993 	 * 2) from device tree data
1994 	 */
1995 	if (!is_valid_ether_addr(iap)) {
1996 		struct device_node *np = fep->pdev->dev.of_node;
1997 		if (np) {
1998 			ret = of_get_mac_address(np, tmpaddr);
1999 			if (!ret)
2000 				iap = tmpaddr;
2001 			else if (ret == -EPROBE_DEFER)
2002 				return ret;
2003 		}
2004 	}
2005 
2006 	/*
2007 	 * 3) from flash or fuse (via platform data)
2008 	 */
2009 	if (!is_valid_ether_addr(iap)) {
2010 #ifdef CONFIG_M5272
2011 		if (FEC_FLASHMAC)
2012 			iap = (unsigned char *)FEC_FLASHMAC;
2013 #else
2014 		struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
2015 
2016 		if (pdata)
2017 			iap = (unsigned char *)&pdata->mac;
2018 #endif
2019 	}
2020 
2021 	/*
2022 	 * 4) FEC mac registers set by bootloader
2023 	 */
2024 	if (!is_valid_ether_addr(iap)) {
2025 		*((__be32 *) &tmpaddr[0]) =
2026 			cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
2027 		*((__be16 *) &tmpaddr[4]) =
2028 			cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
2029 		iap = &tmpaddr[0];
2030 	}
2031 
2032 	/*
2033 	 * 5) random mac address
2034 	 */
2035 	if (!is_valid_ether_addr(iap)) {
2036 		/* Report it and use a random ethernet address instead */
2037 		dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
2038 		eth_hw_addr_random(ndev);
2039 		dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
2040 			 ndev->dev_addr);
2041 		return 0;
2042 	}
2043 
2044 	/* Adjust MAC if using macaddr */
2045 	eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0);
2046 
2047 	return 0;
2048 }
2049 
2050 /* ------------------------------------------------------------------------- */
2051 
2052 /*
2053  * Phy section
2054  */
fec_enet_adjust_link(struct net_device * ndev)2055 static void fec_enet_adjust_link(struct net_device *ndev)
2056 {
2057 	struct fec_enet_private *fep = netdev_priv(ndev);
2058 	struct phy_device *phy_dev = ndev->phydev;
2059 	int status_change = 0;
2060 
2061 	/*
2062 	 * If the netdev is down, or is going down, we're not interested
2063 	 * in link state events, so just mark our idea of the link as down
2064 	 * and ignore the event.
2065 	 */
2066 	if (!netif_running(ndev) || !netif_device_present(ndev)) {
2067 		fep->link = 0;
2068 	} else if (phy_dev->link) {
2069 		if (!fep->link) {
2070 			fep->link = phy_dev->link;
2071 			status_change = 1;
2072 		}
2073 
2074 		if (fep->full_duplex != phy_dev->duplex) {
2075 			fep->full_duplex = phy_dev->duplex;
2076 			status_change = 1;
2077 		}
2078 
2079 		if (phy_dev->speed != fep->speed) {
2080 			fep->speed = phy_dev->speed;
2081 			status_change = 1;
2082 		}
2083 
2084 		/* if any of the above changed restart the FEC */
2085 		if (status_change) {
2086 			netif_stop_queue(ndev);
2087 			napi_disable(&fep->napi);
2088 			netif_tx_lock_bh(ndev);
2089 			fec_restart(ndev);
2090 			netif_tx_wake_all_queues(ndev);
2091 			netif_tx_unlock_bh(ndev);
2092 			napi_enable(&fep->napi);
2093 		}
2094 	} else {
2095 		if (fep->link) {
2096 			netif_stop_queue(ndev);
2097 			napi_disable(&fep->napi);
2098 			netif_tx_lock_bh(ndev);
2099 			fec_stop(ndev);
2100 			netif_tx_unlock_bh(ndev);
2101 			napi_enable(&fep->napi);
2102 			fep->link = phy_dev->link;
2103 			status_change = 1;
2104 		}
2105 	}
2106 
2107 	if (status_change)
2108 		phy_print_status(phy_dev);
2109 }
2110 
fec_enet_mdio_wait(struct fec_enet_private * fep)2111 static int fec_enet_mdio_wait(struct fec_enet_private *fep)
2112 {
2113 	uint ievent;
2114 	int ret;
2115 
2116 	ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
2117 					ievent & FEC_ENET_MII, 2, 30000);
2118 
2119 	if (!ret)
2120 		writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2121 
2122 	return ret;
2123 }
2124 
fec_enet_mdio_read_c22(struct mii_bus * bus,int mii_id,int regnum)2125 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
2126 {
2127 	struct fec_enet_private *fep = bus->priv;
2128 	struct device *dev = &fep->pdev->dev;
2129 	int ret = 0, frame_start, frame_addr, frame_op;
2130 
2131 	ret = pm_runtime_resume_and_get(dev);
2132 	if (ret < 0)
2133 		return ret;
2134 
2135 	/* C22 read */
2136 	frame_op = FEC_MMFR_OP_READ;
2137 	frame_start = FEC_MMFR_ST;
2138 	frame_addr = regnum;
2139 
2140 	/* start a read op */
2141 	writel(frame_start | frame_op |
2142 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2143 	       FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2144 
2145 	/* wait for end of transfer */
2146 	ret = fec_enet_mdio_wait(fep);
2147 	if (ret) {
2148 		netdev_err(fep->netdev, "MDIO read timeout\n");
2149 		goto out;
2150 	}
2151 
2152 	ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2153 
2154 out:
2155 	pm_runtime_mark_last_busy(dev);
2156 	pm_runtime_put_autosuspend(dev);
2157 
2158 	return ret;
2159 }
2160 
fec_enet_mdio_read_c45(struct mii_bus * bus,int mii_id,int devad,int regnum)2161 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id,
2162 				  int devad, int regnum)
2163 {
2164 	struct fec_enet_private *fep = bus->priv;
2165 	struct device *dev = &fep->pdev->dev;
2166 	int ret = 0, frame_start, frame_op;
2167 
2168 	ret = pm_runtime_resume_and_get(dev);
2169 	if (ret < 0)
2170 		return ret;
2171 
2172 	frame_start = FEC_MMFR_ST_C45;
2173 
2174 	/* write address */
2175 	writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2176 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2177 	       FEC_MMFR_TA | (regnum & 0xFFFF),
2178 	       fep->hwp + FEC_MII_DATA);
2179 
2180 	/* wait for end of transfer */
2181 	ret = fec_enet_mdio_wait(fep);
2182 	if (ret) {
2183 		netdev_err(fep->netdev, "MDIO address write timeout\n");
2184 		goto out;
2185 	}
2186 
2187 	frame_op = FEC_MMFR_OP_READ_C45;
2188 
2189 	/* start a read op */
2190 	writel(frame_start | frame_op |
2191 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2192 	       FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2193 
2194 	/* wait for end of transfer */
2195 	ret = fec_enet_mdio_wait(fep);
2196 	if (ret) {
2197 		netdev_err(fep->netdev, "MDIO read timeout\n");
2198 		goto out;
2199 	}
2200 
2201 	ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2202 
2203 out:
2204 	pm_runtime_mark_last_busy(dev);
2205 	pm_runtime_put_autosuspend(dev);
2206 
2207 	return ret;
2208 }
2209 
fec_enet_mdio_write_c22(struct mii_bus * bus,int mii_id,int regnum,u16 value)2210 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
2211 				   u16 value)
2212 {
2213 	struct fec_enet_private *fep = bus->priv;
2214 	struct device *dev = &fep->pdev->dev;
2215 	int ret, frame_start, frame_addr;
2216 
2217 	ret = pm_runtime_resume_and_get(dev);
2218 	if (ret < 0)
2219 		return ret;
2220 
2221 	/* C22 write */
2222 	frame_start = FEC_MMFR_ST;
2223 	frame_addr = regnum;
2224 
2225 	/* start a write op */
2226 	writel(frame_start | FEC_MMFR_OP_WRITE |
2227 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2228 	       FEC_MMFR_TA | FEC_MMFR_DATA(value),
2229 	       fep->hwp + FEC_MII_DATA);
2230 
2231 	/* wait for end of transfer */
2232 	ret = fec_enet_mdio_wait(fep);
2233 	if (ret)
2234 		netdev_err(fep->netdev, "MDIO write timeout\n");
2235 
2236 	pm_runtime_mark_last_busy(dev);
2237 	pm_runtime_put_autosuspend(dev);
2238 
2239 	return ret;
2240 }
2241 
fec_enet_mdio_write_c45(struct mii_bus * bus,int mii_id,int devad,int regnum,u16 value)2242 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id,
2243 				   int devad, int regnum, u16 value)
2244 {
2245 	struct fec_enet_private *fep = bus->priv;
2246 	struct device *dev = &fep->pdev->dev;
2247 	int ret, frame_start;
2248 
2249 	ret = pm_runtime_resume_and_get(dev);
2250 	if (ret < 0)
2251 		return ret;
2252 
2253 	frame_start = FEC_MMFR_ST_C45;
2254 
2255 	/* write address */
2256 	writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2257 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2258 	       FEC_MMFR_TA | (regnum & 0xFFFF),
2259 	       fep->hwp + FEC_MII_DATA);
2260 
2261 	/* wait for end of transfer */
2262 	ret = fec_enet_mdio_wait(fep);
2263 	if (ret) {
2264 		netdev_err(fep->netdev, "MDIO address write timeout\n");
2265 		goto out;
2266 	}
2267 
2268 	/* start a write op */
2269 	writel(frame_start | FEC_MMFR_OP_WRITE |
2270 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2271 	       FEC_MMFR_TA | FEC_MMFR_DATA(value),
2272 	       fep->hwp + FEC_MII_DATA);
2273 
2274 	/* wait for end of transfer */
2275 	ret = fec_enet_mdio_wait(fep);
2276 	if (ret)
2277 		netdev_err(fep->netdev, "MDIO write timeout\n");
2278 
2279 out:
2280 	pm_runtime_mark_last_busy(dev);
2281 	pm_runtime_put_autosuspend(dev);
2282 
2283 	return ret;
2284 }
2285 
fec_enet_phy_reset_after_clk_enable(struct net_device * ndev)2286 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
2287 {
2288 	struct fec_enet_private *fep = netdev_priv(ndev);
2289 	struct phy_device *phy_dev = ndev->phydev;
2290 
2291 	if (phy_dev) {
2292 		phy_reset_after_clk_enable(phy_dev);
2293 	} else if (fep->phy_node) {
2294 		/*
2295 		 * If the PHY still is not bound to the MAC, but there is
2296 		 * OF PHY node and a matching PHY device instance already,
2297 		 * use the OF PHY node to obtain the PHY device instance,
2298 		 * and then use that PHY device instance when triggering
2299 		 * the PHY reset.
2300 		 */
2301 		phy_dev = of_phy_find_device(fep->phy_node);
2302 		phy_reset_after_clk_enable(phy_dev);
2303 		put_device(&phy_dev->mdio.dev);
2304 	}
2305 }
2306 
fec_enet_clk_enable(struct net_device * ndev,bool enable)2307 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
2308 {
2309 	struct fec_enet_private *fep = netdev_priv(ndev);
2310 	int ret;
2311 
2312 	if (enable) {
2313 		ret = clk_prepare_enable(fep->clk_enet_out);
2314 		if (ret)
2315 			return ret;
2316 
2317 		if (fep->clk_ptp) {
2318 			mutex_lock(&fep->ptp_clk_mutex);
2319 			ret = clk_prepare_enable(fep->clk_ptp);
2320 			if (ret) {
2321 				mutex_unlock(&fep->ptp_clk_mutex);
2322 				goto failed_clk_ptp;
2323 			} else {
2324 				fep->ptp_clk_on = true;
2325 			}
2326 			mutex_unlock(&fep->ptp_clk_mutex);
2327 		}
2328 
2329 		ret = clk_prepare_enable(fep->clk_ref);
2330 		if (ret)
2331 			goto failed_clk_ref;
2332 
2333 		ret = clk_prepare_enable(fep->clk_2x_txclk);
2334 		if (ret)
2335 			goto failed_clk_2x_txclk;
2336 
2337 		fec_enet_phy_reset_after_clk_enable(ndev);
2338 	} else {
2339 		clk_disable_unprepare(fep->clk_enet_out);
2340 		if (fep->clk_ptp) {
2341 			mutex_lock(&fep->ptp_clk_mutex);
2342 			clk_disable_unprepare(fep->clk_ptp);
2343 			fep->ptp_clk_on = false;
2344 			mutex_unlock(&fep->ptp_clk_mutex);
2345 		}
2346 		clk_disable_unprepare(fep->clk_ref);
2347 		clk_disable_unprepare(fep->clk_2x_txclk);
2348 	}
2349 
2350 	return 0;
2351 
2352 failed_clk_2x_txclk:
2353 	if (fep->clk_ref)
2354 		clk_disable_unprepare(fep->clk_ref);
2355 failed_clk_ref:
2356 	if (fep->clk_ptp) {
2357 		mutex_lock(&fep->ptp_clk_mutex);
2358 		clk_disable_unprepare(fep->clk_ptp);
2359 		fep->ptp_clk_on = false;
2360 		mutex_unlock(&fep->ptp_clk_mutex);
2361 	}
2362 failed_clk_ptp:
2363 	clk_disable_unprepare(fep->clk_enet_out);
2364 
2365 	return ret;
2366 }
2367 
fec_enet_parse_rgmii_delay(struct fec_enet_private * fep,struct device_node * np)2368 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep,
2369 				      struct device_node *np)
2370 {
2371 	u32 rgmii_tx_delay, rgmii_rx_delay;
2372 
2373 	/* For rgmii tx internal delay, valid values are 0ps and 2000ps */
2374 	if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) {
2375 		if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) {
2376 			dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps");
2377 			return -EINVAL;
2378 		} else if (rgmii_tx_delay == 2000) {
2379 			fep->rgmii_txc_dly = true;
2380 		}
2381 	}
2382 
2383 	/* For rgmii rx internal delay, valid values are 0ps and 2000ps */
2384 	if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) {
2385 		if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) {
2386 			dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps");
2387 			return -EINVAL;
2388 		} else if (rgmii_rx_delay == 2000) {
2389 			fep->rgmii_rxc_dly = true;
2390 		}
2391 	}
2392 
2393 	return 0;
2394 }
2395 
fec_enet_mii_probe(struct net_device * ndev)2396 static int fec_enet_mii_probe(struct net_device *ndev)
2397 {
2398 	struct fec_enet_private *fep = netdev_priv(ndev);
2399 	struct phy_device *phy_dev = NULL;
2400 	char mdio_bus_id[MII_BUS_ID_SIZE];
2401 	char phy_name[MII_BUS_ID_SIZE + 3];
2402 	int phy_id;
2403 	int dev_id = fep->dev_id;
2404 
2405 	if (fep->phy_node) {
2406 		phy_dev = of_phy_connect(ndev, fep->phy_node,
2407 					 &fec_enet_adjust_link, 0,
2408 					 fep->phy_interface);
2409 		if (!phy_dev) {
2410 			netdev_err(ndev, "Unable to connect to phy\n");
2411 			return -ENODEV;
2412 		}
2413 	} else {
2414 		/* check for attached phy */
2415 		for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2416 			if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2417 				continue;
2418 			if (dev_id--)
2419 				continue;
2420 			strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2421 			break;
2422 		}
2423 
2424 		if (phy_id >= PHY_MAX_ADDR) {
2425 			netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2426 			strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2427 			phy_id = 0;
2428 		}
2429 
2430 		snprintf(phy_name, sizeof(phy_name),
2431 			 PHY_ID_FMT, mdio_bus_id, phy_id);
2432 		phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2433 				      fep->phy_interface);
2434 	}
2435 
2436 	if (IS_ERR(phy_dev)) {
2437 		netdev_err(ndev, "could not attach to PHY\n");
2438 		return PTR_ERR(phy_dev);
2439 	}
2440 
2441 	/* mask with MAC supported features */
2442 	if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2443 		phy_set_max_speed(phy_dev, 1000);
2444 		phy_remove_link_mode(phy_dev,
2445 				     ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2446 #if !defined(CONFIG_M5272)
2447 		phy_support_sym_pause(phy_dev);
2448 #endif
2449 	}
2450 	else
2451 		phy_set_max_speed(phy_dev, 100);
2452 
2453 	fep->link = 0;
2454 	fep->full_duplex = 0;
2455 
2456 	phy_attached_info(phy_dev);
2457 
2458 	return 0;
2459 }
2460 
fec_enet_mii_init(struct platform_device * pdev)2461 static int fec_enet_mii_init(struct platform_device *pdev)
2462 {
2463 	static struct mii_bus *fec0_mii_bus;
2464 	struct net_device *ndev = platform_get_drvdata(pdev);
2465 	struct fec_enet_private *fep = netdev_priv(ndev);
2466 	bool suppress_preamble = false;
2467 	struct phy_device *phydev;
2468 	struct device_node *node;
2469 	int err = -ENXIO;
2470 	u32 mii_speed, holdtime;
2471 	u32 bus_freq;
2472 	int addr;
2473 
2474 	/*
2475 	 * The i.MX28 dual fec interfaces are not equal.
2476 	 * Here are the differences:
2477 	 *
2478 	 *  - fec0 supports MII & RMII modes while fec1 only supports RMII
2479 	 *  - fec0 acts as the 1588 time master while fec1 is slave
2480 	 *  - external phys can only be configured by fec0
2481 	 *
2482 	 * That is to say fec1 can not work independently. It only works
2483 	 * when fec0 is working. The reason behind this design is that the
2484 	 * second interface is added primarily for Switch mode.
2485 	 *
2486 	 * Because of the last point above, both phys are attached on fec0
2487 	 * mdio interface in board design, and need to be configured by
2488 	 * fec0 mii_bus.
2489 	 */
2490 	if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2491 		/* fec1 uses fec0 mii_bus */
2492 		if (mii_cnt && fec0_mii_bus) {
2493 			fep->mii_bus = fec0_mii_bus;
2494 			mii_cnt++;
2495 			return 0;
2496 		}
2497 		return -ENOENT;
2498 	}
2499 
2500 	bus_freq = 2500000; /* 2.5MHz by default */
2501 	node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2502 	if (node) {
2503 		of_property_read_u32(node, "clock-frequency", &bus_freq);
2504 		suppress_preamble = of_property_read_bool(node,
2505 							  "suppress-preamble");
2506 	}
2507 
2508 	/*
2509 	 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2510 	 *
2511 	 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2512 	 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.  The i.MX28
2513 	 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2514 	 * document.
2515 	 */
2516 	mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2517 	if (fep->quirks & FEC_QUIRK_ENET_MAC)
2518 		mii_speed--;
2519 	if (mii_speed > 63) {
2520 		dev_err(&pdev->dev,
2521 			"fec clock (%lu) too fast to get right mii speed\n",
2522 			clk_get_rate(fep->clk_ipg));
2523 		err = -EINVAL;
2524 		goto err_out;
2525 	}
2526 
2527 	/*
2528 	 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2529 	 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2530 	 * versions are RAZ there, so just ignore the difference and write the
2531 	 * register always.
2532 	 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2533 	 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2534 	 * output.
2535 	 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2536 	 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2537 	 * holdtime cannot result in a value greater than 3.
2538 	 */
2539 	holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2540 
2541 	fep->phy_speed = mii_speed << 1 | holdtime << 8;
2542 
2543 	if (suppress_preamble)
2544 		fep->phy_speed |= BIT(7);
2545 
2546 	if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2547 		/* Clear MMFR to avoid to generate MII event by writing MSCR.
2548 		 * MII event generation condition:
2549 		 * - writing MSCR:
2550 		 *	- mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2551 		 *	  mscr_reg_data_in[7:0] != 0
2552 		 * - writing MMFR:
2553 		 *	- mscr[7:0]_not_zero
2554 		 */
2555 		writel(0, fep->hwp + FEC_MII_DATA);
2556 	}
2557 
2558 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2559 
2560 	/* Clear any pending transaction complete indication */
2561 	writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2562 
2563 	fep->mii_bus = mdiobus_alloc();
2564 	if (fep->mii_bus == NULL) {
2565 		err = -ENOMEM;
2566 		goto err_out;
2567 	}
2568 
2569 	fep->mii_bus->name = "fec_enet_mii_bus";
2570 	fep->mii_bus->read = fec_enet_mdio_read_c22;
2571 	fep->mii_bus->write = fec_enet_mdio_write_c22;
2572 	if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) {
2573 		fep->mii_bus->read_c45 = fec_enet_mdio_read_c45;
2574 		fep->mii_bus->write_c45 = fec_enet_mdio_write_c45;
2575 	}
2576 	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2577 		pdev->name, fep->dev_id + 1);
2578 	fep->mii_bus->priv = fep;
2579 	fep->mii_bus->parent = &pdev->dev;
2580 
2581 	err = of_mdiobus_register(fep->mii_bus, node);
2582 	if (err)
2583 		goto err_out_free_mdiobus;
2584 	of_node_put(node);
2585 
2586 	/* find all the PHY devices on the bus and set mac_managed_pm to true */
2587 	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
2588 		phydev = mdiobus_get_phy(fep->mii_bus, addr);
2589 		if (phydev)
2590 			phydev->mac_managed_pm = true;
2591 	}
2592 
2593 	mii_cnt++;
2594 
2595 	/* save fec0 mii_bus */
2596 	if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2597 		fec0_mii_bus = fep->mii_bus;
2598 
2599 	return 0;
2600 
2601 err_out_free_mdiobus:
2602 	mdiobus_free(fep->mii_bus);
2603 err_out:
2604 	of_node_put(node);
2605 	return err;
2606 }
2607 
fec_enet_mii_remove(struct fec_enet_private * fep)2608 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2609 {
2610 	if (--mii_cnt == 0) {
2611 		mdiobus_unregister(fep->mii_bus);
2612 		mdiobus_free(fep->mii_bus);
2613 	}
2614 }
2615 
fec_enet_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * info)2616 static void fec_enet_get_drvinfo(struct net_device *ndev,
2617 				 struct ethtool_drvinfo *info)
2618 {
2619 	struct fec_enet_private *fep = netdev_priv(ndev);
2620 
2621 	strscpy(info->driver, fep->pdev->dev.driver->name,
2622 		sizeof(info->driver));
2623 	strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2624 }
2625 
fec_enet_get_regs_len(struct net_device * ndev)2626 static int fec_enet_get_regs_len(struct net_device *ndev)
2627 {
2628 	struct fec_enet_private *fep = netdev_priv(ndev);
2629 	struct resource *r;
2630 	int s = 0;
2631 
2632 	r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2633 	if (r)
2634 		s = resource_size(r);
2635 
2636 	return s;
2637 }
2638 
2639 /* List of registers that can be safety be read to dump them with ethtool */
2640 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2641 	defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2642 	defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2643 static __u32 fec_enet_register_version = 2;
2644 static u32 fec_enet_register_offset[] = {
2645 	FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2646 	FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2647 	FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2648 	FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2649 	FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2650 	FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2651 	FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2652 	FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2653 	FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2654 	FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2655 	FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2656 	FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2657 	RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2658 	RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2659 	RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2660 	RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2661 	RMON_T_P_GTE2048, RMON_T_OCTETS,
2662 	IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2663 	IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2664 	IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2665 	RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2666 	RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2667 	RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2668 	RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2669 	RMON_R_P_GTE2048, RMON_R_OCTETS,
2670 	IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2671 	IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2672 };
2673 /* for i.MX6ul */
2674 static u32 fec_enet_register_offset_6ul[] = {
2675 	FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2676 	FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2677 	FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0,
2678 	FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH,
2679 	FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0,
2680 	FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2681 	FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC,
2682 	RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2683 	RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2684 	RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2685 	RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2686 	RMON_T_P_GTE2048, RMON_T_OCTETS,
2687 	IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2688 	IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2689 	IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2690 	RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2691 	RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2692 	RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2693 	RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2694 	RMON_R_P_GTE2048, RMON_R_OCTETS,
2695 	IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2696 	IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2697 };
2698 #else
2699 static __u32 fec_enet_register_version = 1;
2700 static u32 fec_enet_register_offset[] = {
2701 	FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2702 	FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2703 	FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2704 	FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2705 	FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2706 	FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2707 	FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2708 	FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2709 	FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2710 };
2711 #endif
2712 
fec_enet_get_regs(struct net_device * ndev,struct ethtool_regs * regs,void * regbuf)2713 static void fec_enet_get_regs(struct net_device *ndev,
2714 			      struct ethtool_regs *regs, void *regbuf)
2715 {
2716 	struct fec_enet_private *fep = netdev_priv(ndev);
2717 	u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2718 	struct device *dev = &fep->pdev->dev;
2719 	u32 *buf = (u32 *)regbuf;
2720 	u32 i, off;
2721 	int ret;
2722 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2723 	defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2724 	defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2725 	u32 *reg_list;
2726 	u32 reg_cnt;
2727 
2728 	if (!of_machine_is_compatible("fsl,imx6ul")) {
2729 		reg_list = fec_enet_register_offset;
2730 		reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2731 	} else {
2732 		reg_list = fec_enet_register_offset_6ul;
2733 		reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul);
2734 	}
2735 #else
2736 	/* coldfire */
2737 	static u32 *reg_list = fec_enet_register_offset;
2738 	static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2739 #endif
2740 	ret = pm_runtime_resume_and_get(dev);
2741 	if (ret < 0)
2742 		return;
2743 
2744 	regs->version = fec_enet_register_version;
2745 
2746 	memset(buf, 0, regs->len);
2747 
2748 	for (i = 0; i < reg_cnt; i++) {
2749 		off = reg_list[i];
2750 
2751 		if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2752 		    !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2753 			continue;
2754 
2755 		off >>= 2;
2756 		buf[off] = readl(&theregs[off]);
2757 	}
2758 
2759 	pm_runtime_mark_last_busy(dev);
2760 	pm_runtime_put_autosuspend(dev);
2761 }
2762 
fec_enet_get_ts_info(struct net_device * ndev,struct ethtool_ts_info * info)2763 static int fec_enet_get_ts_info(struct net_device *ndev,
2764 				struct ethtool_ts_info *info)
2765 {
2766 	struct fec_enet_private *fep = netdev_priv(ndev);
2767 
2768 	if (fep->bufdesc_ex) {
2769 
2770 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2771 					SOF_TIMESTAMPING_RX_SOFTWARE |
2772 					SOF_TIMESTAMPING_SOFTWARE |
2773 					SOF_TIMESTAMPING_TX_HARDWARE |
2774 					SOF_TIMESTAMPING_RX_HARDWARE |
2775 					SOF_TIMESTAMPING_RAW_HARDWARE;
2776 		if (fep->ptp_clock)
2777 			info->phc_index = ptp_clock_index(fep->ptp_clock);
2778 		else
2779 			info->phc_index = -1;
2780 
2781 		info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2782 				 (1 << HWTSTAMP_TX_ON);
2783 
2784 		info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2785 				   (1 << HWTSTAMP_FILTER_ALL);
2786 		return 0;
2787 	} else {
2788 		return ethtool_op_get_ts_info(ndev, info);
2789 	}
2790 }
2791 
2792 #if !defined(CONFIG_M5272)
2793 
fec_enet_get_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)2794 static void fec_enet_get_pauseparam(struct net_device *ndev,
2795 				    struct ethtool_pauseparam *pause)
2796 {
2797 	struct fec_enet_private *fep = netdev_priv(ndev);
2798 
2799 	pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2800 	pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2801 	pause->rx_pause = pause->tx_pause;
2802 }
2803 
fec_enet_set_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)2804 static int fec_enet_set_pauseparam(struct net_device *ndev,
2805 				   struct ethtool_pauseparam *pause)
2806 {
2807 	struct fec_enet_private *fep = netdev_priv(ndev);
2808 
2809 	if (!ndev->phydev)
2810 		return -ENODEV;
2811 
2812 	if (pause->tx_pause != pause->rx_pause) {
2813 		netdev_info(ndev,
2814 			"hardware only support enable/disable both tx and rx");
2815 		return -EINVAL;
2816 	}
2817 
2818 	fep->pause_flag = 0;
2819 
2820 	/* tx pause must be same as rx pause */
2821 	fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2822 	fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2823 
2824 	phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2825 			  pause->autoneg);
2826 
2827 	if (pause->autoneg) {
2828 		if (netif_running(ndev))
2829 			fec_stop(ndev);
2830 		phy_start_aneg(ndev->phydev);
2831 	}
2832 	if (netif_running(ndev)) {
2833 		napi_disable(&fep->napi);
2834 		netif_tx_lock_bh(ndev);
2835 		fec_restart(ndev);
2836 		netif_tx_wake_all_queues(ndev);
2837 		netif_tx_unlock_bh(ndev);
2838 		napi_enable(&fep->napi);
2839 	}
2840 
2841 	return 0;
2842 }
2843 
2844 static const struct fec_stat {
2845 	char name[ETH_GSTRING_LEN];
2846 	u16 offset;
2847 } fec_stats[] = {
2848 	/* RMON TX */
2849 	{ "tx_dropped", RMON_T_DROP },
2850 	{ "tx_packets", RMON_T_PACKETS },
2851 	{ "tx_broadcast", RMON_T_BC_PKT },
2852 	{ "tx_multicast", RMON_T_MC_PKT },
2853 	{ "tx_crc_errors", RMON_T_CRC_ALIGN },
2854 	{ "tx_undersize", RMON_T_UNDERSIZE },
2855 	{ "tx_oversize", RMON_T_OVERSIZE },
2856 	{ "tx_fragment", RMON_T_FRAG },
2857 	{ "tx_jabber", RMON_T_JAB },
2858 	{ "tx_collision", RMON_T_COL },
2859 	{ "tx_64byte", RMON_T_P64 },
2860 	{ "tx_65to127byte", RMON_T_P65TO127 },
2861 	{ "tx_128to255byte", RMON_T_P128TO255 },
2862 	{ "tx_256to511byte", RMON_T_P256TO511 },
2863 	{ "tx_512to1023byte", RMON_T_P512TO1023 },
2864 	{ "tx_1024to2047byte", RMON_T_P1024TO2047 },
2865 	{ "tx_GTE2048byte", RMON_T_P_GTE2048 },
2866 	{ "tx_octets", RMON_T_OCTETS },
2867 
2868 	/* IEEE TX */
2869 	{ "IEEE_tx_drop", IEEE_T_DROP },
2870 	{ "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2871 	{ "IEEE_tx_1col", IEEE_T_1COL },
2872 	{ "IEEE_tx_mcol", IEEE_T_MCOL },
2873 	{ "IEEE_tx_def", IEEE_T_DEF },
2874 	{ "IEEE_tx_lcol", IEEE_T_LCOL },
2875 	{ "IEEE_tx_excol", IEEE_T_EXCOL },
2876 	{ "IEEE_tx_macerr", IEEE_T_MACERR },
2877 	{ "IEEE_tx_cserr", IEEE_T_CSERR },
2878 	{ "IEEE_tx_sqe", IEEE_T_SQE },
2879 	{ "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2880 	{ "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2881 
2882 	/* RMON RX */
2883 	{ "rx_packets", RMON_R_PACKETS },
2884 	{ "rx_broadcast", RMON_R_BC_PKT },
2885 	{ "rx_multicast", RMON_R_MC_PKT },
2886 	{ "rx_crc_errors", RMON_R_CRC_ALIGN },
2887 	{ "rx_undersize", RMON_R_UNDERSIZE },
2888 	{ "rx_oversize", RMON_R_OVERSIZE },
2889 	{ "rx_fragment", RMON_R_FRAG },
2890 	{ "rx_jabber", RMON_R_JAB },
2891 	{ "rx_64byte", RMON_R_P64 },
2892 	{ "rx_65to127byte", RMON_R_P65TO127 },
2893 	{ "rx_128to255byte", RMON_R_P128TO255 },
2894 	{ "rx_256to511byte", RMON_R_P256TO511 },
2895 	{ "rx_512to1023byte", RMON_R_P512TO1023 },
2896 	{ "rx_1024to2047byte", RMON_R_P1024TO2047 },
2897 	{ "rx_GTE2048byte", RMON_R_P_GTE2048 },
2898 	{ "rx_octets", RMON_R_OCTETS },
2899 
2900 	/* IEEE RX */
2901 	{ "IEEE_rx_drop", IEEE_R_DROP },
2902 	{ "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2903 	{ "IEEE_rx_crc", IEEE_R_CRC },
2904 	{ "IEEE_rx_align", IEEE_R_ALIGN },
2905 	{ "IEEE_rx_macerr", IEEE_R_MACERR },
2906 	{ "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2907 	{ "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2908 };
2909 
2910 #define FEC_STATS_SIZE		(ARRAY_SIZE(fec_stats) * sizeof(u64))
2911 
2912 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = {
2913 	"rx_xdp_redirect",           /* RX_XDP_REDIRECT = 0, */
2914 	"rx_xdp_pass",               /* RX_XDP_PASS, */
2915 	"rx_xdp_drop",               /* RX_XDP_DROP, */
2916 	"rx_xdp_tx",                 /* RX_XDP_TX, */
2917 	"rx_xdp_tx_errors",          /* RX_XDP_TX_ERRORS, */
2918 	"tx_xdp_xmit",               /* TX_XDP_XMIT, */
2919 	"tx_xdp_xmit_errors",        /* TX_XDP_XMIT_ERRORS, */
2920 };
2921 
fec_enet_update_ethtool_stats(struct net_device * dev)2922 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2923 {
2924 	struct fec_enet_private *fep = netdev_priv(dev);
2925 	int i;
2926 
2927 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2928 		fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2929 }
2930 
fec_enet_get_xdp_stats(struct fec_enet_private * fep,u64 * data)2931 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data)
2932 {
2933 	u64 xdp_stats[XDP_STATS_TOTAL] = { 0 };
2934 	struct fec_enet_priv_rx_q *rxq;
2935 	int i, j;
2936 
2937 	for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2938 		rxq = fep->rx_queue[i];
2939 
2940 		for (j = 0; j < XDP_STATS_TOTAL; j++)
2941 			xdp_stats[j] += rxq->stats[j];
2942 	}
2943 
2944 	memcpy(data, xdp_stats, sizeof(xdp_stats));
2945 }
2946 
fec_enet_page_pool_stats(struct fec_enet_private * fep,u64 * data)2947 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data)
2948 {
2949 #ifdef CONFIG_PAGE_POOL_STATS
2950 	struct page_pool_stats stats = {};
2951 	struct fec_enet_priv_rx_q *rxq;
2952 	int i;
2953 
2954 	for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2955 		rxq = fep->rx_queue[i];
2956 
2957 		if (!rxq->page_pool)
2958 			continue;
2959 
2960 		page_pool_get_stats(rxq->page_pool, &stats);
2961 	}
2962 
2963 	page_pool_ethtool_stats_get(data, &stats);
2964 #endif
2965 }
2966 
fec_enet_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2967 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2968 				       struct ethtool_stats *stats, u64 *data)
2969 {
2970 	struct fec_enet_private *fep = netdev_priv(dev);
2971 
2972 	if (netif_running(dev))
2973 		fec_enet_update_ethtool_stats(dev);
2974 
2975 	memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2976 	data += FEC_STATS_SIZE / sizeof(u64);
2977 
2978 	fec_enet_get_xdp_stats(fep, data);
2979 	data += XDP_STATS_TOTAL;
2980 
2981 	fec_enet_page_pool_stats(fep, data);
2982 }
2983 
fec_enet_get_strings(struct net_device * netdev,u32 stringset,u8 * data)2984 static void fec_enet_get_strings(struct net_device *netdev,
2985 	u32 stringset, u8 *data)
2986 {
2987 	int i;
2988 	switch (stringset) {
2989 	case ETH_SS_STATS:
2990 		for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
2991 			memcpy(data, fec_stats[i].name, ETH_GSTRING_LEN);
2992 			data += ETH_GSTRING_LEN;
2993 		}
2994 		for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) {
2995 			strncpy(data, fec_xdp_stat_strs[i], ETH_GSTRING_LEN);
2996 			data += ETH_GSTRING_LEN;
2997 		}
2998 		page_pool_ethtool_stats_get_strings(data);
2999 
3000 		break;
3001 	case ETH_SS_TEST:
3002 		net_selftest_get_strings(data);
3003 		break;
3004 	}
3005 }
3006 
fec_enet_get_sset_count(struct net_device * dev,int sset)3007 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
3008 {
3009 	int count;
3010 
3011 	switch (sset) {
3012 	case ETH_SS_STATS:
3013 		count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL;
3014 		count += page_pool_ethtool_stats_get_count();
3015 		return count;
3016 
3017 	case ETH_SS_TEST:
3018 		return net_selftest_get_count();
3019 	default:
3020 		return -EOPNOTSUPP;
3021 	}
3022 }
3023 
fec_enet_clear_ethtool_stats(struct net_device * dev)3024 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
3025 {
3026 	struct fec_enet_private *fep = netdev_priv(dev);
3027 	struct fec_enet_priv_rx_q *rxq;
3028 	int i, j;
3029 
3030 	/* Disable MIB statistics counters */
3031 	writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
3032 
3033 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
3034 		writel(0, fep->hwp + fec_stats[i].offset);
3035 
3036 	for (i = fep->num_rx_queues - 1; i >= 0; i--) {
3037 		rxq = fep->rx_queue[i];
3038 		for (j = 0; j < XDP_STATS_TOTAL; j++)
3039 			rxq->stats[j] = 0;
3040 	}
3041 
3042 	/* Don't disable MIB statistics counters */
3043 	writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
3044 }
3045 
3046 #else	/* !defined(CONFIG_M5272) */
3047 #define FEC_STATS_SIZE	0
fec_enet_update_ethtool_stats(struct net_device * dev)3048 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
3049 {
3050 }
3051 
fec_enet_clear_ethtool_stats(struct net_device * dev)3052 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
3053 {
3054 }
3055 #endif /* !defined(CONFIG_M5272) */
3056 
3057 /* ITR clock source is enet system clock (clk_ahb).
3058  * TCTT unit is cycle_ns * 64 cycle
3059  * So, the ICTT value = X us / (cycle_ns * 64)
3060  */
fec_enet_us_to_itr_clock(struct net_device * ndev,int us)3061 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
3062 {
3063 	struct fec_enet_private *fep = netdev_priv(ndev);
3064 
3065 	return us * (fep->itr_clk_rate / 64000) / 1000;
3066 }
3067 
3068 /* Set threshold for interrupt coalescing */
fec_enet_itr_coal_set(struct net_device * ndev)3069 static void fec_enet_itr_coal_set(struct net_device *ndev)
3070 {
3071 	struct fec_enet_private *fep = netdev_priv(ndev);
3072 	int rx_itr, tx_itr;
3073 
3074 	/* Must be greater than zero to avoid unpredictable behavior */
3075 	if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
3076 	    !fep->tx_time_itr || !fep->tx_pkts_itr)
3077 		return;
3078 
3079 	/* Select enet system clock as Interrupt Coalescing
3080 	 * timer Clock Source
3081 	 */
3082 	rx_itr = FEC_ITR_CLK_SEL;
3083 	tx_itr = FEC_ITR_CLK_SEL;
3084 
3085 	/* set ICFT and ICTT */
3086 	rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
3087 	rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
3088 	tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
3089 	tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
3090 
3091 	rx_itr |= FEC_ITR_EN;
3092 	tx_itr |= FEC_ITR_EN;
3093 
3094 	writel(tx_itr, fep->hwp + FEC_TXIC0);
3095 	writel(rx_itr, fep->hwp + FEC_RXIC0);
3096 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
3097 		writel(tx_itr, fep->hwp + FEC_TXIC1);
3098 		writel(rx_itr, fep->hwp + FEC_RXIC1);
3099 		writel(tx_itr, fep->hwp + FEC_TXIC2);
3100 		writel(rx_itr, fep->hwp + FEC_RXIC2);
3101 	}
3102 }
3103 
fec_enet_get_coalesce(struct net_device * ndev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)3104 static int fec_enet_get_coalesce(struct net_device *ndev,
3105 				 struct ethtool_coalesce *ec,
3106 				 struct kernel_ethtool_coalesce *kernel_coal,
3107 				 struct netlink_ext_ack *extack)
3108 {
3109 	struct fec_enet_private *fep = netdev_priv(ndev);
3110 
3111 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3112 		return -EOPNOTSUPP;
3113 
3114 	ec->rx_coalesce_usecs = fep->rx_time_itr;
3115 	ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
3116 
3117 	ec->tx_coalesce_usecs = fep->tx_time_itr;
3118 	ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
3119 
3120 	return 0;
3121 }
3122 
fec_enet_set_coalesce(struct net_device * ndev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)3123 static int fec_enet_set_coalesce(struct net_device *ndev,
3124 				 struct ethtool_coalesce *ec,
3125 				 struct kernel_ethtool_coalesce *kernel_coal,
3126 				 struct netlink_ext_ack *extack)
3127 {
3128 	struct fec_enet_private *fep = netdev_priv(ndev);
3129 	struct device *dev = &fep->pdev->dev;
3130 	unsigned int cycle;
3131 
3132 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3133 		return -EOPNOTSUPP;
3134 
3135 	if (ec->rx_max_coalesced_frames > 255) {
3136 		dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
3137 		return -EINVAL;
3138 	}
3139 
3140 	if (ec->tx_max_coalesced_frames > 255) {
3141 		dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
3142 		return -EINVAL;
3143 	}
3144 
3145 	cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
3146 	if (cycle > 0xFFFF) {
3147 		dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
3148 		return -EINVAL;
3149 	}
3150 
3151 	cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
3152 	if (cycle > 0xFFFF) {
3153 		dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
3154 		return -EINVAL;
3155 	}
3156 
3157 	fep->rx_time_itr = ec->rx_coalesce_usecs;
3158 	fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
3159 
3160 	fep->tx_time_itr = ec->tx_coalesce_usecs;
3161 	fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
3162 
3163 	fec_enet_itr_coal_set(ndev);
3164 
3165 	return 0;
3166 }
3167 
3168 /* LPI Sleep Ts count base on tx clk (clk_ref).
3169  * The lpi sleep cnt value = X us / (cycle_ns).
3170  */
fec_enet_us_to_tx_cycle(struct net_device * ndev,int us)3171 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us)
3172 {
3173 	struct fec_enet_private *fep = netdev_priv(ndev);
3174 
3175 	return us * (fep->clk_ref_rate / 1000) / 1000;
3176 }
3177 
fec_enet_eee_mode_set(struct net_device * ndev,bool enable)3178 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable)
3179 {
3180 	struct fec_enet_private *fep = netdev_priv(ndev);
3181 	struct ethtool_eee *p = &fep->eee;
3182 	unsigned int sleep_cycle, wake_cycle;
3183 	int ret = 0;
3184 
3185 	if (enable) {
3186 		ret = phy_init_eee(ndev->phydev, false);
3187 		if (ret)
3188 			return ret;
3189 
3190 		sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer);
3191 		wake_cycle = sleep_cycle;
3192 	} else {
3193 		sleep_cycle = 0;
3194 		wake_cycle = 0;
3195 	}
3196 
3197 	p->tx_lpi_enabled = enable;
3198 	p->eee_enabled = enable;
3199 	p->eee_active = enable;
3200 
3201 	writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
3202 	writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
3203 
3204 	return 0;
3205 }
3206 
3207 static int
fec_enet_get_eee(struct net_device * ndev,struct ethtool_eee * edata)3208 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
3209 {
3210 	struct fec_enet_private *fep = netdev_priv(ndev);
3211 	struct ethtool_eee *p = &fep->eee;
3212 
3213 	if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3214 		return -EOPNOTSUPP;
3215 
3216 	if (!netif_running(ndev))
3217 		return -ENETDOWN;
3218 
3219 	edata->eee_enabled = p->eee_enabled;
3220 	edata->eee_active = p->eee_active;
3221 	edata->tx_lpi_timer = p->tx_lpi_timer;
3222 	edata->tx_lpi_enabled = p->tx_lpi_enabled;
3223 
3224 	return phy_ethtool_get_eee(ndev->phydev, edata);
3225 }
3226 
3227 static int
fec_enet_set_eee(struct net_device * ndev,struct ethtool_eee * edata)3228 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
3229 {
3230 	struct fec_enet_private *fep = netdev_priv(ndev);
3231 	struct ethtool_eee *p = &fep->eee;
3232 	int ret = 0;
3233 
3234 	if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3235 		return -EOPNOTSUPP;
3236 
3237 	if (!netif_running(ndev))
3238 		return -ENETDOWN;
3239 
3240 	p->tx_lpi_timer = edata->tx_lpi_timer;
3241 
3242 	if (!edata->eee_enabled || !edata->tx_lpi_enabled ||
3243 	    !edata->tx_lpi_timer)
3244 		ret = fec_enet_eee_mode_set(ndev, false);
3245 	else
3246 		ret = fec_enet_eee_mode_set(ndev, true);
3247 
3248 	if (ret)
3249 		return ret;
3250 
3251 	return phy_ethtool_set_eee(ndev->phydev, edata);
3252 }
3253 
3254 static void
fec_enet_get_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)3255 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3256 {
3257 	struct fec_enet_private *fep = netdev_priv(ndev);
3258 
3259 	if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
3260 		wol->supported = WAKE_MAGIC;
3261 		wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
3262 	} else {
3263 		wol->supported = wol->wolopts = 0;
3264 	}
3265 }
3266 
3267 static int
fec_enet_set_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)3268 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3269 {
3270 	struct fec_enet_private *fep = netdev_priv(ndev);
3271 
3272 	if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
3273 		return -EINVAL;
3274 
3275 	if (wol->wolopts & ~WAKE_MAGIC)
3276 		return -EINVAL;
3277 
3278 	device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
3279 	if (device_may_wakeup(&ndev->dev))
3280 		fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
3281 	else
3282 		fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
3283 
3284 	return 0;
3285 }
3286 
3287 static const struct ethtool_ops fec_enet_ethtool_ops = {
3288 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3289 				     ETHTOOL_COALESCE_MAX_FRAMES,
3290 	.get_drvinfo		= fec_enet_get_drvinfo,
3291 	.get_regs_len		= fec_enet_get_regs_len,
3292 	.get_regs		= fec_enet_get_regs,
3293 	.nway_reset		= phy_ethtool_nway_reset,
3294 	.get_link		= ethtool_op_get_link,
3295 	.get_coalesce		= fec_enet_get_coalesce,
3296 	.set_coalesce		= fec_enet_set_coalesce,
3297 #ifndef CONFIG_M5272
3298 	.get_pauseparam		= fec_enet_get_pauseparam,
3299 	.set_pauseparam		= fec_enet_set_pauseparam,
3300 	.get_strings		= fec_enet_get_strings,
3301 	.get_ethtool_stats	= fec_enet_get_ethtool_stats,
3302 	.get_sset_count		= fec_enet_get_sset_count,
3303 #endif
3304 	.get_ts_info		= fec_enet_get_ts_info,
3305 	.get_wol		= fec_enet_get_wol,
3306 	.set_wol		= fec_enet_set_wol,
3307 	.get_eee		= fec_enet_get_eee,
3308 	.set_eee		= fec_enet_set_eee,
3309 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
3310 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
3311 	.self_test		= net_selftest,
3312 };
3313 
fec_enet_free_buffers(struct net_device * ndev)3314 static void fec_enet_free_buffers(struct net_device *ndev)
3315 {
3316 	struct fec_enet_private *fep = netdev_priv(ndev);
3317 	unsigned int i;
3318 	struct fec_enet_priv_tx_q *txq;
3319 	struct fec_enet_priv_rx_q *rxq;
3320 	unsigned int q;
3321 
3322 	for (q = 0; q < fep->num_rx_queues; q++) {
3323 		rxq = fep->rx_queue[q];
3324 		for (i = 0; i < rxq->bd.ring_size; i++)
3325 			page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false);
3326 
3327 		for (i = 0; i < XDP_STATS_TOTAL; i++)
3328 			rxq->stats[i] = 0;
3329 
3330 		if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
3331 			xdp_rxq_info_unreg(&rxq->xdp_rxq);
3332 		page_pool_destroy(rxq->page_pool);
3333 		rxq->page_pool = NULL;
3334 	}
3335 
3336 	for (q = 0; q < fep->num_tx_queues; q++) {
3337 		txq = fep->tx_queue[q];
3338 		for (i = 0; i < txq->bd.ring_size; i++) {
3339 			kfree(txq->tx_bounce[i]);
3340 			txq->tx_bounce[i] = NULL;
3341 
3342 			if (!txq->tx_buf[i].buf_p) {
3343 				txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3344 				continue;
3345 			}
3346 
3347 			if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
3348 				dev_kfree_skb(txq->tx_buf[i].buf_p);
3349 			} else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
3350 				xdp_return_frame(txq->tx_buf[i].buf_p);
3351 			} else {
3352 				struct page *page = txq->tx_buf[i].buf_p;
3353 
3354 				page_pool_put_page(page->pp, page, 0, false);
3355 			}
3356 
3357 			txq->tx_buf[i].buf_p = NULL;
3358 			txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3359 		}
3360 	}
3361 }
3362 
fec_enet_free_queue(struct net_device * ndev)3363 static void fec_enet_free_queue(struct net_device *ndev)
3364 {
3365 	struct fec_enet_private *fep = netdev_priv(ndev);
3366 	int i;
3367 	struct fec_enet_priv_tx_q *txq;
3368 
3369 	for (i = 0; i < fep->num_tx_queues; i++)
3370 		if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
3371 			txq = fep->tx_queue[i];
3372 			dma_free_coherent(&fep->pdev->dev,
3373 					  txq->bd.ring_size * TSO_HEADER_SIZE,
3374 					  txq->tso_hdrs,
3375 					  txq->tso_hdrs_dma);
3376 		}
3377 
3378 	for (i = 0; i < fep->num_rx_queues; i++)
3379 		kfree(fep->rx_queue[i]);
3380 	for (i = 0; i < fep->num_tx_queues; i++)
3381 		kfree(fep->tx_queue[i]);
3382 }
3383 
fec_enet_alloc_queue(struct net_device * ndev)3384 static int fec_enet_alloc_queue(struct net_device *ndev)
3385 {
3386 	struct fec_enet_private *fep = netdev_priv(ndev);
3387 	int i;
3388 	int ret = 0;
3389 	struct fec_enet_priv_tx_q *txq;
3390 
3391 	for (i = 0; i < fep->num_tx_queues; i++) {
3392 		txq = kzalloc(sizeof(*txq), GFP_KERNEL);
3393 		if (!txq) {
3394 			ret = -ENOMEM;
3395 			goto alloc_failed;
3396 		}
3397 
3398 		fep->tx_queue[i] = txq;
3399 		txq->bd.ring_size = TX_RING_SIZE;
3400 		fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
3401 
3402 		txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
3403 		txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS;
3404 
3405 		txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
3406 					txq->bd.ring_size * TSO_HEADER_SIZE,
3407 					&txq->tso_hdrs_dma,
3408 					GFP_KERNEL);
3409 		if (!txq->tso_hdrs) {
3410 			ret = -ENOMEM;
3411 			goto alloc_failed;
3412 		}
3413 	}
3414 
3415 	for (i = 0; i < fep->num_rx_queues; i++) {
3416 		fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
3417 					   GFP_KERNEL);
3418 		if (!fep->rx_queue[i]) {
3419 			ret = -ENOMEM;
3420 			goto alloc_failed;
3421 		}
3422 
3423 		fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
3424 		fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
3425 	}
3426 	return ret;
3427 
3428 alloc_failed:
3429 	fec_enet_free_queue(ndev);
3430 	return ret;
3431 }
3432 
3433 static int
fec_enet_alloc_rxq_buffers(struct net_device * ndev,unsigned int queue)3434 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
3435 {
3436 	struct fec_enet_private *fep = netdev_priv(ndev);
3437 	struct fec_enet_priv_rx_q *rxq;
3438 	dma_addr_t phys_addr;
3439 	struct bufdesc	*bdp;
3440 	struct page *page;
3441 	int i, err;
3442 
3443 	rxq = fep->rx_queue[queue];
3444 	bdp = rxq->bd.base;
3445 
3446 	err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size);
3447 	if (err < 0) {
3448 		netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err);
3449 		return err;
3450 	}
3451 
3452 	for (i = 0; i < rxq->bd.ring_size; i++) {
3453 		page = page_pool_dev_alloc_pages(rxq->page_pool);
3454 		if (!page)
3455 			goto err_alloc;
3456 
3457 		phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM;
3458 		bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
3459 
3460 		rxq->rx_skb_info[i].page = page;
3461 		rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM;
3462 		bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
3463 
3464 		if (fep->bufdesc_ex) {
3465 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3466 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
3467 		}
3468 
3469 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
3470 	}
3471 
3472 	/* Set the last buffer to wrap. */
3473 	bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
3474 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3475 	return 0;
3476 
3477  err_alloc:
3478 	fec_enet_free_buffers(ndev);
3479 	return -ENOMEM;
3480 }
3481 
3482 static int
fec_enet_alloc_txq_buffers(struct net_device * ndev,unsigned int queue)3483 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
3484 {
3485 	struct fec_enet_private *fep = netdev_priv(ndev);
3486 	unsigned int i;
3487 	struct bufdesc  *bdp;
3488 	struct fec_enet_priv_tx_q *txq;
3489 
3490 	txq = fep->tx_queue[queue];
3491 	bdp = txq->bd.base;
3492 	for (i = 0; i < txq->bd.ring_size; i++) {
3493 		txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
3494 		if (!txq->tx_bounce[i])
3495 			goto err_alloc;
3496 
3497 		bdp->cbd_sc = cpu_to_fec16(0);
3498 		bdp->cbd_bufaddr = cpu_to_fec32(0);
3499 
3500 		if (fep->bufdesc_ex) {
3501 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3502 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
3503 		}
3504 
3505 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3506 	}
3507 
3508 	/* Set the last buffer to wrap. */
3509 	bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
3510 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3511 
3512 	return 0;
3513 
3514  err_alloc:
3515 	fec_enet_free_buffers(ndev);
3516 	return -ENOMEM;
3517 }
3518 
fec_enet_alloc_buffers(struct net_device * ndev)3519 static int fec_enet_alloc_buffers(struct net_device *ndev)
3520 {
3521 	struct fec_enet_private *fep = netdev_priv(ndev);
3522 	unsigned int i;
3523 
3524 	for (i = 0; i < fep->num_rx_queues; i++)
3525 		if (fec_enet_alloc_rxq_buffers(ndev, i))
3526 			return -ENOMEM;
3527 
3528 	for (i = 0; i < fep->num_tx_queues; i++)
3529 		if (fec_enet_alloc_txq_buffers(ndev, i))
3530 			return -ENOMEM;
3531 	return 0;
3532 }
3533 
3534 static int
fec_enet_open(struct net_device * ndev)3535 fec_enet_open(struct net_device *ndev)
3536 {
3537 	struct fec_enet_private *fep = netdev_priv(ndev);
3538 	int ret;
3539 	bool reset_again;
3540 
3541 	ret = pm_runtime_resume_and_get(&fep->pdev->dev);
3542 	if (ret < 0)
3543 		return ret;
3544 
3545 	pinctrl_pm_select_default_state(&fep->pdev->dev);
3546 	ret = fec_enet_clk_enable(ndev, true);
3547 	if (ret)
3548 		goto clk_enable;
3549 
3550 	/* During the first fec_enet_open call the PHY isn't probed at this
3551 	 * point. Therefore the phy_reset_after_clk_enable() call within
3552 	 * fec_enet_clk_enable() fails. As we need this reset in order to be
3553 	 * sure the PHY is working correctly we check if we need to reset again
3554 	 * later when the PHY is probed
3555 	 */
3556 	if (ndev->phydev && ndev->phydev->drv)
3557 		reset_again = false;
3558 	else
3559 		reset_again = true;
3560 
3561 	/* I should reset the ring buffers here, but I don't yet know
3562 	 * a simple way to do that.
3563 	 */
3564 
3565 	ret = fec_enet_alloc_buffers(ndev);
3566 	if (ret)
3567 		goto err_enet_alloc;
3568 
3569 	/* Init MAC prior to mii bus probe */
3570 	fec_restart(ndev);
3571 
3572 	/* Call phy_reset_after_clk_enable() again if it failed during
3573 	 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3574 	 */
3575 	if (reset_again)
3576 		fec_enet_phy_reset_after_clk_enable(ndev);
3577 
3578 	/* Probe and connect to PHY when open the interface */
3579 	ret = fec_enet_mii_probe(ndev);
3580 	if (ret)
3581 		goto err_enet_mii_probe;
3582 
3583 	if (fep->quirks & FEC_QUIRK_ERR006687)
3584 		imx6q_cpuidle_fec_irqs_used();
3585 
3586 	if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3587 		cpu_latency_qos_add_request(&fep->pm_qos_req, 0);
3588 
3589 	napi_enable(&fep->napi);
3590 	phy_start(ndev->phydev);
3591 	netif_tx_start_all_queues(ndev);
3592 
3593 	device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3594 				 FEC_WOL_FLAG_ENABLE);
3595 
3596 	return 0;
3597 
3598 err_enet_mii_probe:
3599 	fec_enet_free_buffers(ndev);
3600 err_enet_alloc:
3601 	fec_enet_clk_enable(ndev, false);
3602 clk_enable:
3603 	pm_runtime_mark_last_busy(&fep->pdev->dev);
3604 	pm_runtime_put_autosuspend(&fep->pdev->dev);
3605 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3606 	return ret;
3607 }
3608 
3609 static int
fec_enet_close(struct net_device * ndev)3610 fec_enet_close(struct net_device *ndev)
3611 {
3612 	struct fec_enet_private *fep = netdev_priv(ndev);
3613 
3614 	phy_stop(ndev->phydev);
3615 
3616 	if (netif_device_present(ndev)) {
3617 		napi_disable(&fep->napi);
3618 		netif_tx_disable(ndev);
3619 		fec_stop(ndev);
3620 	}
3621 
3622 	phy_disconnect(ndev->phydev);
3623 
3624 	if (fep->quirks & FEC_QUIRK_ERR006687)
3625 		imx6q_cpuidle_fec_irqs_unused();
3626 
3627 	fec_enet_update_ethtool_stats(ndev);
3628 
3629 	fec_enet_clk_enable(ndev, false);
3630 	if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3631 		cpu_latency_qos_remove_request(&fep->pm_qos_req);
3632 
3633 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3634 	pm_runtime_mark_last_busy(&fep->pdev->dev);
3635 	pm_runtime_put_autosuspend(&fep->pdev->dev);
3636 
3637 	fec_enet_free_buffers(ndev);
3638 
3639 	return 0;
3640 }
3641 
3642 /* Set or clear the multicast filter for this adaptor.
3643  * Skeleton taken from sunlance driver.
3644  * The CPM Ethernet implementation allows Multicast as well as individual
3645  * MAC address filtering.  Some of the drivers check to make sure it is
3646  * a group multicast address, and discard those that are not.  I guess I
3647  * will do the same for now, but just remove the test if you want
3648  * individual filtering as well (do the upper net layers want or support
3649  * this kind of feature?).
3650  */
3651 
3652 #define FEC_HASH_BITS	6		/* #bits in hash */
3653 
set_multicast_list(struct net_device * ndev)3654 static void set_multicast_list(struct net_device *ndev)
3655 {
3656 	struct fec_enet_private *fep = netdev_priv(ndev);
3657 	struct netdev_hw_addr *ha;
3658 	unsigned int crc, tmp;
3659 	unsigned char hash;
3660 	unsigned int hash_high = 0, hash_low = 0;
3661 
3662 	if (ndev->flags & IFF_PROMISC) {
3663 		tmp = readl(fep->hwp + FEC_R_CNTRL);
3664 		tmp |= 0x8;
3665 		writel(tmp, fep->hwp + FEC_R_CNTRL);
3666 		return;
3667 	}
3668 
3669 	tmp = readl(fep->hwp + FEC_R_CNTRL);
3670 	tmp &= ~0x8;
3671 	writel(tmp, fep->hwp + FEC_R_CNTRL);
3672 
3673 	if (ndev->flags & IFF_ALLMULTI) {
3674 		/* Catch all multicast addresses, so set the
3675 		 * filter to all 1's
3676 		 */
3677 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3678 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3679 
3680 		return;
3681 	}
3682 
3683 	/* Add the addresses in hash register */
3684 	netdev_for_each_mc_addr(ha, ndev) {
3685 		/* calculate crc32 value of mac address */
3686 		crc = ether_crc_le(ndev->addr_len, ha->addr);
3687 
3688 		/* only upper 6 bits (FEC_HASH_BITS) are used
3689 		 * which point to specific bit in the hash registers
3690 		 */
3691 		hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3692 
3693 		if (hash > 31)
3694 			hash_high |= 1 << (hash - 32);
3695 		else
3696 			hash_low |= 1 << hash;
3697 	}
3698 
3699 	writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3700 	writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3701 }
3702 
3703 /* Set a MAC change in hardware. */
3704 static int
fec_set_mac_address(struct net_device * ndev,void * p)3705 fec_set_mac_address(struct net_device *ndev, void *p)
3706 {
3707 	struct fec_enet_private *fep = netdev_priv(ndev);
3708 	struct sockaddr *addr = p;
3709 
3710 	if (addr) {
3711 		if (!is_valid_ether_addr(addr->sa_data))
3712 			return -EADDRNOTAVAIL;
3713 		eth_hw_addr_set(ndev, addr->sa_data);
3714 	}
3715 
3716 	/* Add netif status check here to avoid system hang in below case:
3717 	 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3718 	 * After ethx down, fec all clocks are gated off and then register
3719 	 * access causes system hang.
3720 	 */
3721 	if (!netif_running(ndev))
3722 		return 0;
3723 
3724 	writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3725 		(ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3726 		fep->hwp + FEC_ADDR_LOW);
3727 	writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3728 		fep->hwp + FEC_ADDR_HIGH);
3729 	return 0;
3730 }
3731 
fec_enet_set_netdev_features(struct net_device * netdev,netdev_features_t features)3732 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3733 	netdev_features_t features)
3734 {
3735 	struct fec_enet_private *fep = netdev_priv(netdev);
3736 	netdev_features_t changed = features ^ netdev->features;
3737 
3738 	netdev->features = features;
3739 
3740 	/* Receive checksum has been changed */
3741 	if (changed & NETIF_F_RXCSUM) {
3742 		if (features & NETIF_F_RXCSUM)
3743 			fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3744 		else
3745 			fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3746 	}
3747 }
3748 
fec_set_features(struct net_device * netdev,netdev_features_t features)3749 static int fec_set_features(struct net_device *netdev,
3750 	netdev_features_t features)
3751 {
3752 	struct fec_enet_private *fep = netdev_priv(netdev);
3753 	netdev_features_t changed = features ^ netdev->features;
3754 
3755 	if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3756 		napi_disable(&fep->napi);
3757 		netif_tx_lock_bh(netdev);
3758 		fec_stop(netdev);
3759 		fec_enet_set_netdev_features(netdev, features);
3760 		fec_restart(netdev);
3761 		netif_tx_wake_all_queues(netdev);
3762 		netif_tx_unlock_bh(netdev);
3763 		napi_enable(&fep->napi);
3764 	} else {
3765 		fec_enet_set_netdev_features(netdev, features);
3766 	}
3767 
3768 	return 0;
3769 }
3770 
fec_enet_select_queue(struct net_device * ndev,struct sk_buff * skb,struct net_device * sb_dev)3771 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3772 				 struct net_device *sb_dev)
3773 {
3774 	struct fec_enet_private *fep = netdev_priv(ndev);
3775 	u16 vlan_tag = 0;
3776 
3777 	if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3778 		return netdev_pick_tx(ndev, skb, NULL);
3779 
3780 	/* VLAN is present in the payload.*/
3781 	if (eth_type_vlan(skb->protocol)) {
3782 		struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb);
3783 
3784 		vlan_tag = ntohs(vhdr->h_vlan_TCI);
3785 	/*  VLAN is present in the skb but not yet pushed in the payload.*/
3786 	} else if (skb_vlan_tag_present(skb)) {
3787 		vlan_tag = skb->vlan_tci;
3788 	} else {
3789 		return vlan_tag;
3790 	}
3791 
3792 	return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3793 }
3794 
fec_enet_bpf(struct net_device * dev,struct netdev_bpf * bpf)3795 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf)
3796 {
3797 	struct fec_enet_private *fep = netdev_priv(dev);
3798 	bool is_run = netif_running(dev);
3799 	struct bpf_prog *old_prog;
3800 
3801 	switch (bpf->command) {
3802 	case XDP_SETUP_PROG:
3803 		/* No need to support the SoCs that require to
3804 		 * do the frame swap because the performance wouldn't be
3805 		 * better than the skb mode.
3806 		 */
3807 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
3808 			return -EOPNOTSUPP;
3809 
3810 		if (!bpf->prog)
3811 			xdp_features_clear_redirect_target(dev);
3812 
3813 		if (is_run) {
3814 			napi_disable(&fep->napi);
3815 			netif_tx_disable(dev);
3816 		}
3817 
3818 		old_prog = xchg(&fep->xdp_prog, bpf->prog);
3819 		if (old_prog)
3820 			bpf_prog_put(old_prog);
3821 
3822 		fec_restart(dev);
3823 
3824 		if (is_run) {
3825 			napi_enable(&fep->napi);
3826 			netif_tx_start_all_queues(dev);
3827 		}
3828 
3829 		if (bpf->prog)
3830 			xdp_features_set_redirect_target(dev, false);
3831 
3832 		return 0;
3833 
3834 	case XDP_SETUP_XSK_POOL:
3835 		return -EOPNOTSUPP;
3836 
3837 	default:
3838 		return -EOPNOTSUPP;
3839 	}
3840 }
3841 
3842 static int
fec_enet_xdp_get_tx_queue(struct fec_enet_private * fep,int index)3843 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index)
3844 {
3845 	if (unlikely(index < 0))
3846 		return 0;
3847 
3848 	return (index % fep->num_tx_queues);
3849 }
3850 
fec_enet_txq_xmit_frame(struct fec_enet_private * fep,struct fec_enet_priv_tx_q * txq,void * frame,u32 dma_sync_len,bool ndo_xmit)3851 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep,
3852 				   struct fec_enet_priv_tx_q *txq,
3853 				   void *frame, u32 dma_sync_len,
3854 				   bool ndo_xmit)
3855 {
3856 	unsigned int index, status, estatus;
3857 	struct bufdesc *bdp;
3858 	dma_addr_t dma_addr;
3859 	int entries_free;
3860 	u16 frame_len;
3861 
3862 	entries_free = fec_enet_get_free_txdesc_num(txq);
3863 	if (entries_free < MAX_SKB_FRAGS + 1) {
3864 		netdev_err_once(fep->netdev, "NOT enough BD for SG!\n");
3865 		return -EBUSY;
3866 	}
3867 
3868 	/* Fill in a Tx ring entry */
3869 	bdp = txq->bd.cur;
3870 	status = fec16_to_cpu(bdp->cbd_sc);
3871 	status &= ~BD_ENET_TX_STATS;
3872 
3873 	index = fec_enet_get_bd_index(bdp, &txq->bd);
3874 
3875 	if (ndo_xmit) {
3876 		struct xdp_frame *xdpf = frame;
3877 
3878 		dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data,
3879 					  xdpf->len, DMA_TO_DEVICE);
3880 		if (dma_mapping_error(&fep->pdev->dev, dma_addr))
3881 			return -ENOMEM;
3882 
3883 		frame_len = xdpf->len;
3884 		txq->tx_buf[index].buf_p = xdpf;
3885 		txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO;
3886 	} else {
3887 		struct xdp_buff *xdpb = frame;
3888 		struct page *page;
3889 
3890 		page = virt_to_page(xdpb->data);
3891 		dma_addr = page_pool_get_dma_addr(page) +
3892 			   (xdpb->data - xdpb->data_hard_start);
3893 		dma_sync_single_for_device(&fep->pdev->dev, dma_addr,
3894 					   dma_sync_len, DMA_BIDIRECTIONAL);
3895 		frame_len = xdpb->data_end - xdpb->data;
3896 		txq->tx_buf[index].buf_p = page;
3897 		txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX;
3898 	}
3899 
3900 	status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
3901 	if (fep->bufdesc_ex)
3902 		estatus = BD_ENET_TX_INT;
3903 
3904 	bdp->cbd_bufaddr = cpu_to_fec32(dma_addr);
3905 	bdp->cbd_datlen = cpu_to_fec16(frame_len);
3906 
3907 	if (fep->bufdesc_ex) {
3908 		struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3909 
3910 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
3911 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
3912 
3913 		ebdp->cbd_bdu = 0;
3914 		ebdp->cbd_esc = cpu_to_fec32(estatus);
3915 	}
3916 
3917 	/* Make sure the updates to rest of the descriptor are performed before
3918 	 * transferring ownership.
3919 	 */
3920 	dma_wmb();
3921 
3922 	/* Send it on its way.  Tell FEC it's ready, interrupt when done,
3923 	 * it's the last BD of the frame, and to put the CRC on the end.
3924 	 */
3925 	status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
3926 	bdp->cbd_sc = cpu_to_fec16(status);
3927 
3928 	/* If this was the last BD in the ring, start at the beginning again. */
3929 	bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3930 
3931 	/* Make sure the update to bdp are performed before txq->bd.cur. */
3932 	dma_wmb();
3933 
3934 	txq->bd.cur = bdp;
3935 
3936 	/* Trigger transmission start */
3937 	writel(0, txq->bd.reg_desc_active);
3938 
3939 	return 0;
3940 }
3941 
fec_enet_xdp_tx_xmit(struct fec_enet_private * fep,int cpu,struct xdp_buff * xdp,u32 dma_sync_len)3942 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
3943 				int cpu, struct xdp_buff *xdp,
3944 				u32 dma_sync_len)
3945 {
3946 	struct fec_enet_priv_tx_q *txq;
3947 	struct netdev_queue *nq;
3948 	int queue, ret;
3949 
3950 	queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3951 	txq = fep->tx_queue[queue];
3952 	nq = netdev_get_tx_queue(fep->netdev, queue);
3953 
3954 	__netif_tx_lock(nq, cpu);
3955 
3956 	/* Avoid tx timeout as XDP shares the queue with kernel stack */
3957 	txq_trans_cond_update(nq);
3958 	ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false);
3959 
3960 	__netif_tx_unlock(nq);
3961 
3962 	return ret;
3963 }
3964 
fec_enet_xdp_xmit(struct net_device * dev,int num_frames,struct xdp_frame ** frames,u32 flags)3965 static int fec_enet_xdp_xmit(struct net_device *dev,
3966 			     int num_frames,
3967 			     struct xdp_frame **frames,
3968 			     u32 flags)
3969 {
3970 	struct fec_enet_private *fep = netdev_priv(dev);
3971 	struct fec_enet_priv_tx_q *txq;
3972 	int cpu = smp_processor_id();
3973 	unsigned int sent_frames = 0;
3974 	struct netdev_queue *nq;
3975 	unsigned int queue;
3976 	int i;
3977 
3978 	queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3979 	txq = fep->tx_queue[queue];
3980 	nq = netdev_get_tx_queue(fep->netdev, queue);
3981 
3982 	__netif_tx_lock(nq, cpu);
3983 
3984 	/* Avoid tx timeout as XDP shares the queue with kernel stack */
3985 	txq_trans_cond_update(nq);
3986 	for (i = 0; i < num_frames; i++) {
3987 		if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0)
3988 			break;
3989 		sent_frames++;
3990 	}
3991 
3992 	__netif_tx_unlock(nq);
3993 
3994 	return sent_frames;
3995 }
3996 
fec_hwtstamp_get(struct net_device * ndev,struct kernel_hwtstamp_config * config)3997 static int fec_hwtstamp_get(struct net_device *ndev,
3998 			    struct kernel_hwtstamp_config *config)
3999 {
4000 	struct fec_enet_private *fep = netdev_priv(ndev);
4001 
4002 	if (!netif_running(ndev))
4003 		return -EINVAL;
4004 
4005 	if (!fep->bufdesc_ex)
4006 		return -EOPNOTSUPP;
4007 
4008 	fec_ptp_get(ndev, config);
4009 
4010 	return 0;
4011 }
4012 
fec_hwtstamp_set(struct net_device * ndev,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)4013 static int fec_hwtstamp_set(struct net_device *ndev,
4014 			    struct kernel_hwtstamp_config *config,
4015 			    struct netlink_ext_ack *extack)
4016 {
4017 	struct fec_enet_private *fep = netdev_priv(ndev);
4018 
4019 	if (!netif_running(ndev))
4020 		return -EINVAL;
4021 
4022 	if (!fep->bufdesc_ex)
4023 		return -EOPNOTSUPP;
4024 
4025 	return fec_ptp_set(ndev, config, extack);
4026 }
4027 
4028 static const struct net_device_ops fec_netdev_ops = {
4029 	.ndo_open		= fec_enet_open,
4030 	.ndo_stop		= fec_enet_close,
4031 	.ndo_start_xmit		= fec_enet_start_xmit,
4032 	.ndo_select_queue       = fec_enet_select_queue,
4033 	.ndo_set_rx_mode	= set_multicast_list,
4034 	.ndo_validate_addr	= eth_validate_addr,
4035 	.ndo_tx_timeout		= fec_timeout,
4036 	.ndo_set_mac_address	= fec_set_mac_address,
4037 	.ndo_eth_ioctl		= phy_do_ioctl_running,
4038 	.ndo_set_features	= fec_set_features,
4039 	.ndo_bpf		= fec_enet_bpf,
4040 	.ndo_xdp_xmit		= fec_enet_xdp_xmit,
4041 	.ndo_hwtstamp_get	= fec_hwtstamp_get,
4042 	.ndo_hwtstamp_set	= fec_hwtstamp_set,
4043 };
4044 
4045 static const unsigned short offset_des_active_rxq[] = {
4046 	FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
4047 };
4048 
4049 static const unsigned short offset_des_active_txq[] = {
4050 	FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
4051 };
4052 
4053  /*
4054   * XXX:  We need to clean up on failure exits here.
4055   *
4056   */
fec_enet_init(struct net_device * ndev)4057 static int fec_enet_init(struct net_device *ndev)
4058 {
4059 	struct fec_enet_private *fep = netdev_priv(ndev);
4060 	struct bufdesc *cbd_base;
4061 	dma_addr_t bd_dma;
4062 	int bd_size;
4063 	unsigned int i;
4064 	unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
4065 			sizeof(struct bufdesc);
4066 	unsigned dsize_log2 = __fls(dsize);
4067 	int ret;
4068 
4069 	WARN_ON(dsize != (1 << dsize_log2));
4070 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
4071 	fep->rx_align = 0xf;
4072 	fep->tx_align = 0xf;
4073 #else
4074 	fep->rx_align = 0x3;
4075 	fep->tx_align = 0x3;
4076 #endif
4077 	fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4078 	fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4079 	fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT;
4080 	fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT;
4081 
4082 	/* Check mask of the streaming and coherent API */
4083 	ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
4084 	if (ret < 0) {
4085 		dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
4086 		return ret;
4087 	}
4088 
4089 	ret = fec_enet_alloc_queue(ndev);
4090 	if (ret)
4091 		return ret;
4092 
4093 	bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
4094 
4095 	/* Allocate memory for buffer descriptors. */
4096 	cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
4097 				       GFP_KERNEL);
4098 	if (!cbd_base) {
4099 		ret = -ENOMEM;
4100 		goto free_queue_mem;
4101 	}
4102 
4103 	/* Get the Ethernet address */
4104 	ret = fec_get_mac(ndev);
4105 	if (ret)
4106 		goto free_queue_mem;
4107 
4108 	/* Set receive and transmit descriptor base. */
4109 	for (i = 0; i < fep->num_rx_queues; i++) {
4110 		struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
4111 		unsigned size = dsize * rxq->bd.ring_size;
4112 
4113 		rxq->bd.qid = i;
4114 		rxq->bd.base = cbd_base;
4115 		rxq->bd.cur = cbd_base;
4116 		rxq->bd.dma = bd_dma;
4117 		rxq->bd.dsize = dsize;
4118 		rxq->bd.dsize_log2 = dsize_log2;
4119 		rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
4120 		bd_dma += size;
4121 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4122 		rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4123 	}
4124 
4125 	for (i = 0; i < fep->num_tx_queues; i++) {
4126 		struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
4127 		unsigned size = dsize * txq->bd.ring_size;
4128 
4129 		txq->bd.qid = i;
4130 		txq->bd.base = cbd_base;
4131 		txq->bd.cur = cbd_base;
4132 		txq->bd.dma = bd_dma;
4133 		txq->bd.dsize = dsize;
4134 		txq->bd.dsize_log2 = dsize_log2;
4135 		txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
4136 		bd_dma += size;
4137 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4138 		txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4139 	}
4140 
4141 
4142 	/* The FEC Ethernet specific entries in the device structure */
4143 	ndev->watchdog_timeo = TX_TIMEOUT;
4144 	ndev->netdev_ops = &fec_netdev_ops;
4145 	ndev->ethtool_ops = &fec_enet_ethtool_ops;
4146 
4147 	writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
4148 	netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi);
4149 
4150 	if (fep->quirks & FEC_QUIRK_HAS_VLAN)
4151 		/* enable hw VLAN support */
4152 		ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
4153 
4154 	if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
4155 		netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS);
4156 
4157 		/* enable hw accelerator */
4158 		ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
4159 				| NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
4160 		fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
4161 	}
4162 
4163 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
4164 		fep->tx_align = 0;
4165 		fep->rx_align = 0x3f;
4166 	}
4167 
4168 	ndev->hw_features = ndev->features;
4169 
4170 	if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME))
4171 		ndev->xdp_features = NETDEV_XDP_ACT_BASIC |
4172 				     NETDEV_XDP_ACT_REDIRECT;
4173 
4174 	fec_restart(ndev);
4175 
4176 	if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
4177 		fec_enet_clear_ethtool_stats(ndev);
4178 	else
4179 		fec_enet_update_ethtool_stats(ndev);
4180 
4181 	return 0;
4182 
4183 free_queue_mem:
4184 	fec_enet_free_queue(ndev);
4185 	return ret;
4186 }
4187 
fec_enet_deinit(struct net_device * ndev)4188 static void fec_enet_deinit(struct net_device *ndev)
4189 {
4190 	struct fec_enet_private *fep = netdev_priv(ndev);
4191 
4192 	netif_napi_del(&fep->napi);
4193 	fec_enet_free_queue(ndev);
4194 }
4195 
4196 #ifdef CONFIG_OF
fec_reset_phy(struct platform_device * pdev)4197 static int fec_reset_phy(struct platform_device *pdev)
4198 {
4199 	struct gpio_desc *phy_reset;
4200 	int msec = 1, phy_post_delay = 0;
4201 	struct device_node *np = pdev->dev.of_node;
4202 	int err;
4203 
4204 	if (!np)
4205 		return 0;
4206 
4207 	err = of_property_read_u32(np, "phy-reset-duration", &msec);
4208 	/* A sane reset duration should not be longer than 1s */
4209 	if (!err && msec > 1000)
4210 		msec = 1;
4211 
4212 	err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
4213 	/* valid reset duration should be less than 1s */
4214 	if (!err && phy_post_delay > 1000)
4215 		return -EINVAL;
4216 
4217 	phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset",
4218 					    GPIOD_OUT_HIGH);
4219 	if (IS_ERR(phy_reset))
4220 		return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset),
4221 				     "failed to get phy-reset-gpios\n");
4222 
4223 	if (!phy_reset)
4224 		return 0;
4225 
4226 	if (msec > 20)
4227 		msleep(msec);
4228 	else
4229 		usleep_range(msec * 1000, msec * 1000 + 1000);
4230 
4231 	gpiod_set_value_cansleep(phy_reset, 0);
4232 
4233 	if (!phy_post_delay)
4234 		return 0;
4235 
4236 	if (phy_post_delay > 20)
4237 		msleep(phy_post_delay);
4238 	else
4239 		usleep_range(phy_post_delay * 1000,
4240 			     phy_post_delay * 1000 + 1000);
4241 
4242 	return 0;
4243 }
4244 #else /* CONFIG_OF */
fec_reset_phy(struct platform_device * pdev)4245 static int fec_reset_phy(struct platform_device *pdev)
4246 {
4247 	/*
4248 	 * In case of platform probe, the reset has been done
4249 	 * by machine code.
4250 	 */
4251 	return 0;
4252 }
4253 #endif /* CONFIG_OF */
4254 
4255 static void
fec_enet_get_queue_num(struct platform_device * pdev,int * num_tx,int * num_rx)4256 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
4257 {
4258 	struct device_node *np = pdev->dev.of_node;
4259 
4260 	*num_tx = *num_rx = 1;
4261 
4262 	if (!np || !of_device_is_available(np))
4263 		return;
4264 
4265 	/* parse the num of tx and rx queues */
4266 	of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
4267 
4268 	of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
4269 
4270 	if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
4271 		dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
4272 			 *num_tx);
4273 		*num_tx = 1;
4274 		return;
4275 	}
4276 
4277 	if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
4278 		dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
4279 			 *num_rx);
4280 		*num_rx = 1;
4281 		return;
4282 	}
4283 
4284 }
4285 
fec_enet_get_irq_cnt(struct platform_device * pdev)4286 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
4287 {
4288 	int irq_cnt = platform_irq_count(pdev);
4289 
4290 	if (irq_cnt > FEC_IRQ_NUM)
4291 		irq_cnt = FEC_IRQ_NUM;	/* last for pps */
4292 	else if (irq_cnt == 2)
4293 		irq_cnt = 1;	/* last for pps */
4294 	else if (irq_cnt <= 0)
4295 		irq_cnt = 1;	/* At least 1 irq is needed */
4296 	return irq_cnt;
4297 }
4298 
fec_enet_get_wakeup_irq(struct platform_device * pdev)4299 static void fec_enet_get_wakeup_irq(struct platform_device *pdev)
4300 {
4301 	struct net_device *ndev = platform_get_drvdata(pdev);
4302 	struct fec_enet_private *fep = netdev_priv(ndev);
4303 
4304 	if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2)
4305 		fep->wake_irq = fep->irq[2];
4306 	else
4307 		fep->wake_irq = fep->irq[0];
4308 }
4309 
fec_enet_init_stop_mode(struct fec_enet_private * fep,struct device_node * np)4310 static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
4311 				   struct device_node *np)
4312 {
4313 	struct device_node *gpr_np;
4314 	u32 out_val[3];
4315 	int ret = 0;
4316 
4317 	gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
4318 	if (!gpr_np)
4319 		return 0;
4320 
4321 	ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
4322 					 ARRAY_SIZE(out_val));
4323 	if (ret) {
4324 		dev_dbg(&fep->pdev->dev, "no stop mode property\n");
4325 		goto out;
4326 	}
4327 
4328 	fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
4329 	if (IS_ERR(fep->stop_gpr.gpr)) {
4330 		dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
4331 		ret = PTR_ERR(fep->stop_gpr.gpr);
4332 		fep->stop_gpr.gpr = NULL;
4333 		goto out;
4334 	}
4335 
4336 	fep->stop_gpr.reg = out_val[1];
4337 	fep->stop_gpr.bit = out_val[2];
4338 
4339 out:
4340 	of_node_put(gpr_np);
4341 
4342 	return ret;
4343 }
4344 
4345 static int
fec_probe(struct platform_device * pdev)4346 fec_probe(struct platform_device *pdev)
4347 {
4348 	struct fec_enet_private *fep;
4349 	struct fec_platform_data *pdata;
4350 	phy_interface_t interface;
4351 	struct net_device *ndev;
4352 	int i, irq, ret = 0;
4353 	const struct of_device_id *of_id;
4354 	static int dev_id;
4355 	struct device_node *np = pdev->dev.of_node, *phy_node;
4356 	int num_tx_qs;
4357 	int num_rx_qs;
4358 	char irq_name[8];
4359 	int irq_cnt;
4360 	struct fec_devinfo *dev_info;
4361 
4362 	fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
4363 
4364 	/* Init network device */
4365 	ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
4366 				  FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
4367 	if (!ndev)
4368 		return -ENOMEM;
4369 
4370 	SET_NETDEV_DEV(ndev, &pdev->dev);
4371 
4372 	/* setup board info structure */
4373 	fep = netdev_priv(ndev);
4374 
4375 	of_id = of_match_device(fec_dt_ids, &pdev->dev);
4376 	if (of_id)
4377 		pdev->id_entry = of_id->data;
4378 	dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data;
4379 	if (dev_info)
4380 		fep->quirks = dev_info->quirks;
4381 
4382 	fep->netdev = ndev;
4383 	fep->num_rx_queues = num_rx_qs;
4384 	fep->num_tx_queues = num_tx_qs;
4385 
4386 #if !defined(CONFIG_M5272)
4387 	/* default enable pause frame auto negotiation */
4388 	if (fep->quirks & FEC_QUIRK_HAS_GBIT)
4389 		fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
4390 #endif
4391 
4392 	/* Select default pin state */
4393 	pinctrl_pm_select_default_state(&pdev->dev);
4394 
4395 	fep->hwp = devm_platform_ioremap_resource(pdev, 0);
4396 	if (IS_ERR(fep->hwp)) {
4397 		ret = PTR_ERR(fep->hwp);
4398 		goto failed_ioremap;
4399 	}
4400 
4401 	fep->pdev = pdev;
4402 	fep->dev_id = dev_id++;
4403 
4404 	platform_set_drvdata(pdev, ndev);
4405 
4406 	if ((of_machine_is_compatible("fsl,imx6q") ||
4407 	     of_machine_is_compatible("fsl,imx6dl")) &&
4408 	    !of_property_read_bool(np, "fsl,err006687-workaround-present"))
4409 		fep->quirks |= FEC_QUIRK_ERR006687;
4410 
4411 	ret = fec_enet_ipc_handle_init(fep);
4412 	if (ret)
4413 		goto failed_ipc_init;
4414 
4415 	if (of_property_read_bool(np, "fsl,magic-packet"))
4416 		fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
4417 
4418 	ret = fec_enet_init_stop_mode(fep, np);
4419 	if (ret)
4420 		goto failed_stop_mode;
4421 
4422 	phy_node = of_parse_phandle(np, "phy-handle", 0);
4423 	if (!phy_node && of_phy_is_fixed_link(np)) {
4424 		ret = of_phy_register_fixed_link(np);
4425 		if (ret < 0) {
4426 			dev_err(&pdev->dev,
4427 				"broken fixed-link specification\n");
4428 			goto failed_phy;
4429 		}
4430 		phy_node = of_node_get(np);
4431 	}
4432 	fep->phy_node = phy_node;
4433 
4434 	ret = of_get_phy_mode(pdev->dev.of_node, &interface);
4435 	if (ret) {
4436 		pdata = dev_get_platdata(&pdev->dev);
4437 		if (pdata)
4438 			fep->phy_interface = pdata->phy;
4439 		else
4440 			fep->phy_interface = PHY_INTERFACE_MODE_MII;
4441 	} else {
4442 		fep->phy_interface = interface;
4443 	}
4444 
4445 	ret = fec_enet_parse_rgmii_delay(fep, np);
4446 	if (ret)
4447 		goto failed_rgmii_delay;
4448 
4449 	fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
4450 	if (IS_ERR(fep->clk_ipg)) {
4451 		ret = PTR_ERR(fep->clk_ipg);
4452 		goto failed_clk;
4453 	}
4454 
4455 	fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
4456 	if (IS_ERR(fep->clk_ahb)) {
4457 		ret = PTR_ERR(fep->clk_ahb);
4458 		goto failed_clk;
4459 	}
4460 
4461 	fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
4462 
4463 	/* enet_out is optional, depends on board */
4464 	fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out");
4465 	if (IS_ERR(fep->clk_enet_out)) {
4466 		ret = PTR_ERR(fep->clk_enet_out);
4467 		goto failed_clk;
4468 	}
4469 
4470 	fep->ptp_clk_on = false;
4471 	mutex_init(&fep->ptp_clk_mutex);
4472 
4473 	/* clk_ref is optional, depends on board */
4474 	fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref");
4475 	if (IS_ERR(fep->clk_ref)) {
4476 		ret = PTR_ERR(fep->clk_ref);
4477 		goto failed_clk;
4478 	}
4479 	fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
4480 
4481 	/* clk_2x_txclk is optional, depends on board */
4482 	if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) {
4483 		fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk");
4484 		if (IS_ERR(fep->clk_2x_txclk))
4485 			fep->clk_2x_txclk = NULL;
4486 	}
4487 
4488 	fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
4489 	fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
4490 	if (IS_ERR(fep->clk_ptp)) {
4491 		fep->clk_ptp = NULL;
4492 		fep->bufdesc_ex = false;
4493 	}
4494 
4495 	ret = fec_enet_clk_enable(ndev, true);
4496 	if (ret)
4497 		goto failed_clk;
4498 
4499 	ret = clk_prepare_enable(fep->clk_ipg);
4500 	if (ret)
4501 		goto failed_clk_ipg;
4502 	ret = clk_prepare_enable(fep->clk_ahb);
4503 	if (ret)
4504 		goto failed_clk_ahb;
4505 
4506 	fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
4507 	if (!IS_ERR(fep->reg_phy)) {
4508 		ret = regulator_enable(fep->reg_phy);
4509 		if (ret) {
4510 			dev_err(&pdev->dev,
4511 				"Failed to enable phy regulator: %d\n", ret);
4512 			goto failed_regulator;
4513 		}
4514 	} else {
4515 		if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
4516 			ret = -EPROBE_DEFER;
4517 			goto failed_regulator;
4518 		}
4519 		fep->reg_phy = NULL;
4520 	}
4521 
4522 	pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
4523 	pm_runtime_use_autosuspend(&pdev->dev);
4524 	pm_runtime_get_noresume(&pdev->dev);
4525 	pm_runtime_set_active(&pdev->dev);
4526 	pm_runtime_enable(&pdev->dev);
4527 
4528 	ret = fec_reset_phy(pdev);
4529 	if (ret)
4530 		goto failed_reset;
4531 
4532 	irq_cnt = fec_enet_get_irq_cnt(pdev);
4533 	if (fep->bufdesc_ex)
4534 		fec_ptp_init(pdev, irq_cnt);
4535 
4536 	ret = fec_enet_init(ndev);
4537 	if (ret)
4538 		goto failed_init;
4539 
4540 	for (i = 0; i < irq_cnt; i++) {
4541 		snprintf(irq_name, sizeof(irq_name), "int%d", i);
4542 		irq = platform_get_irq_byname_optional(pdev, irq_name);
4543 		if (irq < 0)
4544 			irq = platform_get_irq(pdev, i);
4545 		if (irq < 0) {
4546 			ret = irq;
4547 			goto failed_irq;
4548 		}
4549 		ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
4550 				       0, pdev->name, ndev);
4551 		if (ret)
4552 			goto failed_irq;
4553 
4554 		fep->irq[i] = irq;
4555 	}
4556 
4557 	/* Decide which interrupt line is wakeup capable */
4558 	fec_enet_get_wakeup_irq(pdev);
4559 
4560 	ret = fec_enet_mii_init(pdev);
4561 	if (ret)
4562 		goto failed_mii_init;
4563 
4564 	/* Carrier starts down, phylib will bring it up */
4565 	netif_carrier_off(ndev);
4566 	fec_enet_clk_enable(ndev, false);
4567 	pinctrl_pm_select_sleep_state(&pdev->dev);
4568 
4569 	ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
4570 
4571 	ret = register_netdev(ndev);
4572 	if (ret)
4573 		goto failed_register;
4574 
4575 	device_init_wakeup(&ndev->dev, fep->wol_flag &
4576 			   FEC_WOL_HAS_MAGIC_PACKET);
4577 
4578 	if (fep->bufdesc_ex && fep->ptp_clock)
4579 		netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
4580 
4581 	INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
4582 
4583 	pm_runtime_mark_last_busy(&pdev->dev);
4584 	pm_runtime_put_autosuspend(&pdev->dev);
4585 
4586 	return 0;
4587 
4588 failed_register:
4589 	fec_enet_mii_remove(fep);
4590 failed_mii_init:
4591 failed_irq:
4592 	fec_enet_deinit(ndev);
4593 failed_init:
4594 	fec_ptp_stop(pdev);
4595 failed_reset:
4596 	pm_runtime_put_noidle(&pdev->dev);
4597 	pm_runtime_disable(&pdev->dev);
4598 	if (fep->reg_phy)
4599 		regulator_disable(fep->reg_phy);
4600 failed_regulator:
4601 	clk_disable_unprepare(fep->clk_ahb);
4602 failed_clk_ahb:
4603 	clk_disable_unprepare(fep->clk_ipg);
4604 failed_clk_ipg:
4605 	fec_enet_clk_enable(ndev, false);
4606 failed_clk:
4607 failed_rgmii_delay:
4608 	if (of_phy_is_fixed_link(np))
4609 		of_phy_deregister_fixed_link(np);
4610 	of_node_put(phy_node);
4611 failed_stop_mode:
4612 failed_ipc_init:
4613 failed_phy:
4614 	dev_id--;
4615 failed_ioremap:
4616 	free_netdev(ndev);
4617 
4618 	return ret;
4619 }
4620 
4621 static void
fec_drv_remove(struct platform_device * pdev)4622 fec_drv_remove(struct platform_device *pdev)
4623 {
4624 	struct net_device *ndev = platform_get_drvdata(pdev);
4625 	struct fec_enet_private *fep = netdev_priv(ndev);
4626 	struct device_node *np = pdev->dev.of_node;
4627 	int ret;
4628 
4629 	ret = pm_runtime_get_sync(&pdev->dev);
4630 	if (ret < 0)
4631 		dev_err(&pdev->dev,
4632 			"Failed to resume device in remove callback (%pe)\n",
4633 			ERR_PTR(ret));
4634 
4635 	cancel_work_sync(&fep->tx_timeout_work);
4636 	fec_ptp_stop(pdev);
4637 	unregister_netdev(ndev);
4638 	fec_enet_mii_remove(fep);
4639 	if (fep->reg_phy)
4640 		regulator_disable(fep->reg_phy);
4641 
4642 	if (of_phy_is_fixed_link(np))
4643 		of_phy_deregister_fixed_link(np);
4644 	of_node_put(fep->phy_node);
4645 
4646 	/* After pm_runtime_get_sync() failed, the clks are still off, so skip
4647 	 * disabling them again.
4648 	 */
4649 	if (ret >= 0) {
4650 		clk_disable_unprepare(fep->clk_ahb);
4651 		clk_disable_unprepare(fep->clk_ipg);
4652 	}
4653 	pm_runtime_put_noidle(&pdev->dev);
4654 	pm_runtime_disable(&pdev->dev);
4655 
4656 	fec_enet_deinit(ndev);
4657 	free_netdev(ndev);
4658 }
4659 
fec_suspend(struct device * dev)4660 static int __maybe_unused fec_suspend(struct device *dev)
4661 {
4662 	struct net_device *ndev = dev_get_drvdata(dev);
4663 	struct fec_enet_private *fep = netdev_priv(ndev);
4664 	int ret;
4665 
4666 	rtnl_lock();
4667 	if (netif_running(ndev)) {
4668 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
4669 			fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
4670 		phy_stop(ndev->phydev);
4671 		napi_disable(&fep->napi);
4672 		netif_tx_lock_bh(ndev);
4673 		netif_device_detach(ndev);
4674 		netif_tx_unlock_bh(ndev);
4675 		fec_stop(ndev);
4676 		if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4677 			fec_irqs_disable(ndev);
4678 			pinctrl_pm_select_sleep_state(&fep->pdev->dev);
4679 		} else {
4680 			fec_irqs_disable_except_wakeup(ndev);
4681 			if (fep->wake_irq > 0) {
4682 				disable_irq(fep->wake_irq);
4683 				enable_irq_wake(fep->wake_irq);
4684 			}
4685 			fec_enet_stop_mode(fep, true);
4686 		}
4687 		/* It's safe to disable clocks since interrupts are masked */
4688 		fec_enet_clk_enable(ndev, false);
4689 
4690 		fep->rpm_active = !pm_runtime_status_suspended(dev);
4691 		if (fep->rpm_active) {
4692 			ret = pm_runtime_force_suspend(dev);
4693 			if (ret < 0) {
4694 				rtnl_unlock();
4695 				return ret;
4696 			}
4697 		}
4698 	}
4699 	rtnl_unlock();
4700 
4701 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
4702 		regulator_disable(fep->reg_phy);
4703 
4704 	/* SOC supply clock to phy, when clock is disabled, phy link down
4705 	 * SOC control phy regulator, when regulator is disabled, phy link down
4706 	 */
4707 	if (fep->clk_enet_out || fep->reg_phy)
4708 		fep->link = 0;
4709 
4710 	return 0;
4711 }
4712 
fec_resume(struct device * dev)4713 static int __maybe_unused fec_resume(struct device *dev)
4714 {
4715 	struct net_device *ndev = dev_get_drvdata(dev);
4716 	struct fec_enet_private *fep = netdev_priv(ndev);
4717 	int ret;
4718 	int val;
4719 
4720 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4721 		ret = regulator_enable(fep->reg_phy);
4722 		if (ret)
4723 			return ret;
4724 	}
4725 
4726 	rtnl_lock();
4727 	if (netif_running(ndev)) {
4728 		if (fep->rpm_active)
4729 			pm_runtime_force_resume(dev);
4730 
4731 		ret = fec_enet_clk_enable(ndev, true);
4732 		if (ret) {
4733 			rtnl_unlock();
4734 			goto failed_clk;
4735 		}
4736 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
4737 			fec_enet_stop_mode(fep, false);
4738 			if (fep->wake_irq) {
4739 				disable_irq_wake(fep->wake_irq);
4740 				enable_irq(fep->wake_irq);
4741 			}
4742 
4743 			val = readl(fep->hwp + FEC_ECNTRL);
4744 			val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
4745 			writel(val, fep->hwp + FEC_ECNTRL);
4746 			fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
4747 		} else {
4748 			pinctrl_pm_select_default_state(&fep->pdev->dev);
4749 		}
4750 		fec_restart(ndev);
4751 		netif_tx_lock_bh(ndev);
4752 		netif_device_attach(ndev);
4753 		netif_tx_unlock_bh(ndev);
4754 		napi_enable(&fep->napi);
4755 		phy_init_hw(ndev->phydev);
4756 		phy_start(ndev->phydev);
4757 	}
4758 	rtnl_unlock();
4759 
4760 	return 0;
4761 
4762 failed_clk:
4763 	if (fep->reg_phy)
4764 		regulator_disable(fep->reg_phy);
4765 	return ret;
4766 }
4767 
fec_runtime_suspend(struct device * dev)4768 static int __maybe_unused fec_runtime_suspend(struct device *dev)
4769 {
4770 	struct net_device *ndev = dev_get_drvdata(dev);
4771 	struct fec_enet_private *fep = netdev_priv(ndev);
4772 
4773 	clk_disable_unprepare(fep->clk_ahb);
4774 	clk_disable_unprepare(fep->clk_ipg);
4775 
4776 	return 0;
4777 }
4778 
fec_runtime_resume(struct device * dev)4779 static int __maybe_unused fec_runtime_resume(struct device *dev)
4780 {
4781 	struct net_device *ndev = dev_get_drvdata(dev);
4782 	struct fec_enet_private *fep = netdev_priv(ndev);
4783 	int ret;
4784 
4785 	ret = clk_prepare_enable(fep->clk_ahb);
4786 	if (ret)
4787 		return ret;
4788 	ret = clk_prepare_enable(fep->clk_ipg);
4789 	if (ret)
4790 		goto failed_clk_ipg;
4791 
4792 	return 0;
4793 
4794 failed_clk_ipg:
4795 	clk_disable_unprepare(fep->clk_ahb);
4796 	return ret;
4797 }
4798 
4799 static const struct dev_pm_ops fec_pm_ops = {
4800 	SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
4801 	SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
4802 };
4803 
4804 static struct platform_driver fec_driver = {
4805 	.driver	= {
4806 		.name	= DRIVER_NAME,
4807 		.pm	= &fec_pm_ops,
4808 		.of_match_table = fec_dt_ids,
4809 		.suppress_bind_attrs = true,
4810 	},
4811 	.id_table = fec_devtype,
4812 	.probe	= fec_probe,
4813 	.remove_new = fec_drv_remove,
4814 };
4815 
4816 module_platform_driver(fec_driver);
4817 
4818 MODULE_LICENSE("GPL");
4819