1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/soc.h>
12 #include <asm/arch-fsl-layerscape/fsl_icid.h>
13 #include <fdt_support.h>
14 #include <hwconfig.h>
15 #include <ahci.h>
16 #include <mmc.h>
17 #include <scsi.h>
18 #include <fm_eth.h>
19 #include <fsl_esdhc.h>
20 #include <fsl_ifc.h>
21 #include <fsl_sec.h>
22 #include "cpld.h"
23 #ifdef CONFIG_U_QE
24 #include <fsl_qe.h>
25 #endif
26 #include <asm/arch/ppa.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #ifdef CONFIG_TFABOOT
31 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
32 {
33 "nor",
34 CONFIG_SYS_NOR_CSPR,
35 CONFIG_SYS_NOR_CSPR_EXT,
36 CONFIG_SYS_NOR_AMASK,
37 CONFIG_SYS_NOR_CSOR,
38 {
39 CONFIG_SYS_NOR_FTIM0,
40 CONFIG_SYS_NOR_FTIM1,
41 CONFIG_SYS_NOR_FTIM2,
42 CONFIG_SYS_NOR_FTIM3
43 },
44
45 },
46 {
47 "nand",
48 CONFIG_SYS_NAND_CSPR,
49 CONFIG_SYS_NAND_CSPR_EXT,
50 CONFIG_SYS_NAND_AMASK,
51 CONFIG_SYS_NAND_CSOR,
52 {
53 CONFIG_SYS_NAND_FTIM0,
54 CONFIG_SYS_NAND_FTIM1,
55 CONFIG_SYS_NAND_FTIM2,
56 CONFIG_SYS_NAND_FTIM3
57 },
58 },
59 {
60 "cpld",
61 CONFIG_SYS_CPLD_CSPR,
62 CONFIG_SYS_CPLD_CSPR_EXT,
63 CONFIG_SYS_CPLD_AMASK,
64 CONFIG_SYS_CPLD_CSOR,
65 {
66 CONFIG_SYS_CPLD_FTIM0,
67 CONFIG_SYS_CPLD_FTIM1,
68 CONFIG_SYS_CPLD_FTIM2,
69 CONFIG_SYS_CPLD_FTIM3
70 },
71 }
72 };
73
74 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
75 {
76 "nand",
77 CONFIG_SYS_NAND_CSPR,
78 CONFIG_SYS_NAND_CSPR_EXT,
79 CONFIG_SYS_NAND_AMASK,
80 CONFIG_SYS_NAND_CSOR,
81 {
82 CONFIG_SYS_NAND_FTIM0,
83 CONFIG_SYS_NAND_FTIM1,
84 CONFIG_SYS_NAND_FTIM2,
85 CONFIG_SYS_NAND_FTIM3
86 },
87 },
88 {
89 "nor",
90 CONFIG_SYS_NOR_CSPR,
91 CONFIG_SYS_NOR_CSPR_EXT,
92 CONFIG_SYS_NOR_AMASK,
93 CONFIG_SYS_NOR_CSOR,
94 {
95 CONFIG_SYS_NOR_FTIM0,
96 CONFIG_SYS_NOR_FTIM1,
97 CONFIG_SYS_NOR_FTIM2,
98 CONFIG_SYS_NOR_FTIM3
99 },
100 },
101 {
102 "cpld",
103 CONFIG_SYS_CPLD_CSPR,
104 CONFIG_SYS_CPLD_CSPR_EXT,
105 CONFIG_SYS_CPLD_AMASK,
106 CONFIG_SYS_CPLD_CSOR,
107 {
108 CONFIG_SYS_CPLD_FTIM0,
109 CONFIG_SYS_CPLD_FTIM1,
110 CONFIG_SYS_CPLD_FTIM2,
111 CONFIG_SYS_CPLD_FTIM3
112 },
113 }
114 };
115
ifc_cfg_boot_info(struct ifc_regs_info * regs_info)116 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
117 {
118 enum boot_src src = get_boot_src();
119
120 if (src == BOOT_SOURCE_IFC_NAND)
121 regs_info->regs = ifc_cfg_nand_boot;
122 else
123 regs_info->regs = ifc_cfg_nor_boot;
124 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
125 }
126
127 #endif
board_early_init_f(void)128 int board_early_init_f(void)
129 {
130 fsl_lsch2_early_init_f();
131
132 return 0;
133 }
134
135 #ifndef CONFIG_SPL_BUILD
136
checkboard(void)137 int checkboard(void)
138 {
139 #ifdef CONFIG_TFABOOT
140 enum boot_src src = get_boot_src();
141 #endif
142 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
143 #ifndef CONFIG_SD_BOOT
144 u8 cfg_rcw_src1, cfg_rcw_src2;
145 u16 cfg_rcw_src;
146 #endif
147 u8 sd1refclk_sel;
148
149 printf("Board: LS1043ARDB, boot from ");
150
151 #ifdef CONFIG_TFABOOT
152 if (src == BOOT_SOURCE_SD_MMC)
153 puts("SD\n");
154 else {
155 #endif
156
157 #ifdef CONFIG_SD_BOOT
158 puts("SD\n");
159 #else
160 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
161 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
162 cpld_rev_bit(&cfg_rcw_src1);
163 cfg_rcw_src = cfg_rcw_src1;
164 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
165
166 if (cfg_rcw_src == 0x25)
167 printf("vBank %d\n", CPLD_READ(vbank));
168 else if (cfg_rcw_src == 0x106)
169 puts("NAND\n");
170 else
171 printf("Invalid setting of SW4\n");
172 #endif
173
174 #ifdef CONFIG_TFABOOT
175 }
176 #endif
177 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
178 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
179
180 puts("SERDES Reference Clocks:\n");
181 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
182 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
183
184 return 0;
185 }
186
board_init(void)187 int board_init(void)
188 {
189 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
190
191 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
192 erratum_a010315();
193 #endif
194
195 #ifdef CONFIG_FSL_IFC
196 init_final_memctl_regs();
197 #endif
198
199 #ifdef CONFIG_SECURE_BOOT
200 /* In case of Secure Boot, the IBR configures the SMMU
201 * to allow only Secure transactions.
202 * SMMU must be reset in bypass mode.
203 * Set the ClientPD bit and Clear the USFCFG Bit
204 */
205 u32 val;
206 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
207 out_le32(SMMU_SCR0, val);
208 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
209 out_le32(SMMU_NSCR0, val);
210 #endif
211
212 #ifdef CONFIG_FSL_CAAM
213 sec_init();
214 #endif
215
216 #ifdef CONFIG_FSL_LS_PPA
217 ppa_init();
218 #endif
219
220 #ifdef CONFIG_U_QE
221 u_qe_init();
222 #endif
223 /* invert AQR105 IRQ pins polarity */
224 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
225
226 return 0;
227 }
228
config_board_mux(void)229 int config_board_mux(void)
230 {
231 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
232 u32 usb_pwrfault;
233
234 if (hwconfig("qe-hdlc")) {
235 out_be32(&scfg->rcwpmuxcr0,
236 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
237 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
238 in_be32(&scfg->rcwpmuxcr0));
239 } else {
240 #ifdef CONFIG_HAS_FSL_XHCI_USB
241 out_be32(&scfg->rcwpmuxcr0, 0x3333);
242 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
243 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
244 SCFG_USBPWRFAULT_USB3_SHIFT) |
245 (SCFG_USBPWRFAULT_DEDICATED <<
246 SCFG_USBPWRFAULT_USB2_SHIFT) |
247 (SCFG_USBPWRFAULT_SHARED <<
248 SCFG_USBPWRFAULT_USB1_SHIFT);
249 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
250 #endif
251 }
252 return 0;
253 }
254
255 #if defined(CONFIG_MISC_INIT_R)
misc_init_r(void)256 int misc_init_r(void)
257 {
258 config_board_mux();
259 return 0;
260 }
261 #endif
262
fdt_del_qe(void * blob)263 void fdt_del_qe(void *blob)
264 {
265 int nodeoff = 0;
266
267 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
268 "fsl,qe")) >= 0) {
269 fdt_del_node(blob, nodeoff);
270 }
271 }
272
ft_board_setup(void * blob,bd_t * bd)273 int ft_board_setup(void *blob, bd_t *bd)
274 {
275 u64 base[CONFIG_NR_DRAM_BANKS];
276 u64 size[CONFIG_NR_DRAM_BANKS];
277
278 /* fixup DT for the two DDR banks */
279 base[0] = gd->bd->bi_dram[0].start;
280 size[0] = gd->bd->bi_dram[0].size;
281 base[1] = gd->bd->bi_dram[1].start;
282 size[1] = gd->bd->bi_dram[1].size;
283
284 fdt_fixup_memory_banks(blob, base, size, 2);
285 ft_cpu_setup(blob, bd);
286
287 #ifdef CONFIG_SYS_DPAA_FMAN
288 fdt_fixup_fman_ethernet(blob);
289 #endif
290
291 fdt_fixup_icid(blob);
292
293 /*
294 * qe-hdlc and usb multi-use the pins,
295 * when set hwconfig to qe-hdlc, delete usb node.
296 */
297 if (hwconfig("qe-hdlc"))
298 #ifdef CONFIG_HAS_FSL_XHCI_USB
299 fdt_del_node_and_alias(blob, "usb1");
300 #endif
301 /*
302 * qe just support qe-uart and qe-hdlc,
303 * if qe-uart and qe-hdlc are not set in hwconfig,
304 * delete qe node.
305 */
306 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
307 fdt_del_qe(blob);
308
309 return 0;
310 }
311
flash_read8(void * addr)312 u8 flash_read8(void *addr)
313 {
314 return __raw_readb(addr + 1);
315 }
316
flash_write16(u16 val,void * addr)317 void flash_write16(u16 val, void *addr)
318 {
319 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
320
321 __raw_writew(shftval, addr);
322 }
323
flash_read16(void * addr)324 u16 flash_read16(void *addr)
325 {
326 u16 val = __raw_readw(addr);
327
328 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
329 }
330
331 #endif
332