1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/of.h>
14 #include <linux/mfd/stmpe.h>
15 #include <linux/seq_file.h>
16 #include <linux/bitops.h>
17
18 /*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22 enum { REG_RE, REG_FE, REG_IE };
23
24 enum { LSB, CSB, MSB };
25
26 #define CACHE_NR_REGS 3
27 /* No variant has more than 24 GPIOs */
28 #define CACHE_NR_BANKS (24 / 8)
29
30 struct stmpe_gpio {
31 struct gpio_chip chip;
32 struct stmpe *stmpe;
33 struct device *dev;
34 struct mutex irq_lock;
35 u32 norequest_mask;
36 /* Caches of interrupt control registers for bus_lock */
37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
39 };
40
stmpe_gpio_get(struct gpio_chip * chip,unsigned offset)41 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
42 {
43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
44 struct stmpe *stmpe = stmpe_gpio->stmpe;
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
46 u8 mask = BIT(offset % 8);
47 int ret;
48
49 ret = stmpe_reg_read(stmpe, reg);
50 if (ret < 0)
51 return ret;
52
53 return !!(ret & mask);
54 }
55
stmpe_gpio_set(struct gpio_chip * chip,unsigned offset,int val)56 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57 {
58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
59 struct stmpe *stmpe = stmpe_gpio->stmpe;
60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
61 u8 reg = stmpe->regs[which + (offset / 8)];
62 u8 mask = BIT(offset % 8);
63
64 /*
65 * Some variants have single register for gpio set/clear functionality.
66 * For them we need to write 0 to clear and 1 to set.
67 */
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
70 else
71 stmpe_reg_write(stmpe, reg, mask);
72 }
73
stmpe_gpio_get_direction(struct gpio_chip * chip,unsigned offset)74 static int stmpe_gpio_get_direction(struct gpio_chip *chip,
75 unsigned offset)
76 {
77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
78 struct stmpe *stmpe = stmpe_gpio->stmpe;
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
80 u8 mask = BIT(offset % 8);
81 int ret;
82
83 ret = stmpe_reg_read(stmpe, reg);
84 if (ret < 0)
85 return ret;
86
87 if (ret & mask)
88 return GPIO_LINE_DIRECTION_OUT;
89
90 return GPIO_LINE_DIRECTION_IN;
91 }
92
stmpe_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int val)93 static int stmpe_gpio_direction_output(struct gpio_chip *chip,
94 unsigned offset, int val)
95 {
96 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
97 struct stmpe *stmpe = stmpe_gpio->stmpe;
98 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
99 u8 mask = BIT(offset % 8);
100
101 stmpe_gpio_set(chip, offset, val);
102
103 return stmpe_set_bits(stmpe, reg, mask, mask);
104 }
105
stmpe_gpio_direction_input(struct gpio_chip * chip,unsigned offset)106 static int stmpe_gpio_direction_input(struct gpio_chip *chip,
107 unsigned offset)
108 {
109 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
110 struct stmpe *stmpe = stmpe_gpio->stmpe;
111 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
112 u8 mask = BIT(offset % 8);
113
114 return stmpe_set_bits(stmpe, reg, mask, 0);
115 }
116
stmpe_gpio_request(struct gpio_chip * chip,unsigned offset)117 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
118 {
119 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
120 struct stmpe *stmpe = stmpe_gpio->stmpe;
121
122 if (stmpe_gpio->norequest_mask & BIT(offset))
123 return -EINVAL;
124
125 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
126 }
127
128 static const struct gpio_chip template_chip = {
129 .label = "stmpe",
130 .owner = THIS_MODULE,
131 .get_direction = stmpe_gpio_get_direction,
132 .direction_input = stmpe_gpio_direction_input,
133 .get = stmpe_gpio_get,
134 .direction_output = stmpe_gpio_direction_output,
135 .set = stmpe_gpio_set,
136 .request = stmpe_gpio_request,
137 .can_sleep = true,
138 };
139
stmpe_gpio_irq_set_type(struct irq_data * d,unsigned int type)140 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
141 {
142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
143 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
144 int offset = d->hwirq;
145 int regoffset = offset / 8;
146 int mask = BIT(offset % 8);
147
148 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
149 return -EINVAL;
150
151 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
152 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
153 stmpe_gpio->stmpe->partnum == STMPE1600)
154 return 0;
155
156 if (type & IRQ_TYPE_EDGE_RISING)
157 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
158 else
159 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
160
161 if (type & IRQ_TYPE_EDGE_FALLING)
162 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
163 else
164 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
165
166 return 0;
167 }
168
stmpe_gpio_irq_lock(struct irq_data * d)169 static void stmpe_gpio_irq_lock(struct irq_data *d)
170 {
171 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
172 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
173
174 mutex_lock(&stmpe_gpio->irq_lock);
175 }
176
stmpe_gpio_irq_sync_unlock(struct irq_data * d)177 static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
178 {
179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
180 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
181 struct stmpe *stmpe = stmpe_gpio->stmpe;
182 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
183 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
184 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
185 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
186 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
187 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
188 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
189 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
190 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
191 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
192 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
193 };
194 int ret, i, j;
195
196 /*
197 * STMPE1600: to be able to get IRQ from pins,
198 * a read must be done on GPMR register, or a write in
199 * GPSR or GPCR registers
200 */
201 if (stmpe->partnum == STMPE1600) {
202 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
203 if (ret < 0) {
204 dev_err(stmpe->dev, "Failed to read GPMR_LSB: %d\n", ret);
205 goto err;
206 }
207 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
208 if (ret < 0) {
209 dev_err(stmpe->dev, "Failed to read GPMR_CSB: %d\n", ret);
210 goto err;
211 }
212 }
213
214 for (i = 0; i < CACHE_NR_REGS; i++) {
215 /* STMPE801 and STMPE1600 don't have RE and FE registers */
216 if ((stmpe->partnum == STMPE801 ||
217 stmpe->partnum == STMPE1600) &&
218 (i != REG_IE))
219 continue;
220
221 for (j = 0; j < num_banks; j++) {
222 u8 old = stmpe_gpio->oldregs[i][j];
223 u8 new = stmpe_gpio->regs[i][j];
224
225 if (new == old)
226 continue;
227
228 stmpe_gpio->oldregs[i][j] = new;
229 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
230 }
231 }
232
233 err:
234 mutex_unlock(&stmpe_gpio->irq_lock);
235 }
236
stmpe_gpio_irq_mask(struct irq_data * d)237 static void stmpe_gpio_irq_mask(struct irq_data *d)
238 {
239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
240 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
241 int offset = d->hwirq;
242 int regoffset = offset / 8;
243 int mask = BIT(offset % 8);
244
245 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
246 gpiochip_disable_irq(gc, offset);
247 }
248
stmpe_gpio_irq_unmask(struct irq_data * d)249 static void stmpe_gpio_irq_unmask(struct irq_data *d)
250 {
251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
252 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
253 int offset = d->hwirq;
254 int regoffset = offset / 8;
255 int mask = BIT(offset % 8);
256
257 gpiochip_enable_irq(gc, offset);
258 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
259 }
260
stmpe_dbg_show_one(struct seq_file * s,struct gpio_chip * gc,unsigned offset,unsigned gpio)261 static void stmpe_dbg_show_one(struct seq_file *s,
262 struct gpio_chip *gc,
263 unsigned offset, unsigned gpio)
264 {
265 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
266 struct stmpe *stmpe = stmpe_gpio->stmpe;
267 const char *label = gpiochip_is_requested(gc, offset);
268 bool val = !!stmpe_gpio_get(gc, offset);
269 u8 bank = offset / 8;
270 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
271 u8 mask = BIT(offset % 8);
272 int ret;
273 u8 dir;
274
275 ret = stmpe_reg_read(stmpe, dir_reg);
276 if (ret < 0)
277 return;
278 dir = !!(ret & mask);
279
280 if (dir) {
281 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
282 gpio, label ?: "(none)",
283 val ? "hi" : "lo");
284 } else {
285 u8 edge_det_reg;
286 u8 rise_reg;
287 u8 fall_reg;
288 u8 irqen_reg;
289
290 static const char * const edge_det_values[] = {
291 "edge-inactive",
292 "edge-asserted",
293 "not-supported"
294 };
295 static const char * const rise_values[] = {
296 "no-rising-edge-detection",
297 "rising-edge-detection",
298 "not-supported"
299 };
300 static const char * const fall_values[] = {
301 "no-falling-edge-detection",
302 "falling-edge-detection",
303 "not-supported"
304 };
305 #define NOT_SUPPORTED_IDX 2
306 u8 edge_det = NOT_SUPPORTED_IDX;
307 u8 rise = NOT_SUPPORTED_IDX;
308 u8 fall = NOT_SUPPORTED_IDX;
309 bool irqen;
310
311 switch (stmpe->partnum) {
312 case STMPE610:
313 case STMPE811:
314 case STMPE1601:
315 case STMPE2401:
316 case STMPE2403:
317 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
318 ret = stmpe_reg_read(stmpe, edge_det_reg);
319 if (ret < 0)
320 return;
321 edge_det = !!(ret & mask);
322 fallthrough;
323 case STMPE1801:
324 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
325 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
326
327 ret = stmpe_reg_read(stmpe, rise_reg);
328 if (ret < 0)
329 return;
330 rise = !!(ret & mask);
331 ret = stmpe_reg_read(stmpe, fall_reg);
332 if (ret < 0)
333 return;
334 fall = !!(ret & mask);
335 fallthrough;
336 case STMPE801:
337 case STMPE1600:
338 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
339 break;
340
341 default:
342 return;
343 }
344
345 ret = stmpe_reg_read(stmpe, irqen_reg);
346 if (ret < 0)
347 return;
348 irqen = !!(ret & mask);
349
350 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
351 gpio, label ?: "(none)",
352 val ? "hi" : "lo",
353 edge_det_values[edge_det],
354 irqen ? "IRQ-enabled" : "IRQ-disabled",
355 rise_values[rise],
356 fall_values[fall]);
357 }
358 }
359
stmpe_dbg_show(struct seq_file * s,struct gpio_chip * gc)360 static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
361 {
362 unsigned i;
363 unsigned gpio = gc->base;
364
365 for (i = 0; i < gc->ngpio; i++, gpio++) {
366 stmpe_dbg_show_one(s, gc, i, gpio);
367 seq_putc(s, '\n');
368 }
369 }
370
371 static const struct irq_chip stmpe_gpio_irq_chip = {
372 .name = "stmpe-gpio",
373 .irq_bus_lock = stmpe_gpio_irq_lock,
374 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
375 .irq_mask = stmpe_gpio_irq_mask,
376 .irq_unmask = stmpe_gpio_irq_unmask,
377 .irq_set_type = stmpe_gpio_irq_set_type,
378 .flags = IRQCHIP_IMMUTABLE,
379 GPIOCHIP_IRQ_RESOURCE_HELPERS,
380 };
381
382 #define MAX_GPIOS 24
383
stmpe_gpio_irq(int irq,void * dev)384 static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
385 {
386 struct stmpe_gpio *stmpe_gpio = dev;
387 struct stmpe *stmpe = stmpe_gpio->stmpe;
388 u8 statmsbreg;
389 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
390 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
391 int ret;
392 int i;
393
394 /*
395 * the stmpe_block_read() call below, imposes to set statmsbreg
396 * with the register located at the lowest address. As STMPE1600
397 * variant is the only one which respect registers address's order
398 * (LSB regs located at lowest address than MSB ones) whereas all
399 * the others have a registers layout with MSB located before the
400 * LSB regs.
401 */
402 if (stmpe->partnum == STMPE1600)
403 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
404 else
405 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
406
407 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
408 if (ret < 0)
409 return IRQ_NONE;
410
411 for (i = 0; i < num_banks; i++) {
412 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
413 num_banks - i - 1;
414 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
415 unsigned int stat = status[i];
416
417 stat &= enabled;
418 if (!stat)
419 continue;
420
421 while (stat) {
422 int bit = __ffs(stat);
423 int line = bank * 8 + bit;
424 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
425 line);
426
427 handle_nested_irq(child_irq);
428 stat &= ~BIT(bit);
429 }
430
431 /*
432 * interrupt status register write has no effect on
433 * 801/1801/1600, bits are cleared when read.
434 * Edge detect register is not present on 801/1600/1801
435 */
436 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
437 stmpe->partnum != STMPE1801) {
438 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
439 stmpe_reg_write(stmpe,
440 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
441 status[i]);
442 }
443 }
444
445 return IRQ_HANDLED;
446 }
447
stmpe_init_irq_valid_mask(struct gpio_chip * gc,unsigned long * valid_mask,unsigned int ngpios)448 static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
449 unsigned long *valid_mask,
450 unsigned int ngpios)
451 {
452 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
453 int i;
454
455 if (!stmpe_gpio->norequest_mask)
456 return;
457
458 /* Forbid unused lines to be mapped as IRQs */
459 for (i = 0; i < sizeof(u32); i++) {
460 if (stmpe_gpio->norequest_mask & BIT(i))
461 clear_bit(i, valid_mask);
462 }
463 }
464
stmpe_gpio_disable(void * stmpe)465 static void stmpe_gpio_disable(void *stmpe)
466 {
467 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
468 }
469
stmpe_gpio_probe(struct platform_device * pdev)470 static int stmpe_gpio_probe(struct platform_device *pdev)
471 {
472 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
473 struct device_node *np = pdev->dev.of_node;
474 struct stmpe_gpio *stmpe_gpio;
475 int ret, irq;
476
477 if (stmpe->num_gpios > MAX_GPIOS) {
478 dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
479 return -EINVAL;
480 }
481
482 stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL);
483 if (!stmpe_gpio)
484 return -ENOMEM;
485
486 mutex_init(&stmpe_gpio->irq_lock);
487
488 stmpe_gpio->dev = &pdev->dev;
489 stmpe_gpio->stmpe = stmpe;
490 stmpe_gpio->chip = template_chip;
491 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
492 stmpe_gpio->chip.parent = &pdev->dev;
493 stmpe_gpio->chip.base = -1;
494
495 if (IS_ENABLED(CONFIG_DEBUG_FS))
496 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
497
498 of_property_read_u32(np, "st,norequest-mask",
499 &stmpe_gpio->norequest_mask);
500
501 irq = platform_get_irq(pdev, 0);
502 if (irq < 0)
503 dev_info(&pdev->dev,
504 "device configured in no-irq mode: "
505 "irqs are not available\n");
506
507 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
508 if (ret)
509 return ret;
510
511 ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe);
512 if (ret)
513 return ret;
514
515 if (irq > 0) {
516 struct gpio_irq_chip *girq;
517
518 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
519 stmpe_gpio_irq, IRQF_ONESHOT,
520 "stmpe-gpio", stmpe_gpio);
521 if (ret) {
522 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
523 return ret;
524 }
525
526 girq = &stmpe_gpio->chip.irq;
527 gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
528 /* This will let us handle the parent IRQ in the driver */
529 girq->parent_handler = NULL;
530 girq->num_parents = 0;
531 girq->parents = NULL;
532 girq->default_type = IRQ_TYPE_NONE;
533 girq->handler = handle_simple_irq;
534 girq->threaded = true;
535 girq->init_valid_mask = stmpe_init_irq_valid_mask;
536 }
537
538 return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio);
539 }
540
541 static struct platform_driver stmpe_gpio_driver = {
542 .driver = {
543 .suppress_bind_attrs = true,
544 .name = "stmpe-gpio",
545 },
546 .probe = stmpe_gpio_probe,
547 };
548
stmpe_gpio_init(void)549 static int __init stmpe_gpio_init(void)
550 {
551 return platform_driver_register(&stmpe_gpio_driver);
552 }
553 subsys_initcall(stmpe_gpio_init);
554