1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/delay.h>
13 #include <linux/netdevice.h>
14 #include <linux/interrupt.h>
15 #include <linux/tcp.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/cpu.h>
23 #include <linux/smp.h>
24 #include <linux/pm_qos.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/prefetch.h>
27 #include <linux/suspend.h>
28
29 #include "e1000.h"
30 #define CREATE_TRACE_POINTS
31 #include "e1000e_trace.h"
32
33 char e1000e_driver_name[] = "e1000e";
34
35 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
36 static int debug = -1;
37 module_param(debug, int, 0);
38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
39
40 static const struct e1000_info *e1000_info_tbl[] = {
41 [board_82571] = &e1000_82571_info,
42 [board_82572] = &e1000_82572_info,
43 [board_82573] = &e1000_82573_info,
44 [board_82574] = &e1000_82574_info,
45 [board_82583] = &e1000_82583_info,
46 [board_80003es2lan] = &e1000_es2_info,
47 [board_ich8lan] = &e1000_ich8_info,
48 [board_ich9lan] = &e1000_ich9_info,
49 [board_ich10lan] = &e1000_ich10_info,
50 [board_pchlan] = &e1000_pch_info,
51 [board_pch2lan] = &e1000_pch2_info,
52 [board_pch_lpt] = &e1000_pch_lpt_info,
53 [board_pch_spt] = &e1000_pch_spt_info,
54 [board_pch_cnp] = &e1000_pch_cnp_info,
55 [board_pch_tgp] = &e1000_pch_tgp_info,
56 [board_pch_adp] = &e1000_pch_adp_info,
57 [board_pch_mtp] = &e1000_pch_mtp_info,
58 };
59
60 struct e1000_reg_info {
61 u32 ofs;
62 char *name;
63 };
64
65 static const struct e1000_reg_info e1000_reg_info_tbl[] = {
66 /* General Registers */
67 {E1000_CTRL, "CTRL"},
68 {E1000_STATUS, "STATUS"},
69 {E1000_CTRL_EXT, "CTRL_EXT"},
70
71 /* Interrupt Registers */
72 {E1000_ICR, "ICR"},
73
74 /* Rx Registers */
75 {E1000_RCTL, "RCTL"},
76 {E1000_RDLEN(0), "RDLEN"},
77 {E1000_RDH(0), "RDH"},
78 {E1000_RDT(0), "RDT"},
79 {E1000_RDTR, "RDTR"},
80 {E1000_RXDCTL(0), "RXDCTL"},
81 {E1000_ERT, "ERT"},
82 {E1000_RDBAL(0), "RDBAL"},
83 {E1000_RDBAH(0), "RDBAH"},
84 {E1000_RDFH, "RDFH"},
85 {E1000_RDFT, "RDFT"},
86 {E1000_RDFHS, "RDFHS"},
87 {E1000_RDFTS, "RDFTS"},
88 {E1000_RDFPC, "RDFPC"},
89
90 /* Tx Registers */
91 {E1000_TCTL, "TCTL"},
92 {E1000_TDBAL(0), "TDBAL"},
93 {E1000_TDBAH(0), "TDBAH"},
94 {E1000_TDLEN(0), "TDLEN"},
95 {E1000_TDH(0), "TDH"},
96 {E1000_TDT(0), "TDT"},
97 {E1000_TIDV, "TIDV"},
98 {E1000_TXDCTL(0), "TXDCTL"},
99 {E1000_TADV, "TADV"},
100 {E1000_TARC(0), "TARC"},
101 {E1000_TDFH, "TDFH"},
102 {E1000_TDFT, "TDFT"},
103 {E1000_TDFHS, "TDFHS"},
104 {E1000_TDFTS, "TDFTS"},
105 {E1000_TDFPC, "TDFPC"},
106
107 /* List Terminator */
108 {0, NULL}
109 };
110
111 /**
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
113 * @hw: pointer to the HW structure
114 *
115 * When updating the MAC CSR registers, the Manageability Engine (ME) could
116 * be accessing the registers at the same time. Normally, this is handled in
117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
118 * accesses later than it should which could result in the register to have
119 * an incorrect value. Workaround this by checking the FWSM register which
120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
121 * and try again a number of times.
122 **/
__ew32_prepare(struct e1000_hw * hw)123 static void __ew32_prepare(struct e1000_hw *hw)
124 {
125 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
126
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
128 udelay(50);
129 }
130
__ew32(struct e1000_hw * hw,unsigned long reg,u32 val)131 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
132 {
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
134 __ew32_prepare(hw);
135
136 writel(val, hw->hw_addr + reg);
137 }
138
139 /**
140 * e1000_regdump - register printout routine
141 * @hw: pointer to the HW structure
142 * @reginfo: pointer to the register info table
143 **/
e1000_regdump(struct e1000_hw * hw,struct e1000_reg_info * reginfo)144 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
145 {
146 int n = 0;
147 char rname[16];
148 u32 regs[8];
149
150 switch (reginfo->ofs) {
151 case E1000_RXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_RXDCTL(n));
154 break;
155 case E1000_TXDCTL(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TXDCTL(n));
158 break;
159 case E1000_TARC(0):
160 for (n = 0; n < 2; n++)
161 regs[n] = __er32(hw, E1000_TARC(n));
162 break;
163 default:
164 pr_info("%-15s %08x\n",
165 reginfo->name, __er32(hw, reginfo->ofs));
166 return;
167 }
168
169 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
170 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
171 }
172
e1000e_dump_ps_pages(struct e1000_adapter * adapter,struct e1000_buffer * bi)173 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
174 struct e1000_buffer *bi)
175 {
176 int i;
177 struct e1000_ps_page *ps_page;
178
179 for (i = 0; i < adapter->rx_ps_pages; i++) {
180 ps_page = &bi->ps_pages[i];
181
182 if (ps_page->page) {
183 pr_info("packet dump for ps_page %d:\n", i);
184 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
185 16, 1, page_address(ps_page->page),
186 PAGE_SIZE, true);
187 }
188 }
189 }
190
191 /**
192 * e1000e_dump - Print registers, Tx-ring and Rx-ring
193 * @adapter: board private structure
194 **/
e1000e_dump(struct e1000_adapter * adapter)195 static void e1000e_dump(struct e1000_adapter *adapter)
196 {
197 struct net_device *netdev = adapter->netdev;
198 struct e1000_hw *hw = &adapter->hw;
199 struct e1000_reg_info *reginfo;
200 struct e1000_ring *tx_ring = adapter->tx_ring;
201 struct e1000_tx_desc *tx_desc;
202 struct my_u0 {
203 __le64 a;
204 __le64 b;
205 } *u0;
206 struct e1000_buffer *buffer_info;
207 struct e1000_ring *rx_ring = adapter->rx_ring;
208 union e1000_rx_desc_packet_split *rx_desc_ps;
209 union e1000_rx_desc_extended *rx_desc;
210 struct my_u1 {
211 __le64 a;
212 __le64 b;
213 __le64 c;
214 __le64 d;
215 } *u1;
216 u32 staterr;
217 int i = 0;
218
219 if (!netif_msg_hw(adapter))
220 return;
221
222 /* Print netdevice Info */
223 if (netdev) {
224 dev_info(&adapter->pdev->dev, "Net device Info\n");
225 pr_info("Device Name state trans_start\n");
226 pr_info("%-15s %016lX %016lX\n", netdev->name,
227 netdev->state, dev_trans_start(netdev));
228 }
229
230 /* Print Registers */
231 dev_info(&adapter->pdev->dev, "Register Dump\n");
232 pr_info(" Register Name Value\n");
233 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
234 reginfo->name; reginfo++) {
235 e1000_regdump(hw, reginfo);
236 }
237
238 /* Print Tx Ring Summary */
239 if (!netdev || !netif_running(netdev))
240 return;
241
242 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
243 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
244 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
245 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
246 0, tx_ring->next_to_use, tx_ring->next_to_clean,
247 (unsigned long long)buffer_info->dma,
248 buffer_info->length,
249 buffer_info->next_to_watch,
250 (unsigned long long)buffer_info->time_stamp);
251
252 /* Print Tx Ring */
253 if (!netif_msg_tx_done(adapter))
254 goto rx_ring_summary;
255
256 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
257
258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
259 *
260 * Legacy Transmit Descriptor
261 * +--------------------------------------------------------------+
262 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
263 * +--------------------------------------------------------------+
264 * 8 | Special | CSS | Status | CMD | CSO | Length |
265 * +--------------------------------------------------------------+
266 * 63 48 47 36 35 32 31 24 23 16 15 0
267 *
268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
269 * 63 48 47 40 39 32 31 16 15 8 7 0
270 * +----------------------------------------------------------------+
271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
272 * +----------------------------------------------------------------+
273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
274 * +----------------------------------------------------------------+
275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
276 *
277 * Extended Data Descriptor (DTYP=0x1)
278 * +----------------------------------------------------------------+
279 * 0 | Buffer Address [63:0] |
280 * +----------------------------------------------------------------+
281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
282 * +----------------------------------------------------------------+
283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
284 */
285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
288 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
289 const char *next_desc;
290 tx_desc = E1000_TX_DESC(*tx_ring, i);
291 buffer_info = &tx_ring->buffer_info[i];
292 u0 = (struct my_u0 *)tx_desc;
293 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
294 next_desc = " NTC/U";
295 else if (i == tx_ring->next_to_use)
296 next_desc = " NTU";
297 else if (i == tx_ring->next_to_clean)
298 next_desc = " NTC";
299 else
300 next_desc = "";
301 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
302 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
303 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
304 i,
305 (unsigned long long)le64_to_cpu(u0->a),
306 (unsigned long long)le64_to_cpu(u0->b),
307 (unsigned long long)buffer_info->dma,
308 buffer_info->length, buffer_info->next_to_watch,
309 (unsigned long long)buffer_info->time_stamp,
310 buffer_info->skb, next_desc);
311
312 if (netif_msg_pktdata(adapter) && buffer_info->skb)
313 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
314 16, 1, buffer_info->skb->data,
315 buffer_info->skb->len, true);
316 }
317
318 /* Print Rx Ring Summary */
319 rx_ring_summary:
320 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
321 pr_info("Queue [NTU] [NTC]\n");
322 pr_info(" %5d %5X %5X\n",
323 0, rx_ring->next_to_use, rx_ring->next_to_clean);
324
325 /* Print Rx Ring */
326 if (!netif_msg_rx_status(adapter))
327 return;
328
329 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
330 switch (adapter->rx_ps_pages) {
331 case 1:
332 case 2:
333 case 3:
334 /* [Extended] Packet Split Receive Descriptor Format
335 *
336 * +-----------------------------------------------------+
337 * 0 | Buffer Address 0 [63:0] |
338 * +-----------------------------------------------------+
339 * 8 | Buffer Address 1 [63:0] |
340 * +-----------------------------------------------------+
341 * 16 | Buffer Address 2 [63:0] |
342 * +-----------------------------------------------------+
343 * 24 | Buffer Address 3 [63:0] |
344 * +-----------------------------------------------------+
345 */
346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
347 /* [Extended] Receive Descriptor (Write-Back) Format
348 *
349 * 63 48 47 32 31 13 12 8 7 4 3 0
350 * +------------------------------------------------------+
351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
352 * | Checksum | Ident | | Queue | | Type |
353 * +------------------------------------------------------+
354 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
355 * +------------------------------------------------------+
356 * 63 48 47 32 31 20 19 0
357 */
358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
359 for (i = 0; i < rx_ring->count; i++) {
360 const char *next_desc;
361 buffer_info = &rx_ring->buffer_info[i];
362 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
363 u1 = (struct my_u1 *)rx_desc_ps;
364 staterr =
365 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
366
367 if (i == rx_ring->next_to_use)
368 next_desc = " NTU";
369 else if (i == rx_ring->next_to_clean)
370 next_desc = " NTC";
371 else
372 next_desc = "";
373
374 if (staterr & E1000_RXD_STAT_DD) {
375 /* Descriptor Done */
376 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
377 "RWB", i,
378 (unsigned long long)le64_to_cpu(u1->a),
379 (unsigned long long)le64_to_cpu(u1->b),
380 (unsigned long long)le64_to_cpu(u1->c),
381 (unsigned long long)le64_to_cpu(u1->d),
382 buffer_info->skb, next_desc);
383 } else {
384 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
385 "R ", i,
386 (unsigned long long)le64_to_cpu(u1->a),
387 (unsigned long long)le64_to_cpu(u1->b),
388 (unsigned long long)le64_to_cpu(u1->c),
389 (unsigned long long)le64_to_cpu(u1->d),
390 (unsigned long long)buffer_info->dma,
391 buffer_info->skb, next_desc);
392
393 if (netif_msg_pktdata(adapter))
394 e1000e_dump_ps_pages(adapter,
395 buffer_info);
396 }
397 }
398 break;
399 default:
400 case 0:
401 /* Extended Receive Descriptor (Read) Format
402 *
403 * +-----------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +-----------------------------------------------------+
406 * 8 | Reserved |
407 * +-----------------------------------------------------+
408 */
409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
410 /* Extended Receive Descriptor (Write-Back) Format
411 *
412 * 63 48 47 32 31 24 23 4 3 0
413 * +------------------------------------------------------+
414 * | RSS Hash | | | |
415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
416 * | Packet | IP | | | Type |
417 * | Checksum | Ident | | | |
418 * +------------------------------------------------------+
419 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
420 * +------------------------------------------------------+
421 * 63 48 47 32 31 20 19 0
422 */
423 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
424
425 for (i = 0; i < rx_ring->count; i++) {
426 const char *next_desc;
427
428 buffer_info = &rx_ring->buffer_info[i];
429 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
430 u1 = (struct my_u1 *)rx_desc;
431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
432
433 if (i == rx_ring->next_to_use)
434 next_desc = " NTU";
435 else if (i == rx_ring->next_to_clean)
436 next_desc = " NTC";
437 else
438 next_desc = "";
439
440 if (staterr & E1000_RXD_STAT_DD) {
441 /* Descriptor Done */
442 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
443 "RWB", i,
444 (unsigned long long)le64_to_cpu(u1->a),
445 (unsigned long long)le64_to_cpu(u1->b),
446 buffer_info->skb, next_desc);
447 } else {
448 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
449 "R ", i,
450 (unsigned long long)le64_to_cpu(u1->a),
451 (unsigned long long)le64_to_cpu(u1->b),
452 (unsigned long long)buffer_info->dma,
453 buffer_info->skb, next_desc);
454
455 if (netif_msg_pktdata(adapter) &&
456 buffer_info->skb)
457 print_hex_dump(KERN_INFO, "",
458 DUMP_PREFIX_ADDRESS, 16,
459 1,
460 buffer_info->skb->data,
461 adapter->rx_buffer_len,
462 true);
463 }
464 }
465 }
466 }
467
468 /**
469 * e1000_desc_unused - calculate if we have unused descriptors
470 * @ring: pointer to ring struct to perform calculation on
471 **/
e1000_desc_unused(struct e1000_ring * ring)472 static int e1000_desc_unused(struct e1000_ring *ring)
473 {
474 if (ring->next_to_clean > ring->next_to_use)
475 return ring->next_to_clean - ring->next_to_use - 1;
476
477 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478 }
479
480 /**
481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482 * @adapter: board private structure
483 * @hwtstamps: time stamp structure to update
484 * @systim: unsigned 64bit system time value.
485 *
486 * Convert the system time value stored in the RX/TXSTMP registers into a
487 * hwtstamp which can be used by the upper level time stamping functions.
488 *
489 * The 'systim_lock' spinlock is used to protect the consistency of the
490 * system time value. This is needed because reading the 64 bit time
491 * value involves reading two 32 bit registers. The first read latches the
492 * value.
493 **/
e1000e_systim_to_hwtstamp(struct e1000_adapter * adapter,struct skb_shared_hwtstamps * hwtstamps,u64 systim)494 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 struct skb_shared_hwtstamps *hwtstamps,
496 u64 systim)
497 {
498 u64 ns;
499 unsigned long flags;
500
501 spin_lock_irqsave(&adapter->systim_lock, flags);
502 ns = timecounter_cyc2time(&adapter->tc, systim);
503 spin_unlock_irqrestore(&adapter->systim_lock, flags);
504
505 memset(hwtstamps, 0, sizeof(*hwtstamps));
506 hwtstamps->hwtstamp = ns_to_ktime(ns);
507 }
508
509 /**
510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511 * @adapter: board private structure
512 * @status: descriptor extended error and status field
513 * @skb: particular skb to include time stamp
514 *
515 * If the time stamp is valid, convert it into the timecounter ns value
516 * and store that result into the shhwtstamps structure which is passed
517 * up the network stack.
518 **/
e1000e_rx_hwtstamp(struct e1000_adapter * adapter,u32 status,struct sk_buff * skb)519 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 struct sk_buff *skb)
521 {
522 struct e1000_hw *hw = &adapter->hw;
523 u64 rxstmp;
524
525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 !(status & E1000_RXDEXT_STATERR_TST) ||
527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 return;
529
530 /* The Rx time stamp registers contain the time stamp. No other
531 * received packet will be time stamped until the Rx time stamp
532 * registers are read. Because only one packet can be time stamped
533 * at a time, the register values must belong to this packet and
534 * therefore none of the other additional attributes need to be
535 * compared.
536 */
537 rxstmp = (u64)er32(RXSTMPL);
538 rxstmp |= (u64)er32(RXSTMPH) << 32;
539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
540
541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542 }
543
544 /**
545 * e1000_receive_skb - helper function to handle Rx indications
546 * @adapter: board private structure
547 * @netdev: pointer to netdev struct
548 * @staterr: descriptor extended error and status field as written by hardware
549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
550 * @skb: pointer to sk_buff to be indicated to stack
551 **/
e1000_receive_skb(struct e1000_adapter * adapter,struct net_device * netdev,struct sk_buff * skb,u32 staterr,__le16 vlan)552 static void e1000_receive_skb(struct e1000_adapter *adapter,
553 struct net_device *netdev, struct sk_buff *skb,
554 u32 staterr, __le16 vlan)
555 {
556 u16 tag = le16_to_cpu(vlan);
557
558 e1000e_rx_hwtstamp(adapter, staterr, skb);
559
560 skb->protocol = eth_type_trans(skb, netdev);
561
562 if (staterr & E1000_RXD_STAT_VP)
563 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
564
565 napi_gro_receive(&adapter->napi, skb);
566 }
567
568 /**
569 * e1000_rx_checksum - Receive Checksum Offload
570 * @adapter: board private structure
571 * @status_err: receive descriptor status and error fields
572 * @skb: socket buffer with received data
573 **/
e1000_rx_checksum(struct e1000_adapter * adapter,u32 status_err,struct sk_buff * skb)574 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
575 struct sk_buff *skb)
576 {
577 u16 status = (u16)status_err;
578 u8 errors = (u8)(status_err >> 24);
579
580 skb_checksum_none_assert(skb);
581
582 /* Rx checksum disabled */
583 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 return;
585
586 /* Ignore Checksum bit is set */
587 if (status & E1000_RXD_STAT_IXSM)
588 return;
589
590 /* TCP/UDP checksum error bit or IP checksum error bit is set */
591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
592 /* let the stack verify checksum errors */
593 adapter->hw_csum_err++;
594 return;
595 }
596
597 /* TCP/UDP Checksum has not been calculated */
598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 return;
600
601 /* It must be a TCP or UDP packet with a valid checksum */
602 skb->ip_summed = CHECKSUM_UNNECESSARY;
603 adapter->hw_csum_good++;
604 }
605
e1000e_update_rdt_wa(struct e1000_ring * rx_ring,unsigned int i)606 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
607 {
608 struct e1000_adapter *adapter = rx_ring->adapter;
609 struct e1000_hw *hw = &adapter->hw;
610
611 __ew32_prepare(hw);
612 writel(i, rx_ring->tail);
613
614 if (unlikely(i != readl(rx_ring->tail))) {
615 u32 rctl = er32(RCTL);
616
617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 e_err("ME firmware caused invalid RDT - resetting\n");
619 schedule_work(&adapter->reset_task);
620 }
621 }
622
e1000e_update_tdt_wa(struct e1000_ring * tx_ring,unsigned int i)623 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
624 {
625 struct e1000_adapter *adapter = tx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627
628 __ew32_prepare(hw);
629 writel(i, tx_ring->tail);
630
631 if (unlikely(i != readl(tx_ring->tail))) {
632 u32 tctl = er32(TCTL);
633
634 ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 e_err("ME firmware caused invalid TDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638 }
639
640 /**
641 * e1000_alloc_rx_buffers - Replace used receive buffers
642 * @rx_ring: Rx descriptor ring
643 * @cleaned_count: number to reallocate
644 * @gfp: flags for allocation
645 **/
e1000_alloc_rx_buffers(struct e1000_ring * rx_ring,int cleaned_count,gfp_t gfp)646 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
647 int cleaned_count, gfp_t gfp)
648 {
649 struct e1000_adapter *adapter = rx_ring->adapter;
650 struct net_device *netdev = adapter->netdev;
651 struct pci_dev *pdev = adapter->pdev;
652 union e1000_rx_desc_extended *rx_desc;
653 struct e1000_buffer *buffer_info;
654 struct sk_buff *skb;
655 unsigned int i;
656 unsigned int bufsz = adapter->rx_buffer_len;
657
658 i = rx_ring->next_to_use;
659 buffer_info = &rx_ring->buffer_info[i];
660
661 while (cleaned_count--) {
662 skb = buffer_info->skb;
663 if (skb) {
664 skb_trim(skb, 0);
665 goto map_skb;
666 }
667
668 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
669 if (!skb) {
670 /* Better luck next round */
671 adapter->alloc_rx_buff_failed++;
672 break;
673 }
674
675 buffer_info->skb = skb;
676 map_skb:
677 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
678 adapter->rx_buffer_len,
679 DMA_FROM_DEVICE);
680 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
681 dev_err(&pdev->dev, "Rx DMA map failed\n");
682 adapter->rx_dma_failed++;
683 break;
684 }
685
686 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
687 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
688
689 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
690 /* Force memory writes to complete before letting h/w
691 * know there are new descriptors to fetch. (Only
692 * applicable for weak-ordered memory model archs,
693 * such as IA-64).
694 */
695 wmb();
696 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
697 e1000e_update_rdt_wa(rx_ring, i);
698 else
699 writel(i, rx_ring->tail);
700 }
701 i++;
702 if (i == rx_ring->count)
703 i = 0;
704 buffer_info = &rx_ring->buffer_info[i];
705 }
706
707 rx_ring->next_to_use = i;
708 }
709
710 /**
711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
712 * @rx_ring: Rx descriptor ring
713 * @cleaned_count: number to reallocate
714 * @gfp: flags for allocation
715 **/
e1000_alloc_rx_buffers_ps(struct e1000_ring * rx_ring,int cleaned_count,gfp_t gfp)716 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
717 int cleaned_count, gfp_t gfp)
718 {
719 struct e1000_adapter *adapter = rx_ring->adapter;
720 struct net_device *netdev = adapter->netdev;
721 struct pci_dev *pdev = adapter->pdev;
722 union e1000_rx_desc_packet_split *rx_desc;
723 struct e1000_buffer *buffer_info;
724 struct e1000_ps_page *ps_page;
725 struct sk_buff *skb;
726 unsigned int i, j;
727
728 i = rx_ring->next_to_use;
729 buffer_info = &rx_ring->buffer_info[i];
730
731 while (cleaned_count--) {
732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
733
734 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
735 ps_page = &buffer_info->ps_pages[j];
736 if (j >= adapter->rx_ps_pages) {
737 /* all unused desc entries get hw null ptr */
738 rx_desc->read.buffer_addr[j + 1] =
739 ~cpu_to_le64(0);
740 continue;
741 }
742 if (!ps_page->page) {
743 ps_page->page = alloc_page(gfp);
744 if (!ps_page->page) {
745 adapter->alloc_rx_buff_failed++;
746 goto no_buffers;
747 }
748 ps_page->dma = dma_map_page(&pdev->dev,
749 ps_page->page,
750 0, PAGE_SIZE,
751 DMA_FROM_DEVICE);
752 if (dma_mapping_error(&pdev->dev,
753 ps_page->dma)) {
754 dev_err(&adapter->pdev->dev,
755 "Rx DMA page map failed\n");
756 adapter->rx_dma_failed++;
757 goto no_buffers;
758 }
759 }
760 /* Refresh the desc even if buffer_addrs
761 * didn't change because each write-back
762 * erases this info.
763 */
764 rx_desc->read.buffer_addr[j + 1] =
765 cpu_to_le64(ps_page->dma);
766 }
767
768 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
769 gfp);
770
771 if (!skb) {
772 adapter->alloc_rx_buff_failed++;
773 break;
774 }
775
776 buffer_info->skb = skb;
777 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
778 adapter->rx_ps_bsize0,
779 DMA_FROM_DEVICE);
780 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
781 dev_err(&pdev->dev, "Rx DMA map failed\n");
782 adapter->rx_dma_failed++;
783 /* cleanup skb */
784 dev_kfree_skb_any(skb);
785 buffer_info->skb = NULL;
786 break;
787 }
788
789 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
790
791 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
792 /* Force memory writes to complete before letting h/w
793 * know there are new descriptors to fetch. (Only
794 * applicable for weak-ordered memory model archs,
795 * such as IA-64).
796 */
797 wmb();
798 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
799 e1000e_update_rdt_wa(rx_ring, i << 1);
800 else
801 writel(i << 1, rx_ring->tail);
802 }
803
804 i++;
805 if (i == rx_ring->count)
806 i = 0;
807 buffer_info = &rx_ring->buffer_info[i];
808 }
809
810 no_buffers:
811 rx_ring->next_to_use = i;
812 }
813
814 /**
815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
816 * @rx_ring: Rx descriptor ring
817 * @cleaned_count: number of buffers to allocate this pass
818 * @gfp: flags for allocation
819 **/
820
e1000_alloc_jumbo_rx_buffers(struct e1000_ring * rx_ring,int cleaned_count,gfp_t gfp)821 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
822 int cleaned_count, gfp_t gfp)
823 {
824 struct e1000_adapter *adapter = rx_ring->adapter;
825 struct net_device *netdev = adapter->netdev;
826 struct pci_dev *pdev = adapter->pdev;
827 union e1000_rx_desc_extended *rx_desc;
828 struct e1000_buffer *buffer_info;
829 struct sk_buff *skb;
830 unsigned int i;
831 unsigned int bufsz = 256 - 16; /* for skb_reserve */
832
833 i = rx_ring->next_to_use;
834 buffer_info = &rx_ring->buffer_info[i];
835
836 while (cleaned_count--) {
837 skb = buffer_info->skb;
838 if (skb) {
839 skb_trim(skb, 0);
840 goto check_page;
841 }
842
843 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
844 if (unlikely(!skb)) {
845 /* Better luck next round */
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849
850 buffer_info->skb = skb;
851 check_page:
852 /* allocate a new page if necessary */
853 if (!buffer_info->page) {
854 buffer_info->page = alloc_page(gfp);
855 if (unlikely(!buffer_info->page)) {
856 adapter->alloc_rx_buff_failed++;
857 break;
858 }
859 }
860
861 if (!buffer_info->dma) {
862 buffer_info->dma = dma_map_page(&pdev->dev,
863 buffer_info->page, 0,
864 PAGE_SIZE,
865 DMA_FROM_DEVICE);
866 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
867 adapter->alloc_rx_buff_failed++;
868 break;
869 }
870 }
871
872 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
873 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
874
875 if (unlikely(++i == rx_ring->count))
876 i = 0;
877 buffer_info = &rx_ring->buffer_info[i];
878 }
879
880 if (likely(rx_ring->next_to_use != i)) {
881 rx_ring->next_to_use = i;
882 if (unlikely(i-- == 0))
883 i = (rx_ring->count - 1);
884
885 /* Force memory writes to complete before letting h/w
886 * know there are new descriptors to fetch. (Only
887 * applicable for weak-ordered memory model archs,
888 * such as IA-64).
889 */
890 wmb();
891 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
892 e1000e_update_rdt_wa(rx_ring, i);
893 else
894 writel(i, rx_ring->tail);
895 }
896 }
897
e1000_rx_hash(struct net_device * netdev,__le32 rss,struct sk_buff * skb)898 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
899 struct sk_buff *skb)
900 {
901 if (netdev->features & NETIF_F_RXHASH)
902 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
903 }
904
905 /**
906 * e1000_clean_rx_irq - Send received data up the network stack
907 * @rx_ring: Rx descriptor ring
908 * @work_done: output parameter for indicating completed work
909 * @work_to_do: how many packets we can clean
910 *
911 * the return value indicates whether actual cleaning was done, there
912 * is no guarantee that everything was cleaned
913 **/
e1000_clean_rx_irq(struct e1000_ring * rx_ring,int * work_done,int work_to_do)914 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
915 int work_to_do)
916 {
917 struct e1000_adapter *adapter = rx_ring->adapter;
918 struct net_device *netdev = adapter->netdev;
919 struct pci_dev *pdev = adapter->pdev;
920 struct e1000_hw *hw = &adapter->hw;
921 union e1000_rx_desc_extended *rx_desc, *next_rxd;
922 struct e1000_buffer *buffer_info, *next_buffer;
923 u32 length, staterr;
924 unsigned int i;
925 int cleaned_count = 0;
926 bool cleaned = false;
927 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
928
929 i = rx_ring->next_to_clean;
930 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
931 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
932 buffer_info = &rx_ring->buffer_info[i];
933
934 while (staterr & E1000_RXD_STAT_DD) {
935 struct sk_buff *skb;
936
937 if (*work_done >= work_to_do)
938 break;
939 (*work_done)++;
940 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
941
942 skb = buffer_info->skb;
943 buffer_info->skb = NULL;
944
945 prefetch(skb->data - NET_IP_ALIGN);
946
947 i++;
948 if (i == rx_ring->count)
949 i = 0;
950 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
951 prefetch(next_rxd);
952
953 next_buffer = &rx_ring->buffer_info[i];
954
955 cleaned = true;
956 cleaned_count++;
957 dma_unmap_single(&pdev->dev, buffer_info->dma,
958 adapter->rx_buffer_len, DMA_FROM_DEVICE);
959 buffer_info->dma = 0;
960
961 length = le16_to_cpu(rx_desc->wb.upper.length);
962
963 /* !EOP means multiple descriptors were used to store a single
964 * packet, if that's the case we need to toss it. In fact, we
965 * need to toss every packet with the EOP bit clear and the
966 * next frame that _does_ have the EOP bit set, as it is by
967 * definition only a frame fragment
968 */
969 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
970 adapter->flags2 |= FLAG2_IS_DISCARDING;
971
972 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
973 /* All receives must fit into a single buffer */
974 e_dbg("Receive packet consumed multiple buffers\n");
975 /* recycle */
976 buffer_info->skb = skb;
977 if (staterr & E1000_RXD_STAT_EOP)
978 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
979 goto next_desc;
980 }
981
982 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
983 !(netdev->features & NETIF_F_RXALL))) {
984 /* recycle */
985 buffer_info->skb = skb;
986 goto next_desc;
987 }
988
989 /* adjust length to remove Ethernet CRC */
990 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
991 /* If configured to store CRC, don't subtract FCS,
992 * but keep the FCS bytes out of the total_rx_bytes
993 * counter
994 */
995 if (netdev->features & NETIF_F_RXFCS)
996 total_rx_bytes -= 4;
997 else
998 length -= 4;
999 }
1000
1001 total_rx_bytes += length;
1002 total_rx_packets++;
1003
1004 /* code added for copybreak, this should improve
1005 * performance for small packets with large amounts
1006 * of reassembly being done in the stack
1007 */
1008 if (length < copybreak) {
1009 struct sk_buff *new_skb =
1010 napi_alloc_skb(&adapter->napi, length);
1011 if (new_skb) {
1012 skb_copy_to_linear_data_offset(new_skb,
1013 -NET_IP_ALIGN,
1014 (skb->data -
1015 NET_IP_ALIGN),
1016 (length +
1017 NET_IP_ALIGN));
1018 /* save the skb in buffer_info as good */
1019 buffer_info->skb = skb;
1020 skb = new_skb;
1021 }
1022 /* else just continue with the old one */
1023 }
1024 /* end copybreak code */
1025 skb_put(skb, length);
1026
1027 /* Receive Checksum Offload */
1028 e1000_rx_checksum(adapter, staterr, skb);
1029
1030 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1031
1032 e1000_receive_skb(adapter, netdev, skb, staterr,
1033 rx_desc->wb.upper.vlan);
1034
1035 next_desc:
1036 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1037
1038 /* return some buffers to hardware, one at a time is too slow */
1039 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1040 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1041 GFP_ATOMIC);
1042 cleaned_count = 0;
1043 }
1044
1045 /* use prefetched values */
1046 rx_desc = next_rxd;
1047 buffer_info = next_buffer;
1048
1049 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1050 }
1051 rx_ring->next_to_clean = i;
1052
1053 cleaned_count = e1000_desc_unused(rx_ring);
1054 if (cleaned_count)
1055 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1056
1057 adapter->total_rx_bytes += total_rx_bytes;
1058 adapter->total_rx_packets += total_rx_packets;
1059 return cleaned;
1060 }
1061
e1000_put_txbuf(struct e1000_ring * tx_ring,struct e1000_buffer * buffer_info,bool drop)1062 static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1063 struct e1000_buffer *buffer_info,
1064 bool drop)
1065 {
1066 struct e1000_adapter *adapter = tx_ring->adapter;
1067
1068 if (buffer_info->dma) {
1069 if (buffer_info->mapped_as_page)
1070 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1071 buffer_info->length, DMA_TO_DEVICE);
1072 else
1073 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1074 buffer_info->length, DMA_TO_DEVICE);
1075 buffer_info->dma = 0;
1076 }
1077 if (buffer_info->skb) {
1078 if (drop)
1079 dev_kfree_skb_any(buffer_info->skb);
1080 else
1081 dev_consume_skb_any(buffer_info->skb);
1082 buffer_info->skb = NULL;
1083 }
1084 buffer_info->time_stamp = 0;
1085 }
1086
e1000_print_hw_hang(struct work_struct * work)1087 static void e1000_print_hw_hang(struct work_struct *work)
1088 {
1089 struct e1000_adapter *adapter = container_of(work,
1090 struct e1000_adapter,
1091 print_hang_task);
1092 struct net_device *netdev = adapter->netdev;
1093 struct e1000_ring *tx_ring = adapter->tx_ring;
1094 unsigned int i = tx_ring->next_to_clean;
1095 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1096 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1097 struct e1000_hw *hw = &adapter->hw;
1098 u16 phy_status, phy_1000t_status, phy_ext_status;
1099 u16 pci_status;
1100
1101 if (test_bit(__E1000_DOWN, &adapter->state))
1102 return;
1103
1104 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1105 /* May be block on write-back, flush and detect again
1106 * flush pending descriptor writebacks to memory
1107 */
1108 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1109 /* execute the writes immediately */
1110 e1e_flush();
1111 /* Due to rare timing issues, write to TIDV again to ensure
1112 * the write is successful
1113 */
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115 /* execute the writes immediately */
1116 e1e_flush();
1117 adapter->tx_hang_recheck = true;
1118 return;
1119 }
1120 adapter->tx_hang_recheck = false;
1121
1122 if (er32(TDH(0)) == er32(TDT(0))) {
1123 e_dbg("false hang detected, ignoring\n");
1124 return;
1125 }
1126
1127 /* Real hang detected */
1128 netif_stop_queue(netdev);
1129
1130 e1e_rphy(hw, MII_BMSR, &phy_status);
1131 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1132 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1133
1134 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1135
1136 /* detected Hardware unit hang */
1137 e_err("Detected Hardware Unit Hang:\n"
1138 " TDH <%x>\n"
1139 " TDT <%x>\n"
1140 " next_to_use <%x>\n"
1141 " next_to_clean <%x>\n"
1142 "buffer_info[next_to_clean]:\n"
1143 " time_stamp <%lx>\n"
1144 " next_to_watch <%x>\n"
1145 " jiffies <%lx>\n"
1146 " next_to_watch.status <%x>\n"
1147 "MAC Status <%x>\n"
1148 "PHY Status <%x>\n"
1149 "PHY 1000BASE-T Status <%x>\n"
1150 "PHY Extended Status <%x>\n"
1151 "PCI Status <%x>\n",
1152 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1153 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1154 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1155 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1156
1157 e1000e_dump(adapter);
1158
1159 /* Suggest workaround for known h/w issue */
1160 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1161 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1162 }
1163
1164 /**
1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1166 * @work: pointer to work struct
1167 *
1168 * This work function polls the TSYNCTXCTL valid bit to determine when a
1169 * timestamp has been taken for the current stored skb. The timestamp must
1170 * be for this skb because only one such packet is allowed in the queue.
1171 */
e1000e_tx_hwtstamp_work(struct work_struct * work)1172 static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1173 {
1174 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1175 tx_hwtstamp_work);
1176 struct e1000_hw *hw = &adapter->hw;
1177
1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1179 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1180 struct skb_shared_hwtstamps shhwtstamps;
1181 u64 txstmp;
1182
1183 txstmp = er32(TXSTMPL);
1184 txstmp |= (u64)er32(TXSTMPH) << 32;
1185
1186 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1187
1188 /* Clear the global tx_hwtstamp_skb pointer and force writes
1189 * prior to notifying the stack of a Tx timestamp.
1190 */
1191 adapter->tx_hwtstamp_skb = NULL;
1192 wmb(); /* force write prior to skb_tstamp_tx */
1193
1194 skb_tstamp_tx(skb, &shhwtstamps);
1195 dev_consume_skb_any(skb);
1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
1201 e_warn("clearing Tx timestamp hang\n");
1202 } else {
1203 /* reschedule to check later */
1204 schedule_work(&adapter->tx_hwtstamp_work);
1205 }
1206 }
1207
1208 /**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1210 * @tx_ring: Tx descriptor ring
1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
e1000_clean_tx_irq(struct e1000_ring * tx_ring)1215 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1216 {
1217 struct e1000_adapter *adapter = tx_ring->adapter;
1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1225 unsigned int bytes_compl = 0, pkts_compl = 0;
1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
1233 bool cleaned = false;
1234
1235 dma_rmb(); /* read buffer_info after eop_desc */
1236 for (; !cleaned; count++) {
1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
1248 }
1249
1250 e1000_put_txbuf(tx_ring, buffer_info, false);
1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
1258 if (i == tx_ring->next_to_use)
1259 break;
1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1267
1268 #define TX_WAKE_THRESHOLD 32
1269 if (count && netif_carrier_ok(netdev) &&
1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1274 smp_mb();
1275
1276 if (netif_queue_stopped(netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
1284 /* Detect a transmit hang in hardware, this serializes the
1285 * check with the clearing of time_stamp and movement of i
1286 */
1287 adapter->detect_tx_hung = false;
1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1290 + (adapter->tx_timeout_factor * HZ)) &&
1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
1292 schedule_work(&adapter->print_hang_task);
1293 else
1294 adapter->tx_hang_recheck = false;
1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
1298 return count < tx_ring->count;
1299 }
1300
1301 /**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1303 * @rx_ring: Rx descriptor ring
1304 * @work_done: output parameter for indicating completed work
1305 * @work_to_do: how many packets we can clean
1306 *
1307 * the return value indicates whether actual cleaning was done, there
1308 * is no guarantee that everything was cleaned
1309 **/
e1000_clean_rx_irq_ps(struct e1000_ring * rx_ring,int * work_done,int work_to_do)1310 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1311 int work_to_do)
1312 {
1313 struct e1000_adapter *adapter = rx_ring->adapter;
1314 struct e1000_hw *hw = &adapter->hw;
1315 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1316 struct net_device *netdev = adapter->netdev;
1317 struct pci_dev *pdev = adapter->pdev;
1318 struct e1000_buffer *buffer_info, *next_buffer;
1319 struct e1000_ps_page *ps_page;
1320 struct sk_buff *skb;
1321 unsigned int i, j;
1322 u32 length, staterr;
1323 int cleaned_count = 0;
1324 bool cleaned = false;
1325 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1326
1327 i = rx_ring->next_to_clean;
1328 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1329 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1330 buffer_info = &rx_ring->buffer_info[i];
1331
1332 while (staterr & E1000_RXD_STAT_DD) {
1333 if (*work_done >= work_to_do)
1334 break;
1335 (*work_done)++;
1336 skb = buffer_info->skb;
1337 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1338
1339 /* in the packet split case this is header only */
1340 prefetch(skb->data - NET_IP_ALIGN);
1341
1342 i++;
1343 if (i == rx_ring->count)
1344 i = 0;
1345 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1346 prefetch(next_rxd);
1347
1348 next_buffer = &rx_ring->buffer_info[i];
1349
1350 cleaned = true;
1351 cleaned_count++;
1352 dma_unmap_single(&pdev->dev, buffer_info->dma,
1353 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1354 buffer_info->dma = 0;
1355
1356 /* see !EOP comment in other Rx routine */
1357 if (!(staterr & E1000_RXD_STAT_EOP))
1358 adapter->flags2 |= FLAG2_IS_DISCARDING;
1359
1360 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1361 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1362 dev_kfree_skb_irq(skb);
1363 if (staterr & E1000_RXD_STAT_EOP)
1364 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1365 goto next_desc;
1366 }
1367
1368 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1369 !(netdev->features & NETIF_F_RXALL))) {
1370 dev_kfree_skb_irq(skb);
1371 goto next_desc;
1372 }
1373
1374 length = le16_to_cpu(rx_desc->wb.middle.length0);
1375
1376 if (!length) {
1377 e_dbg("Last part of the packet spanning multiple descriptors\n");
1378 dev_kfree_skb_irq(skb);
1379 goto next_desc;
1380 }
1381
1382 /* Good Receive */
1383 skb_put(skb, length);
1384
1385 {
1386 /* this looks ugly, but it seems compiler issues make
1387 * it more efficient than reusing j
1388 */
1389 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1390
1391 /* page alloc/put takes too long and effects small
1392 * packet throughput, so unsplit small packets and
1393 * save the alloc/put
1394 */
1395 if (l1 && (l1 <= copybreak) &&
1396 ((length + l1) <= adapter->rx_ps_bsize0)) {
1397 ps_page = &buffer_info->ps_pages[0];
1398
1399 dma_sync_single_for_cpu(&pdev->dev,
1400 ps_page->dma,
1401 PAGE_SIZE,
1402 DMA_FROM_DEVICE);
1403 memcpy(skb_tail_pointer(skb),
1404 page_address(ps_page->page), l1);
1405 dma_sync_single_for_device(&pdev->dev,
1406 ps_page->dma,
1407 PAGE_SIZE,
1408 DMA_FROM_DEVICE);
1409
1410 /* remove the CRC */
1411 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1412 if (!(netdev->features & NETIF_F_RXFCS))
1413 l1 -= 4;
1414 }
1415
1416 skb_put(skb, l1);
1417 goto copydone;
1418 } /* if */
1419 }
1420
1421 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1422 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1423 if (!length)
1424 break;
1425
1426 ps_page = &buffer_info->ps_pages[j];
1427 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1428 DMA_FROM_DEVICE);
1429 ps_page->dma = 0;
1430 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1431 ps_page->page = NULL;
1432 skb->len += length;
1433 skb->data_len += length;
1434 skb->truesize += PAGE_SIZE;
1435 }
1436
1437 /* strip the ethernet crc, problem is we're using pages now so
1438 * this whole operation can get a little cpu intensive
1439 */
1440 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1441 if (!(netdev->features & NETIF_F_RXFCS))
1442 pskb_trim(skb, skb->len - 4);
1443 }
1444
1445 copydone:
1446 total_rx_bytes += skb->len;
1447 total_rx_packets++;
1448
1449 e1000_rx_checksum(adapter, staterr, skb);
1450
1451 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1452
1453 if (rx_desc->wb.upper.header_status &
1454 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1455 adapter->rx_hdr_split++;
1456
1457 e1000_receive_skb(adapter, netdev, skb, staterr,
1458 rx_desc->wb.middle.vlan);
1459
1460 next_desc:
1461 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1462 buffer_info->skb = NULL;
1463
1464 /* return some buffers to hardware, one at a time is too slow */
1465 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1466 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1467 GFP_ATOMIC);
1468 cleaned_count = 0;
1469 }
1470
1471 /* use prefetched values */
1472 rx_desc = next_rxd;
1473 buffer_info = next_buffer;
1474
1475 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1476 }
1477 rx_ring->next_to_clean = i;
1478
1479 cleaned_count = e1000_desc_unused(rx_ring);
1480 if (cleaned_count)
1481 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1482
1483 adapter->total_rx_bytes += total_rx_bytes;
1484 adapter->total_rx_packets += total_rx_packets;
1485 return cleaned;
1486 }
1487
e1000_consume_page(struct e1000_buffer * bi,struct sk_buff * skb,u16 length)1488 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1489 u16 length)
1490 {
1491 bi->page = NULL;
1492 skb->len += length;
1493 skb->data_len += length;
1494 skb->truesize += PAGE_SIZE;
1495 }
1496
1497 /**
1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1499 * @rx_ring: Rx descriptor ring
1500 * @work_done: output parameter for indicating completed work
1501 * @work_to_do: how many packets we can clean
1502 *
1503 * the return value indicates whether actual cleaning was done, there
1504 * is no guarantee that everything was cleaned
1505 **/
e1000_clean_jumbo_rx_irq(struct e1000_ring * rx_ring,int * work_done,int work_to_do)1506 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 int work_to_do)
1508 {
1509 struct e1000_adapter *adapter = rx_ring->adapter;
1510 struct net_device *netdev = adapter->netdev;
1511 struct pci_dev *pdev = adapter->pdev;
1512 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1513 struct e1000_buffer *buffer_info, *next_buffer;
1514 u32 length, staterr;
1515 unsigned int i;
1516 int cleaned_count = 0;
1517 bool cleaned = false;
1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1519 struct skb_shared_info *shinfo;
1520
1521 i = rx_ring->next_to_clean;
1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1524 buffer_info = &rx_ring->buffer_info[i];
1525
1526 while (staterr & E1000_RXD_STAT_DD) {
1527 struct sk_buff *skb;
1528
1529 if (*work_done >= work_to_do)
1530 break;
1531 (*work_done)++;
1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1533
1534 skb = buffer_info->skb;
1535 buffer_info->skb = NULL;
1536
1537 ++i;
1538 if (i == rx_ring->count)
1539 i = 0;
1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1541 prefetch(next_rxd);
1542
1543 next_buffer = &rx_ring->buffer_info[i];
1544
1545 cleaned = true;
1546 cleaned_count++;
1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 DMA_FROM_DEVICE);
1549 buffer_info->dma = 0;
1550
1551 length = le16_to_cpu(rx_desc->wb.upper.length);
1552
1553 /* errors is only valid for DD + EOP descriptors */
1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 !(netdev->features & NETIF_F_RXALL)))) {
1557 /* recycle both page and skb */
1558 buffer_info->skb = skb;
1559 /* an error means any chain goes out the window too */
1560 if (rx_ring->rx_skb_top)
1561 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1562 rx_ring->rx_skb_top = NULL;
1563 goto next_desc;
1564 }
1565 #define rxtop (rx_ring->rx_skb_top)
1566 if (!(staterr & E1000_RXD_STAT_EOP)) {
1567 /* this descriptor is only the beginning (or middle) */
1568 if (!rxtop) {
1569 /* this is the beginning of a chain */
1570 rxtop = skb;
1571 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1572 0, length);
1573 } else {
1574 /* this is the middle of a chain */
1575 shinfo = skb_shinfo(rxtop);
1576 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1577 buffer_info->page, 0,
1578 length);
1579 /* re-use the skb, only consumed the page */
1580 buffer_info->skb = skb;
1581 }
1582 e1000_consume_page(buffer_info, rxtop, length);
1583 goto next_desc;
1584 } else {
1585 if (rxtop) {
1586 /* end of the chain */
1587 shinfo = skb_shinfo(rxtop);
1588 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1589 buffer_info->page, 0,
1590 length);
1591 /* re-use the current skb, we only consumed the
1592 * page
1593 */
1594 buffer_info->skb = skb;
1595 skb = rxtop;
1596 rxtop = NULL;
1597 e1000_consume_page(buffer_info, skb, length);
1598 } else {
1599 /* no chain, got EOP, this buf is the packet
1600 * copybreak to save the put_page/alloc_page
1601 */
1602 if (length <= copybreak &&
1603 skb_tailroom(skb) >= length) {
1604 memcpy(skb_tail_pointer(skb),
1605 page_address(buffer_info->page),
1606 length);
1607 /* re-use the page, so don't erase
1608 * buffer_info->page
1609 */
1610 skb_put(skb, length);
1611 } else {
1612 skb_fill_page_desc(skb, 0,
1613 buffer_info->page, 0,
1614 length);
1615 e1000_consume_page(buffer_info, skb,
1616 length);
1617 }
1618 }
1619 }
1620
1621 /* Receive Checksum Offload */
1622 e1000_rx_checksum(adapter, staterr, skb);
1623
1624 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1625
1626 /* probably a little skewed due to removing CRC */
1627 total_rx_bytes += skb->len;
1628 total_rx_packets++;
1629
1630 /* eth type trans needs skb->data to point to something */
1631 if (!pskb_may_pull(skb, ETH_HLEN)) {
1632 e_err("pskb_may_pull failed.\n");
1633 dev_kfree_skb_irq(skb);
1634 goto next_desc;
1635 }
1636
1637 e1000_receive_skb(adapter, netdev, skb, staterr,
1638 rx_desc->wb.upper.vlan);
1639
1640 next_desc:
1641 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1642
1643 /* return some buffers to hardware, one at a time is too slow */
1644 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1645 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1646 GFP_ATOMIC);
1647 cleaned_count = 0;
1648 }
1649
1650 /* use prefetched values */
1651 rx_desc = next_rxd;
1652 buffer_info = next_buffer;
1653
1654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1655 }
1656 rx_ring->next_to_clean = i;
1657
1658 cleaned_count = e1000_desc_unused(rx_ring);
1659 if (cleaned_count)
1660 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1661
1662 adapter->total_rx_bytes += total_rx_bytes;
1663 adapter->total_rx_packets += total_rx_packets;
1664 return cleaned;
1665 }
1666
1667 /**
1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1669 * @rx_ring: Rx descriptor ring
1670 **/
e1000_clean_rx_ring(struct e1000_ring * rx_ring)1671 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1672 {
1673 struct e1000_adapter *adapter = rx_ring->adapter;
1674 struct e1000_buffer *buffer_info;
1675 struct e1000_ps_page *ps_page;
1676 struct pci_dev *pdev = adapter->pdev;
1677 unsigned int i, j;
1678
1679 /* Free all the Rx ring sk_buffs */
1680 for (i = 0; i < rx_ring->count; i++) {
1681 buffer_info = &rx_ring->buffer_info[i];
1682 if (buffer_info->dma) {
1683 if (adapter->clean_rx == e1000_clean_rx_irq)
1684 dma_unmap_single(&pdev->dev, buffer_info->dma,
1685 adapter->rx_buffer_len,
1686 DMA_FROM_DEVICE);
1687 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1688 dma_unmap_page(&pdev->dev, buffer_info->dma,
1689 PAGE_SIZE, DMA_FROM_DEVICE);
1690 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1691 dma_unmap_single(&pdev->dev, buffer_info->dma,
1692 adapter->rx_ps_bsize0,
1693 DMA_FROM_DEVICE);
1694 buffer_info->dma = 0;
1695 }
1696
1697 if (buffer_info->page) {
1698 put_page(buffer_info->page);
1699 buffer_info->page = NULL;
1700 }
1701
1702 if (buffer_info->skb) {
1703 dev_kfree_skb(buffer_info->skb);
1704 buffer_info->skb = NULL;
1705 }
1706
1707 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1708 ps_page = &buffer_info->ps_pages[j];
1709 if (!ps_page->page)
1710 break;
1711 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1712 DMA_FROM_DEVICE);
1713 ps_page->dma = 0;
1714 put_page(ps_page->page);
1715 ps_page->page = NULL;
1716 }
1717 }
1718
1719 /* there also may be some cached data from a chained receive */
1720 if (rx_ring->rx_skb_top) {
1721 dev_kfree_skb(rx_ring->rx_skb_top);
1722 rx_ring->rx_skb_top = NULL;
1723 }
1724
1725 /* Zero out the descriptor ring */
1726 memset(rx_ring->desc, 0, rx_ring->size);
1727
1728 rx_ring->next_to_clean = 0;
1729 rx_ring->next_to_use = 0;
1730 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1731 }
1732
e1000e_downshift_workaround(struct work_struct * work)1733 static void e1000e_downshift_workaround(struct work_struct *work)
1734 {
1735 struct e1000_adapter *adapter = container_of(work,
1736 struct e1000_adapter,
1737 downshift_task);
1738
1739 if (test_bit(__E1000_DOWN, &adapter->state))
1740 return;
1741
1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1743 }
1744
1745 /**
1746 * e1000_intr_msi - Interrupt Handler
1747 * @irq: interrupt number
1748 * @data: pointer to a network interface device structure
1749 **/
e1000_intr_msi(int __always_unused irq,void * data)1750 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1751 {
1752 struct net_device *netdev = data;
1753 struct e1000_adapter *adapter = netdev_priv(netdev);
1754 struct e1000_hw *hw = &adapter->hw;
1755 u32 icr = er32(ICR);
1756
1757 /* read ICR disables interrupts using IAM */
1758 if (icr & E1000_ICR_LSC) {
1759 hw->mac.get_link_status = true;
1760 /* ICH8 workaround-- Call gig speed drop workaround on cable
1761 * disconnect (LSC) before accessing any PHY registers
1762 */
1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1764 (!(er32(STATUS) & E1000_STATUS_LU)))
1765 schedule_work(&adapter->downshift_task);
1766
1767 /* 80003ES2LAN workaround-- For packet buffer work-around on
1768 * link down event; disable receives here in the ISR and reset
1769 * adapter in watchdog
1770 */
1771 if (netif_carrier_ok(netdev) &&
1772 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1773 /* disable receives */
1774 u32 rctl = er32(RCTL);
1775
1776 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1777 adapter->flags |= FLAG_RESTART_NOW;
1778 }
1779 /* guard against interrupt when we're going down */
1780 if (!test_bit(__E1000_DOWN, &adapter->state))
1781 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1782 }
1783
1784 /* Reset on uncorrectable ECC error */
1785 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1786 u32 pbeccsts = er32(PBECCSTS);
1787
1788 adapter->corr_errors +=
1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1790 adapter->uncorr_errors +=
1791 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1792
1793 /* Do the reset outside of interrupt context */
1794 schedule_work(&adapter->reset_task);
1795
1796 /* return immediately since reset is imminent */
1797 return IRQ_HANDLED;
1798 }
1799
1800 if (napi_schedule_prep(&adapter->napi)) {
1801 adapter->total_tx_bytes = 0;
1802 adapter->total_tx_packets = 0;
1803 adapter->total_rx_bytes = 0;
1804 adapter->total_rx_packets = 0;
1805 __napi_schedule(&adapter->napi);
1806 }
1807
1808 return IRQ_HANDLED;
1809 }
1810
1811 /**
1812 * e1000_intr - Interrupt Handler
1813 * @irq: interrupt number
1814 * @data: pointer to a network interface device structure
1815 **/
e1000_intr(int __always_unused irq,void * data)1816 static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1817 {
1818 struct net_device *netdev = data;
1819 struct e1000_adapter *adapter = netdev_priv(netdev);
1820 struct e1000_hw *hw = &adapter->hw;
1821 u32 rctl, icr = er32(ICR);
1822
1823 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1824 return IRQ_NONE; /* Not our interrupt */
1825
1826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1827 * not set, then the adapter didn't send an interrupt
1828 */
1829 if (!(icr & E1000_ICR_INT_ASSERTED))
1830 return IRQ_NONE;
1831
1832 /* Interrupt Auto-Mask...upon reading ICR,
1833 * interrupts are masked. No need for the
1834 * IMC write
1835 */
1836
1837 if (icr & E1000_ICR_LSC) {
1838 hw->mac.get_link_status = true;
1839 /* ICH8 workaround-- Call gig speed drop workaround on cable
1840 * disconnect (LSC) before accessing any PHY registers
1841 */
1842 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1843 (!(er32(STATUS) & E1000_STATUS_LU)))
1844 schedule_work(&adapter->downshift_task);
1845
1846 /* 80003ES2LAN workaround--
1847 * For packet buffer work-around on link down event;
1848 * disable receives here in the ISR and
1849 * reset adapter in watchdog
1850 */
1851 if (netif_carrier_ok(netdev) &&
1852 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1853 /* disable receives */
1854 rctl = er32(RCTL);
1855 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1856 adapter->flags |= FLAG_RESTART_NOW;
1857 }
1858 /* guard against interrupt when we're going down */
1859 if (!test_bit(__E1000_DOWN, &adapter->state))
1860 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1861 }
1862
1863 /* Reset on uncorrectable ECC error */
1864 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1865 u32 pbeccsts = er32(PBECCSTS);
1866
1867 adapter->corr_errors +=
1868 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1869 adapter->uncorr_errors +=
1870 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1871
1872 /* Do the reset outside of interrupt context */
1873 schedule_work(&adapter->reset_task);
1874
1875 /* return immediately since reset is imminent */
1876 return IRQ_HANDLED;
1877 }
1878
1879 if (napi_schedule_prep(&adapter->napi)) {
1880 adapter->total_tx_bytes = 0;
1881 adapter->total_tx_packets = 0;
1882 adapter->total_rx_bytes = 0;
1883 adapter->total_rx_packets = 0;
1884 __napi_schedule(&adapter->napi);
1885 }
1886
1887 return IRQ_HANDLED;
1888 }
1889
e1000_msix_other(int __always_unused irq,void * data)1890 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1891 {
1892 struct net_device *netdev = data;
1893 struct e1000_adapter *adapter = netdev_priv(netdev);
1894 struct e1000_hw *hw = &adapter->hw;
1895 u32 icr = er32(ICR);
1896
1897 if (icr & adapter->eiac_mask)
1898 ew32(ICS, (icr & adapter->eiac_mask));
1899
1900 if (icr & E1000_ICR_LSC) {
1901 hw->mac.get_link_status = true;
1902 /* guard against interrupt when we're going down */
1903 if (!test_bit(__E1000_DOWN, &adapter->state))
1904 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1905 }
1906
1907 if (!test_bit(__E1000_DOWN, &adapter->state))
1908 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1909
1910 return IRQ_HANDLED;
1911 }
1912
e1000_intr_msix_tx(int __always_unused irq,void * data)1913 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1914 {
1915 struct net_device *netdev = data;
1916 struct e1000_adapter *adapter = netdev_priv(netdev);
1917 struct e1000_hw *hw = &adapter->hw;
1918 struct e1000_ring *tx_ring = adapter->tx_ring;
1919
1920 adapter->total_tx_bytes = 0;
1921 adapter->total_tx_packets = 0;
1922
1923 if (!e1000_clean_tx_irq(tx_ring))
1924 /* Ring was not completely cleaned, so fire another interrupt */
1925 ew32(ICS, tx_ring->ims_val);
1926
1927 if (!test_bit(__E1000_DOWN, &adapter->state))
1928 ew32(IMS, adapter->tx_ring->ims_val);
1929
1930 return IRQ_HANDLED;
1931 }
1932
e1000_intr_msix_rx(int __always_unused irq,void * data)1933 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1934 {
1935 struct net_device *netdev = data;
1936 struct e1000_adapter *adapter = netdev_priv(netdev);
1937 struct e1000_ring *rx_ring = adapter->rx_ring;
1938
1939 /* Write the ITR value calculated at the end of the
1940 * previous interrupt.
1941 */
1942 if (rx_ring->set_itr) {
1943 u32 itr = rx_ring->itr_val ?
1944 1000000000 / (rx_ring->itr_val * 256) : 0;
1945
1946 writel(itr, rx_ring->itr_register);
1947 rx_ring->set_itr = 0;
1948 }
1949
1950 if (napi_schedule_prep(&adapter->napi)) {
1951 adapter->total_rx_bytes = 0;
1952 adapter->total_rx_packets = 0;
1953 __napi_schedule(&adapter->napi);
1954 }
1955 return IRQ_HANDLED;
1956 }
1957
1958 /**
1959 * e1000_configure_msix - Configure MSI-X hardware
1960 * @adapter: board private structure
1961 *
1962 * e1000_configure_msix sets up the hardware to properly
1963 * generate MSI-X interrupts.
1964 **/
e1000_configure_msix(struct e1000_adapter * adapter)1965 static void e1000_configure_msix(struct e1000_adapter *adapter)
1966 {
1967 struct e1000_hw *hw = &adapter->hw;
1968 struct e1000_ring *rx_ring = adapter->rx_ring;
1969 struct e1000_ring *tx_ring = adapter->tx_ring;
1970 int vector = 0;
1971 u32 ctrl_ext, ivar = 0;
1972
1973 adapter->eiac_mask = 0;
1974
1975 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1976 if (hw->mac.type == e1000_82574) {
1977 u32 rfctl = er32(RFCTL);
1978
1979 rfctl |= E1000_RFCTL_ACK_DIS;
1980 ew32(RFCTL, rfctl);
1981 }
1982
1983 /* Configure Rx vector */
1984 rx_ring->ims_val = E1000_IMS_RXQ0;
1985 adapter->eiac_mask |= rx_ring->ims_val;
1986 if (rx_ring->itr_val)
1987 writel(1000000000 / (rx_ring->itr_val * 256),
1988 rx_ring->itr_register);
1989 else
1990 writel(1, rx_ring->itr_register);
1991 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1992
1993 /* Configure Tx vector */
1994 tx_ring->ims_val = E1000_IMS_TXQ0;
1995 vector++;
1996 if (tx_ring->itr_val)
1997 writel(1000000000 / (tx_ring->itr_val * 256),
1998 tx_ring->itr_register);
1999 else
2000 writel(1, tx_ring->itr_register);
2001 adapter->eiac_mask |= tx_ring->ims_val;
2002 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2003
2004 /* set vector for Other Causes, e.g. link changes */
2005 vector++;
2006 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2007 if (rx_ring->itr_val)
2008 writel(1000000000 / (rx_ring->itr_val * 256),
2009 hw->hw_addr + E1000_EITR_82574(vector));
2010 else
2011 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2012
2013 /* Cause Tx interrupts on every write back */
2014 ivar |= BIT(31);
2015
2016 ew32(IVAR, ivar);
2017
2018 /* enable MSI-X PBA support */
2019 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2020 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2021 ew32(CTRL_EXT, ctrl_ext);
2022 e1e_flush();
2023 }
2024
e1000e_reset_interrupt_capability(struct e1000_adapter * adapter)2025 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2026 {
2027 if (adapter->msix_entries) {
2028 pci_disable_msix(adapter->pdev);
2029 kfree(adapter->msix_entries);
2030 adapter->msix_entries = NULL;
2031 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2032 pci_disable_msi(adapter->pdev);
2033 adapter->flags &= ~FLAG_MSI_ENABLED;
2034 }
2035 }
2036
2037 /**
2038 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2039 * @adapter: board private structure
2040 *
2041 * Attempt to configure interrupts using the best available
2042 * capabilities of the hardware and kernel.
2043 **/
e1000e_set_interrupt_capability(struct e1000_adapter * adapter)2044 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2045 {
2046 int err;
2047 int i;
2048
2049 switch (adapter->int_mode) {
2050 case E1000E_INT_MODE_MSIX:
2051 if (adapter->flags & FLAG_HAS_MSIX) {
2052 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2053 adapter->msix_entries = kcalloc(adapter->num_vectors,
2054 sizeof(struct
2055 msix_entry),
2056 GFP_KERNEL);
2057 if (adapter->msix_entries) {
2058 struct e1000_adapter *a = adapter;
2059
2060 for (i = 0; i < adapter->num_vectors; i++)
2061 adapter->msix_entries[i].entry = i;
2062
2063 err = pci_enable_msix_range(a->pdev,
2064 a->msix_entries,
2065 a->num_vectors,
2066 a->num_vectors);
2067 if (err > 0)
2068 return;
2069 }
2070 /* MSI-X failed, so fall through and try MSI */
2071 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2072 e1000e_reset_interrupt_capability(adapter);
2073 }
2074 adapter->int_mode = E1000E_INT_MODE_MSI;
2075 fallthrough;
2076 case E1000E_INT_MODE_MSI:
2077 if (!pci_enable_msi(adapter->pdev)) {
2078 adapter->flags |= FLAG_MSI_ENABLED;
2079 } else {
2080 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2081 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2082 }
2083 fallthrough;
2084 case E1000E_INT_MODE_LEGACY:
2085 /* Don't do anything; this is the system default */
2086 break;
2087 }
2088
2089 /* store the number of vectors being used */
2090 adapter->num_vectors = 1;
2091 }
2092
2093 /**
2094 * e1000_request_msix - Initialize MSI-X interrupts
2095 * @adapter: board private structure
2096 *
2097 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2098 * kernel.
2099 **/
e1000_request_msix(struct e1000_adapter * adapter)2100 static int e1000_request_msix(struct e1000_adapter *adapter)
2101 {
2102 struct net_device *netdev = adapter->netdev;
2103 int err = 0, vector = 0;
2104
2105 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2106 snprintf(adapter->rx_ring->name,
2107 sizeof(adapter->rx_ring->name) - 1,
2108 "%.14s-rx-0", netdev->name);
2109 else
2110 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2111 err = request_irq(adapter->msix_entries[vector].vector,
2112 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2113 netdev);
2114 if (err)
2115 return err;
2116 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2117 E1000_EITR_82574(vector);
2118 adapter->rx_ring->itr_val = adapter->itr;
2119 vector++;
2120
2121 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2122 snprintf(adapter->tx_ring->name,
2123 sizeof(adapter->tx_ring->name) - 1,
2124 "%.14s-tx-0", netdev->name);
2125 else
2126 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2127 err = request_irq(adapter->msix_entries[vector].vector,
2128 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2129 netdev);
2130 if (err)
2131 return err;
2132 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2133 E1000_EITR_82574(vector);
2134 adapter->tx_ring->itr_val = adapter->itr;
2135 vector++;
2136
2137 err = request_irq(adapter->msix_entries[vector].vector,
2138 e1000_msix_other, 0, netdev->name, netdev);
2139 if (err)
2140 return err;
2141
2142 e1000_configure_msix(adapter);
2143
2144 return 0;
2145 }
2146
2147 /**
2148 * e1000_request_irq - initialize interrupts
2149 * @adapter: board private structure
2150 *
2151 * Attempts to configure interrupts using the best available
2152 * capabilities of the hardware and kernel.
2153 **/
e1000_request_irq(struct e1000_adapter * adapter)2154 static int e1000_request_irq(struct e1000_adapter *adapter)
2155 {
2156 struct net_device *netdev = adapter->netdev;
2157 int err;
2158
2159 if (adapter->msix_entries) {
2160 err = e1000_request_msix(adapter);
2161 if (!err)
2162 return err;
2163 /* fall back to MSI */
2164 e1000e_reset_interrupt_capability(adapter);
2165 adapter->int_mode = E1000E_INT_MODE_MSI;
2166 e1000e_set_interrupt_capability(adapter);
2167 }
2168 if (adapter->flags & FLAG_MSI_ENABLED) {
2169 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2170 netdev->name, netdev);
2171 if (!err)
2172 return err;
2173
2174 /* fall back to legacy interrupt */
2175 e1000e_reset_interrupt_capability(adapter);
2176 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2177 }
2178
2179 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2180 netdev->name, netdev);
2181 if (err)
2182 e_err("Unable to allocate interrupt, Error: %d\n", err);
2183
2184 return err;
2185 }
2186
e1000_free_irq(struct e1000_adapter * adapter)2187 static void e1000_free_irq(struct e1000_adapter *adapter)
2188 {
2189 struct net_device *netdev = adapter->netdev;
2190
2191 if (adapter->msix_entries) {
2192 int vector = 0;
2193
2194 free_irq(adapter->msix_entries[vector].vector, netdev);
2195 vector++;
2196
2197 free_irq(adapter->msix_entries[vector].vector, netdev);
2198 vector++;
2199
2200 /* Other Causes interrupt vector */
2201 free_irq(adapter->msix_entries[vector].vector, netdev);
2202 return;
2203 }
2204
2205 free_irq(adapter->pdev->irq, netdev);
2206 }
2207
2208 /**
2209 * e1000_irq_disable - Mask off interrupt generation on the NIC
2210 * @adapter: board private structure
2211 **/
e1000_irq_disable(struct e1000_adapter * adapter)2212 static void e1000_irq_disable(struct e1000_adapter *adapter)
2213 {
2214 struct e1000_hw *hw = &adapter->hw;
2215
2216 ew32(IMC, ~0);
2217 if (adapter->msix_entries)
2218 ew32(EIAC_82574, 0);
2219 e1e_flush();
2220
2221 if (adapter->msix_entries) {
2222 int i;
2223
2224 for (i = 0; i < adapter->num_vectors; i++)
2225 synchronize_irq(adapter->msix_entries[i].vector);
2226 } else {
2227 synchronize_irq(adapter->pdev->irq);
2228 }
2229 }
2230
2231 /**
2232 * e1000_irq_enable - Enable default interrupt generation settings
2233 * @adapter: board private structure
2234 **/
e1000_irq_enable(struct e1000_adapter * adapter)2235 static void e1000_irq_enable(struct e1000_adapter *adapter)
2236 {
2237 struct e1000_hw *hw = &adapter->hw;
2238
2239 if (adapter->msix_entries) {
2240 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2241 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2242 IMS_OTHER_MASK);
2243 } else if (hw->mac.type >= e1000_pch_lpt) {
2244 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2245 } else {
2246 ew32(IMS, IMS_ENABLE_MASK);
2247 }
2248 e1e_flush();
2249 }
2250
2251 /**
2252 * e1000e_get_hw_control - get control of the h/w from f/w
2253 * @adapter: address of board private structure
2254 *
2255 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2256 * For ASF and Pass Through versions of f/w this means that
2257 * the driver is loaded. For AMT version (only with 82573)
2258 * of the f/w this means that the network i/f is open.
2259 **/
e1000e_get_hw_control(struct e1000_adapter * adapter)2260 void e1000e_get_hw_control(struct e1000_adapter *adapter)
2261 {
2262 struct e1000_hw *hw = &adapter->hw;
2263 u32 ctrl_ext;
2264 u32 swsm;
2265
2266 /* Let firmware know the driver has taken over */
2267 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2268 swsm = er32(SWSM);
2269 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2270 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2271 ctrl_ext = er32(CTRL_EXT);
2272 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2273 }
2274 }
2275
2276 /**
2277 * e1000e_release_hw_control - release control of the h/w to f/w
2278 * @adapter: address of board private structure
2279 *
2280 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2281 * For ASF and Pass Through versions of f/w this means that the
2282 * driver is no longer loaded. For AMT version (only with 82573) i
2283 * of the f/w this means that the network i/f is closed.
2284 *
2285 **/
e1000e_release_hw_control(struct e1000_adapter * adapter)2286 void e1000e_release_hw_control(struct e1000_adapter *adapter)
2287 {
2288 struct e1000_hw *hw = &adapter->hw;
2289 u32 ctrl_ext;
2290 u32 swsm;
2291
2292 /* Let firmware taken over control of h/w */
2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2294 swsm = er32(SWSM);
2295 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2297 ctrl_ext = er32(CTRL_EXT);
2298 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2299 }
2300 }
2301
2302 /**
2303 * e1000_alloc_ring_dma - allocate memory for a ring structure
2304 * @adapter: board private structure
2305 * @ring: ring struct for which to allocate dma
2306 **/
e1000_alloc_ring_dma(struct e1000_adapter * adapter,struct e1000_ring * ring)2307 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2308 struct e1000_ring *ring)
2309 {
2310 struct pci_dev *pdev = adapter->pdev;
2311
2312 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2313 GFP_KERNEL);
2314 if (!ring->desc)
2315 return -ENOMEM;
2316
2317 return 0;
2318 }
2319
2320 /**
2321 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2322 * @tx_ring: Tx descriptor ring
2323 *
2324 * Return 0 on success, negative on failure
2325 **/
e1000e_setup_tx_resources(struct e1000_ring * tx_ring)2326 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2327 {
2328 struct e1000_adapter *adapter = tx_ring->adapter;
2329 int err = -ENOMEM, size;
2330
2331 size = sizeof(struct e1000_buffer) * tx_ring->count;
2332 tx_ring->buffer_info = vzalloc(size);
2333 if (!tx_ring->buffer_info)
2334 goto err;
2335
2336 /* round up to nearest 4K */
2337 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2338 tx_ring->size = ALIGN(tx_ring->size, 4096);
2339
2340 err = e1000_alloc_ring_dma(adapter, tx_ring);
2341 if (err)
2342 goto err;
2343
2344 tx_ring->next_to_use = 0;
2345 tx_ring->next_to_clean = 0;
2346
2347 return 0;
2348 err:
2349 vfree(tx_ring->buffer_info);
2350 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2351 return err;
2352 }
2353
2354 /**
2355 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2356 * @rx_ring: Rx descriptor ring
2357 *
2358 * Returns 0 on success, negative on failure
2359 **/
e1000e_setup_rx_resources(struct e1000_ring * rx_ring)2360 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2361 {
2362 struct e1000_adapter *adapter = rx_ring->adapter;
2363 struct e1000_buffer *buffer_info;
2364 int i, size, desc_len, err = -ENOMEM;
2365
2366 size = sizeof(struct e1000_buffer) * rx_ring->count;
2367 rx_ring->buffer_info = vzalloc(size);
2368 if (!rx_ring->buffer_info)
2369 goto err;
2370
2371 for (i = 0; i < rx_ring->count; i++) {
2372 buffer_info = &rx_ring->buffer_info[i];
2373 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2374 sizeof(struct e1000_ps_page),
2375 GFP_KERNEL);
2376 if (!buffer_info->ps_pages)
2377 goto err_pages;
2378 }
2379
2380 desc_len = sizeof(union e1000_rx_desc_packet_split);
2381
2382 /* Round up to nearest 4K */
2383 rx_ring->size = rx_ring->count * desc_len;
2384 rx_ring->size = ALIGN(rx_ring->size, 4096);
2385
2386 err = e1000_alloc_ring_dma(adapter, rx_ring);
2387 if (err)
2388 goto err_pages;
2389
2390 rx_ring->next_to_clean = 0;
2391 rx_ring->next_to_use = 0;
2392 rx_ring->rx_skb_top = NULL;
2393
2394 return 0;
2395
2396 err_pages:
2397 for (i = 0; i < rx_ring->count; i++) {
2398 buffer_info = &rx_ring->buffer_info[i];
2399 kfree(buffer_info->ps_pages);
2400 }
2401 err:
2402 vfree(rx_ring->buffer_info);
2403 e_err("Unable to allocate memory for the receive descriptor ring\n");
2404 return err;
2405 }
2406
2407 /**
2408 * e1000_clean_tx_ring - Free Tx Buffers
2409 * @tx_ring: Tx descriptor ring
2410 **/
e1000_clean_tx_ring(struct e1000_ring * tx_ring)2411 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2412 {
2413 struct e1000_adapter *adapter = tx_ring->adapter;
2414 struct e1000_buffer *buffer_info;
2415 unsigned long size;
2416 unsigned int i;
2417
2418 for (i = 0; i < tx_ring->count; i++) {
2419 buffer_info = &tx_ring->buffer_info[i];
2420 e1000_put_txbuf(tx_ring, buffer_info, false);
2421 }
2422
2423 netdev_reset_queue(adapter->netdev);
2424 size = sizeof(struct e1000_buffer) * tx_ring->count;
2425 memset(tx_ring->buffer_info, 0, size);
2426
2427 memset(tx_ring->desc, 0, tx_ring->size);
2428
2429 tx_ring->next_to_use = 0;
2430 tx_ring->next_to_clean = 0;
2431 }
2432
2433 /**
2434 * e1000e_free_tx_resources - Free Tx Resources per Queue
2435 * @tx_ring: Tx descriptor ring
2436 *
2437 * Free all transmit software resources
2438 **/
e1000e_free_tx_resources(struct e1000_ring * tx_ring)2439 void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2440 {
2441 struct e1000_adapter *adapter = tx_ring->adapter;
2442 struct pci_dev *pdev = adapter->pdev;
2443
2444 e1000_clean_tx_ring(tx_ring);
2445
2446 vfree(tx_ring->buffer_info);
2447 tx_ring->buffer_info = NULL;
2448
2449 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2450 tx_ring->dma);
2451 tx_ring->desc = NULL;
2452 }
2453
2454 /**
2455 * e1000e_free_rx_resources - Free Rx Resources
2456 * @rx_ring: Rx descriptor ring
2457 *
2458 * Free all receive software resources
2459 **/
e1000e_free_rx_resources(struct e1000_ring * rx_ring)2460 void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2461 {
2462 struct e1000_adapter *adapter = rx_ring->adapter;
2463 struct pci_dev *pdev = adapter->pdev;
2464 int i;
2465
2466 e1000_clean_rx_ring(rx_ring);
2467
2468 for (i = 0; i < rx_ring->count; i++)
2469 kfree(rx_ring->buffer_info[i].ps_pages);
2470
2471 vfree(rx_ring->buffer_info);
2472 rx_ring->buffer_info = NULL;
2473
2474 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2475 rx_ring->dma);
2476 rx_ring->desc = NULL;
2477 }
2478
2479 /**
2480 * e1000_update_itr - update the dynamic ITR value based on statistics
2481 * @itr_setting: current adapter->itr
2482 * @packets: the number of packets during this measurement interval
2483 * @bytes: the number of bytes during this measurement interval
2484 *
2485 * Stores a new ITR value based on packets and byte
2486 * counts during the last interrupt. The advantage of per interrupt
2487 * computation is faster updates and more accurate ITR for the current
2488 * traffic pattern. Constants in this function were computed
2489 * based on theoretical maximum wire speed and thresholds were set based
2490 * on testing data as well as attempting to minimize response time
2491 * while increasing bulk throughput. This functionality is controlled
2492 * by the InterruptThrottleRate module parameter.
2493 **/
e1000_update_itr(u16 itr_setting,int packets,int bytes)2494 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2495 {
2496 unsigned int retval = itr_setting;
2497
2498 if (packets == 0)
2499 return itr_setting;
2500
2501 switch (itr_setting) {
2502 case lowest_latency:
2503 /* handle TSO and jumbo frames */
2504 if (bytes / packets > 8000)
2505 retval = bulk_latency;
2506 else if ((packets < 5) && (bytes > 512))
2507 retval = low_latency;
2508 break;
2509 case low_latency: /* 50 usec aka 20000 ints/s */
2510 if (bytes > 10000) {
2511 /* this if handles the TSO accounting */
2512 if (bytes / packets > 8000)
2513 retval = bulk_latency;
2514 else if ((packets < 10) || ((bytes / packets) > 1200))
2515 retval = bulk_latency;
2516 else if ((packets > 35))
2517 retval = lowest_latency;
2518 } else if (bytes / packets > 2000) {
2519 retval = bulk_latency;
2520 } else if (packets <= 2 && bytes < 512) {
2521 retval = lowest_latency;
2522 }
2523 break;
2524 case bulk_latency: /* 250 usec aka 4000 ints/s */
2525 if (bytes > 25000) {
2526 if (packets > 35)
2527 retval = low_latency;
2528 } else if (bytes < 6000) {
2529 retval = low_latency;
2530 }
2531 break;
2532 }
2533
2534 return retval;
2535 }
2536
e1000_set_itr(struct e1000_adapter * adapter)2537 static void e1000_set_itr(struct e1000_adapter *adapter)
2538 {
2539 u16 current_itr;
2540 u32 new_itr = adapter->itr;
2541
2542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2543 if (adapter->link_speed != SPEED_1000) {
2544 new_itr = 4000;
2545 goto set_itr_now;
2546 }
2547
2548 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2549 new_itr = 0;
2550 goto set_itr_now;
2551 }
2552
2553 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2554 adapter->total_tx_packets,
2555 adapter->total_tx_bytes);
2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2557 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2558 adapter->tx_itr = low_latency;
2559
2560 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2561 adapter->total_rx_packets,
2562 adapter->total_rx_bytes);
2563 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2564 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2565 adapter->rx_itr = low_latency;
2566
2567 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2568
2569 /* counts and packets in update_itr are dependent on these numbers */
2570 switch (current_itr) {
2571 case lowest_latency:
2572 new_itr = 70000;
2573 break;
2574 case low_latency:
2575 new_itr = 20000; /* aka hwitr = ~200 */
2576 break;
2577 case bulk_latency:
2578 new_itr = 4000;
2579 break;
2580 default:
2581 break;
2582 }
2583
2584 set_itr_now:
2585 if (new_itr != adapter->itr) {
2586 /* this attempts to bias the interrupt rate towards Bulk
2587 * by adding intermediate steps when interrupt rate is
2588 * increasing
2589 */
2590 new_itr = new_itr > adapter->itr ?
2591 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2592 adapter->itr = new_itr;
2593 adapter->rx_ring->itr_val = new_itr;
2594 if (adapter->msix_entries)
2595 adapter->rx_ring->set_itr = 1;
2596 else
2597 e1000e_write_itr(adapter, new_itr);
2598 }
2599 }
2600
2601 /**
2602 * e1000e_write_itr - write the ITR value to the appropriate registers
2603 * @adapter: address of board private structure
2604 * @itr: new ITR value to program
2605 *
2606 * e1000e_write_itr determines if the adapter is in MSI-X mode
2607 * and, if so, writes the EITR registers with the ITR value.
2608 * Otherwise, it writes the ITR value into the ITR register.
2609 **/
e1000e_write_itr(struct e1000_adapter * adapter,u32 itr)2610 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2611 {
2612 struct e1000_hw *hw = &adapter->hw;
2613 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2614
2615 if (adapter->msix_entries) {
2616 int vector;
2617
2618 for (vector = 0; vector < adapter->num_vectors; vector++)
2619 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2620 } else {
2621 ew32(ITR, new_itr);
2622 }
2623 }
2624
2625 /**
2626 * e1000_alloc_queues - Allocate memory for all rings
2627 * @adapter: board private structure to initialize
2628 **/
e1000_alloc_queues(struct e1000_adapter * adapter)2629 static int e1000_alloc_queues(struct e1000_adapter *adapter)
2630 {
2631 int size = sizeof(struct e1000_ring);
2632
2633 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2634 if (!adapter->tx_ring)
2635 goto err;
2636 adapter->tx_ring->count = adapter->tx_ring_count;
2637 adapter->tx_ring->adapter = adapter;
2638
2639 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2640 if (!adapter->rx_ring)
2641 goto err;
2642 adapter->rx_ring->count = adapter->rx_ring_count;
2643 adapter->rx_ring->adapter = adapter;
2644
2645 return 0;
2646 err:
2647 e_err("Unable to allocate memory for queues\n");
2648 kfree(adapter->rx_ring);
2649 kfree(adapter->tx_ring);
2650 return -ENOMEM;
2651 }
2652
2653 /**
2654 * e1000e_poll - NAPI Rx polling callback
2655 * @napi: struct associated with this polling callback
2656 * @budget: number of packets driver is allowed to process this poll
2657 **/
e1000e_poll(struct napi_struct * napi,int budget)2658 static int e1000e_poll(struct napi_struct *napi, int budget)
2659 {
2660 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2661 napi);
2662 struct e1000_hw *hw = &adapter->hw;
2663 struct net_device *poll_dev = adapter->netdev;
2664 int tx_cleaned = 1, work_done = 0;
2665
2666 adapter = netdev_priv(poll_dev);
2667
2668 if (!adapter->msix_entries ||
2669 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2670 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2671
2672 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2673
2674 if (!tx_cleaned || work_done == budget)
2675 return budget;
2676
2677 /* Exit the polling mode, but don't re-enable interrupts if stack might
2678 * poll us due to busy-polling
2679 */
2680 if (likely(napi_complete_done(napi, work_done))) {
2681 if (adapter->itr_setting & 3)
2682 e1000_set_itr(adapter);
2683 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2684 if (adapter->msix_entries)
2685 ew32(IMS, adapter->rx_ring->ims_val);
2686 else
2687 e1000_irq_enable(adapter);
2688 }
2689 }
2690
2691 return work_done;
2692 }
2693
e1000_vlan_rx_add_vid(struct net_device * netdev,__always_unused __be16 proto,u16 vid)2694 static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2695 __always_unused __be16 proto, u16 vid)
2696 {
2697 struct e1000_adapter *adapter = netdev_priv(netdev);
2698 struct e1000_hw *hw = &adapter->hw;
2699 u32 vfta, index;
2700
2701 /* don't update vlan cookie if already programmed */
2702 if ((adapter->hw.mng_cookie.status &
2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2704 (vid == adapter->mng_vlan_id))
2705 return 0;
2706
2707 /* add VID to filter table */
2708 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2709 index = (vid >> 5) & 0x7F;
2710 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2711 vfta |= BIT((vid & 0x1F));
2712 hw->mac.ops.write_vfta(hw, index, vfta);
2713 }
2714
2715 set_bit(vid, adapter->active_vlans);
2716
2717 return 0;
2718 }
2719
e1000_vlan_rx_kill_vid(struct net_device * netdev,__always_unused __be16 proto,u16 vid)2720 static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2721 __always_unused __be16 proto, u16 vid)
2722 {
2723 struct e1000_adapter *adapter = netdev_priv(netdev);
2724 struct e1000_hw *hw = &adapter->hw;
2725 u32 vfta, index;
2726
2727 if ((adapter->hw.mng_cookie.status &
2728 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2729 (vid == adapter->mng_vlan_id)) {
2730 /* release control to f/w */
2731 e1000e_release_hw_control(adapter);
2732 return 0;
2733 }
2734
2735 /* remove VID from filter table */
2736 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2737 index = (vid >> 5) & 0x7F;
2738 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2739 vfta &= ~BIT((vid & 0x1F));
2740 hw->mac.ops.write_vfta(hw, index, vfta);
2741 }
2742
2743 clear_bit(vid, adapter->active_vlans);
2744
2745 return 0;
2746 }
2747
2748 /**
2749 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2750 * @adapter: board private structure to initialize
2751 **/
e1000e_vlan_filter_disable(struct e1000_adapter * adapter)2752 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2753 {
2754 struct net_device *netdev = adapter->netdev;
2755 struct e1000_hw *hw = &adapter->hw;
2756 u32 rctl;
2757
2758 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2759 /* disable VLAN receive filtering */
2760 rctl = er32(RCTL);
2761 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2762 ew32(RCTL, rctl);
2763
2764 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2765 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2766 adapter->mng_vlan_id);
2767 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2768 }
2769 }
2770 }
2771
2772 /**
2773 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2774 * @adapter: board private structure to initialize
2775 **/
e1000e_vlan_filter_enable(struct e1000_adapter * adapter)2776 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2777 {
2778 struct e1000_hw *hw = &adapter->hw;
2779 u32 rctl;
2780
2781 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2782 /* enable VLAN receive filtering */
2783 rctl = er32(RCTL);
2784 rctl |= E1000_RCTL_VFE;
2785 rctl &= ~E1000_RCTL_CFIEN;
2786 ew32(RCTL, rctl);
2787 }
2788 }
2789
2790 /**
2791 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2792 * @adapter: board private structure to initialize
2793 **/
e1000e_vlan_strip_disable(struct e1000_adapter * adapter)2794 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2795 {
2796 struct e1000_hw *hw = &adapter->hw;
2797 u32 ctrl;
2798
2799 /* disable VLAN tag insert/strip */
2800 ctrl = er32(CTRL);
2801 ctrl &= ~E1000_CTRL_VME;
2802 ew32(CTRL, ctrl);
2803 }
2804
2805 /**
2806 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2807 * @adapter: board private structure to initialize
2808 **/
e1000e_vlan_strip_enable(struct e1000_adapter * adapter)2809 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2810 {
2811 struct e1000_hw *hw = &adapter->hw;
2812 u32 ctrl;
2813
2814 /* enable VLAN tag insert/strip */
2815 ctrl = er32(CTRL);
2816 ctrl |= E1000_CTRL_VME;
2817 ew32(CTRL, ctrl);
2818 }
2819
e1000_update_mng_vlan(struct e1000_adapter * adapter)2820 static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2821 {
2822 struct net_device *netdev = adapter->netdev;
2823 u16 vid = adapter->hw.mng_cookie.vlan_id;
2824 u16 old_vid = adapter->mng_vlan_id;
2825
2826 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2827 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2828 adapter->mng_vlan_id = vid;
2829 }
2830
2831 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2832 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2833 }
2834
e1000_restore_vlan(struct e1000_adapter * adapter)2835 static void e1000_restore_vlan(struct e1000_adapter *adapter)
2836 {
2837 u16 vid;
2838
2839 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2840
2841 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2842 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2843 }
2844
e1000_init_manageability_pt(struct e1000_adapter * adapter)2845 static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2846 {
2847 struct e1000_hw *hw = &adapter->hw;
2848 u32 manc, manc2h, mdef, i, j;
2849
2850 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2851 return;
2852
2853 manc = er32(MANC);
2854
2855 /* enable receiving management packets to the host. this will probably
2856 * generate destination unreachable messages from the host OS, but
2857 * the packets will be handled on SMBUS
2858 */
2859 manc |= E1000_MANC_EN_MNG2HOST;
2860 manc2h = er32(MANC2H);
2861
2862 switch (hw->mac.type) {
2863 default:
2864 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2865 break;
2866 case e1000_82574:
2867 case e1000_82583:
2868 /* Check if IPMI pass-through decision filter already exists;
2869 * if so, enable it.
2870 */
2871 for (i = 0, j = 0; i < 8; i++) {
2872 mdef = er32(MDEF(i));
2873
2874 /* Ignore filters with anything other than IPMI ports */
2875 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2876 continue;
2877
2878 /* Enable this decision filter in MANC2H */
2879 if (mdef)
2880 manc2h |= BIT(i);
2881
2882 j |= mdef;
2883 }
2884
2885 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2886 break;
2887
2888 /* Create new decision filter in an empty filter */
2889 for (i = 0, j = 0; i < 8; i++)
2890 if (er32(MDEF(i)) == 0) {
2891 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2892 E1000_MDEF_PORT_664));
2893 manc2h |= BIT(1);
2894 j++;
2895 break;
2896 }
2897
2898 if (!j)
2899 e_warn("Unable to create IPMI pass-through filter\n");
2900 break;
2901 }
2902
2903 ew32(MANC2H, manc2h);
2904 ew32(MANC, manc);
2905 }
2906
2907 /**
2908 * e1000_configure_tx - Configure Transmit Unit after Reset
2909 * @adapter: board private structure
2910 *
2911 * Configure the Tx unit of the MAC after a reset.
2912 **/
e1000_configure_tx(struct e1000_adapter * adapter)2913 static void e1000_configure_tx(struct e1000_adapter *adapter)
2914 {
2915 struct e1000_hw *hw = &adapter->hw;
2916 struct e1000_ring *tx_ring = adapter->tx_ring;
2917 u64 tdba;
2918 u32 tdlen, tctl, tarc;
2919
2920 /* Setup the HW Tx Head and Tail descriptor pointers */
2921 tdba = tx_ring->dma;
2922 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2923 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2924 ew32(TDBAH(0), (tdba >> 32));
2925 ew32(TDLEN(0), tdlen);
2926 ew32(TDH(0), 0);
2927 ew32(TDT(0), 0);
2928 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2929 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2930
2931 writel(0, tx_ring->head);
2932 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2933 e1000e_update_tdt_wa(tx_ring, 0);
2934 else
2935 writel(0, tx_ring->tail);
2936
2937 /* Set the Tx Interrupt Delay register */
2938 ew32(TIDV, adapter->tx_int_delay);
2939 /* Tx irq moderation */
2940 ew32(TADV, adapter->tx_abs_int_delay);
2941
2942 if (adapter->flags2 & FLAG2_DMA_BURST) {
2943 u32 txdctl = er32(TXDCTL(0));
2944
2945 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2946 E1000_TXDCTL_WTHRESH);
2947 /* set up some performance related parameters to encourage the
2948 * hardware to use the bus more efficiently in bursts, depends
2949 * on the tx_int_delay to be enabled,
2950 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2951 * hthresh = 1 ==> prefetch when one or more available
2952 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2953 * BEWARE: this seems to work but should be considered first if
2954 * there are Tx hangs or other Tx related bugs
2955 */
2956 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2957 ew32(TXDCTL(0), txdctl);
2958 }
2959 /* erratum work around: set txdctl the same for both queues */
2960 ew32(TXDCTL(1), er32(TXDCTL(0)));
2961
2962 /* Program the Transmit Control Register */
2963 tctl = er32(TCTL);
2964 tctl &= ~E1000_TCTL_CT;
2965 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2966 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2967
2968 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2969 tarc = er32(TARC(0));
2970 /* set the speed mode bit, we'll clear it if we're not at
2971 * gigabit link later
2972 */
2973 #define SPEED_MODE_BIT BIT(21)
2974 tarc |= SPEED_MODE_BIT;
2975 ew32(TARC(0), tarc);
2976 }
2977
2978 /* errata: program both queues to unweighted RR */
2979 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2980 tarc = er32(TARC(0));
2981 tarc |= 1;
2982 ew32(TARC(0), tarc);
2983 tarc = er32(TARC(1));
2984 tarc |= 1;
2985 ew32(TARC(1), tarc);
2986 }
2987
2988 /* Setup Transmit Descriptor Settings for eop descriptor */
2989 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2990
2991 /* only set IDE if we are delaying interrupts using the timers */
2992 if (adapter->tx_int_delay)
2993 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2994
2995 /* enable Report Status bit */
2996 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2997
2998 ew32(TCTL, tctl);
2999
3000 hw->mac.ops.config_collision_dist(hw);
3001
3002 /* SPT and KBL Si errata workaround to avoid data corruption */
3003 if (hw->mac.type == e1000_pch_spt) {
3004 u32 reg_val;
3005
3006 reg_val = er32(IOSFPC);
3007 reg_val |= E1000_RCTL_RDMTS_HEX;
3008 ew32(IOSFPC, reg_val);
3009
3010 reg_val = er32(TARC(0));
3011 /* SPT and KBL Si errata workaround to avoid Tx hang.
3012 * Dropping the number of outstanding requests from
3013 * 3 to 2 in order to avoid a buffer overrun.
3014 */
3015 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3016 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3017 ew32(TARC(0), reg_val);
3018 }
3019 }
3020
3021 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3022 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3023
3024 /**
3025 * e1000_setup_rctl - configure the receive control registers
3026 * @adapter: Board private structure
3027 **/
e1000_setup_rctl(struct e1000_adapter * adapter)3028 static void e1000_setup_rctl(struct e1000_adapter *adapter)
3029 {
3030 struct e1000_hw *hw = &adapter->hw;
3031 u32 rctl, rfctl;
3032 u32 pages = 0;
3033
3034 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3035 * If jumbo frames not set, program related MAC/PHY registers
3036 * to h/w defaults
3037 */
3038 if (hw->mac.type >= e1000_pch2lan) {
3039 s32 ret_val;
3040
3041 if (adapter->netdev->mtu > ETH_DATA_LEN)
3042 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3043 else
3044 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3045
3046 if (ret_val)
3047 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3048 }
3049
3050 /* Program MC offset vector base */
3051 rctl = er32(RCTL);
3052 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3053 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3054 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3055 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3056
3057 /* Do not Store bad packets */
3058 rctl &= ~E1000_RCTL_SBP;
3059
3060 /* Enable Long Packet receive */
3061 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3062 rctl &= ~E1000_RCTL_LPE;
3063 else
3064 rctl |= E1000_RCTL_LPE;
3065
3066 /* Some systems expect that the CRC is included in SMBUS traffic. The
3067 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3068 * host memory when this is enabled
3069 */
3070 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3071 rctl |= E1000_RCTL_SECRC;
3072
3073 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3074 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3075 u16 phy_data;
3076
3077 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3078 phy_data &= 0xfff8;
3079 phy_data |= BIT(2);
3080 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3081
3082 e1e_rphy(hw, 22, &phy_data);
3083 phy_data &= 0x0fff;
3084 phy_data |= BIT(14);
3085 e1e_wphy(hw, 0x10, 0x2823);
3086 e1e_wphy(hw, 0x11, 0x0003);
3087 e1e_wphy(hw, 22, phy_data);
3088 }
3089
3090 /* Setup buffer sizes */
3091 rctl &= ~E1000_RCTL_SZ_4096;
3092 rctl |= E1000_RCTL_BSEX;
3093 switch (adapter->rx_buffer_len) {
3094 case 2048:
3095 default:
3096 rctl |= E1000_RCTL_SZ_2048;
3097 rctl &= ~E1000_RCTL_BSEX;
3098 break;
3099 case 4096:
3100 rctl |= E1000_RCTL_SZ_4096;
3101 break;
3102 case 8192:
3103 rctl |= E1000_RCTL_SZ_8192;
3104 break;
3105 case 16384:
3106 rctl |= E1000_RCTL_SZ_16384;
3107 break;
3108 }
3109
3110 /* Enable Extended Status in all Receive Descriptors */
3111 rfctl = er32(RFCTL);
3112 rfctl |= E1000_RFCTL_EXTEN;
3113 ew32(RFCTL, rfctl);
3114
3115 /* 82571 and greater support packet-split where the protocol
3116 * header is placed in skb->data and the packet data is
3117 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3118 * In the case of a non-split, skb->data is linearly filled,
3119 * followed by the page buffers. Therefore, skb->data is
3120 * sized to hold the largest protocol header.
3121 *
3122 * allocations using alloc_page take too long for regular MTU
3123 * so only enable packet split for jumbo frames
3124 *
3125 * Using pages when the page size is greater than 16k wastes
3126 * a lot of memory, since we allocate 3 pages at all times
3127 * per packet.
3128 */
3129 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3130 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3131 adapter->rx_ps_pages = pages;
3132 else
3133 adapter->rx_ps_pages = 0;
3134
3135 if (adapter->rx_ps_pages) {
3136 u32 psrctl = 0;
3137
3138 /* Enable Packet split descriptors */
3139 rctl |= E1000_RCTL_DTYP_PS;
3140
3141 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3142
3143 switch (adapter->rx_ps_pages) {
3144 case 3:
3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3146 fallthrough;
3147 case 2:
3148 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3149 fallthrough;
3150 case 1:
3151 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3152 break;
3153 }
3154
3155 ew32(PSRCTL, psrctl);
3156 }
3157
3158 /* This is useful for sniffing bad packets. */
3159 if (adapter->netdev->features & NETIF_F_RXALL) {
3160 /* UPE and MPE will be handled by normal PROMISC logic
3161 * in e1000e_set_rx_mode
3162 */
3163 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3164 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3165 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3166
3167 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3168 E1000_RCTL_DPF | /* Allow filtered pause */
3169 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3170 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3171 * and that breaks VLANs.
3172 */
3173 }
3174
3175 ew32(RCTL, rctl);
3176 /* just started the receive unit, no need to restart */
3177 adapter->flags &= ~FLAG_RESTART_NOW;
3178 }
3179
3180 /**
3181 * e1000_configure_rx - Configure Receive Unit after Reset
3182 * @adapter: board private structure
3183 *
3184 * Configure the Rx unit of the MAC after a reset.
3185 **/
e1000_configure_rx(struct e1000_adapter * adapter)3186 static void e1000_configure_rx(struct e1000_adapter *adapter)
3187 {
3188 struct e1000_hw *hw = &adapter->hw;
3189 struct e1000_ring *rx_ring = adapter->rx_ring;
3190 u64 rdba;
3191 u32 rdlen, rctl, rxcsum, ctrl_ext;
3192
3193 if (adapter->rx_ps_pages) {
3194 /* this is a 32 byte descriptor */
3195 rdlen = rx_ring->count *
3196 sizeof(union e1000_rx_desc_packet_split);
3197 adapter->clean_rx = e1000_clean_rx_irq_ps;
3198 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3199 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3200 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3201 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3202 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3203 } else {
3204 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3205 adapter->clean_rx = e1000_clean_rx_irq;
3206 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3207 }
3208
3209 /* disable receives while setting up the descriptors */
3210 rctl = er32(RCTL);
3211 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3212 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3213 e1e_flush();
3214 usleep_range(10000, 11000);
3215
3216 if (adapter->flags2 & FLAG2_DMA_BURST) {
3217 /* set the writeback threshold (only takes effect if the RDTR
3218 * is set). set GRAN=1 and write back up to 0x4 worth, and
3219 * enable prefetching of 0x20 Rx descriptors
3220 * granularity = 01
3221 * wthresh = 04,
3222 * hthresh = 04,
3223 * pthresh = 0x20
3224 */
3225 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3226 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3227 }
3228
3229 /* set the Receive Delay Timer Register */
3230 ew32(RDTR, adapter->rx_int_delay);
3231
3232 /* irq moderation */
3233 ew32(RADV, adapter->rx_abs_int_delay);
3234 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3235 e1000e_write_itr(adapter, adapter->itr);
3236
3237 ctrl_ext = er32(CTRL_EXT);
3238 /* Auto-Mask interrupts upon ICR access */
3239 ctrl_ext |= E1000_CTRL_EXT_IAME;
3240 ew32(IAM, 0xffffffff);
3241 ew32(CTRL_EXT, ctrl_ext);
3242 e1e_flush();
3243
3244 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3245 * the Base and Length of the Rx Descriptor Ring
3246 */
3247 rdba = rx_ring->dma;
3248 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3249 ew32(RDBAH(0), (rdba >> 32));
3250 ew32(RDLEN(0), rdlen);
3251 ew32(RDH(0), 0);
3252 ew32(RDT(0), 0);
3253 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3254 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3255
3256 writel(0, rx_ring->head);
3257 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3258 e1000e_update_rdt_wa(rx_ring, 0);
3259 else
3260 writel(0, rx_ring->tail);
3261
3262 /* Enable Receive Checksum Offload for TCP and UDP */
3263 rxcsum = er32(RXCSUM);
3264 if (adapter->netdev->features & NETIF_F_RXCSUM)
3265 rxcsum |= E1000_RXCSUM_TUOFL;
3266 else
3267 rxcsum &= ~E1000_RXCSUM_TUOFL;
3268 ew32(RXCSUM, rxcsum);
3269
3270 /* With jumbo frames, excessive C-state transition latencies result
3271 * in dropped transactions.
3272 */
3273 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3274 u32 lat =
3275 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3276 adapter->max_frame_size) * 8 / 1000;
3277
3278 if (adapter->flags & FLAG_IS_ICH) {
3279 u32 rxdctl = er32(RXDCTL(0));
3280
3281 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3282 }
3283
3284 dev_info(&adapter->pdev->dev,
3285 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3286 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
3287 } else {
3288 cpu_latency_qos_update_request(&adapter->pm_qos_req,
3289 PM_QOS_DEFAULT_VALUE);
3290 }
3291
3292 /* Enable Receives */
3293 ew32(RCTL, rctl);
3294 }
3295
3296 /**
3297 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3298 * @netdev: network interface device structure
3299 *
3300 * Writes multicast address list to the MTA hash table.
3301 * Returns: -ENOMEM on failure
3302 * 0 on no addresses written
3303 * X on writing X addresses to MTA
3304 */
e1000e_write_mc_addr_list(struct net_device * netdev)3305 static int e1000e_write_mc_addr_list(struct net_device *netdev)
3306 {
3307 struct e1000_adapter *adapter = netdev_priv(netdev);
3308 struct e1000_hw *hw = &adapter->hw;
3309 struct netdev_hw_addr *ha;
3310 u8 *mta_list;
3311 int i;
3312
3313 if (netdev_mc_empty(netdev)) {
3314 /* nothing to program, so clear mc list */
3315 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3316 return 0;
3317 }
3318
3319 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3320 if (!mta_list)
3321 return -ENOMEM;
3322
3323 /* update_mc_addr_list expects a packed array of only addresses. */
3324 i = 0;
3325 netdev_for_each_mc_addr(ha, netdev)
3326 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3327
3328 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3329 kfree(mta_list);
3330
3331 return netdev_mc_count(netdev);
3332 }
3333
3334 /**
3335 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3336 * @netdev: network interface device structure
3337 *
3338 * Writes unicast address list to the RAR table.
3339 * Returns: -ENOMEM on failure/insufficient address space
3340 * 0 on no addresses written
3341 * X on writing X addresses to the RAR table
3342 **/
e1000e_write_uc_addr_list(struct net_device * netdev)3343 static int e1000e_write_uc_addr_list(struct net_device *netdev)
3344 {
3345 struct e1000_adapter *adapter = netdev_priv(netdev);
3346 struct e1000_hw *hw = &adapter->hw;
3347 unsigned int rar_entries;
3348 int count = 0;
3349
3350 rar_entries = hw->mac.ops.rar_get_count(hw);
3351
3352 /* save a rar entry for our hardware address */
3353 rar_entries--;
3354
3355 /* save a rar entry for the LAA workaround */
3356 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3357 rar_entries--;
3358
3359 /* return ENOMEM indicating insufficient memory for addresses */
3360 if (netdev_uc_count(netdev) > rar_entries)
3361 return -ENOMEM;
3362
3363 if (!netdev_uc_empty(netdev) && rar_entries) {
3364 struct netdev_hw_addr *ha;
3365
3366 /* write the addresses in reverse order to avoid write
3367 * combining
3368 */
3369 netdev_for_each_uc_addr(ha, netdev) {
3370 int ret_val;
3371
3372 if (!rar_entries)
3373 break;
3374 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3375 if (ret_val < 0)
3376 return -ENOMEM;
3377 count++;
3378 }
3379 }
3380
3381 /* zero out the remaining RAR entries not used above */
3382 for (; rar_entries > 0; rar_entries--) {
3383 ew32(RAH(rar_entries), 0);
3384 ew32(RAL(rar_entries), 0);
3385 }
3386 e1e_flush();
3387
3388 return count;
3389 }
3390
3391 /**
3392 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3393 * @netdev: network interface device structure
3394 *
3395 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3396 * address list or the network interface flags are updated. This routine is
3397 * responsible for configuring the hardware for proper unicast, multicast,
3398 * promiscuous mode, and all-multi behavior.
3399 **/
e1000e_set_rx_mode(struct net_device * netdev)3400 static void e1000e_set_rx_mode(struct net_device *netdev)
3401 {
3402 struct e1000_adapter *adapter = netdev_priv(netdev);
3403 struct e1000_hw *hw = &adapter->hw;
3404 u32 rctl;
3405
3406 if (pm_runtime_suspended(netdev->dev.parent))
3407 return;
3408
3409 /* Check for Promiscuous and All Multicast modes */
3410 rctl = er32(RCTL);
3411
3412 /* clear the affected bits */
3413 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3414
3415 if (netdev->flags & IFF_PROMISC) {
3416 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3417 /* Do not hardware filter VLANs in promisc mode */
3418 e1000e_vlan_filter_disable(adapter);
3419 } else {
3420 int count;
3421
3422 if (netdev->flags & IFF_ALLMULTI) {
3423 rctl |= E1000_RCTL_MPE;
3424 } else {
3425 /* Write addresses to the MTA, if the attempt fails
3426 * then we should just turn on promiscuous mode so
3427 * that we can at least receive multicast traffic
3428 */
3429 count = e1000e_write_mc_addr_list(netdev);
3430 if (count < 0)
3431 rctl |= E1000_RCTL_MPE;
3432 }
3433 e1000e_vlan_filter_enable(adapter);
3434 /* Write addresses to available RAR registers, if there is not
3435 * sufficient space to store all the addresses then enable
3436 * unicast promiscuous mode
3437 */
3438 count = e1000e_write_uc_addr_list(netdev);
3439 if (count < 0)
3440 rctl |= E1000_RCTL_UPE;
3441 }
3442
3443 ew32(RCTL, rctl);
3444
3445 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3446 e1000e_vlan_strip_enable(adapter);
3447 else
3448 e1000e_vlan_strip_disable(adapter);
3449 }
3450
e1000e_setup_rss_hash(struct e1000_adapter * adapter)3451 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3452 {
3453 struct e1000_hw *hw = &adapter->hw;
3454 u32 mrqc, rxcsum;
3455 u32 rss_key[10];
3456 int i;
3457
3458 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3459 for (i = 0; i < 10; i++)
3460 ew32(RSSRK(i), rss_key[i]);
3461
3462 /* Direct all traffic to queue 0 */
3463 for (i = 0; i < 32; i++)
3464 ew32(RETA(i), 0);
3465
3466 /* Disable raw packet checksumming so that RSS hash is placed in
3467 * descriptor on writeback.
3468 */
3469 rxcsum = er32(RXCSUM);
3470 rxcsum |= E1000_RXCSUM_PCSD;
3471
3472 ew32(RXCSUM, rxcsum);
3473
3474 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3475 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3476 E1000_MRQC_RSS_FIELD_IPV6 |
3477 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3478 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3479
3480 ew32(MRQC, mrqc);
3481 }
3482
3483 /**
3484 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3485 * @adapter: board private structure
3486 * @timinca: pointer to returned time increment attributes
3487 *
3488 * Get attributes for incrementing the System Time Register SYSTIML/H at
3489 * the default base frequency, and set the cyclecounter shift value.
3490 **/
e1000e_get_base_timinca(struct e1000_adapter * adapter,u32 * timinca)3491 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3492 {
3493 struct e1000_hw *hw = &adapter->hw;
3494 u32 incvalue, incperiod, shift;
3495
3496 /* Make sure clock is enabled on I217/I218/I219 before checking
3497 * the frequency
3498 */
3499 if ((hw->mac.type >= e1000_pch_lpt) &&
3500 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3501 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3502 u32 fextnvm7 = er32(FEXTNVM7);
3503
3504 if (!(fextnvm7 & BIT(0))) {
3505 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3506 e1e_flush();
3507 }
3508 }
3509
3510 switch (hw->mac.type) {
3511 case e1000_pch2lan:
3512 /* Stable 96MHz frequency */
3513 incperiod = INCPERIOD_96MHZ;
3514 incvalue = INCVALUE_96MHZ;
3515 shift = INCVALUE_SHIFT_96MHZ;
3516 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3517 break;
3518 case e1000_pch_lpt:
3519 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3520 /* Stable 96MHz frequency */
3521 incperiod = INCPERIOD_96MHZ;
3522 incvalue = INCVALUE_96MHZ;
3523 shift = INCVALUE_SHIFT_96MHZ;
3524 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3525 } else {
3526 /* Stable 25MHz frequency */
3527 incperiod = INCPERIOD_25MHZ;
3528 incvalue = INCVALUE_25MHZ;
3529 shift = INCVALUE_SHIFT_25MHZ;
3530 adapter->cc.shift = shift;
3531 }
3532 break;
3533 case e1000_pch_spt:
3534 /* Stable 24MHz frequency */
3535 incperiod = INCPERIOD_24MHZ;
3536 incvalue = INCVALUE_24MHZ;
3537 shift = INCVALUE_SHIFT_24MHZ;
3538 adapter->cc.shift = shift;
3539 break;
3540 case e1000_pch_cnp:
3541 case e1000_pch_tgp:
3542 case e1000_pch_adp:
3543 case e1000_pch_nvp:
3544 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3545 /* Stable 24MHz frequency */
3546 incperiod = INCPERIOD_24MHZ;
3547 incvalue = INCVALUE_24MHZ;
3548 shift = INCVALUE_SHIFT_24MHZ;
3549 adapter->cc.shift = shift;
3550 } else {
3551 /* Stable 38400KHz frequency */
3552 incperiod = INCPERIOD_38400KHZ;
3553 incvalue = INCVALUE_38400KHZ;
3554 shift = INCVALUE_SHIFT_38400KHZ;
3555 adapter->cc.shift = shift;
3556 }
3557 break;
3558 case e1000_pch_mtp:
3559 case e1000_pch_lnp:
3560 case e1000_pch_ptp:
3561 /* System firmware can misreport this value, so set it to a
3562 * stable 38400KHz frequency.
3563 */
3564 incperiod = INCPERIOD_38400KHZ;
3565 incvalue = INCVALUE_38400KHZ;
3566 shift = INCVALUE_SHIFT_38400KHZ;
3567 adapter->cc.shift = shift;
3568 break;
3569 case e1000_82574:
3570 case e1000_82583:
3571 /* Stable 25MHz frequency */
3572 incperiod = INCPERIOD_25MHZ;
3573 incvalue = INCVALUE_25MHZ;
3574 shift = INCVALUE_SHIFT_25MHZ;
3575 adapter->cc.shift = shift;
3576 break;
3577 default:
3578 return -EINVAL;
3579 }
3580
3581 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3582 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3583
3584 return 0;
3585 }
3586
3587 /**
3588 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3589 * @adapter: board private structure
3590 * @config: timestamp configuration
3591 *
3592 * Outgoing time stamping can be enabled and disabled. Play nice and
3593 * disable it when requested, although it shouldn't cause any overhead
3594 * when no packet needs it. At most one packet in the queue may be
3595 * marked for time stamping, otherwise it would be impossible to tell
3596 * for sure to which packet the hardware time stamp belongs.
3597 *
3598 * Incoming time stamping has to be configured via the hardware filters.
3599 * Not all combinations are supported, in particular event type has to be
3600 * specified. Matching the kind of event packet is not supported, with the
3601 * exception of "all V2 events regardless of level 2 or 4".
3602 **/
e1000e_config_hwtstamp(struct e1000_adapter * adapter,struct hwtstamp_config * config)3603 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3604 struct hwtstamp_config *config)
3605 {
3606 struct e1000_hw *hw = &adapter->hw;
3607 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3608 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3609 u32 rxmtrl = 0;
3610 u16 rxudp = 0;
3611 bool is_l4 = false;
3612 bool is_l2 = false;
3613 u32 regval;
3614
3615 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3616 return -EINVAL;
3617
3618 switch (config->tx_type) {
3619 case HWTSTAMP_TX_OFF:
3620 tsync_tx_ctl = 0;
3621 break;
3622 case HWTSTAMP_TX_ON:
3623 break;
3624 default:
3625 return -ERANGE;
3626 }
3627
3628 switch (config->rx_filter) {
3629 case HWTSTAMP_FILTER_NONE:
3630 tsync_rx_ctl = 0;
3631 break;
3632 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3633 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3634 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3635 is_l4 = true;
3636 break;
3637 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3638 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3639 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3640 is_l4 = true;
3641 break;
3642 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3643 /* Also time stamps V2 L2 Path Delay Request/Response */
3644 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3645 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3646 is_l2 = true;
3647 break;
3648 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3649 /* Also time stamps V2 L2 Path Delay Request/Response. */
3650 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3651 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3652 is_l2 = true;
3653 break;
3654 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3655 /* Hardware cannot filter just V2 L4 Sync messages */
3656 fallthrough;
3657 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3658 /* Also time stamps V2 Path Delay Request/Response. */
3659 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3660 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3661 is_l2 = true;
3662 is_l4 = true;
3663 break;
3664 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3665 /* Hardware cannot filter just V2 L4 Delay Request messages */
3666 fallthrough;
3667 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3668 /* Also time stamps V2 Path Delay Request/Response. */
3669 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3670 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3671 is_l2 = true;
3672 is_l4 = true;
3673 break;
3674 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3675 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3676 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3677 fallthrough;
3678 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3679 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3680 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3681 is_l2 = true;
3682 is_l4 = true;
3683 break;
3684 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3685 /* For V1, the hardware can only filter Sync messages or
3686 * Delay Request messages but not both so fall-through to
3687 * time stamp all packets.
3688 */
3689 fallthrough;
3690 case HWTSTAMP_FILTER_NTP_ALL:
3691 case HWTSTAMP_FILTER_ALL:
3692 is_l2 = true;
3693 is_l4 = true;
3694 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3695 config->rx_filter = HWTSTAMP_FILTER_ALL;
3696 break;
3697 default:
3698 return -ERANGE;
3699 }
3700
3701 adapter->hwtstamp_config = *config;
3702
3703 /* enable/disable Tx h/w time stamping */
3704 regval = er32(TSYNCTXCTL);
3705 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3706 regval |= tsync_tx_ctl;
3707 ew32(TSYNCTXCTL, regval);
3708 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3709 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3710 e_err("Timesync Tx Control register not set as expected\n");
3711 return -EAGAIN;
3712 }
3713
3714 /* enable/disable Rx h/w time stamping */
3715 regval = er32(TSYNCRXCTL);
3716 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3717 regval |= tsync_rx_ctl;
3718 ew32(TSYNCRXCTL, regval);
3719 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3720 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3721 (regval & (E1000_TSYNCRXCTL_ENABLED |
3722 E1000_TSYNCRXCTL_TYPE_MASK))) {
3723 e_err("Timesync Rx Control register not set as expected\n");
3724 return -EAGAIN;
3725 }
3726
3727 /* L2: define ethertype filter for time stamped packets */
3728 if (is_l2)
3729 rxmtrl |= ETH_P_1588;
3730
3731 /* define which PTP packets get time stamped */
3732 ew32(RXMTRL, rxmtrl);
3733
3734 /* Filter by destination port */
3735 if (is_l4) {
3736 rxudp = PTP_EV_PORT;
3737 cpu_to_be16s(&rxudp);
3738 }
3739 ew32(RXUDP, rxudp);
3740
3741 e1e_flush();
3742
3743 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3744 er32(RXSTMPH);
3745 er32(TXSTMPH);
3746
3747 return 0;
3748 }
3749
3750 /**
3751 * e1000_configure - configure the hardware for Rx and Tx
3752 * @adapter: private board structure
3753 **/
e1000_configure(struct e1000_adapter * adapter)3754 static void e1000_configure(struct e1000_adapter *adapter)
3755 {
3756 struct e1000_ring *rx_ring = adapter->rx_ring;
3757
3758 e1000e_set_rx_mode(adapter->netdev);
3759
3760 e1000_restore_vlan(adapter);
3761 e1000_init_manageability_pt(adapter);
3762
3763 e1000_configure_tx(adapter);
3764
3765 if (adapter->netdev->features & NETIF_F_RXHASH)
3766 e1000e_setup_rss_hash(adapter);
3767 e1000_setup_rctl(adapter);
3768 e1000_configure_rx(adapter);
3769 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3770 }
3771
3772 /**
3773 * e1000e_power_up_phy - restore link in case the phy was powered down
3774 * @adapter: address of board private structure
3775 *
3776 * The phy may be powered down to save power and turn off link when the
3777 * driver is unloaded and wake on lan is not enabled (among others)
3778 * *** this routine MUST be followed by a call to e1000e_reset ***
3779 **/
e1000e_power_up_phy(struct e1000_adapter * adapter)3780 void e1000e_power_up_phy(struct e1000_adapter *adapter)
3781 {
3782 if (adapter->hw.phy.ops.power_up)
3783 adapter->hw.phy.ops.power_up(&adapter->hw);
3784
3785 adapter->hw.mac.ops.setup_link(&adapter->hw);
3786 }
3787
3788 /**
3789 * e1000_power_down_phy - Power down the PHY
3790 * @adapter: board private structure
3791 *
3792 * Power down the PHY so no link is implied when interface is down.
3793 * The PHY cannot be powered down if management or WoL is active.
3794 */
e1000_power_down_phy(struct e1000_adapter * adapter)3795 static void e1000_power_down_phy(struct e1000_adapter *adapter)
3796 {
3797 if (adapter->hw.phy.ops.power_down)
3798 adapter->hw.phy.ops.power_down(&adapter->hw);
3799 }
3800
3801 /**
3802 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3803 * @adapter: board private structure
3804 *
3805 * We want to clear all pending descriptors from the TX ring.
3806 * zeroing happens when the HW reads the regs. We assign the ring itself as
3807 * the data of the next descriptor. We don't care about the data we are about
3808 * to reset the HW.
3809 */
e1000_flush_tx_ring(struct e1000_adapter * adapter)3810 static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3811 {
3812 struct e1000_hw *hw = &adapter->hw;
3813 struct e1000_ring *tx_ring = adapter->tx_ring;
3814 struct e1000_tx_desc *tx_desc = NULL;
3815 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3816 u16 size = 512;
3817
3818 tctl = er32(TCTL);
3819 ew32(TCTL, tctl | E1000_TCTL_EN);
3820 tdt = er32(TDT(0));
3821 BUG_ON(tdt != tx_ring->next_to_use);
3822 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3823 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
3824
3825 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3826 tx_desc->upper.data = 0;
3827 /* flush descriptors to memory before notifying the HW */
3828 wmb();
3829 tx_ring->next_to_use++;
3830 if (tx_ring->next_to_use == tx_ring->count)
3831 tx_ring->next_to_use = 0;
3832 ew32(TDT(0), tx_ring->next_to_use);
3833 usleep_range(200, 250);
3834 }
3835
3836 /**
3837 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3838 * @adapter: board private structure
3839 *
3840 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3841 */
e1000_flush_rx_ring(struct e1000_adapter * adapter)3842 static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3843 {
3844 u32 rctl, rxdctl;
3845 struct e1000_hw *hw = &adapter->hw;
3846
3847 rctl = er32(RCTL);
3848 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3849 e1e_flush();
3850 usleep_range(100, 150);
3851
3852 rxdctl = er32(RXDCTL(0));
3853 /* zero the lower 14 bits (prefetch and host thresholds) */
3854 rxdctl &= 0xffffc000;
3855
3856 /* update thresholds: prefetch threshold to 31, host threshold to 1
3857 * and make sure the granularity is "descriptors" and not "cache lines"
3858 */
3859 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3860
3861 ew32(RXDCTL(0), rxdctl);
3862 /* momentarily enable the RX ring for the changes to take effect */
3863 ew32(RCTL, rctl | E1000_RCTL_EN);
3864 e1e_flush();
3865 usleep_range(100, 150);
3866 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3867 }
3868
3869 /**
3870 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3871 * @adapter: board private structure
3872 *
3873 * In i219, the descriptor rings must be emptied before resetting the HW
3874 * or before changing the device state to D3 during runtime (runtime PM).
3875 *
3876 * Failure to do this will cause the HW to enter a unit hang state which can
3877 * only be released by PCI reset on the device
3878 *
3879 */
3880
e1000_flush_desc_rings(struct e1000_adapter * adapter)3881 static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3882 {
3883 u16 hang_state;
3884 u32 fext_nvm11, tdlen;
3885 struct e1000_hw *hw = &adapter->hw;
3886
3887 /* First, disable MULR fix in FEXTNVM11 */
3888 fext_nvm11 = er32(FEXTNVM11);
3889 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3890 ew32(FEXTNVM11, fext_nvm11);
3891 /* do nothing if we're not in faulty state, or if the queue is empty */
3892 tdlen = er32(TDLEN(0));
3893 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3894 &hang_state);
3895 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3896 return;
3897 e1000_flush_tx_ring(adapter);
3898 /* recheck, maybe the fault is caused by the rx ring */
3899 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3900 &hang_state);
3901 if (hang_state & FLUSH_DESC_REQUIRED)
3902 e1000_flush_rx_ring(adapter);
3903 }
3904
3905 /**
3906 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3907 * @adapter: board private structure
3908 *
3909 * When the MAC is reset, all hardware bits for timesync will be reset to the
3910 * default values. This function will restore the settings last in place.
3911 * Since the clock SYSTIME registers are reset, we will simply restore the
3912 * cyclecounter to the kernel real clock time.
3913 **/
e1000e_systim_reset(struct e1000_adapter * adapter)3914 static void e1000e_systim_reset(struct e1000_adapter *adapter)
3915 {
3916 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3917 struct e1000_hw *hw = &adapter->hw;
3918 unsigned long flags;
3919 u32 timinca;
3920 s32 ret_val;
3921
3922 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3923 return;
3924
3925 if (info->adjfine) {
3926 /* restore the previous ptp frequency delta */
3927 ret_val = info->adjfine(info, adapter->ptp_delta);
3928 } else {
3929 /* set the default base frequency if no adjustment possible */
3930 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3931 if (!ret_val)
3932 ew32(TIMINCA, timinca);
3933 }
3934
3935 if (ret_val) {
3936 dev_warn(&adapter->pdev->dev,
3937 "Failed to restore TIMINCA clock rate delta: %d\n",
3938 ret_val);
3939 return;
3940 }
3941
3942 /* reset the systim ns time counter */
3943 spin_lock_irqsave(&adapter->systim_lock, flags);
3944 timecounter_init(&adapter->tc, &adapter->cc,
3945 ktime_to_ns(ktime_get_real()));
3946 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3947
3948 /* restore the previous hwtstamp configuration settings */
3949 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3950 }
3951
3952 /**
3953 * e1000e_reset - bring the hardware into a known good state
3954 * @adapter: board private structure
3955 *
3956 * This function boots the hardware and enables some settings that
3957 * require a configuration cycle of the hardware - those cannot be
3958 * set/changed during runtime. After reset the device needs to be
3959 * properly configured for Rx, Tx etc.
3960 */
e1000e_reset(struct e1000_adapter * adapter)3961 void e1000e_reset(struct e1000_adapter *adapter)
3962 {
3963 struct e1000_mac_info *mac = &adapter->hw.mac;
3964 struct e1000_fc_info *fc = &adapter->hw.fc;
3965 struct e1000_hw *hw = &adapter->hw;
3966 u32 tx_space, min_tx_space, min_rx_space;
3967 u32 pba = adapter->pba;
3968 u16 hwm;
3969
3970 /* reset Packet Buffer Allocation to default */
3971 ew32(PBA, pba);
3972
3973 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3974 /* To maintain wire speed transmits, the Tx FIFO should be
3975 * large enough to accommodate two full transmit packets,
3976 * rounded up to the next 1KB and expressed in KB. Likewise,
3977 * the Rx FIFO should be large enough to accommodate at least
3978 * one full receive packet and is similarly rounded up and
3979 * expressed in KB.
3980 */
3981 pba = er32(PBA);
3982 /* upper 16 bits has Tx packet buffer allocation size in KB */
3983 tx_space = pba >> 16;
3984 /* lower 16 bits has Rx packet buffer allocation size in KB */
3985 pba &= 0xffff;
3986 /* the Tx fifo also stores 16 bytes of information about the Tx
3987 * but don't include ethernet FCS because hardware appends it
3988 */
3989 min_tx_space = (adapter->max_frame_size +
3990 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3991 min_tx_space = ALIGN(min_tx_space, 1024);
3992 min_tx_space >>= 10;
3993 /* software strips receive CRC, so leave room for it */
3994 min_rx_space = adapter->max_frame_size;
3995 min_rx_space = ALIGN(min_rx_space, 1024);
3996 min_rx_space >>= 10;
3997
3998 /* If current Tx allocation is less than the min Tx FIFO size,
3999 * and the min Tx FIFO size is less than the current Rx FIFO
4000 * allocation, take space away from current Rx allocation
4001 */
4002 if ((tx_space < min_tx_space) &&
4003 ((min_tx_space - tx_space) < pba)) {
4004 pba -= min_tx_space - tx_space;
4005
4006 /* if short on Rx space, Rx wins and must trump Tx
4007 * adjustment
4008 */
4009 if (pba < min_rx_space)
4010 pba = min_rx_space;
4011 }
4012
4013 ew32(PBA, pba);
4014 }
4015
4016 /* flow control settings
4017 *
4018 * The high water mark must be low enough to fit one full frame
4019 * (or the size used for early receive) above it in the Rx FIFO.
4020 * Set it to the lower of:
4021 * - 90% of the Rx FIFO size, and
4022 * - the full Rx FIFO size minus one full frame
4023 */
4024 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4025 fc->pause_time = 0xFFFF;
4026 else
4027 fc->pause_time = E1000_FC_PAUSE_TIME;
4028 fc->send_xon = true;
4029 fc->current_mode = fc->requested_mode;
4030
4031 switch (hw->mac.type) {
4032 case e1000_ich9lan:
4033 case e1000_ich10lan:
4034 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4035 pba = 14;
4036 ew32(PBA, pba);
4037 fc->high_water = 0x2800;
4038 fc->low_water = fc->high_water - 8;
4039 break;
4040 }
4041 fallthrough;
4042 default:
4043 hwm = min(((pba << 10) * 9 / 10),
4044 ((pba << 10) - adapter->max_frame_size));
4045
4046 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4047 fc->low_water = fc->high_water - 8;
4048 break;
4049 case e1000_pchlan:
4050 /* Workaround PCH LOM adapter hangs with certain network
4051 * loads. If hangs persist, try disabling Tx flow control.
4052 */
4053 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4054 fc->high_water = 0x3500;
4055 fc->low_water = 0x1500;
4056 } else {
4057 fc->high_water = 0x5000;
4058 fc->low_water = 0x3000;
4059 }
4060 fc->refresh_time = 0x1000;
4061 break;
4062 case e1000_pch2lan:
4063 case e1000_pch_lpt:
4064 case e1000_pch_spt:
4065 case e1000_pch_cnp:
4066 case e1000_pch_tgp:
4067 case e1000_pch_adp:
4068 case e1000_pch_mtp:
4069 case e1000_pch_lnp:
4070 case e1000_pch_ptp:
4071 case e1000_pch_nvp:
4072 fc->refresh_time = 0xFFFF;
4073 fc->pause_time = 0xFFFF;
4074
4075 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4076 fc->high_water = 0x05C20;
4077 fc->low_water = 0x05048;
4078 break;
4079 }
4080
4081 pba = 14;
4082 ew32(PBA, pba);
4083 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4084 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4085 break;
4086 }
4087
4088 /* Alignment of Tx data is on an arbitrary byte boundary with the
4089 * maximum size per Tx descriptor limited only to the transmit
4090 * allocation of the packet buffer minus 96 bytes with an upper
4091 * limit of 24KB due to receive synchronization limitations.
4092 */
4093 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4094 24 << 10);
4095
4096 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4097 * fit in receive buffer.
4098 */
4099 if (adapter->itr_setting & 0x3) {
4100 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4101 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4102 dev_info(&adapter->pdev->dev,
4103 "Interrupt Throttle Rate off\n");
4104 adapter->flags2 |= FLAG2_DISABLE_AIM;
4105 e1000e_write_itr(adapter, 0);
4106 }
4107 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4108 dev_info(&adapter->pdev->dev,
4109 "Interrupt Throttle Rate on\n");
4110 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4111 adapter->itr = 20000;
4112 e1000e_write_itr(adapter, adapter->itr);
4113 }
4114 }
4115
4116 if (hw->mac.type >= e1000_pch_spt)
4117 e1000_flush_desc_rings(adapter);
4118 /* Allow time for pending master requests to run */
4119 mac->ops.reset_hw(hw);
4120
4121 /* For parts with AMT enabled, let the firmware know
4122 * that the network interface is in control
4123 */
4124 if (adapter->flags & FLAG_HAS_AMT)
4125 e1000e_get_hw_control(adapter);
4126
4127 ew32(WUC, 0);
4128
4129 if (mac->ops.init_hw(hw))
4130 e_err("Hardware Error\n");
4131
4132 e1000_update_mng_vlan(adapter);
4133
4134 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4135 ew32(VET, ETH_P_8021Q);
4136
4137 e1000e_reset_adaptive(hw);
4138
4139 /* restore systim and hwtstamp settings */
4140 e1000e_systim_reset(adapter);
4141
4142 /* Set EEE advertisement as appropriate */
4143 if (adapter->flags2 & FLAG2_HAS_EEE) {
4144 s32 ret_val;
4145 u16 adv_addr;
4146
4147 switch (hw->phy.type) {
4148 case e1000_phy_82579:
4149 adv_addr = I82579_EEE_ADVERTISEMENT;
4150 break;
4151 case e1000_phy_i217:
4152 adv_addr = I217_EEE_ADVERTISEMENT;
4153 break;
4154 default:
4155 dev_err(&adapter->pdev->dev,
4156 "Invalid PHY type setting EEE advertisement\n");
4157 return;
4158 }
4159
4160 ret_val = hw->phy.ops.acquire(hw);
4161 if (ret_val) {
4162 dev_err(&adapter->pdev->dev,
4163 "EEE advertisement - unable to acquire PHY\n");
4164 return;
4165 }
4166
4167 e1000_write_emi_reg_locked(hw, adv_addr,
4168 hw->dev_spec.ich8lan.eee_disable ?
4169 0 : adapter->eee_advert);
4170
4171 hw->phy.ops.release(hw);
4172 }
4173
4174 if (!netif_running(adapter->netdev) &&
4175 !test_bit(__E1000_TESTING, &adapter->state))
4176 e1000_power_down_phy(adapter);
4177
4178 e1000_get_phy_info(hw);
4179
4180 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4181 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4182 u16 phy_data = 0;
4183 /* speed up time to link by disabling smart power down, ignore
4184 * the return value of this function because there is nothing
4185 * different we would do if it failed
4186 */
4187 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4188 phy_data &= ~IGP02E1000_PM_SPD;
4189 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4190 }
4191 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4192 u32 reg;
4193
4194 /* Fextnvm7 @ 0xe4[2] = 1 */
4195 reg = er32(FEXTNVM7);
4196 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4197 ew32(FEXTNVM7, reg);
4198 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4199 reg = er32(FEXTNVM9);
4200 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4201 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4202 ew32(FEXTNVM9, reg);
4203 }
4204
4205 }
4206
4207 /**
4208 * e1000e_trigger_lsc - trigger an LSC interrupt
4209 * @adapter: board private structure
4210 *
4211 * Fire a link status change interrupt to start the watchdog.
4212 **/
e1000e_trigger_lsc(struct e1000_adapter * adapter)4213 static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4214 {
4215 struct e1000_hw *hw = &adapter->hw;
4216
4217 if (adapter->msix_entries)
4218 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4219 else
4220 ew32(ICS, E1000_ICS_LSC);
4221 }
4222
e1000e_up(struct e1000_adapter * adapter)4223 void e1000e_up(struct e1000_adapter *adapter)
4224 {
4225 /* hardware has been reset, we need to reload some things */
4226 e1000_configure(adapter);
4227
4228 clear_bit(__E1000_DOWN, &adapter->state);
4229
4230 if (adapter->msix_entries)
4231 e1000_configure_msix(adapter);
4232 e1000_irq_enable(adapter);
4233
4234 /* Tx queue started by watchdog timer when link is up */
4235
4236 e1000e_trigger_lsc(adapter);
4237 }
4238
e1000e_flush_descriptors(struct e1000_adapter * adapter)4239 static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4240 {
4241 struct e1000_hw *hw = &adapter->hw;
4242
4243 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4244 return;
4245
4246 /* flush pending descriptor writebacks to memory */
4247 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4248 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4249
4250 /* execute the writes immediately */
4251 e1e_flush();
4252
4253 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4254 * write is successful
4255 */
4256 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4257 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4258
4259 /* execute the writes immediately */
4260 e1e_flush();
4261 }
4262
4263 static void e1000e_update_stats(struct e1000_adapter *adapter);
4264
4265 /**
4266 * e1000e_down - quiesce the device and optionally reset the hardware
4267 * @adapter: board private structure
4268 * @reset: boolean flag to reset the hardware or not
4269 */
e1000e_down(struct e1000_adapter * adapter,bool reset)4270 void e1000e_down(struct e1000_adapter *adapter, bool reset)
4271 {
4272 struct net_device *netdev = adapter->netdev;
4273 struct e1000_hw *hw = &adapter->hw;
4274 u32 tctl, rctl;
4275
4276 /* signal that we're down so the interrupt handler does not
4277 * reschedule our watchdog timer
4278 */
4279 set_bit(__E1000_DOWN, &adapter->state);
4280
4281 netif_carrier_off(netdev);
4282
4283 /* disable receives in the hardware */
4284 rctl = er32(RCTL);
4285 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4286 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4287 /* flush and sleep below */
4288
4289 netif_stop_queue(netdev);
4290
4291 /* disable transmits in the hardware */
4292 tctl = er32(TCTL);
4293 tctl &= ~E1000_TCTL_EN;
4294 ew32(TCTL, tctl);
4295
4296 /* flush both disables and wait for them to finish */
4297 e1e_flush();
4298 usleep_range(10000, 11000);
4299
4300 e1000_irq_disable(adapter);
4301
4302 napi_synchronize(&adapter->napi);
4303
4304 del_timer_sync(&adapter->watchdog_timer);
4305 del_timer_sync(&adapter->phy_info_timer);
4306
4307 spin_lock(&adapter->stats64_lock);
4308 e1000e_update_stats(adapter);
4309 spin_unlock(&adapter->stats64_lock);
4310
4311 e1000e_flush_descriptors(adapter);
4312
4313 adapter->link_speed = 0;
4314 adapter->link_duplex = 0;
4315
4316 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4317 if ((hw->mac.type >= e1000_pch2lan) &&
4318 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4319 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4320 e_dbg("failed to disable jumbo frame workaround mode\n");
4321
4322 if (!pci_channel_offline(adapter->pdev)) {
4323 if (reset)
4324 e1000e_reset(adapter);
4325 else if (hw->mac.type >= e1000_pch_spt)
4326 e1000_flush_desc_rings(adapter);
4327 }
4328 e1000_clean_tx_ring(adapter->tx_ring);
4329 e1000_clean_rx_ring(adapter->rx_ring);
4330 }
4331
e1000e_reinit_locked(struct e1000_adapter * adapter)4332 void e1000e_reinit_locked(struct e1000_adapter *adapter)
4333 {
4334 might_sleep();
4335 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4336 usleep_range(1000, 1100);
4337 e1000e_down(adapter, true);
4338 e1000e_up(adapter);
4339 clear_bit(__E1000_RESETTING, &adapter->state);
4340 }
4341
4342 /**
4343 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4344 * @hw: pointer to the HW structure
4345 * @systim: PHC time value read, sanitized and returned
4346 * @sts: structure to hold system time before and after reading SYSTIML,
4347 * may be NULL
4348 *
4349 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4350 * check to see that the time is incrementing at a reasonable
4351 * rate and is a multiple of incvalue.
4352 **/
e1000e_sanitize_systim(struct e1000_hw * hw,u64 systim,struct ptp_system_timestamp * sts)4353 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4354 struct ptp_system_timestamp *sts)
4355 {
4356 u64 time_delta, rem, temp;
4357 u64 systim_next;
4358 u32 incvalue;
4359 int i;
4360
4361 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4362 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4363 /* latch SYSTIMH on read of SYSTIML */
4364 ptp_read_system_prets(sts);
4365 systim_next = (u64)er32(SYSTIML);
4366 ptp_read_system_postts(sts);
4367 systim_next |= (u64)er32(SYSTIMH) << 32;
4368
4369 time_delta = systim_next - systim;
4370 temp = time_delta;
4371 /* VMWare users have seen incvalue of zero, don't div / 0 */
4372 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4373
4374 systim = systim_next;
4375
4376 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4377 break;
4378 }
4379
4380 return systim;
4381 }
4382
4383 /**
4384 * e1000e_read_systim - read SYSTIM register
4385 * @adapter: board private structure
4386 * @sts: structure which will contain system time before and after reading
4387 * SYSTIML, may be NULL
4388 **/
e1000e_read_systim(struct e1000_adapter * adapter,struct ptp_system_timestamp * sts)4389 u64 e1000e_read_systim(struct e1000_adapter *adapter,
4390 struct ptp_system_timestamp *sts)
4391 {
4392 struct e1000_hw *hw = &adapter->hw;
4393 u32 systimel, systimel_2, systimeh;
4394 u64 systim;
4395 /* SYSTIMH latching upon SYSTIML read does not work well.
4396 * This means that if SYSTIML overflows after we read it but before
4397 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4398 * will experience a huge non linear increment in the systime value
4399 * to fix that we test for overflow and if true, we re-read systime.
4400 */
4401 ptp_read_system_prets(sts);
4402 systimel = er32(SYSTIML);
4403 ptp_read_system_postts(sts);
4404 systimeh = er32(SYSTIMH);
4405 /* Is systimel is so large that overflow is possible? */
4406 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4407 ptp_read_system_prets(sts);
4408 systimel_2 = er32(SYSTIML);
4409 ptp_read_system_postts(sts);
4410 if (systimel > systimel_2) {
4411 /* There was an overflow, read again SYSTIMH, and use
4412 * systimel_2
4413 */
4414 systimeh = er32(SYSTIMH);
4415 systimel = systimel_2;
4416 }
4417 }
4418 systim = (u64)systimel;
4419 systim |= (u64)systimeh << 32;
4420
4421 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4422 systim = e1000e_sanitize_systim(hw, systim, sts);
4423
4424 return systim;
4425 }
4426
4427 /**
4428 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4429 * @cc: cyclecounter structure
4430 **/
e1000e_cyclecounter_read(const struct cyclecounter * cc)4431 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4432 {
4433 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4434 cc);
4435
4436 return e1000e_read_systim(adapter, NULL);
4437 }
4438
4439 /**
4440 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4441 * @adapter: board private structure to initialize
4442 *
4443 * e1000_sw_init initializes the Adapter private data structure.
4444 * Fields are initialized based on PCI device information and
4445 * OS network device settings (MTU size).
4446 **/
e1000_sw_init(struct e1000_adapter * adapter)4447 static int e1000_sw_init(struct e1000_adapter *adapter)
4448 {
4449 struct net_device *netdev = adapter->netdev;
4450
4451 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4452 adapter->rx_ps_bsize0 = 128;
4453 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4454 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4455 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4456 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4457
4458 spin_lock_init(&adapter->stats64_lock);
4459
4460 e1000e_set_interrupt_capability(adapter);
4461
4462 if (e1000_alloc_queues(adapter))
4463 return -ENOMEM;
4464
4465 /* Setup hardware time stamping cyclecounter */
4466 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4467 adapter->cc.read = e1000e_cyclecounter_read;
4468 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4469 adapter->cc.mult = 1;
4470 /* cc.shift set in e1000e_get_base_tininca() */
4471
4472 spin_lock_init(&adapter->systim_lock);
4473 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4474 }
4475
4476 /* Explicitly disable IRQ since the NIC can be in any state. */
4477 e1000_irq_disable(adapter);
4478
4479 set_bit(__E1000_DOWN, &adapter->state);
4480 return 0;
4481 }
4482
4483 /**
4484 * e1000_intr_msi_test - Interrupt Handler
4485 * @irq: interrupt number
4486 * @data: pointer to a network interface device structure
4487 **/
e1000_intr_msi_test(int __always_unused irq,void * data)4488 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4489 {
4490 struct net_device *netdev = data;
4491 struct e1000_adapter *adapter = netdev_priv(netdev);
4492 struct e1000_hw *hw = &adapter->hw;
4493 u32 icr = er32(ICR);
4494
4495 e_dbg("icr is %08X\n", icr);
4496 if (icr & E1000_ICR_RXSEQ) {
4497 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4498 /* Force memory writes to complete before acknowledging the
4499 * interrupt is handled.
4500 */
4501 wmb();
4502 }
4503
4504 return IRQ_HANDLED;
4505 }
4506
4507 /**
4508 * e1000_test_msi_interrupt - Returns 0 for successful test
4509 * @adapter: board private struct
4510 *
4511 * code flow taken from tg3.c
4512 **/
e1000_test_msi_interrupt(struct e1000_adapter * adapter)4513 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4514 {
4515 struct net_device *netdev = adapter->netdev;
4516 struct e1000_hw *hw = &adapter->hw;
4517 int err;
4518
4519 /* poll_enable hasn't been called yet, so don't need disable */
4520 /* clear any pending events */
4521 er32(ICR);
4522
4523 /* free the real vector and request a test handler */
4524 e1000_free_irq(adapter);
4525 e1000e_reset_interrupt_capability(adapter);
4526
4527 /* Assume that the test fails, if it succeeds then the test
4528 * MSI irq handler will unset this flag
4529 */
4530 adapter->flags |= FLAG_MSI_TEST_FAILED;
4531
4532 err = pci_enable_msi(adapter->pdev);
4533 if (err)
4534 goto msi_test_failed;
4535
4536 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4537 netdev->name, netdev);
4538 if (err) {
4539 pci_disable_msi(adapter->pdev);
4540 goto msi_test_failed;
4541 }
4542
4543 /* Force memory writes to complete before enabling and firing an
4544 * interrupt.
4545 */
4546 wmb();
4547
4548 e1000_irq_enable(adapter);
4549
4550 /* fire an unusual interrupt on the test handler */
4551 ew32(ICS, E1000_ICS_RXSEQ);
4552 e1e_flush();
4553 msleep(100);
4554
4555 e1000_irq_disable(adapter);
4556
4557 rmb(); /* read flags after interrupt has been fired */
4558
4559 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4560 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4561 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4562 } else {
4563 e_dbg("MSI interrupt test succeeded!\n");
4564 }
4565
4566 free_irq(adapter->pdev->irq, netdev);
4567 pci_disable_msi(adapter->pdev);
4568
4569 msi_test_failed:
4570 e1000e_set_interrupt_capability(adapter);
4571 return e1000_request_irq(adapter);
4572 }
4573
4574 /**
4575 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4576 * @adapter: board private struct
4577 *
4578 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4579 **/
e1000_test_msi(struct e1000_adapter * adapter)4580 static int e1000_test_msi(struct e1000_adapter *adapter)
4581 {
4582 int err;
4583 u16 pci_cmd;
4584
4585 if (!(adapter->flags & FLAG_MSI_ENABLED))
4586 return 0;
4587
4588 /* disable SERR in case the MSI write causes a master abort */
4589 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4590 if (pci_cmd & PCI_COMMAND_SERR)
4591 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4592 pci_cmd & ~PCI_COMMAND_SERR);
4593
4594 err = e1000_test_msi_interrupt(adapter);
4595
4596 /* re-enable SERR */
4597 if (pci_cmd & PCI_COMMAND_SERR) {
4598 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4599 pci_cmd |= PCI_COMMAND_SERR;
4600 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4601 }
4602
4603 return err;
4604 }
4605
4606 /**
4607 * e1000e_open - Called when a network interface is made active
4608 * @netdev: network interface device structure
4609 *
4610 * Returns 0 on success, negative value on failure
4611 *
4612 * The open entry point is called when a network interface is made
4613 * active by the system (IFF_UP). At this point all resources needed
4614 * for transmit and receive operations are allocated, the interrupt
4615 * handler is registered with the OS, the watchdog timer is started,
4616 * and the stack is notified that the interface is ready.
4617 **/
e1000e_open(struct net_device * netdev)4618 int e1000e_open(struct net_device *netdev)
4619 {
4620 struct e1000_adapter *adapter = netdev_priv(netdev);
4621 struct e1000_hw *hw = &adapter->hw;
4622 struct pci_dev *pdev = adapter->pdev;
4623 int err;
4624
4625 /* disallow open during test */
4626 if (test_bit(__E1000_TESTING, &adapter->state))
4627 return -EBUSY;
4628
4629 pm_runtime_get_sync(&pdev->dev);
4630
4631 netif_carrier_off(netdev);
4632 netif_stop_queue(netdev);
4633
4634 /* allocate transmit descriptors */
4635 err = e1000e_setup_tx_resources(adapter->tx_ring);
4636 if (err)
4637 goto err_setup_tx;
4638
4639 /* allocate receive descriptors */
4640 err = e1000e_setup_rx_resources(adapter->rx_ring);
4641 if (err)
4642 goto err_setup_rx;
4643
4644 /* If AMT is enabled, let the firmware know that the network
4645 * interface is now open and reset the part to a known state.
4646 */
4647 if (adapter->flags & FLAG_HAS_AMT) {
4648 e1000e_get_hw_control(adapter);
4649 e1000e_reset(adapter);
4650 }
4651
4652 e1000e_power_up_phy(adapter);
4653
4654 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4655 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4656 e1000_update_mng_vlan(adapter);
4657
4658 /* DMA latency requirement to workaround jumbo issue */
4659 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
4660
4661 /* before we allocate an interrupt, we must be ready to handle it.
4662 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4663 * as soon as we call pci_request_irq, so we have to setup our
4664 * clean_rx handler before we do so.
4665 */
4666 e1000_configure(adapter);
4667
4668 err = e1000_request_irq(adapter);
4669 if (err)
4670 goto err_req_irq;
4671
4672 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4673 * ignore e1000e MSI messages, which means we need to test our MSI
4674 * interrupt now
4675 */
4676 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4677 err = e1000_test_msi(adapter);
4678 if (err) {
4679 e_err("Interrupt allocation failed\n");
4680 goto err_req_irq;
4681 }
4682 }
4683
4684 /* From here on the code is the same as e1000e_up() */
4685 clear_bit(__E1000_DOWN, &adapter->state);
4686
4687 napi_enable(&adapter->napi);
4688
4689 e1000_irq_enable(adapter);
4690
4691 adapter->tx_hang_recheck = false;
4692
4693 hw->mac.get_link_status = true;
4694 pm_runtime_put(&pdev->dev);
4695
4696 e1000e_trigger_lsc(adapter);
4697
4698 return 0;
4699
4700 err_req_irq:
4701 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4702 e1000e_release_hw_control(adapter);
4703 e1000_power_down_phy(adapter);
4704 e1000e_free_rx_resources(adapter->rx_ring);
4705 err_setup_rx:
4706 e1000e_free_tx_resources(adapter->tx_ring);
4707 err_setup_tx:
4708 e1000e_reset(adapter);
4709 pm_runtime_put_sync(&pdev->dev);
4710
4711 return err;
4712 }
4713
4714 /**
4715 * e1000e_close - Disables a network interface
4716 * @netdev: network interface device structure
4717 *
4718 * Returns 0, this is not allowed to fail
4719 *
4720 * The close entry point is called when an interface is de-activated
4721 * by the OS. The hardware is still under the drivers control, but
4722 * needs to be disabled. A global MAC reset is issued to stop the
4723 * hardware, and all transmit and receive resources are freed.
4724 **/
e1000e_close(struct net_device * netdev)4725 int e1000e_close(struct net_device *netdev)
4726 {
4727 struct e1000_adapter *adapter = netdev_priv(netdev);
4728 struct pci_dev *pdev = adapter->pdev;
4729 int count = E1000_CHECK_RESET_COUNT;
4730
4731 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4732 usleep_range(10000, 11000);
4733
4734 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4735
4736 pm_runtime_get_sync(&pdev->dev);
4737
4738 if (netif_device_present(netdev)) {
4739 e1000e_down(adapter, true);
4740 e1000_free_irq(adapter);
4741
4742 /* Link status message must follow this format */
4743 netdev_info(netdev, "NIC Link is Down\n");
4744 }
4745
4746 napi_disable(&adapter->napi);
4747
4748 e1000e_free_tx_resources(adapter->tx_ring);
4749 e1000e_free_rx_resources(adapter->rx_ring);
4750
4751 /* kill manageability vlan ID if supported, but not if a vlan with
4752 * the same ID is registered on the host OS (let 8021q kill it)
4753 */
4754 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4755 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4756 adapter->mng_vlan_id);
4757
4758 /* If AMT is enabled, let the firmware know that the network
4759 * interface is now closed
4760 */
4761 if ((adapter->flags & FLAG_HAS_AMT) &&
4762 !test_bit(__E1000_TESTING, &adapter->state))
4763 e1000e_release_hw_control(adapter);
4764
4765 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4766
4767 pm_runtime_put_sync(&pdev->dev);
4768
4769 return 0;
4770 }
4771
4772 /**
4773 * e1000_set_mac - Change the Ethernet Address of the NIC
4774 * @netdev: network interface device structure
4775 * @p: pointer to an address structure
4776 *
4777 * Returns 0 on success, negative on failure
4778 **/
e1000_set_mac(struct net_device * netdev,void * p)4779 static int e1000_set_mac(struct net_device *netdev, void *p)
4780 {
4781 struct e1000_adapter *adapter = netdev_priv(netdev);
4782 struct e1000_hw *hw = &adapter->hw;
4783 struct sockaddr *addr = p;
4784
4785 if (!is_valid_ether_addr(addr->sa_data))
4786 return -EADDRNOTAVAIL;
4787
4788 eth_hw_addr_set(netdev, addr->sa_data);
4789 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4790
4791 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4792
4793 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4794 /* activate the work around */
4795 e1000e_set_laa_state_82571(&adapter->hw, 1);
4796
4797 /* Hold a copy of the LAA in RAR[14] This is done so that
4798 * between the time RAR[0] gets clobbered and the time it
4799 * gets fixed (in e1000_watchdog), the actual LAA is in one
4800 * of the RARs and no incoming packets directed to this port
4801 * are dropped. Eventually the LAA will be in RAR[0] and
4802 * RAR[14]
4803 */
4804 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4805 adapter->hw.mac.rar_entry_count - 1);
4806 }
4807
4808 return 0;
4809 }
4810
4811 /**
4812 * e1000e_update_phy_task - work thread to update phy
4813 * @work: pointer to our work struct
4814 *
4815 * this worker thread exists because we must acquire a
4816 * semaphore to read the phy, which we could msleep while
4817 * waiting for it, and we can't msleep in a timer.
4818 **/
e1000e_update_phy_task(struct work_struct * work)4819 static void e1000e_update_phy_task(struct work_struct *work)
4820 {
4821 struct e1000_adapter *adapter = container_of(work,
4822 struct e1000_adapter,
4823 update_phy_task);
4824 struct e1000_hw *hw = &adapter->hw;
4825
4826 if (test_bit(__E1000_DOWN, &adapter->state))
4827 return;
4828
4829 e1000_get_phy_info(hw);
4830
4831 /* Enable EEE on 82579 after link up */
4832 if (hw->phy.type >= e1000_phy_82579)
4833 e1000_set_eee_pchlan(hw);
4834 }
4835
4836 /**
4837 * e1000_update_phy_info - timre call-back to update PHY info
4838 * @t: pointer to timer_list containing private info adapter
4839 *
4840 * Need to wait a few seconds after link up to get diagnostic information from
4841 * the phy
4842 **/
e1000_update_phy_info(struct timer_list * t)4843 static void e1000_update_phy_info(struct timer_list *t)
4844 {
4845 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4846
4847 if (test_bit(__E1000_DOWN, &adapter->state))
4848 return;
4849
4850 schedule_work(&adapter->update_phy_task);
4851 }
4852
4853 /**
4854 * e1000e_update_phy_stats - Update the PHY statistics counters
4855 * @adapter: board private structure
4856 *
4857 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4858 **/
e1000e_update_phy_stats(struct e1000_adapter * adapter)4859 static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4860 {
4861 struct e1000_hw *hw = &adapter->hw;
4862 s32 ret_val;
4863 u16 phy_data;
4864
4865 ret_val = hw->phy.ops.acquire(hw);
4866 if (ret_val)
4867 return;
4868
4869 /* A page set is expensive so check if already on desired page.
4870 * If not, set to the page with the PHY status registers.
4871 */
4872 hw->phy.addr = 1;
4873 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4874 &phy_data);
4875 if (ret_val)
4876 goto release;
4877 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4878 ret_val = hw->phy.ops.set_page(hw,
4879 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4880 if (ret_val)
4881 goto release;
4882 }
4883
4884 /* Single Collision Count */
4885 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4886 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4887 if (!ret_val)
4888 adapter->stats.scc += phy_data;
4889
4890 /* Excessive Collision Count */
4891 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4892 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4893 if (!ret_val)
4894 adapter->stats.ecol += phy_data;
4895
4896 /* Multiple Collision Count */
4897 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4898 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4899 if (!ret_val)
4900 adapter->stats.mcc += phy_data;
4901
4902 /* Late Collision Count */
4903 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4904 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4905 if (!ret_val)
4906 adapter->stats.latecol += phy_data;
4907
4908 /* Collision Count - also used for adaptive IFS */
4909 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4910 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4911 if (!ret_val)
4912 hw->mac.collision_delta = phy_data;
4913
4914 /* Defer Count */
4915 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4916 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4917 if (!ret_val)
4918 adapter->stats.dc += phy_data;
4919
4920 /* Transmit with no CRS */
4921 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4922 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4923 if (!ret_val)
4924 adapter->stats.tncrs += phy_data;
4925
4926 release:
4927 hw->phy.ops.release(hw);
4928 }
4929
4930 /**
4931 * e1000e_update_stats - Update the board statistics counters
4932 * @adapter: board private structure
4933 **/
e1000e_update_stats(struct e1000_adapter * adapter)4934 static void e1000e_update_stats(struct e1000_adapter *adapter)
4935 {
4936 struct net_device *netdev = adapter->netdev;
4937 struct e1000_hw *hw = &adapter->hw;
4938 struct pci_dev *pdev = adapter->pdev;
4939
4940 /* Prevent stats update while adapter is being reset, or if the pci
4941 * connection is down.
4942 */
4943 if (adapter->link_speed == 0)
4944 return;
4945 if (pci_channel_offline(pdev))
4946 return;
4947
4948 adapter->stats.crcerrs += er32(CRCERRS);
4949 adapter->stats.gprc += er32(GPRC);
4950 adapter->stats.gorc += er32(GORCL);
4951 er32(GORCH); /* Clear gorc */
4952 adapter->stats.bprc += er32(BPRC);
4953 adapter->stats.mprc += er32(MPRC);
4954 adapter->stats.roc += er32(ROC);
4955
4956 adapter->stats.mpc += er32(MPC);
4957
4958 /* Half-duplex statistics */
4959 if (adapter->link_duplex == HALF_DUPLEX) {
4960 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4961 e1000e_update_phy_stats(adapter);
4962 } else {
4963 adapter->stats.scc += er32(SCC);
4964 adapter->stats.ecol += er32(ECOL);
4965 adapter->stats.mcc += er32(MCC);
4966 adapter->stats.latecol += er32(LATECOL);
4967 adapter->stats.dc += er32(DC);
4968
4969 hw->mac.collision_delta = er32(COLC);
4970
4971 if ((hw->mac.type != e1000_82574) &&
4972 (hw->mac.type != e1000_82583))
4973 adapter->stats.tncrs += er32(TNCRS);
4974 }
4975 adapter->stats.colc += hw->mac.collision_delta;
4976 }
4977
4978 adapter->stats.xonrxc += er32(XONRXC);
4979 adapter->stats.xontxc += er32(XONTXC);
4980 adapter->stats.xoffrxc += er32(XOFFRXC);
4981 adapter->stats.xofftxc += er32(XOFFTXC);
4982 adapter->stats.gptc += er32(GPTC);
4983 adapter->stats.gotc += er32(GOTCL);
4984 er32(GOTCH); /* Clear gotc */
4985 adapter->stats.rnbc += er32(RNBC);
4986 adapter->stats.ruc += er32(RUC);
4987
4988 adapter->stats.mptc += er32(MPTC);
4989 adapter->stats.bptc += er32(BPTC);
4990
4991 /* used for adaptive IFS */
4992
4993 hw->mac.tx_packet_delta = er32(TPT);
4994 adapter->stats.tpt += hw->mac.tx_packet_delta;
4995
4996 adapter->stats.algnerrc += er32(ALGNERRC);
4997 adapter->stats.rxerrc += er32(RXERRC);
4998 adapter->stats.cexterr += er32(CEXTERR);
4999 adapter->stats.tsctc += er32(TSCTC);
5000 adapter->stats.tsctfc += er32(TSCTFC);
5001
5002 /* Fill out the OS statistics structure */
5003 netdev->stats.multicast = adapter->stats.mprc;
5004 netdev->stats.collisions = adapter->stats.colc;
5005
5006 /* Rx Errors */
5007
5008 /* RLEC on some newer hardware can be incorrect so build
5009 * our own version based on RUC and ROC
5010 */
5011 netdev->stats.rx_errors = adapter->stats.rxerrc +
5012 adapter->stats.crcerrs + adapter->stats.algnerrc +
5013 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5014 netdev->stats.rx_length_errors = adapter->stats.ruc +
5015 adapter->stats.roc;
5016 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5017 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5018 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5019
5020 /* Tx Errors */
5021 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5022 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5023 netdev->stats.tx_window_errors = adapter->stats.latecol;
5024 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5025
5026 /* Tx Dropped needs to be maintained elsewhere */
5027
5028 /* Management Stats */
5029 adapter->stats.mgptc += er32(MGTPTC);
5030 adapter->stats.mgprc += er32(MGTPRC);
5031 adapter->stats.mgpdc += er32(MGTPDC);
5032
5033 /* Correctable ECC Errors */
5034 if (hw->mac.type >= e1000_pch_lpt) {
5035 u32 pbeccsts = er32(PBECCSTS);
5036
5037 adapter->corr_errors +=
5038 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5039 adapter->uncorr_errors +=
5040 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
5041 }
5042 }
5043
5044 /**
5045 * e1000_phy_read_status - Update the PHY register status snapshot
5046 * @adapter: board private structure
5047 **/
e1000_phy_read_status(struct e1000_adapter * adapter)5048 static void e1000_phy_read_status(struct e1000_adapter *adapter)
5049 {
5050 struct e1000_hw *hw = &adapter->hw;
5051 struct e1000_phy_regs *phy = &adapter->phy_regs;
5052
5053 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5054 (er32(STATUS) & E1000_STATUS_LU) &&
5055 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5056 int ret_val;
5057
5058 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5059 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5060 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5061 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5062 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5063 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5064 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5065 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5066 if (ret_val)
5067 e_warn("Error reading PHY register\n");
5068 } else {
5069 /* Do not read PHY registers if link is not up
5070 * Set values to typical power-on defaults
5071 */
5072 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5073 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5074 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5075 BMSR_ERCAP);
5076 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5077 ADVERTISE_ALL | ADVERTISE_CSMA);
5078 phy->lpa = 0;
5079 phy->expansion = EXPANSION_ENABLENPAGE;
5080 phy->ctrl1000 = ADVERTISE_1000FULL;
5081 phy->stat1000 = 0;
5082 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5083 }
5084 }
5085
e1000_print_link_info(struct e1000_adapter * adapter)5086 static void e1000_print_link_info(struct e1000_adapter *adapter)
5087 {
5088 struct e1000_hw *hw = &adapter->hw;
5089 u32 ctrl = er32(CTRL);
5090
5091 /* Link status message must follow this format for user tools */
5092 netdev_info(adapter->netdev,
5093 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5094 adapter->link_speed,
5095 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5096 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5097 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5098 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5099 }
5100
e1000e_has_link(struct e1000_adapter * adapter)5101 static bool e1000e_has_link(struct e1000_adapter *adapter)
5102 {
5103 struct e1000_hw *hw = &adapter->hw;
5104 bool link_active = false;
5105 s32 ret_val = 0;
5106
5107 /* get_link_status is set on LSC (link status) interrupt or
5108 * Rx sequence error interrupt. get_link_status will stay
5109 * true until the check_for_link establishes link
5110 * for copper adapters ONLY
5111 */
5112 switch (hw->phy.media_type) {
5113 case e1000_media_type_copper:
5114 if (hw->mac.get_link_status) {
5115 ret_val = hw->mac.ops.check_for_link(hw);
5116 link_active = !hw->mac.get_link_status;
5117 } else {
5118 link_active = true;
5119 }
5120 break;
5121 case e1000_media_type_fiber:
5122 ret_val = hw->mac.ops.check_for_link(hw);
5123 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5124 break;
5125 case e1000_media_type_internal_serdes:
5126 ret_val = hw->mac.ops.check_for_link(hw);
5127 link_active = hw->mac.serdes_has_link;
5128 break;
5129 default:
5130 case e1000_media_type_unknown:
5131 break;
5132 }
5133
5134 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5135 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5136 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5137 e_info("Gigabit has been disabled, downgrading speed\n");
5138 }
5139
5140 return link_active;
5141 }
5142
e1000e_enable_receives(struct e1000_adapter * adapter)5143 static void e1000e_enable_receives(struct e1000_adapter *adapter)
5144 {
5145 /* make sure the receive unit is started */
5146 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5147 (adapter->flags & FLAG_RESTART_NOW)) {
5148 struct e1000_hw *hw = &adapter->hw;
5149 u32 rctl = er32(RCTL);
5150
5151 ew32(RCTL, rctl | E1000_RCTL_EN);
5152 adapter->flags &= ~FLAG_RESTART_NOW;
5153 }
5154 }
5155
e1000e_check_82574_phy_workaround(struct e1000_adapter * adapter)5156 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5157 {
5158 struct e1000_hw *hw = &adapter->hw;
5159
5160 /* With 82574 controllers, PHY needs to be checked periodically
5161 * for hung state and reset, if two calls return true
5162 */
5163 if (e1000_check_phy_82574(hw))
5164 adapter->phy_hang_count++;
5165 else
5166 adapter->phy_hang_count = 0;
5167
5168 if (adapter->phy_hang_count > 1) {
5169 adapter->phy_hang_count = 0;
5170 e_dbg("PHY appears hung - resetting\n");
5171 schedule_work(&adapter->reset_task);
5172 }
5173 }
5174
5175 /**
5176 * e1000_watchdog - Timer Call-back
5177 * @t: pointer to timer_list containing private info adapter
5178 **/
e1000_watchdog(struct timer_list * t)5179 static void e1000_watchdog(struct timer_list *t)
5180 {
5181 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5182
5183 /* Do the rest outside of interrupt context */
5184 schedule_work(&adapter->watchdog_task);
5185
5186 /* TODO: make this use queue_delayed_work() */
5187 }
5188
e1000_watchdog_task(struct work_struct * work)5189 static void e1000_watchdog_task(struct work_struct *work)
5190 {
5191 struct e1000_adapter *adapter = container_of(work,
5192 struct e1000_adapter,
5193 watchdog_task);
5194 struct net_device *netdev = adapter->netdev;
5195 struct e1000_mac_info *mac = &adapter->hw.mac;
5196 struct e1000_phy_info *phy = &adapter->hw.phy;
5197 struct e1000_ring *tx_ring = adapter->tx_ring;
5198 u32 dmoff_exit_timeout = 100, tries = 0;
5199 struct e1000_hw *hw = &adapter->hw;
5200 u32 link, tctl, pcim_state;
5201
5202 if (test_bit(__E1000_DOWN, &adapter->state))
5203 return;
5204
5205 link = e1000e_has_link(adapter);
5206 if ((netif_carrier_ok(netdev)) && link) {
5207 /* Cancel scheduled suspend requests. */
5208 pm_runtime_resume(netdev->dev.parent);
5209
5210 e1000e_enable_receives(adapter);
5211 goto link_up;
5212 }
5213
5214 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5215 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5216 e1000_update_mng_vlan(adapter);
5217
5218 if (link) {
5219 if (!netif_carrier_ok(netdev)) {
5220 bool txb2b = true;
5221
5222 /* Cancel scheduled suspend requests. */
5223 pm_runtime_resume(netdev->dev.parent);
5224
5225 /* Checking if MAC is in DMoff state*/
5226 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
5227 pcim_state = er32(STATUS);
5228 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5229 if (tries++ == dmoff_exit_timeout) {
5230 e_dbg("Error in exiting dmoff\n");
5231 break;
5232 }
5233 usleep_range(10000, 20000);
5234 pcim_state = er32(STATUS);
5235
5236 /* Checking if MAC exited DMoff state */
5237 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5238 e1000_phy_hw_reset(&adapter->hw);
5239 }
5240 }
5241
5242 /* update snapshot of PHY registers on LSC */
5243 e1000_phy_read_status(adapter);
5244 mac->ops.get_link_up_info(&adapter->hw,
5245 &adapter->link_speed,
5246 &adapter->link_duplex);
5247 e1000_print_link_info(adapter);
5248
5249 /* check if SmartSpeed worked */
5250 e1000e_check_downshift(hw);
5251 if (phy->speed_downgraded)
5252 netdev_warn(netdev,
5253 "Link Speed was downgraded by SmartSpeed\n");
5254
5255 /* On supported PHYs, check for duplex mismatch only
5256 * if link has autonegotiated at 10/100 half
5257 */
5258 if ((hw->phy.type == e1000_phy_igp_3 ||
5259 hw->phy.type == e1000_phy_bm) &&
5260 hw->mac.autoneg &&
5261 (adapter->link_speed == SPEED_10 ||
5262 adapter->link_speed == SPEED_100) &&
5263 (adapter->link_duplex == HALF_DUPLEX)) {
5264 u16 autoneg_exp;
5265
5266 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5267
5268 if (!(autoneg_exp & EXPANSION_NWAY))
5269 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5270 }
5271
5272 /* adjust timeout factor according to speed/duplex */
5273 adapter->tx_timeout_factor = 1;
5274 switch (adapter->link_speed) {
5275 case SPEED_10:
5276 txb2b = false;
5277 adapter->tx_timeout_factor = 16;
5278 break;
5279 case SPEED_100:
5280 txb2b = false;
5281 adapter->tx_timeout_factor = 10;
5282 break;
5283 }
5284
5285 /* workaround: re-program speed mode bit after
5286 * link-up event
5287 */
5288 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5289 !txb2b) {
5290 u32 tarc0;
5291
5292 tarc0 = er32(TARC(0));
5293 tarc0 &= ~SPEED_MODE_BIT;
5294 ew32(TARC(0), tarc0);
5295 }
5296
5297 /* enable transmits in the hardware, need to do this
5298 * after setting TARC(0)
5299 */
5300 tctl = er32(TCTL);
5301 tctl |= E1000_TCTL_EN;
5302 ew32(TCTL, tctl);
5303
5304 /* Perform any post-link-up configuration before
5305 * reporting link up.
5306 */
5307 if (phy->ops.cfg_on_link_up)
5308 phy->ops.cfg_on_link_up(hw);
5309
5310 netif_wake_queue(netdev);
5311 netif_carrier_on(netdev);
5312
5313 if (!test_bit(__E1000_DOWN, &adapter->state))
5314 mod_timer(&adapter->phy_info_timer,
5315 round_jiffies(jiffies + 2 * HZ));
5316 }
5317 } else {
5318 if (netif_carrier_ok(netdev)) {
5319 adapter->link_speed = 0;
5320 adapter->link_duplex = 0;
5321 /* Link status message must follow this format */
5322 netdev_info(netdev, "NIC Link is Down\n");
5323 netif_carrier_off(netdev);
5324 netif_stop_queue(netdev);
5325 if (!test_bit(__E1000_DOWN, &adapter->state))
5326 mod_timer(&adapter->phy_info_timer,
5327 round_jiffies(jiffies + 2 * HZ));
5328
5329 /* 8000ES2LAN requires a Rx packet buffer work-around
5330 * on link down event; reset the controller to flush
5331 * the Rx packet buffer.
5332 */
5333 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5334 adapter->flags |= FLAG_RESTART_NOW;
5335 else
5336 pm_schedule_suspend(netdev->dev.parent,
5337 LINK_TIMEOUT);
5338 }
5339 }
5340
5341 link_up:
5342 spin_lock(&adapter->stats64_lock);
5343 e1000e_update_stats(adapter);
5344
5345 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5346 adapter->tpt_old = adapter->stats.tpt;
5347 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5348 adapter->colc_old = adapter->stats.colc;
5349
5350 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5351 adapter->gorc_old = adapter->stats.gorc;
5352 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5353 adapter->gotc_old = adapter->stats.gotc;
5354 spin_unlock(&adapter->stats64_lock);
5355
5356 /* If the link is lost the controller stops DMA, but
5357 * if there is queued Tx work it cannot be done. So
5358 * reset the controller to flush the Tx packet buffers.
5359 */
5360 if (!netif_carrier_ok(netdev) &&
5361 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5362 adapter->flags |= FLAG_RESTART_NOW;
5363
5364 /* If reset is necessary, do it outside of interrupt context. */
5365 if (adapter->flags & FLAG_RESTART_NOW) {
5366 schedule_work(&adapter->reset_task);
5367 /* return immediately since reset is imminent */
5368 return;
5369 }
5370
5371 e1000e_update_adaptive(&adapter->hw);
5372
5373 /* Simple mode for Interrupt Throttle Rate (ITR) */
5374 if (adapter->itr_setting == 4) {
5375 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5376 * Total asymmetrical Tx or Rx gets ITR=8000;
5377 * everyone else is between 2000-8000.
5378 */
5379 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5380 u32 dif = (adapter->gotc > adapter->gorc ?
5381 adapter->gotc - adapter->gorc :
5382 adapter->gorc - adapter->gotc) / 10000;
5383 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5384
5385 e1000e_write_itr(adapter, itr);
5386 }
5387
5388 /* Cause software interrupt to ensure Rx ring is cleaned */
5389 if (adapter->msix_entries)
5390 ew32(ICS, adapter->rx_ring->ims_val);
5391 else
5392 ew32(ICS, E1000_ICS_RXDMT0);
5393
5394 /* flush pending descriptors to memory before detecting Tx hang */
5395 e1000e_flush_descriptors(adapter);
5396
5397 /* Force detection of hung controller every watchdog period */
5398 adapter->detect_tx_hung = true;
5399
5400 /* With 82571 controllers, LAA may be overwritten due to controller
5401 * reset from the other port. Set the appropriate LAA in RAR[0]
5402 */
5403 if (e1000e_get_laa_state_82571(hw))
5404 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5405
5406 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5407 e1000e_check_82574_phy_workaround(adapter);
5408
5409 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5410 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5411 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5412 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5413 er32(RXSTMPH);
5414 adapter->rx_hwtstamp_cleared++;
5415 } else {
5416 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5417 }
5418 }
5419
5420 /* Reset the timer */
5421 if (!test_bit(__E1000_DOWN, &adapter->state))
5422 mod_timer(&adapter->watchdog_timer,
5423 round_jiffies(jiffies + 2 * HZ));
5424 }
5425
5426 #define E1000_TX_FLAGS_CSUM 0x00000001
5427 #define E1000_TX_FLAGS_VLAN 0x00000002
5428 #define E1000_TX_FLAGS_TSO 0x00000004
5429 #define E1000_TX_FLAGS_IPV4 0x00000008
5430 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5431 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5432 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5433 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5434
e1000_tso(struct e1000_ring * tx_ring,struct sk_buff * skb,__be16 protocol)5435 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5436 __be16 protocol)
5437 {
5438 struct e1000_context_desc *context_desc;
5439 struct e1000_buffer *buffer_info;
5440 unsigned int i;
5441 u32 cmd_length = 0;
5442 u16 ipcse = 0, mss;
5443 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5444 int err;
5445
5446 if (!skb_is_gso(skb))
5447 return 0;
5448
5449 err = skb_cow_head(skb, 0);
5450 if (err < 0)
5451 return err;
5452
5453 hdr_len = skb_tcp_all_headers(skb);
5454 mss = skb_shinfo(skb)->gso_size;
5455 if (protocol == htons(ETH_P_IP)) {
5456 struct iphdr *iph = ip_hdr(skb);
5457 iph->tot_len = 0;
5458 iph->check = 0;
5459 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5460 0, IPPROTO_TCP, 0);
5461 cmd_length = E1000_TXD_CMD_IP;
5462 ipcse = skb_transport_offset(skb) - 1;
5463 } else if (skb_is_gso_v6(skb)) {
5464 tcp_v6_gso_csum_prep(skb);
5465 ipcse = 0;
5466 }
5467 ipcss = skb_network_offset(skb);
5468 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5469 tucss = skb_transport_offset(skb);
5470 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5471
5472 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5473 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5474
5475 i = tx_ring->next_to_use;
5476 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5477 buffer_info = &tx_ring->buffer_info[i];
5478
5479 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5480 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5481 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5482 context_desc->upper_setup.tcp_fields.tucss = tucss;
5483 context_desc->upper_setup.tcp_fields.tucso = tucso;
5484 context_desc->upper_setup.tcp_fields.tucse = 0;
5485 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5486 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5487 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5488
5489 buffer_info->time_stamp = jiffies;
5490 buffer_info->next_to_watch = i;
5491
5492 i++;
5493 if (i == tx_ring->count)
5494 i = 0;
5495 tx_ring->next_to_use = i;
5496
5497 return 1;
5498 }
5499
e1000_tx_csum(struct e1000_ring * tx_ring,struct sk_buff * skb,__be16 protocol)5500 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5501 __be16 protocol)
5502 {
5503 struct e1000_adapter *adapter = tx_ring->adapter;
5504 struct e1000_context_desc *context_desc;
5505 struct e1000_buffer *buffer_info;
5506 unsigned int i;
5507 u8 css;
5508 u32 cmd_len = E1000_TXD_CMD_DEXT;
5509
5510 if (skb->ip_summed != CHECKSUM_PARTIAL)
5511 return false;
5512
5513 switch (protocol) {
5514 case cpu_to_be16(ETH_P_IP):
5515 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5516 cmd_len |= E1000_TXD_CMD_TCP;
5517 break;
5518 case cpu_to_be16(ETH_P_IPV6):
5519 /* XXX not handling all IPV6 headers */
5520 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5521 cmd_len |= E1000_TXD_CMD_TCP;
5522 break;
5523 default:
5524 if (unlikely(net_ratelimit()))
5525 e_warn("checksum_partial proto=%x!\n",
5526 be16_to_cpu(protocol));
5527 break;
5528 }
5529
5530 css = skb_checksum_start_offset(skb);
5531
5532 i = tx_ring->next_to_use;
5533 buffer_info = &tx_ring->buffer_info[i];
5534 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5535
5536 context_desc->lower_setup.ip_config = 0;
5537 context_desc->upper_setup.tcp_fields.tucss = css;
5538 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5539 context_desc->upper_setup.tcp_fields.tucse = 0;
5540 context_desc->tcp_seg_setup.data = 0;
5541 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5542
5543 buffer_info->time_stamp = jiffies;
5544 buffer_info->next_to_watch = i;
5545
5546 i++;
5547 if (i == tx_ring->count)
5548 i = 0;
5549 tx_ring->next_to_use = i;
5550
5551 return true;
5552 }
5553
e1000_tx_map(struct e1000_ring * tx_ring,struct sk_buff * skb,unsigned int first,unsigned int max_per_txd,unsigned int nr_frags)5554 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5555 unsigned int first, unsigned int max_per_txd,
5556 unsigned int nr_frags)
5557 {
5558 struct e1000_adapter *adapter = tx_ring->adapter;
5559 struct pci_dev *pdev = adapter->pdev;
5560 struct e1000_buffer *buffer_info;
5561 unsigned int len = skb_headlen(skb);
5562 unsigned int offset = 0, size, count = 0, i;
5563 unsigned int f, bytecount, segs;
5564
5565 i = tx_ring->next_to_use;
5566
5567 while (len) {
5568 buffer_info = &tx_ring->buffer_info[i];
5569 size = min(len, max_per_txd);
5570
5571 buffer_info->length = size;
5572 buffer_info->time_stamp = jiffies;
5573 buffer_info->next_to_watch = i;
5574 buffer_info->dma = dma_map_single(&pdev->dev,
5575 skb->data + offset,
5576 size, DMA_TO_DEVICE);
5577 buffer_info->mapped_as_page = false;
5578 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5579 goto dma_error;
5580
5581 len -= size;
5582 offset += size;
5583 count++;
5584
5585 if (len) {
5586 i++;
5587 if (i == tx_ring->count)
5588 i = 0;
5589 }
5590 }
5591
5592 for (f = 0; f < nr_frags; f++) {
5593 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5594
5595 len = skb_frag_size(frag);
5596 offset = 0;
5597
5598 while (len) {
5599 i++;
5600 if (i == tx_ring->count)
5601 i = 0;
5602
5603 buffer_info = &tx_ring->buffer_info[i];
5604 size = min(len, max_per_txd);
5605
5606 buffer_info->length = size;
5607 buffer_info->time_stamp = jiffies;
5608 buffer_info->next_to_watch = i;
5609 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5610 offset, size,
5611 DMA_TO_DEVICE);
5612 buffer_info->mapped_as_page = true;
5613 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5614 goto dma_error;
5615
5616 len -= size;
5617 offset += size;
5618 count++;
5619 }
5620 }
5621
5622 segs = skb_shinfo(skb)->gso_segs ? : 1;
5623 /* multiply data chunks by size of headers */
5624 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5625
5626 tx_ring->buffer_info[i].skb = skb;
5627 tx_ring->buffer_info[i].segs = segs;
5628 tx_ring->buffer_info[i].bytecount = bytecount;
5629 tx_ring->buffer_info[first].next_to_watch = i;
5630
5631 return count;
5632
5633 dma_error:
5634 dev_err(&pdev->dev, "Tx DMA map failed\n");
5635 buffer_info->dma = 0;
5636 if (count)
5637 count--;
5638
5639 while (count--) {
5640 if (i == 0)
5641 i += tx_ring->count;
5642 i--;
5643 buffer_info = &tx_ring->buffer_info[i];
5644 e1000_put_txbuf(tx_ring, buffer_info, true);
5645 }
5646
5647 return 0;
5648 }
5649
e1000_tx_queue(struct e1000_ring * tx_ring,int tx_flags,int count)5650 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5651 {
5652 struct e1000_adapter *adapter = tx_ring->adapter;
5653 struct e1000_tx_desc *tx_desc = NULL;
5654 struct e1000_buffer *buffer_info;
5655 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5656 unsigned int i;
5657
5658 if (tx_flags & E1000_TX_FLAGS_TSO) {
5659 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5660 E1000_TXD_CMD_TSE;
5661 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5662
5663 if (tx_flags & E1000_TX_FLAGS_IPV4)
5664 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5665 }
5666
5667 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5668 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5669 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5670 }
5671
5672 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5673 txd_lower |= E1000_TXD_CMD_VLE;
5674 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5675 }
5676
5677 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5678 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5679
5680 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5681 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5682 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5683 }
5684
5685 i = tx_ring->next_to_use;
5686
5687 do {
5688 buffer_info = &tx_ring->buffer_info[i];
5689 tx_desc = E1000_TX_DESC(*tx_ring, i);
5690 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5691 tx_desc->lower.data = cpu_to_le32(txd_lower |
5692 buffer_info->length);
5693 tx_desc->upper.data = cpu_to_le32(txd_upper);
5694
5695 i++;
5696 if (i == tx_ring->count)
5697 i = 0;
5698 } while (--count > 0);
5699
5700 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5701
5702 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5703 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5704 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5705
5706 /* Force memory writes to complete before letting h/w
5707 * know there are new descriptors to fetch. (Only
5708 * applicable for weak-ordered memory model archs,
5709 * such as IA-64).
5710 */
5711 wmb();
5712
5713 tx_ring->next_to_use = i;
5714 }
5715
5716 #define MINIMUM_DHCP_PACKET_SIZE 282
e1000_transfer_dhcp_info(struct e1000_adapter * adapter,struct sk_buff * skb)5717 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5718 struct sk_buff *skb)
5719 {
5720 struct e1000_hw *hw = &adapter->hw;
5721 u16 length, offset;
5722
5723 if (skb_vlan_tag_present(skb) &&
5724 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5725 (adapter->hw.mng_cookie.status &
5726 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5727 return 0;
5728
5729 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5730 return 0;
5731
5732 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5733 return 0;
5734
5735 {
5736 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5737 struct udphdr *udp;
5738
5739 if (ip->protocol != IPPROTO_UDP)
5740 return 0;
5741
5742 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5743 if (ntohs(udp->dest) != 67)
5744 return 0;
5745
5746 offset = (u8 *)udp + 8 - skb->data;
5747 length = skb->len - offset;
5748 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5749 }
5750
5751 return 0;
5752 }
5753
__e1000_maybe_stop_tx(struct e1000_ring * tx_ring,int size)5754 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5755 {
5756 struct e1000_adapter *adapter = tx_ring->adapter;
5757
5758 netif_stop_queue(adapter->netdev);
5759 /* Herbert's original patch had:
5760 * smp_mb__after_netif_stop_queue();
5761 * but since that doesn't exist yet, just open code it.
5762 */
5763 smp_mb();
5764
5765 /* We need to check again in a case another CPU has just
5766 * made room available.
5767 */
5768 if (e1000_desc_unused(tx_ring) < size)
5769 return -EBUSY;
5770
5771 /* A reprieve! */
5772 netif_start_queue(adapter->netdev);
5773 ++adapter->restart_queue;
5774 return 0;
5775 }
5776
e1000_maybe_stop_tx(struct e1000_ring * tx_ring,int size)5777 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5778 {
5779 BUG_ON(size > tx_ring->count);
5780
5781 if (e1000_desc_unused(tx_ring) >= size)
5782 return 0;
5783 return __e1000_maybe_stop_tx(tx_ring, size);
5784 }
5785
e1000_xmit_frame(struct sk_buff * skb,struct net_device * netdev)5786 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5787 struct net_device *netdev)
5788 {
5789 struct e1000_adapter *adapter = netdev_priv(netdev);
5790 struct e1000_ring *tx_ring = adapter->tx_ring;
5791 unsigned int first;
5792 unsigned int tx_flags = 0;
5793 unsigned int len = skb_headlen(skb);
5794 unsigned int nr_frags;
5795 unsigned int mss;
5796 int count = 0;
5797 int tso;
5798 unsigned int f;
5799 __be16 protocol = vlan_get_protocol(skb);
5800
5801 if (test_bit(__E1000_DOWN, &adapter->state)) {
5802 dev_kfree_skb_any(skb);
5803 return NETDEV_TX_OK;
5804 }
5805
5806 if (skb->len <= 0) {
5807 dev_kfree_skb_any(skb);
5808 return NETDEV_TX_OK;
5809 }
5810
5811 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5812 * pad skb in order to meet this minimum size requirement
5813 */
5814 if (skb_put_padto(skb, 17))
5815 return NETDEV_TX_OK;
5816
5817 mss = skb_shinfo(skb)->gso_size;
5818 if (mss) {
5819 u8 hdr_len;
5820
5821 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5822 * points to just header, pull a few bytes of payload from
5823 * frags into skb->data
5824 */
5825 hdr_len = skb_tcp_all_headers(skb);
5826 /* we do this workaround for ES2LAN, but it is un-necessary,
5827 * avoiding it could save a lot of cycles
5828 */
5829 if (skb->data_len && (hdr_len == len)) {
5830 unsigned int pull_size;
5831
5832 pull_size = min_t(unsigned int, 4, skb->data_len);
5833 if (!__pskb_pull_tail(skb, pull_size)) {
5834 e_err("__pskb_pull_tail failed.\n");
5835 dev_kfree_skb_any(skb);
5836 return NETDEV_TX_OK;
5837 }
5838 len = skb_headlen(skb);
5839 }
5840 }
5841
5842 /* reserve a descriptor for the offload context */
5843 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5844 count++;
5845 count++;
5846
5847 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5848
5849 nr_frags = skb_shinfo(skb)->nr_frags;
5850 for (f = 0; f < nr_frags; f++)
5851 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5852 adapter->tx_fifo_limit);
5853
5854 if (adapter->hw.mac.tx_pkt_filtering)
5855 e1000_transfer_dhcp_info(adapter, skb);
5856
5857 /* need: count + 2 desc gap to keep tail from touching
5858 * head, otherwise try next time
5859 */
5860 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5861 return NETDEV_TX_BUSY;
5862
5863 if (skb_vlan_tag_present(skb)) {
5864 tx_flags |= E1000_TX_FLAGS_VLAN;
5865 tx_flags |= (skb_vlan_tag_get(skb) <<
5866 E1000_TX_FLAGS_VLAN_SHIFT);
5867 }
5868
5869 first = tx_ring->next_to_use;
5870
5871 tso = e1000_tso(tx_ring, skb, protocol);
5872 if (tso < 0) {
5873 dev_kfree_skb_any(skb);
5874 return NETDEV_TX_OK;
5875 }
5876
5877 if (tso)
5878 tx_flags |= E1000_TX_FLAGS_TSO;
5879 else if (e1000_tx_csum(tx_ring, skb, protocol))
5880 tx_flags |= E1000_TX_FLAGS_CSUM;
5881
5882 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5883 * 82571 hardware supports TSO capabilities for IPv6 as well...
5884 * no longer assume, we must.
5885 */
5886 if (protocol == htons(ETH_P_IP))
5887 tx_flags |= E1000_TX_FLAGS_IPV4;
5888
5889 if (unlikely(skb->no_fcs))
5890 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5891
5892 /* if count is 0 then mapping error has occurred */
5893 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5894 nr_frags);
5895 if (count) {
5896 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5897 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5898 if (!adapter->tx_hwtstamp_skb) {
5899 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5900 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5901 adapter->tx_hwtstamp_skb = skb_get(skb);
5902 adapter->tx_hwtstamp_start = jiffies;
5903 schedule_work(&adapter->tx_hwtstamp_work);
5904 } else {
5905 adapter->tx_hwtstamp_skipped++;
5906 }
5907 }
5908
5909 skb_tx_timestamp(skb);
5910
5911 netdev_sent_queue(netdev, skb->len);
5912 e1000_tx_queue(tx_ring, tx_flags, count);
5913 /* Make sure there is space in the ring for the next send. */
5914 e1000_maybe_stop_tx(tx_ring,
5915 ((MAX_SKB_FRAGS + 1) *
5916 DIV_ROUND_UP(PAGE_SIZE,
5917 adapter->tx_fifo_limit) + 4));
5918
5919 if (!netdev_xmit_more() ||
5920 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5921 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5922 e1000e_update_tdt_wa(tx_ring,
5923 tx_ring->next_to_use);
5924 else
5925 writel(tx_ring->next_to_use, tx_ring->tail);
5926 }
5927 } else {
5928 dev_kfree_skb_any(skb);
5929 tx_ring->buffer_info[first].time_stamp = 0;
5930 tx_ring->next_to_use = first;
5931 }
5932
5933 return NETDEV_TX_OK;
5934 }
5935
5936 /**
5937 * e1000_tx_timeout - Respond to a Tx Hang
5938 * @netdev: network interface device structure
5939 * @txqueue: index of the hung queue (unused)
5940 **/
e1000_tx_timeout(struct net_device * netdev,unsigned int __always_unused txqueue)5941 static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
5942 {
5943 struct e1000_adapter *adapter = netdev_priv(netdev);
5944
5945 /* Do the reset outside of interrupt context */
5946 adapter->tx_timeout_count++;
5947 schedule_work(&adapter->reset_task);
5948 }
5949
e1000_reset_task(struct work_struct * work)5950 static void e1000_reset_task(struct work_struct *work)
5951 {
5952 struct e1000_adapter *adapter;
5953 adapter = container_of(work, struct e1000_adapter, reset_task);
5954
5955 rtnl_lock();
5956 /* don't run the task if already down */
5957 if (test_bit(__E1000_DOWN, &adapter->state)) {
5958 rtnl_unlock();
5959 return;
5960 }
5961
5962 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5963 e1000e_dump(adapter);
5964 e_err("Reset adapter unexpectedly\n");
5965 }
5966 e1000e_reinit_locked(adapter);
5967 rtnl_unlock();
5968 }
5969
5970 /**
5971 * e1000e_get_stats64 - Get System Network Statistics
5972 * @netdev: network interface device structure
5973 * @stats: rtnl_link_stats64 pointer
5974 *
5975 * Returns the address of the device statistics structure.
5976 **/
e1000e_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)5977 void e1000e_get_stats64(struct net_device *netdev,
5978 struct rtnl_link_stats64 *stats)
5979 {
5980 struct e1000_adapter *adapter = netdev_priv(netdev);
5981
5982 spin_lock(&adapter->stats64_lock);
5983 e1000e_update_stats(adapter);
5984 /* Fill out the OS statistics structure */
5985 stats->rx_bytes = adapter->stats.gorc;
5986 stats->rx_packets = adapter->stats.gprc;
5987 stats->tx_bytes = adapter->stats.gotc;
5988 stats->tx_packets = adapter->stats.gptc;
5989 stats->multicast = adapter->stats.mprc;
5990 stats->collisions = adapter->stats.colc;
5991
5992 /* Rx Errors */
5993
5994 /* RLEC on some newer hardware can be incorrect so build
5995 * our own version based on RUC and ROC
5996 */
5997 stats->rx_errors = adapter->stats.rxerrc +
5998 adapter->stats.crcerrs + adapter->stats.algnerrc +
5999 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
6000 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
6001 stats->rx_crc_errors = adapter->stats.crcerrs;
6002 stats->rx_frame_errors = adapter->stats.algnerrc;
6003 stats->rx_missed_errors = adapter->stats.mpc;
6004
6005 /* Tx Errors */
6006 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6007 stats->tx_aborted_errors = adapter->stats.ecol;
6008 stats->tx_window_errors = adapter->stats.latecol;
6009 stats->tx_carrier_errors = adapter->stats.tncrs;
6010
6011 /* Tx Dropped needs to be maintained elsewhere */
6012
6013 spin_unlock(&adapter->stats64_lock);
6014 }
6015
6016 /**
6017 * e1000_change_mtu - Change the Maximum Transfer Unit
6018 * @netdev: network interface device structure
6019 * @new_mtu: new value for maximum frame size
6020 *
6021 * Returns 0 on success, negative on failure
6022 **/
e1000_change_mtu(struct net_device * netdev,int new_mtu)6023 static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6024 {
6025 struct e1000_adapter *adapter = netdev_priv(netdev);
6026 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6027
6028 /* Jumbo frame support */
6029 if ((new_mtu > ETH_DATA_LEN) &&
6030 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6031 e_err("Jumbo Frames not supported.\n");
6032 return -EINVAL;
6033 }
6034
6035 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6036 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6037 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6038 (new_mtu > ETH_DATA_LEN)) {
6039 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6040 return -EINVAL;
6041 }
6042
6043 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6044 usleep_range(1000, 1100);
6045 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6046 adapter->max_frame_size = max_frame;
6047 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6048 netdev->mtu, new_mtu);
6049 netdev->mtu = new_mtu;
6050
6051 pm_runtime_get_sync(netdev->dev.parent);
6052
6053 if (netif_running(netdev))
6054 e1000e_down(adapter, true);
6055
6056 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6057 * means we reserve 2 more, this pushes us to allocate from the next
6058 * larger slab size.
6059 * i.e. RXBUFFER_2048 --> size-4096 slab
6060 * However with the new *_jumbo_rx* routines, jumbo receives will use
6061 * fragmented skbs
6062 */
6063
6064 if (max_frame <= 2048)
6065 adapter->rx_buffer_len = 2048;
6066 else
6067 adapter->rx_buffer_len = 4096;
6068
6069 /* adjust allocation if LPE protects us, and we aren't using SBP */
6070 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6071 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6072
6073 if (netif_running(netdev))
6074 e1000e_up(adapter);
6075 else
6076 e1000e_reset(adapter);
6077
6078 pm_runtime_put_sync(netdev->dev.parent);
6079
6080 clear_bit(__E1000_RESETTING, &adapter->state);
6081
6082 return 0;
6083 }
6084
e1000_mii_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)6085 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6086 int cmd)
6087 {
6088 struct e1000_adapter *adapter = netdev_priv(netdev);
6089 struct mii_ioctl_data *data = if_mii(ifr);
6090
6091 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6092 return -EOPNOTSUPP;
6093
6094 switch (cmd) {
6095 case SIOCGMIIPHY:
6096 data->phy_id = adapter->hw.phy.addr;
6097 break;
6098 case SIOCGMIIREG:
6099 e1000_phy_read_status(adapter);
6100
6101 switch (data->reg_num & 0x1F) {
6102 case MII_BMCR:
6103 data->val_out = adapter->phy_regs.bmcr;
6104 break;
6105 case MII_BMSR:
6106 data->val_out = adapter->phy_regs.bmsr;
6107 break;
6108 case MII_PHYSID1:
6109 data->val_out = (adapter->hw.phy.id >> 16);
6110 break;
6111 case MII_PHYSID2:
6112 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6113 break;
6114 case MII_ADVERTISE:
6115 data->val_out = adapter->phy_regs.advertise;
6116 break;
6117 case MII_LPA:
6118 data->val_out = adapter->phy_regs.lpa;
6119 break;
6120 case MII_EXPANSION:
6121 data->val_out = adapter->phy_regs.expansion;
6122 break;
6123 case MII_CTRL1000:
6124 data->val_out = adapter->phy_regs.ctrl1000;
6125 break;
6126 case MII_STAT1000:
6127 data->val_out = adapter->phy_regs.stat1000;
6128 break;
6129 case MII_ESTATUS:
6130 data->val_out = adapter->phy_regs.estatus;
6131 break;
6132 default:
6133 return -EIO;
6134 }
6135 break;
6136 case SIOCSMIIREG:
6137 default:
6138 return -EOPNOTSUPP;
6139 }
6140 return 0;
6141 }
6142
6143 /**
6144 * e1000e_hwtstamp_set - control hardware time stamping
6145 * @netdev: network interface device structure
6146 * @ifr: interface request
6147 *
6148 * Outgoing time stamping can be enabled and disabled. Play nice and
6149 * disable it when requested, although it shouldn't cause any overhead
6150 * when no packet needs it. At most one packet in the queue may be
6151 * marked for time stamping, otherwise it would be impossible to tell
6152 * for sure to which packet the hardware time stamp belongs.
6153 *
6154 * Incoming time stamping has to be configured via the hardware filters.
6155 * Not all combinations are supported, in particular event type has to be
6156 * specified. Matching the kind of event packet is not supported, with the
6157 * exception of "all V2 events regardless of level 2 or 4".
6158 **/
e1000e_hwtstamp_set(struct net_device * netdev,struct ifreq * ifr)6159 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6160 {
6161 struct e1000_adapter *adapter = netdev_priv(netdev);
6162 struct hwtstamp_config config;
6163 int ret_val;
6164
6165 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6166 return -EFAULT;
6167
6168 ret_val = e1000e_config_hwtstamp(adapter, &config);
6169 if (ret_val)
6170 return ret_val;
6171
6172 switch (config.rx_filter) {
6173 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6174 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6175 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6176 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6177 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6178 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6179 /* With V2 type filters which specify a Sync or Delay Request,
6180 * Path Delay Request/Response messages are also time stamped
6181 * by hardware so notify the caller the requested packets plus
6182 * some others are time stamped.
6183 */
6184 config.rx_filter = HWTSTAMP_FILTER_SOME;
6185 break;
6186 default:
6187 break;
6188 }
6189
6190 return copy_to_user(ifr->ifr_data, &config,
6191 sizeof(config)) ? -EFAULT : 0;
6192 }
6193
e1000e_hwtstamp_get(struct net_device * netdev,struct ifreq * ifr)6194 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6195 {
6196 struct e1000_adapter *adapter = netdev_priv(netdev);
6197
6198 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6199 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6200 }
6201
e1000_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)6202 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6203 {
6204 switch (cmd) {
6205 case SIOCGMIIPHY:
6206 case SIOCGMIIREG:
6207 case SIOCSMIIREG:
6208 return e1000_mii_ioctl(netdev, ifr, cmd);
6209 case SIOCSHWTSTAMP:
6210 return e1000e_hwtstamp_set(netdev, ifr);
6211 case SIOCGHWTSTAMP:
6212 return e1000e_hwtstamp_get(netdev, ifr);
6213 default:
6214 return -EOPNOTSUPP;
6215 }
6216 }
6217
e1000_init_phy_wakeup(struct e1000_adapter * adapter,u32 wufc)6218 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6219 {
6220 struct e1000_hw *hw = &adapter->hw;
6221 u32 i, mac_reg, wuc;
6222 u16 phy_reg, wuc_enable;
6223 int retval;
6224
6225 /* copy MAC RARs to PHY RARs */
6226 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6227
6228 retval = hw->phy.ops.acquire(hw);
6229 if (retval) {
6230 e_err("Could not acquire PHY\n");
6231 return retval;
6232 }
6233
6234 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6235 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6236 if (retval)
6237 goto release;
6238
6239 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6240 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6241 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6242 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6243 (u16)(mac_reg & 0xFFFF));
6244 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6245 (u16)((mac_reg >> 16) & 0xFFFF));
6246 }
6247
6248 /* configure PHY Rx Control register */
6249 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6250 mac_reg = er32(RCTL);
6251 if (mac_reg & E1000_RCTL_UPE)
6252 phy_reg |= BM_RCTL_UPE;
6253 if (mac_reg & E1000_RCTL_MPE)
6254 phy_reg |= BM_RCTL_MPE;
6255 phy_reg &= ~(BM_RCTL_MO_MASK);
6256 if (mac_reg & E1000_RCTL_MO_3)
6257 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg)
6258 << BM_RCTL_MO_SHIFT);
6259 if (mac_reg & E1000_RCTL_BAM)
6260 phy_reg |= BM_RCTL_BAM;
6261 if (mac_reg & E1000_RCTL_PMCF)
6262 phy_reg |= BM_RCTL_PMCF;
6263 mac_reg = er32(CTRL);
6264 if (mac_reg & E1000_CTRL_RFCE)
6265 phy_reg |= BM_RCTL_RFCE;
6266 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6267
6268 wuc = E1000_WUC_PME_EN;
6269 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6270 wuc |= E1000_WUC_APME;
6271
6272 /* enable PHY wakeup in MAC register */
6273 ew32(WUFC, wufc);
6274 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6275 E1000_WUC_PME_STATUS | wuc));
6276
6277 /* configure and enable PHY wakeup in PHY registers */
6278 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6279 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6280
6281 /* activate PHY wakeup */
6282 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6283 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6284 if (retval)
6285 e_err("Could not set PHY Host Wakeup bit\n");
6286 release:
6287 hw->phy.ops.release(hw);
6288
6289 return retval;
6290 }
6291
e1000e_flush_lpic(struct pci_dev * pdev)6292 static void e1000e_flush_lpic(struct pci_dev *pdev)
6293 {
6294 struct net_device *netdev = pci_get_drvdata(pdev);
6295 struct e1000_adapter *adapter = netdev_priv(netdev);
6296 struct e1000_hw *hw = &adapter->hw;
6297 u32 ret_val;
6298
6299 pm_runtime_get_sync(netdev->dev.parent);
6300
6301 ret_val = hw->phy.ops.acquire(hw);
6302 if (ret_val)
6303 goto fl_out;
6304
6305 pr_info("EEE TX LPI TIMER: %08X\n",
6306 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6307
6308 hw->phy.ops.release(hw);
6309
6310 fl_out:
6311 pm_runtime_put_sync(netdev->dev.parent);
6312 }
6313
6314 /* S0ix implementation */
e1000e_s0ix_entry_flow(struct e1000_adapter * adapter)6315 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6316 {
6317 struct e1000_hw *hw = &adapter->hw;
6318 u32 mac_data;
6319 u16 phy_data;
6320
6321 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6322 hw->mac.type >= e1000_pch_adp) {
6323 /* Request ME configure the device for S0ix */
6324 mac_data = er32(H2ME);
6325 mac_data |= E1000_H2ME_START_DPG;
6326 mac_data &= ~E1000_H2ME_EXIT_DPG;
6327 trace_e1000e_trace_mac_register(mac_data);
6328 ew32(H2ME, mac_data);
6329 } else {
6330 /* Request driver configure the device to S0ix */
6331 /* Disable the periodic inband message,
6332 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6333 */
6334 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6335 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6336 phy_data |= BIT(10);
6337 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6338
6339 /* Make sure we don't exit K1 every time a new packet arrives
6340 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6341 */
6342 e1e_rphy(hw, I217_CGFREG, &phy_data);
6343 phy_data |= BIT(5);
6344 e1e_wphy(hw, I217_CGFREG, phy_data);
6345
6346 /* Change the MAC/PHY interface to SMBus
6347 * Force the SMBus in PHY page769_23[0] = 1
6348 * Force the SMBus in MAC CTRL_EXT[11] = 1
6349 */
6350 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6351 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6352 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6353 mac_data = er32(CTRL_EXT);
6354 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6355 ew32(CTRL_EXT, mac_data);
6356
6357 /* DFT control: PHY bit: page769_20[0] = 1
6358 * page769_20[7] - PHY PLL stop
6359 * page769_20[8] - PHY go to the electrical idle
6360 * page769_20[9] - PHY serdes disable
6361 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6362 */
6363 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6364 phy_data |= BIT(0);
6365 phy_data |= BIT(7);
6366 phy_data |= BIT(8);
6367 phy_data |= BIT(9);
6368 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6369
6370 mac_data = er32(EXTCNF_CTRL);
6371 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6372 ew32(EXTCNF_CTRL, mac_data);
6373
6374 /* Disable disconnected cable conditioning for Power Gating */
6375 mac_data = er32(DPGFR);
6376 mac_data |= BIT(2);
6377 ew32(DPGFR, mac_data);
6378
6379 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6380 mac_data = er32(CTRL_EXT);
6381 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6382 ew32(CTRL_EXT, mac_data);
6383 }
6384
6385 /* Enable the Dynamic Power Gating in the MAC */
6386 mac_data = er32(FEXTNVM7);
6387 mac_data |= BIT(22);
6388 ew32(FEXTNVM7, mac_data);
6389
6390 /* Don't wake from dynamic Power Gating with clock request */
6391 mac_data = er32(FEXTNVM12);
6392 mac_data |= BIT(12);
6393 ew32(FEXTNVM12, mac_data);
6394
6395 /* Ungate PGCB clock */
6396 mac_data = er32(FEXTNVM9);
6397 mac_data &= ~BIT(28);
6398 ew32(FEXTNVM9, mac_data);
6399
6400 /* Enable K1 off to enable mPHY Power Gating */
6401 mac_data = er32(FEXTNVM6);
6402 mac_data |= BIT(31);
6403 ew32(FEXTNVM6, mac_data);
6404
6405 /* Enable mPHY power gating for any link and speed */
6406 mac_data = er32(FEXTNVM8);
6407 mac_data |= BIT(9);
6408 ew32(FEXTNVM8, mac_data);
6409
6410 /* No MAC DPG gating SLP_S0 in modern standby
6411 * Switch the logic of the lanphypc to use PMC counter
6412 */
6413 mac_data = er32(FEXTNVM5);
6414 mac_data |= BIT(7);
6415 ew32(FEXTNVM5, mac_data);
6416
6417 /* Disable the time synchronization clock */
6418 mac_data = er32(FEXTNVM7);
6419 mac_data |= BIT(31);
6420 mac_data &= ~BIT(0);
6421 ew32(FEXTNVM7, mac_data);
6422
6423 /* Dynamic Power Gating Enable */
6424 mac_data = er32(CTRL_EXT);
6425 mac_data |= BIT(3);
6426 ew32(CTRL_EXT, mac_data);
6427
6428 /* Check MAC Tx/Rx packet buffer pointers.
6429 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6430 * pending traffic indication that would prevent power gating.
6431 */
6432 mac_data = er32(TDFH);
6433 if (mac_data)
6434 ew32(TDFH, 0);
6435 mac_data = er32(TDFT);
6436 if (mac_data)
6437 ew32(TDFT, 0);
6438 mac_data = er32(TDFHS);
6439 if (mac_data)
6440 ew32(TDFHS, 0);
6441 mac_data = er32(TDFTS);
6442 if (mac_data)
6443 ew32(TDFTS, 0);
6444 mac_data = er32(TDFPC);
6445 if (mac_data)
6446 ew32(TDFPC, 0);
6447 mac_data = er32(RDFH);
6448 if (mac_data)
6449 ew32(RDFH, 0);
6450 mac_data = er32(RDFT);
6451 if (mac_data)
6452 ew32(RDFT, 0);
6453 mac_data = er32(RDFHS);
6454 if (mac_data)
6455 ew32(RDFHS, 0);
6456 mac_data = er32(RDFTS);
6457 if (mac_data)
6458 ew32(RDFTS, 0);
6459 mac_data = er32(RDFPC);
6460 if (mac_data)
6461 ew32(RDFPC, 0);
6462 }
6463
e1000e_s0ix_exit_flow(struct e1000_adapter * adapter)6464 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6465 {
6466 struct e1000_hw *hw = &adapter->hw;
6467 bool firmware_bug = false;
6468 u32 mac_data;
6469 u16 phy_data;
6470 u32 i = 0;
6471
6472 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6473 hw->mac.type >= e1000_pch_adp) {
6474 /* Keep the GPT clock enabled for CSME */
6475 mac_data = er32(FEXTNVM);
6476 mac_data |= BIT(3);
6477 ew32(FEXTNVM, mac_data);
6478 /* Request ME unconfigure the device from S0ix */
6479 mac_data = er32(H2ME);
6480 mac_data &= ~E1000_H2ME_START_DPG;
6481 mac_data |= E1000_H2ME_EXIT_DPG;
6482 trace_e1000e_trace_mac_register(mac_data);
6483 ew32(H2ME, mac_data);
6484
6485 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6486 * If this takes more than 1 second, show a warning indicating a
6487 * firmware bug
6488 */
6489 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) {
6490 if (i > 100 && !firmware_bug)
6491 firmware_bug = true;
6492
6493 if (i++ == 250) {
6494 e_dbg("Timeout (firmware bug): %d msec\n",
6495 i * 10);
6496 break;
6497 }
6498
6499 usleep_range(10000, 11000);
6500 }
6501 if (firmware_bug)
6502 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
6503 i * 10);
6504 else
6505 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
6506 } else {
6507 /* Request driver unconfigure the device from S0ix */
6508
6509 /* Cancel disable disconnected cable conditioning
6510 * for Power Gating
6511 */
6512 mac_data = er32(DPGFR);
6513 mac_data &= ~BIT(2);
6514 ew32(DPGFR, mac_data);
6515
6516 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6517 mac_data = er32(CTRL_EXT);
6518 mac_data &= 0xFFF7FFFF;
6519 ew32(CTRL_EXT, mac_data);
6520
6521 /* Enable the periodic inband message,
6522 * Request PCIe clock in K1 page770_17[10:9] =01b
6523 */
6524 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6525 phy_data &= 0xFBFF;
6526 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6527 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6528
6529 /* Return back configuration
6530 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6531 */
6532 e1e_rphy(hw, I217_CGFREG, &phy_data);
6533 phy_data &= 0xFFDF;
6534 e1e_wphy(hw, I217_CGFREG, phy_data);
6535
6536 /* Change the MAC/PHY interface to Kumeran
6537 * Unforce the SMBus in PHY page769_23[0] = 0
6538 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6539 */
6540 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6541 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6542 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6543 mac_data = er32(CTRL_EXT);
6544 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6545 ew32(CTRL_EXT, mac_data);
6546 }
6547
6548 /* Disable Dynamic Power Gating */
6549 mac_data = er32(CTRL_EXT);
6550 mac_data &= 0xFFFFFFF7;
6551 ew32(CTRL_EXT, mac_data);
6552
6553 /* Enable the time synchronization clock */
6554 mac_data = er32(FEXTNVM7);
6555 mac_data &= ~BIT(31);
6556 mac_data |= BIT(0);
6557 ew32(FEXTNVM7, mac_data);
6558
6559 /* Disable the Dynamic Power Gating in the MAC */
6560 mac_data = er32(FEXTNVM7);
6561 mac_data &= 0xFFBFFFFF;
6562 ew32(FEXTNVM7, mac_data);
6563
6564 /* Disable mPHY power gating for any link and speed */
6565 mac_data = er32(FEXTNVM8);
6566 mac_data &= ~BIT(9);
6567 ew32(FEXTNVM8, mac_data);
6568
6569 /* Disable K1 off */
6570 mac_data = er32(FEXTNVM6);
6571 mac_data &= ~BIT(31);
6572 ew32(FEXTNVM6, mac_data);
6573
6574 /* Disable Ungate PGCB clock */
6575 mac_data = er32(FEXTNVM9);
6576 mac_data |= BIT(28);
6577 ew32(FEXTNVM9, mac_data);
6578
6579 /* Cancel not waking from dynamic
6580 * Power Gating with clock request
6581 */
6582 mac_data = er32(FEXTNVM12);
6583 mac_data &= ~BIT(12);
6584 ew32(FEXTNVM12, mac_data);
6585
6586 /* Revert the lanphypc logic to use the internal Gbe counter
6587 * and not the PMC counter
6588 */
6589 mac_data = er32(FEXTNVM5);
6590 mac_data &= 0xFFFFFF7F;
6591 ew32(FEXTNVM5, mac_data);
6592 }
6593
e1000e_pm_freeze(struct device * dev)6594 static int e1000e_pm_freeze(struct device *dev)
6595 {
6596 struct net_device *netdev = dev_get_drvdata(dev);
6597 struct e1000_adapter *adapter = netdev_priv(netdev);
6598 bool present;
6599
6600 rtnl_lock();
6601
6602 present = netif_device_present(netdev);
6603 netif_device_detach(netdev);
6604
6605 if (present && netif_running(netdev)) {
6606 int count = E1000_CHECK_RESET_COUNT;
6607
6608 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6609 usleep_range(10000, 11000);
6610
6611 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6612
6613 /* Quiesce the device without resetting the hardware */
6614 e1000e_down(adapter, false);
6615 e1000_free_irq(adapter);
6616 }
6617 rtnl_unlock();
6618
6619 e1000e_reset_interrupt_capability(adapter);
6620
6621 /* Allow time for pending master requests to run */
6622 e1000e_disable_pcie_master(&adapter->hw);
6623
6624 return 0;
6625 }
6626
__e1000_shutdown(struct pci_dev * pdev,bool runtime)6627 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6628 {
6629 struct net_device *netdev = pci_get_drvdata(pdev);
6630 struct e1000_adapter *adapter = netdev_priv(netdev);
6631 struct e1000_hw *hw = &adapter->hw;
6632 u32 ctrl, ctrl_ext, rctl, status, wufc;
6633 int retval = 0;
6634
6635 /* Runtime suspend should only enable wakeup for link changes */
6636 if (runtime)
6637 wufc = E1000_WUFC_LNKC;
6638 else if (device_may_wakeup(&pdev->dev))
6639 wufc = adapter->wol;
6640 else
6641 wufc = 0;
6642
6643 status = er32(STATUS);
6644 if (status & E1000_STATUS_LU)
6645 wufc &= ~E1000_WUFC_LNKC;
6646
6647 if (wufc) {
6648 e1000_setup_rctl(adapter);
6649 e1000e_set_rx_mode(netdev);
6650
6651 /* turn on all-multi mode if wake on multicast is enabled */
6652 if (wufc & E1000_WUFC_MC) {
6653 rctl = er32(RCTL);
6654 rctl |= E1000_RCTL_MPE;
6655 ew32(RCTL, rctl);
6656 }
6657
6658 ctrl = er32(CTRL);
6659 ctrl |= E1000_CTRL_ADVD3WUC;
6660 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6661 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6662 ew32(CTRL, ctrl);
6663
6664 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6665 adapter->hw.phy.media_type ==
6666 e1000_media_type_internal_serdes) {
6667 /* keep the laser running in D3 */
6668 ctrl_ext = er32(CTRL_EXT);
6669 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6670 ew32(CTRL_EXT, ctrl_ext);
6671 }
6672
6673 if (!runtime)
6674 e1000e_power_up_phy(adapter);
6675
6676 if (adapter->flags & FLAG_IS_ICH)
6677 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6678
6679 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6680 /* enable wakeup by the PHY */
6681 retval = e1000_init_phy_wakeup(adapter, wufc);
6682 if (retval) {
6683 e_err("Failed to enable wakeup\n");
6684 goto skip_phy_configurations;
6685 }
6686 } else {
6687 /* enable wakeup by the MAC */
6688 ew32(WUFC, wufc);
6689 ew32(WUC, E1000_WUC_PME_EN);
6690 }
6691 } else {
6692 ew32(WUC, 0);
6693 ew32(WUFC, 0);
6694
6695 e1000_power_down_phy(adapter);
6696 }
6697
6698 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6699 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6700 } else if (hw->mac.type >= e1000_pch_lpt) {
6701 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) {
6702 /* ULP does not support wake from unicast, multicast
6703 * or broadcast.
6704 */
6705 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6706 if (retval) {
6707 e_err("Failed to enable ULP\n");
6708 goto skip_phy_configurations;
6709 }
6710 }
6711 }
6712
6713 /* Ensure that the appropriate bits are set in LPI_CTRL
6714 * for EEE in Sx
6715 */
6716 if ((hw->phy.type >= e1000_phy_i217) &&
6717 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6718 u16 lpi_ctrl = 0;
6719
6720 retval = hw->phy.ops.acquire(hw);
6721 if (!retval) {
6722 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6723 &lpi_ctrl);
6724 if (!retval) {
6725 if (adapter->eee_advert &
6726 hw->dev_spec.ich8lan.eee_lp_ability &
6727 I82579_EEE_100_SUPPORTED)
6728 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6729 if (adapter->eee_advert &
6730 hw->dev_spec.ich8lan.eee_lp_ability &
6731 I82579_EEE_1000_SUPPORTED)
6732 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6733
6734 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6735 lpi_ctrl);
6736 }
6737 }
6738 hw->phy.ops.release(hw);
6739 }
6740
6741 skip_phy_configurations:
6742 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6743 * would have already happened in close and is redundant.
6744 */
6745 e1000e_release_hw_control(adapter);
6746
6747 pci_clear_master(pdev);
6748
6749 /* The pci-e switch on some quad port adapters will report a
6750 * correctable error when the MAC transitions from D0 to D3. To
6751 * prevent this we need to mask off the correctable errors on the
6752 * downstream port of the pci-e switch.
6753 *
6754 * We don't have the associated upstream bridge while assigning
6755 * the PCI device into guest. For example, the KVM on power is
6756 * one of the cases.
6757 */
6758 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6759 struct pci_dev *us_dev = pdev->bus->self;
6760 u16 devctl;
6761
6762 if (!us_dev)
6763 return 0;
6764
6765 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6766 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6767 (devctl & ~PCI_EXP_DEVCTL_CERE));
6768
6769 pci_save_state(pdev);
6770 pci_prepare_to_sleep(pdev);
6771
6772 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6773 }
6774
6775 return 0;
6776 }
6777
6778 /**
6779 * __e1000e_disable_aspm - Disable ASPM states
6780 * @pdev: pointer to PCI device struct
6781 * @state: bit-mask of ASPM states to disable
6782 * @locked: indication if this context holds pci_bus_sem locked.
6783 *
6784 * Some devices *must* have certain ASPM states disabled per hardware errata.
6785 **/
__e1000e_disable_aspm(struct pci_dev * pdev,u16 state,int locked)6786 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6787 {
6788 struct pci_dev *parent = pdev->bus->self;
6789 u16 aspm_dis_mask = 0;
6790 u16 pdev_aspmc, parent_aspmc;
6791
6792 switch (state) {
6793 case PCIE_LINK_STATE_L0S:
6794 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6795 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6796 fallthrough; /* can't have L1 without L0s */
6797 case PCIE_LINK_STATE_L1:
6798 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6799 break;
6800 default:
6801 return;
6802 }
6803
6804 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6805 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6806
6807 if (parent) {
6808 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6809 &parent_aspmc);
6810 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6811 }
6812
6813 /* Nothing to do if the ASPM states to be disabled already are */
6814 if (!(pdev_aspmc & aspm_dis_mask) &&
6815 (!parent || !(parent_aspmc & aspm_dis_mask)))
6816 return;
6817
6818 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6819 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6820 "L0s" : "",
6821 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6822 "L1" : "");
6823
6824 #ifdef CONFIG_PCIEASPM
6825 if (locked)
6826 pci_disable_link_state_locked(pdev, state);
6827 else
6828 pci_disable_link_state(pdev, state);
6829
6830 /* Double-check ASPM control. If not disabled by the above, the
6831 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6832 * not enabled); override by writing PCI config space directly.
6833 */
6834 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6835 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6836
6837 if (!(aspm_dis_mask & pdev_aspmc))
6838 return;
6839 #endif
6840
6841 /* Both device and parent should have the same ASPM setting.
6842 * Disable ASPM in downstream component first and then upstream.
6843 */
6844 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6845
6846 if (parent)
6847 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6848 aspm_dis_mask);
6849 }
6850
6851 /**
6852 * e1000e_disable_aspm - Disable ASPM states.
6853 * @pdev: pointer to PCI device struct
6854 * @state: bit-mask of ASPM states to disable
6855 *
6856 * This function acquires the pci_bus_sem!
6857 * Some devices *must* have certain ASPM states disabled per hardware errata.
6858 **/
e1000e_disable_aspm(struct pci_dev * pdev,u16 state)6859 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6860 {
6861 __e1000e_disable_aspm(pdev, state, 0);
6862 }
6863
6864 /**
6865 * e1000e_disable_aspm_locked - Disable ASPM states.
6866 * @pdev: pointer to PCI device struct
6867 * @state: bit-mask of ASPM states to disable
6868 *
6869 * This function must be called with pci_bus_sem acquired!
6870 * Some devices *must* have certain ASPM states disabled per hardware errata.
6871 **/
e1000e_disable_aspm_locked(struct pci_dev * pdev,u16 state)6872 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6873 {
6874 __e1000e_disable_aspm(pdev, state, 1);
6875 }
6876
e1000e_pm_thaw(struct device * dev)6877 static int e1000e_pm_thaw(struct device *dev)
6878 {
6879 struct net_device *netdev = dev_get_drvdata(dev);
6880 struct e1000_adapter *adapter = netdev_priv(netdev);
6881 int rc = 0;
6882
6883 e1000e_set_interrupt_capability(adapter);
6884
6885 rtnl_lock();
6886 if (netif_running(netdev)) {
6887 rc = e1000_request_irq(adapter);
6888 if (rc)
6889 goto err_irq;
6890
6891 e1000e_up(adapter);
6892 }
6893
6894 netif_device_attach(netdev);
6895 err_irq:
6896 rtnl_unlock();
6897
6898 return rc;
6899 }
6900
__e1000_resume(struct pci_dev * pdev)6901 static int __e1000_resume(struct pci_dev *pdev)
6902 {
6903 struct net_device *netdev = pci_get_drvdata(pdev);
6904 struct e1000_adapter *adapter = netdev_priv(netdev);
6905 struct e1000_hw *hw = &adapter->hw;
6906 u16 aspm_disable_flag = 0;
6907
6908 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6909 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6910 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6911 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6912 if (aspm_disable_flag)
6913 e1000e_disable_aspm(pdev, aspm_disable_flag);
6914
6915 pci_set_master(pdev);
6916
6917 if (hw->mac.type >= e1000_pch2lan)
6918 e1000_resume_workarounds_pchlan(&adapter->hw);
6919
6920 e1000e_power_up_phy(adapter);
6921
6922 /* report the system wakeup cause from S3/S4 */
6923 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6924 u16 phy_data;
6925
6926 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6927 if (phy_data) {
6928 e_info("PHY Wakeup cause - %s\n",
6929 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6930 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6931 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6932 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6933 phy_data & E1000_WUS_LNKC ?
6934 "Link Status Change" : "other");
6935 }
6936 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6937 } else {
6938 u32 wus = er32(WUS);
6939
6940 if (wus) {
6941 e_info("MAC Wakeup cause - %s\n",
6942 wus & E1000_WUS_EX ? "Unicast Packet" :
6943 wus & E1000_WUS_MC ? "Multicast Packet" :
6944 wus & E1000_WUS_BC ? "Broadcast Packet" :
6945 wus & E1000_WUS_MAG ? "Magic Packet" :
6946 wus & E1000_WUS_LNKC ? "Link Status Change" :
6947 "other");
6948 }
6949 ew32(WUS, ~0);
6950 }
6951
6952 e1000e_reset(adapter);
6953
6954 e1000_init_manageability_pt(adapter);
6955
6956 /* If the controller has AMT, do not set DRV_LOAD until the interface
6957 * is up. For all other cases, let the f/w know that the h/w is now
6958 * under the control of the driver.
6959 */
6960 if (!(adapter->flags & FLAG_HAS_AMT))
6961 e1000e_get_hw_control(adapter);
6962
6963 return 0;
6964 }
6965
e1000e_pm_prepare(struct device * dev)6966 static __maybe_unused int e1000e_pm_prepare(struct device *dev)
6967 {
6968 return pm_runtime_suspended(dev) &&
6969 pm_suspend_via_firmware();
6970 }
6971
e1000e_pm_suspend(struct device * dev)6972 static __maybe_unused int e1000e_pm_suspend(struct device *dev)
6973 {
6974 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6975 struct e1000_adapter *adapter = netdev_priv(netdev);
6976 struct pci_dev *pdev = to_pci_dev(dev);
6977 int rc;
6978
6979 e1000e_flush_lpic(pdev);
6980
6981 e1000e_pm_freeze(dev);
6982
6983 rc = __e1000_shutdown(pdev, false);
6984 if (!rc) {
6985 /* Introduce S0ix implementation */
6986 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6987 e1000e_s0ix_entry_flow(adapter);
6988 }
6989
6990 return 0;
6991 }
6992
e1000e_pm_resume(struct device * dev)6993 static __maybe_unused int e1000e_pm_resume(struct device *dev)
6994 {
6995 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6996 struct e1000_adapter *adapter = netdev_priv(netdev);
6997 struct pci_dev *pdev = to_pci_dev(dev);
6998 int rc;
6999
7000 /* Introduce S0ix implementation */
7001 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
7002 e1000e_s0ix_exit_flow(adapter);
7003
7004 rc = __e1000_resume(pdev);
7005 if (rc)
7006 return rc;
7007
7008 return e1000e_pm_thaw(dev);
7009 }
7010
e1000e_pm_runtime_idle(struct device * dev)7011 static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
7012 {
7013 struct net_device *netdev = dev_get_drvdata(dev);
7014 struct e1000_adapter *adapter = netdev_priv(netdev);
7015 u16 eee_lp;
7016
7017 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
7018
7019 if (!e1000e_has_link(adapter)) {
7020 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
7021 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
7022 }
7023
7024 return -EBUSY;
7025 }
7026
e1000e_pm_runtime_resume(struct device * dev)7027 static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev)
7028 {
7029 struct pci_dev *pdev = to_pci_dev(dev);
7030 struct net_device *netdev = pci_get_drvdata(pdev);
7031 struct e1000_adapter *adapter = netdev_priv(netdev);
7032 int rc;
7033
7034 pdev->pme_poll = true;
7035
7036 rc = __e1000_resume(pdev);
7037 if (rc)
7038 return rc;
7039
7040 if (netdev->flags & IFF_UP)
7041 e1000e_up(adapter);
7042
7043 return rc;
7044 }
7045
e1000e_pm_runtime_suspend(struct device * dev)7046 static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev)
7047 {
7048 struct pci_dev *pdev = to_pci_dev(dev);
7049 struct net_device *netdev = pci_get_drvdata(pdev);
7050 struct e1000_adapter *adapter = netdev_priv(netdev);
7051
7052 if (netdev->flags & IFF_UP) {
7053 int count = E1000_CHECK_RESET_COUNT;
7054
7055 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
7056 usleep_range(10000, 11000);
7057
7058 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7059
7060 /* Down the device without resetting the hardware */
7061 e1000e_down(adapter, false);
7062 }
7063
7064 if (__e1000_shutdown(pdev, true)) {
7065 e1000e_pm_runtime_resume(dev);
7066 return -EBUSY;
7067 }
7068
7069 return 0;
7070 }
7071
e1000_shutdown(struct pci_dev * pdev)7072 static void e1000_shutdown(struct pci_dev *pdev)
7073 {
7074 e1000e_flush_lpic(pdev);
7075
7076 e1000e_pm_freeze(&pdev->dev);
7077
7078 __e1000_shutdown(pdev, false);
7079 }
7080
7081 #ifdef CONFIG_NET_POLL_CONTROLLER
7082
e1000_intr_msix(int __always_unused irq,void * data)7083 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
7084 {
7085 struct net_device *netdev = data;
7086 struct e1000_adapter *adapter = netdev_priv(netdev);
7087
7088 if (adapter->msix_entries) {
7089 int vector, msix_irq;
7090
7091 vector = 0;
7092 msix_irq = adapter->msix_entries[vector].vector;
7093 if (disable_hardirq(msix_irq))
7094 e1000_intr_msix_rx(msix_irq, netdev);
7095 enable_irq(msix_irq);
7096
7097 vector++;
7098 msix_irq = adapter->msix_entries[vector].vector;
7099 if (disable_hardirq(msix_irq))
7100 e1000_intr_msix_tx(msix_irq, netdev);
7101 enable_irq(msix_irq);
7102
7103 vector++;
7104 msix_irq = adapter->msix_entries[vector].vector;
7105 if (disable_hardirq(msix_irq))
7106 e1000_msix_other(msix_irq, netdev);
7107 enable_irq(msix_irq);
7108 }
7109
7110 return IRQ_HANDLED;
7111 }
7112
7113 /**
7114 * e1000_netpoll
7115 * @netdev: network interface device structure
7116 *
7117 * Polling 'interrupt' - used by things like netconsole to send skbs
7118 * without having to re-enable interrupts. It's not called while
7119 * the interrupt routine is executing.
7120 */
e1000_netpoll(struct net_device * netdev)7121 static void e1000_netpoll(struct net_device *netdev)
7122 {
7123 struct e1000_adapter *adapter = netdev_priv(netdev);
7124
7125 switch (adapter->int_mode) {
7126 case E1000E_INT_MODE_MSIX:
7127 e1000_intr_msix(adapter->pdev->irq, netdev);
7128 break;
7129 case E1000E_INT_MODE_MSI:
7130 if (disable_hardirq(adapter->pdev->irq))
7131 e1000_intr_msi(adapter->pdev->irq, netdev);
7132 enable_irq(adapter->pdev->irq);
7133 break;
7134 default: /* E1000E_INT_MODE_LEGACY */
7135 if (disable_hardirq(adapter->pdev->irq))
7136 e1000_intr(adapter->pdev->irq, netdev);
7137 enable_irq(adapter->pdev->irq);
7138 break;
7139 }
7140 }
7141 #endif
7142
7143 /**
7144 * e1000_io_error_detected - called when PCI error is detected
7145 * @pdev: Pointer to PCI device
7146 * @state: The current pci connection state
7147 *
7148 * This function is called after a PCI bus error affecting
7149 * this device has been detected.
7150 */
e1000_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7151 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7152 pci_channel_state_t state)
7153 {
7154 e1000e_pm_freeze(&pdev->dev);
7155
7156 if (state == pci_channel_io_perm_failure)
7157 return PCI_ERS_RESULT_DISCONNECT;
7158
7159 pci_disable_device(pdev);
7160
7161 /* Request a slot reset. */
7162 return PCI_ERS_RESULT_NEED_RESET;
7163 }
7164
7165 /**
7166 * e1000_io_slot_reset - called after the pci bus has been reset.
7167 * @pdev: Pointer to PCI device
7168 *
7169 * Restart the card from scratch, as if from a cold-boot. Implementation
7170 * resembles the first-half of the e1000e_pm_resume routine.
7171 */
e1000_io_slot_reset(struct pci_dev * pdev)7172 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7173 {
7174 struct net_device *netdev = pci_get_drvdata(pdev);
7175 struct e1000_adapter *adapter = netdev_priv(netdev);
7176 struct e1000_hw *hw = &adapter->hw;
7177 u16 aspm_disable_flag = 0;
7178 int err;
7179 pci_ers_result_t result;
7180
7181 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7182 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7183 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7184 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7185 if (aspm_disable_flag)
7186 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
7187
7188 err = pci_enable_device_mem(pdev);
7189 if (err) {
7190 dev_err(&pdev->dev,
7191 "Cannot re-enable PCI device after reset.\n");
7192 result = PCI_ERS_RESULT_DISCONNECT;
7193 } else {
7194 pdev->state_saved = true;
7195 pci_restore_state(pdev);
7196 pci_set_master(pdev);
7197
7198 pci_enable_wake(pdev, PCI_D3hot, 0);
7199 pci_enable_wake(pdev, PCI_D3cold, 0);
7200
7201 e1000e_reset(adapter);
7202 ew32(WUS, ~0);
7203 result = PCI_ERS_RESULT_RECOVERED;
7204 }
7205
7206 return result;
7207 }
7208
7209 /**
7210 * e1000_io_resume - called when traffic can start flowing again.
7211 * @pdev: Pointer to PCI device
7212 *
7213 * This callback is called when the error recovery driver tells us that
7214 * its OK to resume normal operation. Implementation resembles the
7215 * second-half of the e1000e_pm_resume routine.
7216 */
e1000_io_resume(struct pci_dev * pdev)7217 static void e1000_io_resume(struct pci_dev *pdev)
7218 {
7219 struct net_device *netdev = pci_get_drvdata(pdev);
7220 struct e1000_adapter *adapter = netdev_priv(netdev);
7221
7222 e1000_init_manageability_pt(adapter);
7223
7224 e1000e_pm_thaw(&pdev->dev);
7225
7226 /* If the controller has AMT, do not set DRV_LOAD until the interface
7227 * is up. For all other cases, let the f/w know that the h/w is now
7228 * under the control of the driver.
7229 */
7230 if (!(adapter->flags & FLAG_HAS_AMT))
7231 e1000e_get_hw_control(adapter);
7232 }
7233
e1000_print_device_info(struct e1000_adapter * adapter)7234 static void e1000_print_device_info(struct e1000_adapter *adapter)
7235 {
7236 struct e1000_hw *hw = &adapter->hw;
7237 struct net_device *netdev = adapter->netdev;
7238 u32 ret_val;
7239 u8 pba_str[E1000_PBANUM_LENGTH];
7240
7241 /* print bus type/speed/width info */
7242 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7243 /* bus width */
7244 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7245 "Width x1"),
7246 /* MAC address */
7247 netdev->dev_addr);
7248 e_info("Intel(R) PRO/%s Network Connection\n",
7249 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7250 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7251 E1000_PBANUM_LENGTH);
7252 if (ret_val)
7253 strscpy((char *)pba_str, "Unknown", sizeof(pba_str));
7254 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7255 hw->mac.type, hw->phy.type, pba_str);
7256 }
7257
e1000_eeprom_checks(struct e1000_adapter * adapter)7258 static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7259 {
7260 struct e1000_hw *hw = &adapter->hw;
7261 int ret_val;
7262 u16 buf = 0;
7263
7264 if (hw->mac.type != e1000_82573)
7265 return;
7266
7267 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
7268 le16_to_cpus(&buf);
7269 if (!ret_val && (!(buf & BIT(0)))) {
7270 /* Deep Smart Power Down (DSPD) */
7271 dev_warn(&adapter->pdev->dev,
7272 "Warning: detected DSPD enabled in EEPROM\n");
7273 }
7274 }
7275
e1000_fix_features(struct net_device * netdev,netdev_features_t features)7276 static netdev_features_t e1000_fix_features(struct net_device *netdev,
7277 netdev_features_t features)
7278 {
7279 struct e1000_adapter *adapter = netdev_priv(netdev);
7280 struct e1000_hw *hw = &adapter->hw;
7281
7282 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7283 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7284 features &= ~NETIF_F_RXFCS;
7285
7286 /* Since there is no support for separate Rx/Tx vlan accel
7287 * enable/disable make sure Tx flag is always in same state as Rx.
7288 */
7289 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7290 features |= NETIF_F_HW_VLAN_CTAG_TX;
7291 else
7292 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7293
7294 return features;
7295 }
7296
e1000_set_features(struct net_device * netdev,netdev_features_t features)7297 static int e1000_set_features(struct net_device *netdev,
7298 netdev_features_t features)
7299 {
7300 struct e1000_adapter *adapter = netdev_priv(netdev);
7301 netdev_features_t changed = features ^ netdev->features;
7302
7303 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7304 adapter->flags |= FLAG_TSO_FORCE;
7305
7306 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7307 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7308 NETIF_F_RXALL)))
7309 return 0;
7310
7311 if (changed & NETIF_F_RXFCS) {
7312 if (features & NETIF_F_RXFCS) {
7313 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7314 } else {
7315 /* We need to take it back to defaults, which might mean
7316 * stripping is still disabled at the adapter level.
7317 */
7318 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7319 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7320 else
7321 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7322 }
7323 }
7324
7325 netdev->features = features;
7326
7327 if (netif_running(netdev))
7328 e1000e_reinit_locked(adapter);
7329 else
7330 e1000e_reset(adapter);
7331
7332 return 1;
7333 }
7334
7335 static const struct net_device_ops e1000e_netdev_ops = {
7336 .ndo_open = e1000e_open,
7337 .ndo_stop = e1000e_close,
7338 .ndo_start_xmit = e1000_xmit_frame,
7339 .ndo_get_stats64 = e1000e_get_stats64,
7340 .ndo_set_rx_mode = e1000e_set_rx_mode,
7341 .ndo_set_mac_address = e1000_set_mac,
7342 .ndo_change_mtu = e1000_change_mtu,
7343 .ndo_eth_ioctl = e1000_ioctl,
7344 .ndo_tx_timeout = e1000_tx_timeout,
7345 .ndo_validate_addr = eth_validate_addr,
7346
7347 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7348 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7349 #ifdef CONFIG_NET_POLL_CONTROLLER
7350 .ndo_poll_controller = e1000_netpoll,
7351 #endif
7352 .ndo_set_features = e1000_set_features,
7353 .ndo_fix_features = e1000_fix_features,
7354 .ndo_features_check = passthru_features_check,
7355 };
7356
7357 /**
7358 * e1000_probe - Device Initialization Routine
7359 * @pdev: PCI device information struct
7360 * @ent: entry in e1000_pci_tbl
7361 *
7362 * Returns 0 on success, negative on failure
7363 *
7364 * e1000_probe initializes an adapter identified by a pci_dev structure.
7365 * The OS initialization, configuring of the adapter private structure,
7366 * and a hardware reset occur.
7367 **/
e1000_probe(struct pci_dev * pdev,const struct pci_device_id * ent)7368 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7369 {
7370 struct net_device *netdev;
7371 struct e1000_adapter *adapter;
7372 struct e1000_hw *hw;
7373 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7374 resource_size_t mmio_start, mmio_len;
7375 resource_size_t flash_start, flash_len;
7376 static int cards_found;
7377 u16 aspm_disable_flag = 0;
7378 u16 eeprom_data = 0;
7379 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7380 int bars, i, err;
7381 s32 ret_val = 0;
7382
7383 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7384 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7385 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7386 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7387 if (aspm_disable_flag)
7388 e1000e_disable_aspm(pdev, aspm_disable_flag);
7389
7390 err = pci_enable_device_mem(pdev);
7391 if (err)
7392 return err;
7393
7394 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7395 if (err) {
7396 dev_err(&pdev->dev,
7397 "No usable DMA configuration, aborting\n");
7398 goto err_dma;
7399 }
7400
7401 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7402 err = pci_request_selected_regions_exclusive(pdev, bars,
7403 e1000e_driver_name);
7404 if (err)
7405 goto err_pci_reg;
7406
7407 pci_set_master(pdev);
7408 /* PCI config space info */
7409 err = pci_save_state(pdev);
7410 if (err)
7411 goto err_alloc_etherdev;
7412
7413 err = -ENOMEM;
7414 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7415 if (!netdev)
7416 goto err_alloc_etherdev;
7417
7418 SET_NETDEV_DEV(netdev, &pdev->dev);
7419
7420 netdev->irq = pdev->irq;
7421
7422 pci_set_drvdata(pdev, netdev);
7423 adapter = netdev_priv(netdev);
7424 hw = &adapter->hw;
7425 adapter->netdev = netdev;
7426 adapter->pdev = pdev;
7427 adapter->ei = ei;
7428 adapter->pba = ei->pba;
7429 adapter->flags = ei->flags;
7430 adapter->flags2 = ei->flags2;
7431 adapter->hw.adapter = adapter;
7432 adapter->hw.mac.type = ei->mac;
7433 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7434 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7435
7436 mmio_start = pci_resource_start(pdev, 0);
7437 mmio_len = pci_resource_len(pdev, 0);
7438
7439 err = -EIO;
7440 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7441 if (!adapter->hw.hw_addr)
7442 goto err_ioremap;
7443
7444 if ((adapter->flags & FLAG_HAS_FLASH) &&
7445 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7446 (hw->mac.type < e1000_pch_spt)) {
7447 flash_start = pci_resource_start(pdev, 1);
7448 flash_len = pci_resource_len(pdev, 1);
7449 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7450 if (!adapter->hw.flash_address)
7451 goto err_flashmap;
7452 }
7453
7454 /* Set default EEE advertisement */
7455 if (adapter->flags2 & FLAG2_HAS_EEE)
7456 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7457
7458 /* construct the net_device struct */
7459 netdev->netdev_ops = &e1000e_netdev_ops;
7460 e1000e_set_ethtool_ops(netdev);
7461 netdev->watchdog_timeo = 5 * HZ;
7462 netif_napi_add(netdev, &adapter->napi, e1000e_poll);
7463 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7464
7465 netdev->mem_start = mmio_start;
7466 netdev->mem_end = mmio_start + mmio_len;
7467
7468 adapter->bd_number = cards_found++;
7469
7470 e1000e_check_options(adapter);
7471
7472 /* setup adapter struct */
7473 err = e1000_sw_init(adapter);
7474 if (err)
7475 goto err_sw_init;
7476
7477 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7478 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7479 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7480
7481 err = ei->get_variants(adapter);
7482 if (err)
7483 goto err_hw_init;
7484
7485 if ((adapter->flags & FLAG_IS_ICH) &&
7486 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7487 (hw->mac.type < e1000_pch_spt))
7488 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7489
7490 hw->mac.ops.get_bus_info(&adapter->hw);
7491
7492 adapter->hw.phy.autoneg_wait_to_complete = 0;
7493
7494 /* Copper options */
7495 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7496 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7497 adapter->hw.phy.disable_polarity_correction = 0;
7498 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7499 }
7500
7501 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7502 dev_info(&pdev->dev,
7503 "PHY reset is blocked due to SOL/IDER session.\n");
7504
7505 /* Set initial default active device features */
7506 netdev->features = (NETIF_F_SG |
7507 NETIF_F_HW_VLAN_CTAG_RX |
7508 NETIF_F_HW_VLAN_CTAG_TX |
7509 NETIF_F_TSO |
7510 NETIF_F_TSO6 |
7511 NETIF_F_RXHASH |
7512 NETIF_F_RXCSUM |
7513 NETIF_F_HW_CSUM);
7514
7515 /* disable TSO for pcie and 10/100 speeds to avoid
7516 * some hardware issues and for i219 to fix transfer
7517 * speed being capped at 60%
7518 */
7519 if (!(adapter->flags & FLAG_TSO_FORCE)) {
7520 switch (adapter->link_speed) {
7521 case SPEED_10:
7522 case SPEED_100:
7523 e_info("10/100 speed: disabling TSO\n");
7524 netdev->features &= ~NETIF_F_TSO;
7525 netdev->features &= ~NETIF_F_TSO6;
7526 break;
7527 case SPEED_1000:
7528 netdev->features |= NETIF_F_TSO;
7529 netdev->features |= NETIF_F_TSO6;
7530 break;
7531 default:
7532 /* oops */
7533 break;
7534 }
7535 if (hw->mac.type == e1000_pch_spt) {
7536 netdev->features &= ~NETIF_F_TSO;
7537 netdev->features &= ~NETIF_F_TSO6;
7538 }
7539 }
7540
7541 /* Set user-changeable features (subset of all device features) */
7542 netdev->hw_features = netdev->features;
7543 netdev->hw_features |= NETIF_F_RXFCS;
7544 netdev->priv_flags |= IFF_SUPP_NOFCS;
7545 netdev->hw_features |= NETIF_F_RXALL;
7546
7547 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7548 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7549
7550 netdev->vlan_features |= (NETIF_F_SG |
7551 NETIF_F_TSO |
7552 NETIF_F_TSO6 |
7553 NETIF_F_HW_CSUM);
7554
7555 netdev->priv_flags |= IFF_UNICAST_FLT;
7556
7557 netdev->features |= NETIF_F_HIGHDMA;
7558 netdev->vlan_features |= NETIF_F_HIGHDMA;
7559
7560 /* MTU range: 68 - max_hw_frame_size */
7561 netdev->min_mtu = ETH_MIN_MTU;
7562 netdev->max_mtu = adapter->max_hw_frame_size -
7563 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7564
7565 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7566 adapter->flags |= FLAG_MNG_PT_ENABLED;
7567
7568 /* before reading the NVM, reset the controller to
7569 * put the device in a known good starting state
7570 */
7571 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7572
7573 /* systems with ASPM and others may see the checksum fail on the first
7574 * attempt. Let's give it a few tries
7575 */
7576 for (i = 0;; i++) {
7577 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7578 break;
7579 if (i == 2) {
7580 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7581 err = -EIO;
7582 goto err_eeprom;
7583 }
7584 }
7585
7586 e1000_eeprom_checks(adapter);
7587
7588 /* copy the MAC address */
7589 if (e1000e_read_mac_addr(&adapter->hw))
7590 dev_err(&pdev->dev,
7591 "NVM Read Error while reading MAC address\n");
7592
7593 eth_hw_addr_set(netdev, adapter->hw.mac.addr);
7594
7595 if (!is_valid_ether_addr(netdev->dev_addr)) {
7596 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7597 netdev->dev_addr);
7598 err = -EIO;
7599 goto err_eeprom;
7600 }
7601
7602 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7603 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7604
7605 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7606 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7607 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7608 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7609 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7610
7611 /* Initialize link parameters. User can change them with ethtool */
7612 adapter->hw.mac.autoneg = 1;
7613 adapter->fc_autoneg = true;
7614 adapter->hw.fc.requested_mode = e1000_fc_default;
7615 adapter->hw.fc.current_mode = e1000_fc_default;
7616 adapter->hw.phy.autoneg_advertised = 0x2f;
7617
7618 /* Initial Wake on LAN setting - If APM wake is enabled in
7619 * the EEPROM, enable the ACPI Magic Packet filter
7620 */
7621 if (adapter->flags & FLAG_APME_IN_WUC) {
7622 /* APME bit in EEPROM is mapped to WUC.APME */
7623 eeprom_data = er32(WUC);
7624 eeprom_apme_mask = E1000_WUC_APME;
7625 if ((hw->mac.type > e1000_ich10lan) &&
7626 (eeprom_data & E1000_WUC_PHY_WAKE))
7627 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7628 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7629 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7630 (adapter->hw.bus.func == 1))
7631 ret_val = e1000_read_nvm(&adapter->hw,
7632 NVM_INIT_CONTROL3_PORT_B,
7633 1, &eeprom_data);
7634 else
7635 ret_val = e1000_read_nvm(&adapter->hw,
7636 NVM_INIT_CONTROL3_PORT_A,
7637 1, &eeprom_data);
7638 }
7639
7640 /* fetch WoL from EEPROM */
7641 if (ret_val)
7642 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7643 else if (eeprom_data & eeprom_apme_mask)
7644 adapter->eeprom_wol |= E1000_WUFC_MAG;
7645
7646 /* now that we have the eeprom settings, apply the special cases
7647 * where the eeprom may be wrong or the board simply won't support
7648 * wake on lan on a particular port
7649 */
7650 if (!(adapter->flags & FLAG_HAS_WOL))
7651 adapter->eeprom_wol = 0;
7652
7653 /* initialize the wol settings based on the eeprom settings */
7654 adapter->wol = adapter->eeprom_wol;
7655
7656 /* make sure adapter isn't asleep if manageability is enabled */
7657 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7658 (hw->mac.ops.check_mng_mode(hw)))
7659 device_wakeup_enable(&pdev->dev);
7660
7661 /* save off EEPROM version number */
7662 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7663
7664 if (ret_val) {
7665 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7666 adapter->eeprom_vers = 0;
7667 }
7668
7669 /* init PTP hardware clock */
7670 e1000e_ptp_init(adapter);
7671
7672 /* reset the hardware with the new settings */
7673 e1000e_reset(adapter);
7674
7675 /* If the controller has AMT, do not set DRV_LOAD until the interface
7676 * is up. For all other cases, let the f/w know that the h/w is now
7677 * under the control of the driver.
7678 */
7679 if (!(adapter->flags & FLAG_HAS_AMT))
7680 e1000e_get_hw_control(adapter);
7681
7682 if (hw->mac.type >= e1000_pch_cnp)
7683 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7684
7685 strscpy(netdev->name, "eth%d", sizeof(netdev->name));
7686 err = register_netdev(netdev);
7687 if (err)
7688 goto err_register;
7689
7690 /* carrier off reporting is important to ethtool even BEFORE open */
7691 netif_carrier_off(netdev);
7692
7693 e1000_print_device_info(adapter);
7694
7695 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE);
7696
7697 if (pci_dev_run_wake(pdev))
7698 pm_runtime_put_noidle(&pdev->dev);
7699
7700 return 0;
7701
7702 err_register:
7703 if (!(adapter->flags & FLAG_HAS_AMT))
7704 e1000e_release_hw_control(adapter);
7705 err_eeprom:
7706 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7707 e1000_phy_hw_reset(&adapter->hw);
7708 err_hw_init:
7709 kfree(adapter->tx_ring);
7710 kfree(adapter->rx_ring);
7711 err_sw_init:
7712 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7713 iounmap(adapter->hw.flash_address);
7714 e1000e_reset_interrupt_capability(adapter);
7715 err_flashmap:
7716 iounmap(adapter->hw.hw_addr);
7717 err_ioremap:
7718 free_netdev(netdev);
7719 err_alloc_etherdev:
7720 pci_release_mem_regions(pdev);
7721 err_pci_reg:
7722 err_dma:
7723 pci_disable_device(pdev);
7724 return err;
7725 }
7726
7727 /**
7728 * e1000_remove - Device Removal Routine
7729 * @pdev: PCI device information struct
7730 *
7731 * e1000_remove is called by the PCI subsystem to alert the driver
7732 * that it should release a PCI device. This could be caused by a
7733 * Hot-Plug event, or because the driver is going to be removed from
7734 * memory.
7735 **/
e1000_remove(struct pci_dev * pdev)7736 static void e1000_remove(struct pci_dev *pdev)
7737 {
7738 struct net_device *netdev = pci_get_drvdata(pdev);
7739 struct e1000_adapter *adapter = netdev_priv(netdev);
7740
7741 e1000e_ptp_remove(adapter);
7742
7743 /* The timers may be rescheduled, so explicitly disable them
7744 * from being rescheduled.
7745 */
7746 set_bit(__E1000_DOWN, &adapter->state);
7747 del_timer_sync(&adapter->watchdog_timer);
7748 del_timer_sync(&adapter->phy_info_timer);
7749
7750 cancel_work_sync(&adapter->reset_task);
7751 cancel_work_sync(&adapter->watchdog_task);
7752 cancel_work_sync(&adapter->downshift_task);
7753 cancel_work_sync(&adapter->update_phy_task);
7754 cancel_work_sync(&adapter->print_hang_task);
7755
7756 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7757 cancel_work_sync(&adapter->tx_hwtstamp_work);
7758 if (adapter->tx_hwtstamp_skb) {
7759 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7760 adapter->tx_hwtstamp_skb = NULL;
7761 }
7762 }
7763
7764 unregister_netdev(netdev);
7765
7766 if (pci_dev_run_wake(pdev))
7767 pm_runtime_get_noresume(&pdev->dev);
7768
7769 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7770 * would have already happened in close and is redundant.
7771 */
7772 e1000e_release_hw_control(adapter);
7773
7774 e1000e_reset_interrupt_capability(adapter);
7775 kfree(adapter->tx_ring);
7776 kfree(adapter->rx_ring);
7777
7778 iounmap(adapter->hw.hw_addr);
7779 if ((adapter->hw.flash_address) &&
7780 (adapter->hw.mac.type < e1000_pch_spt))
7781 iounmap(adapter->hw.flash_address);
7782 pci_release_mem_regions(pdev);
7783
7784 free_netdev(netdev);
7785
7786 pci_disable_device(pdev);
7787 }
7788
7789 /* PCI Error Recovery (ERS) */
7790 static const struct pci_error_handlers e1000_err_handler = {
7791 .error_detected = e1000_io_error_detected,
7792 .slot_reset = e1000_io_slot_reset,
7793 .resume = e1000_io_resume,
7794 };
7795
7796 static const struct pci_device_id e1000_pci_tbl[] = {
7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7798 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7801 board_82571 },
7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7807
7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7812
7813 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7816
7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7820
7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7822 board_80003es2lan },
7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7824 board_80003es2lan },
7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7826 board_80003es2lan },
7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7828 board_80003es2lan },
7829
7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7838
7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7848
7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7852
7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7856
7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7861
7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7864
7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7868 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp },
7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp },
7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp },
7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp },
7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp },
7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp },
7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp },
7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp },
7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp },
7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp },
7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp },
7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp },
7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp },
7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp },
7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp },
7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp },
7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp },
7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM19), board_pch_adp },
7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V19), board_pch_adp },
7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp },
7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp },
7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp },
7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp },
7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp },
7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp },
7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp },
7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp },
7920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp },
7921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp },
7922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp },
7923 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp },
7924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp },
7925 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp },
7926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), board_pch_mtp },
7927 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), board_pch_mtp },
7928
7929 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7930 };
7931 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7932
7933 static const struct dev_pm_ops e1000_pm_ops = {
7934 #ifdef CONFIG_PM_SLEEP
7935 .prepare = e1000e_pm_prepare,
7936 .suspend = e1000e_pm_suspend,
7937 .resume = e1000e_pm_resume,
7938 .freeze = e1000e_pm_freeze,
7939 .thaw = e1000e_pm_thaw,
7940 .poweroff = e1000e_pm_suspend,
7941 .restore = e1000e_pm_resume,
7942 #endif
7943 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7944 e1000e_pm_runtime_idle)
7945 };
7946
7947 /* PCI Device API Driver */
7948 static struct pci_driver e1000_driver = {
7949 .name = e1000e_driver_name,
7950 .id_table = e1000_pci_tbl,
7951 .probe = e1000_probe,
7952 .remove = e1000_remove,
7953 .driver = {
7954 .pm = &e1000_pm_ops,
7955 },
7956 .shutdown = e1000_shutdown,
7957 .err_handler = &e1000_err_handler
7958 };
7959
7960 /**
7961 * e1000_init_module - Driver Registration Routine
7962 *
7963 * e1000_init_module is the first routine called when the driver is
7964 * loaded. All it does is register with the PCI subsystem.
7965 **/
e1000_init_module(void)7966 static int __init e1000_init_module(void)
7967 {
7968 pr_info("Intel(R) PRO/1000 Network Driver\n");
7969 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7970
7971 return pci_register_driver(&e1000_driver);
7972 }
7973 module_init(e1000_init_module);
7974
7975 /**
7976 * e1000_exit_module - Driver Exit Cleanup Routine
7977 *
7978 * e1000_exit_module is called just before the driver is removed
7979 * from memory.
7980 **/
e1000_exit_module(void)7981 static void __exit e1000_exit_module(void)
7982 {
7983 pci_unregister_driver(&e1000_driver);
7984 }
7985 module_exit(e1000_exit_module);
7986
7987 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7988 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7989 MODULE_LICENSE("GPL v2");
7990
7991 /* netdev.c */
7992