1 /*
2 * sPAPR CPU core device.
3 *
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9 #ifndef HW_SPAPR_CPU_CORE_H
10 #define HW_SPAPR_CPU_CORE_H
11
12 #include "hw/cpu/core.h"
13 #include "hw/qdev-core.h"
14 #include "target/ppc/cpu-qom.h"
15 #include "target/ppc/cpu.h"
16 #include "qom/object.h"
17
18 #define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
19 OBJECT_DECLARE_TYPE(SpaprCpuCore, SpaprCpuCoreClass,
20 SPAPR_CPU_CORE)
21
22 #define SPAPR_CPU_CORE_TYPE_NAME(model) model "-" TYPE_SPAPR_CPU_CORE
23
24 struct SpaprCpuCore {
25 /*< private >*/
26 CPUCore parent_obj;
27
28 /*< public >*/
29 PowerPCCPU **threads;
30 int node_id;
31 };
32
33 struct SpaprCpuCoreClass {
34 DeviceClass parent_class;
35 const char *cpu_type;
36 };
37
38 const char *spapr_get_cpu_core_type(const char *cpu_type);
39 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
40 target_ulong r1, target_ulong r3,
41 target_ulong r4);
42
43 struct nested_ppc_state;
44
45 typedef struct SpaprCpuState {
46 uint64_t vpa_addr;
47 uint64_t slb_shadow_addr, slb_shadow_size;
48 uint64_t dtl_addr, dtl_size;
49 bool prod; /* not migrated, only used to improve dispatch latencies */
50 struct ICPState *icp;
51 struct XiveTCTX *tctx;
52
53 /* Fields for nested-HV support */
54 bool in_nested; /* true while the L2 is executing */
55 struct nested_ppc_state *nested_host_state; /* holds the L1 state while L2 executes */
56 } SpaprCpuState;
57
spapr_cpu_state(PowerPCCPU * cpu)58 static inline SpaprCpuState *spapr_cpu_state(PowerPCCPU *cpu)
59 {
60 return (SpaprCpuState *)cpu->machine_data;
61 }
62
63 #endif
64