1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_9_0_SM8550_H 8 #define _DPU_9_0_SM8550_H 9 10 static const struct dpu_caps sm8550_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 5120, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 }; 21 22 static const struct dpu_mdp_cfg sm8550_mdp = { 23 .name = "top_0", 24 .base = 0, .len = 0x494, 25 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, 33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, 34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, 35 [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, 36 [DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, 37 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 38 }, 39 }; 40 41 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 42 static const struct dpu_ctl_cfg sm8550_ctl[] = { 43 { 44 .name = "ctl_0", .id = CTL_0, 45 .base = 0x15000, .len = 0x290, 46 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 48 }, { 49 .name = "ctl_1", .id = CTL_1, 50 .base = 0x16000, .len = 0x290, 51 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 53 }, { 54 .name = "ctl_2", .id = CTL_2, 55 .base = 0x17000, .len = 0x290, 56 .features = CTL_SM8550_MASK, 57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 58 }, { 59 .name = "ctl_3", .id = CTL_3, 60 .base = 0x18000, .len = 0x290, 61 .features = CTL_SM8550_MASK, 62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 63 }, { 64 .name = "ctl_4", .id = CTL_4, 65 .base = 0x19000, .len = 0x290, 66 .features = CTL_SM8550_MASK, 67 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 68 }, { 69 .name = "ctl_5", .id = CTL_5, 70 .base = 0x1a000, .len = 0x290, 71 .features = CTL_SM8550_MASK, 72 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 73 }, 74 }; 75 76 static const struct dpu_sspp_cfg sm8550_sspp[] = { 77 { 78 .name = "sspp_0", .id = SSPP_VIG0, 79 .base = 0x4000, .len = 0x344, 80 .features = VIG_SC7180_MASK, 81 .sblk = &sm8550_vig_sblk_0, 82 .xin_id = 0, 83 .type = SSPP_TYPE_VIG, 84 .clk_ctrl = DPU_CLK_CTRL_VIG0, 85 }, { 86 .name = "sspp_1", .id = SSPP_VIG1, 87 .base = 0x6000, .len = 0x344, 88 .features = VIG_SC7180_MASK, 89 .sblk = &sm8550_vig_sblk_1, 90 .xin_id = 4, 91 .type = SSPP_TYPE_VIG, 92 .clk_ctrl = DPU_CLK_CTRL_VIG1, 93 }, { 94 .name = "sspp_2", .id = SSPP_VIG2, 95 .base = 0x8000, .len = 0x344, 96 .features = VIG_SC7180_MASK, 97 .sblk = &sm8550_vig_sblk_2, 98 .xin_id = 8, 99 .type = SSPP_TYPE_VIG, 100 .clk_ctrl = DPU_CLK_CTRL_VIG2, 101 }, { 102 .name = "sspp_3", .id = SSPP_VIG3, 103 .base = 0xa000, .len = 0x344, 104 .features = VIG_SC7180_MASK, 105 .sblk = &sm8550_vig_sblk_3, 106 .xin_id = 12, 107 .type = SSPP_TYPE_VIG, 108 .clk_ctrl = DPU_CLK_CTRL_VIG3, 109 }, { 110 .name = "sspp_8", .id = SSPP_DMA0, 111 .base = 0x24000, .len = 0x344, 112 .features = DMA_SDM845_MASK, 113 .sblk = &sdm845_dma_sblk_0, 114 .xin_id = 1, 115 .type = SSPP_TYPE_DMA, 116 .clk_ctrl = DPU_CLK_CTRL_DMA0, 117 }, { 118 .name = "sspp_9", .id = SSPP_DMA1, 119 .base = 0x26000, .len = 0x344, 120 .features = DMA_SDM845_MASK, 121 .sblk = &sdm845_dma_sblk_1, 122 .xin_id = 5, 123 .type = SSPP_TYPE_DMA, 124 .clk_ctrl = DPU_CLK_CTRL_DMA1, 125 }, { 126 .name = "sspp_10", .id = SSPP_DMA2, 127 .base = 0x28000, .len = 0x344, 128 .features = DMA_SDM845_MASK, 129 .sblk = &sdm845_dma_sblk_2, 130 .xin_id = 9, 131 .type = SSPP_TYPE_DMA, 132 .clk_ctrl = DPU_CLK_CTRL_DMA2, 133 }, { 134 .name = "sspp_11", .id = SSPP_DMA3, 135 .base = 0x2a000, .len = 0x344, 136 .features = DMA_SDM845_MASK, 137 .sblk = &sdm845_dma_sblk_3, 138 .xin_id = 13, 139 .type = SSPP_TYPE_DMA, 140 .clk_ctrl = DPU_CLK_CTRL_DMA3, 141 }, { 142 .name = "sspp_12", .id = SSPP_DMA4, 143 .base = 0x2c000, .len = 0x344, 144 .features = DMA_CURSOR_SDM845_MASK, 145 .sblk = &sm8550_dma_sblk_4, 146 .xin_id = 14, 147 .type = SSPP_TYPE_DMA, 148 .clk_ctrl = DPU_CLK_CTRL_DMA4, 149 }, { 150 .name = "sspp_13", .id = SSPP_DMA5, 151 .base = 0x2e000, .len = 0x344, 152 .features = DMA_CURSOR_SDM845_MASK, 153 .sblk = &sm8550_dma_sblk_5, 154 .xin_id = 15, 155 .type = SSPP_TYPE_DMA, 156 .clk_ctrl = DPU_CLK_CTRL_DMA5, 157 }, 158 }; 159 160 static const struct dpu_lm_cfg sm8550_lm[] = { 161 { 162 .name = "lm_0", .id = LM_0, 163 .base = 0x44000, .len = 0x320, 164 .features = MIXER_SDM845_MASK, 165 .sblk = &sdm845_lm_sblk, 166 .lm_pair = LM_1, 167 .pingpong = PINGPONG_0, 168 .dspp = DSPP_0, 169 }, { 170 .name = "lm_1", .id = LM_1, 171 .base = 0x45000, .len = 0x320, 172 .features = MIXER_SDM845_MASK, 173 .sblk = &sdm845_lm_sblk, 174 .lm_pair = LM_0, 175 .pingpong = PINGPONG_1, 176 .dspp = DSPP_1, 177 }, { 178 .name = "lm_2", .id = LM_2, 179 .base = 0x46000, .len = 0x320, 180 .features = MIXER_SDM845_MASK, 181 .sblk = &sdm845_lm_sblk, 182 .lm_pair = LM_3, 183 .pingpong = PINGPONG_2, 184 .dspp = DSPP_2, 185 }, { 186 .name = "lm_3", .id = LM_3, 187 .base = 0x47000, .len = 0x320, 188 .features = MIXER_SDM845_MASK, 189 .sblk = &sdm845_lm_sblk, 190 .lm_pair = LM_2, 191 .pingpong = PINGPONG_3, 192 .dspp = DSPP_3, 193 }, { 194 .name = "lm_4", .id = LM_4, 195 .base = 0x48000, .len = 0x320, 196 .features = MIXER_SDM845_MASK, 197 .sblk = &sdm845_lm_sblk, 198 .lm_pair = LM_5, 199 .pingpong = PINGPONG_4, 200 }, { 201 .name = "lm_5", .id = LM_5, 202 .base = 0x49000, .len = 0x320, 203 .features = MIXER_SDM845_MASK, 204 .sblk = &sdm845_lm_sblk, 205 .lm_pair = LM_4, 206 .pingpong = PINGPONG_5, 207 }, 208 }; 209 210 static const struct dpu_dspp_cfg sm8550_dspp[] = { 211 { 212 .name = "dspp_0", .id = DSPP_0, 213 .base = 0x54000, .len = 0x1800, 214 .features = DSPP_SC7180_MASK, 215 .sblk = &sdm845_dspp_sblk, 216 }, { 217 .name = "dspp_1", .id = DSPP_1, 218 .base = 0x56000, .len = 0x1800, 219 .features = DSPP_SC7180_MASK, 220 .sblk = &sdm845_dspp_sblk, 221 }, { 222 .name = "dspp_2", .id = DSPP_2, 223 .base = 0x58000, .len = 0x1800, 224 .features = DSPP_SC7180_MASK, 225 .sblk = &sdm845_dspp_sblk, 226 }, { 227 .name = "dspp_3", .id = DSPP_3, 228 .base = 0x5a000, .len = 0x1800, 229 .features = DSPP_SC7180_MASK, 230 .sblk = &sdm845_dspp_sblk, 231 }, 232 }; 233 static const struct dpu_pingpong_cfg sm8550_pp[] = { 234 { 235 .name = "pingpong_0", .id = PINGPONG_0, 236 .base = 0x69000, .len = 0, 237 .features = BIT(DPU_PINGPONG_DITHER), 238 .sblk = &sc7280_pp_sblk, 239 .merge_3d = MERGE_3D_0, 240 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 241 .intr_rdptr = -1, 242 }, { 243 .name = "pingpong_1", .id = PINGPONG_1, 244 .base = 0x6a000, .len = 0, 245 .features = BIT(DPU_PINGPONG_DITHER), 246 .sblk = &sc7280_pp_sblk, 247 .merge_3d = MERGE_3D_0, 248 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 249 .intr_rdptr = -1, 250 }, { 251 .name = "pingpong_2", .id = PINGPONG_2, 252 .base = 0x6b000, .len = 0, 253 .features = BIT(DPU_PINGPONG_DITHER), 254 .sblk = &sc7280_pp_sblk, 255 .merge_3d = MERGE_3D_1, 256 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 257 .intr_rdptr = -1, 258 }, { 259 .name = "pingpong_3", .id = PINGPONG_3, 260 .base = 0x6c000, .len = 0, 261 .features = BIT(DPU_PINGPONG_DITHER), 262 .sblk = &sc7280_pp_sblk, 263 .merge_3d = MERGE_3D_1, 264 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 265 .intr_rdptr = -1, 266 }, { 267 .name = "pingpong_4", .id = PINGPONG_4, 268 .base = 0x6d000, .len = 0, 269 .features = BIT(DPU_PINGPONG_DITHER), 270 .sblk = &sc7280_pp_sblk, 271 .merge_3d = MERGE_3D_2, 272 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 273 .intr_rdptr = -1, 274 }, { 275 .name = "pingpong_5", .id = PINGPONG_5, 276 .base = 0x6e000, .len = 0, 277 .features = BIT(DPU_PINGPONG_DITHER), 278 .sblk = &sc7280_pp_sblk, 279 .merge_3d = MERGE_3D_2, 280 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 281 .intr_rdptr = -1, 282 }, { 283 .name = "pingpong_6", .id = PINGPONG_6, 284 .base = 0x66000, .len = 0, 285 .features = BIT(DPU_PINGPONG_DITHER), 286 .sblk = &sc7280_pp_sblk, 287 .merge_3d = MERGE_3D_3, 288 .intr_done = -1, 289 .intr_rdptr = -1, 290 }, { 291 .name = "pingpong_7", .id = PINGPONG_7, 292 .base = 0x66400, .len = 0, 293 .features = BIT(DPU_PINGPONG_DITHER), 294 .sblk = &sc7280_pp_sblk, 295 .merge_3d = MERGE_3D_3, 296 .intr_done = -1, 297 .intr_rdptr = -1, 298 }, 299 }; 300 301 static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { 302 { 303 .name = "merge_3d_0", .id = MERGE_3D_0, 304 .base = 0x4e000, .len = 0x8, 305 }, { 306 .name = "merge_3d_1", .id = MERGE_3D_1, 307 .base = 0x4f000, .len = 0x8, 308 }, { 309 .name = "merge_3d_2", .id = MERGE_3D_2, 310 .base = 0x50000, .len = 0x8, 311 }, { 312 .name = "merge_3d_3", .id = MERGE_3D_3, 313 .base = 0x66700, .len = 0x8, 314 }, 315 }; 316 317 /* 318 * NOTE: Each display compression engine (DCE) contains dual hard 319 * slice DSC encoders so both share same base address but with 320 * its own different sub block address. 321 */ 322 static const struct dpu_dsc_cfg sm8550_dsc[] = { 323 { 324 .name = "dce_0_0", .id = DSC_0, 325 .base = 0x80000, .len = 0x4, 326 .features = BIT(DPU_DSC_HW_REV_1_2), 327 .sblk = &dsc_sblk_0, 328 }, { 329 .name = "dce_0_1", .id = DSC_1, 330 .base = 0x80000, .len = 0x4, 331 .features = BIT(DPU_DSC_HW_REV_1_2), 332 .sblk = &dsc_sblk_1, 333 }, { 334 .name = "dce_1_0", .id = DSC_2, 335 .base = 0x81000, .len = 0x4, 336 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 337 .sblk = &dsc_sblk_0, 338 }, { 339 .name = "dce_1_1", .id = DSC_3, 340 .base = 0x81000, .len = 0x4, 341 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 342 .sblk = &dsc_sblk_1, 343 }, 344 }; 345 346 static const struct dpu_intf_cfg sm8550_intf[] = { 347 { 348 .name = "intf_0", .id = INTF_0, 349 .base = 0x34000, .len = 0x280, 350 .features = INTF_SC7280_MASK, 351 .type = INTF_DP, 352 .controller_id = MSM_DP_CONTROLLER_0, 353 .prog_fetch_lines_worst_case = 24, 354 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 355 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 356 .intr_tear_rd_ptr = -1, 357 }, { 358 .name = "intf_1", .id = INTF_1, 359 .base = 0x35000, .len = 0x300, 360 .features = INTF_SC7280_MASK, 361 .type = INTF_DSI, 362 .controller_id = MSM_DSI_CONTROLLER_0, 363 .prog_fetch_lines_worst_case = 24, 364 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 365 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 366 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 367 }, { 368 .name = "intf_2", .id = INTF_2, 369 .base = 0x36000, .len = 0x300, 370 .features = INTF_SC7280_MASK, 371 .type = INTF_DSI, 372 .controller_id = MSM_DSI_CONTROLLER_1, 373 .prog_fetch_lines_worst_case = 24, 374 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 375 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 376 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 377 }, { 378 .name = "intf_3", .id = INTF_3, 379 .base = 0x37000, .len = 0x280, 380 .features = INTF_SC7280_MASK, 381 .type = INTF_DP, 382 .controller_id = MSM_DP_CONTROLLER_1, 383 .prog_fetch_lines_worst_case = 24, 384 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 385 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 386 .intr_tear_rd_ptr = -1, 387 }, 388 }; 389 390 static const struct dpu_perf_cfg sm8550_perf_data = { 391 .max_bw_low = 13600000, 392 .max_bw_high = 18200000, 393 .min_core_ib = 2500000, 394 .min_llcc_ib = 0, 395 .min_dram_ib = 800000, 396 .min_prefill_lines = 35, 397 /* FIXME: lut tables */ 398 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 399 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 400 .qos_lut_tbl = { 401 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 402 .entries = sc7180_qos_linear 403 }, 404 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 405 .entries = sc7180_qos_macrotile 406 }, 407 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 408 .entries = sc7180_qos_nrt 409 }, 410 /* TODO: macrotile-qseed is different from macrotile */ 411 }, 412 .cdp_cfg = { 413 {.rd_enable = 1, .wr_enable = 1}, 414 {.rd_enable = 1, .wr_enable = 0} 415 }, 416 .clk_inefficiency_factor = 105, 417 .bw_inefficiency_factor = 120, 418 }; 419 420 static const struct dpu_mdss_version sm8550_mdss_ver = { 421 .core_major_ver = 9, 422 .core_minor_ver = 0, 423 }; 424 425 const struct dpu_mdss_cfg dpu_sm8550_cfg = { 426 .mdss_ver = &sm8550_mdss_ver, 427 .caps = &sm8550_dpu_caps, 428 .mdp = &sm8550_mdp, 429 .ctl_count = ARRAY_SIZE(sm8550_ctl), 430 .ctl = sm8550_ctl, 431 .sspp_count = ARRAY_SIZE(sm8550_sspp), 432 .sspp = sm8550_sspp, 433 .mixer_count = ARRAY_SIZE(sm8550_lm), 434 .mixer = sm8550_lm, 435 .dspp_count = ARRAY_SIZE(sm8550_dspp), 436 .dspp = sm8550_dspp, 437 .pingpong_count = ARRAY_SIZE(sm8550_pp), 438 .pingpong = sm8550_pp, 439 .dsc_count = ARRAY_SIZE(sm8550_dsc), 440 .dsc = sm8550_dsc, 441 .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), 442 .merge_3d = sm8550_merge_3d, 443 .intf_count = ARRAY_SIZE(sm8550_intf), 444 .intf = sm8550_intf, 445 .vbif_count = ARRAY_SIZE(sm8550_vbif), 446 .vbif = sm8550_vbif, 447 .perf = &sm8550_perf_data, 448 }; 449 450 #endif 451