1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
3 */
4
5 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6 #include "dpu_encoder_phys.h"
7 #include "dpu_hw_interrupts.h"
8 #include "dpu_hw_merge3d.h"
9 #include "dpu_core_irq.h"
10 #include "dpu_formats.h"
11 #include "dpu_trace.h"
12 #include "disp/msm_disp_snapshot.h"
13
14 #include <drm/drm_managed.h>
15
16 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
17 (e) && (e)->parent ? \
18 (e)->parent->base.id : -1, \
19 (e) && (e)->hw_intf ? \
20 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
21
22 #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
23 (e) && (e)->parent ? \
24 (e)->parent->base.id : -1, \
25 (e) && (e)->hw_intf ? \
26 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
27
28 #define to_dpu_encoder_phys_vid(x) \
29 container_of(x, struct dpu_encoder_phys_vid, base)
30
dpu_encoder_phys_vid_is_master(struct dpu_encoder_phys * phys_enc)31 static bool dpu_encoder_phys_vid_is_master(
32 struct dpu_encoder_phys *phys_enc)
33 {
34 bool ret = false;
35
36 if (phys_enc->split_role != ENC_ROLE_SLAVE)
37 ret = true;
38
39 return ret;
40 }
41
drm_mode_to_intf_timing_params(const struct dpu_encoder_phys * phys_enc,const struct drm_display_mode * mode,struct dpu_hw_intf_timing_params * timing)42 static void drm_mode_to_intf_timing_params(
43 const struct dpu_encoder_phys *phys_enc,
44 const struct drm_display_mode *mode,
45 struct dpu_hw_intf_timing_params *timing)
46 {
47 memset(timing, 0, sizeof(*timing));
48
49 if ((mode->htotal < mode->hsync_end)
50 || (mode->hsync_start < mode->hdisplay)
51 || (mode->vtotal < mode->vsync_end)
52 || (mode->vsync_start < mode->vdisplay)
53 || (mode->hsync_end < mode->hsync_start)
54 || (mode->vsync_end < mode->vsync_start)) {
55 DPU_ERROR(
56 "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
57 mode->hsync_start, mode->hsync_end,
58 mode->htotal, mode->hdisplay);
59 DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
60 mode->vsync_start, mode->vsync_end,
61 mode->vtotal, mode->vdisplay);
62 return;
63 }
64
65 /*
66 * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
67 * Active Region Front Porch Sync Back Porch
68 * <-----------------><------------><-----><----------->
69 * <- [hv]display --->
70 * <--------- [hv]sync_start ------>
71 * <----------------- [hv]sync_end ------->
72 * <---------------------------- [hv]total ------------->
73 */
74 timing->width = mode->hdisplay; /* active width */
75 timing->height = mode->vdisplay; /* active height */
76 timing->xres = timing->width;
77 timing->yres = timing->height;
78 timing->h_back_porch = mode->htotal - mode->hsync_end;
79 timing->h_front_porch = mode->hsync_start - mode->hdisplay;
80 timing->v_back_porch = mode->vtotal - mode->vsync_end;
81 timing->v_front_porch = mode->vsync_start - mode->vdisplay;
82 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
83 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
84 timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
85 timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
86 timing->border_clr = 0;
87 timing->underflow_clr = 0xff;
88 timing->hsync_skew = mode->hskew;
89
90 /* DSI controller cannot handle active-low sync signals. */
91 if (phys_enc->hw_intf->cap->type == INTF_DSI) {
92 timing->hsync_polarity = 0;
93 timing->vsync_polarity = 0;
94 }
95
96 /* for DP/EDP, Shift timings to align it to bottom right */
97 if (phys_enc->hw_intf->cap->type == INTF_DP) {
98 timing->h_back_porch += timing->h_front_porch;
99 timing->h_front_porch = 0;
100 timing->v_back_porch += timing->v_front_porch;
101 timing->v_front_porch = 0;
102 }
103
104 timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
105 timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
106
107 /*
108 * for DP, divide the horizonal parameters by 2 when
109 * widebus is enabled
110 */
111 if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
112 timing->width = timing->width >> 1;
113 timing->xres = timing->xres >> 1;
114 timing->h_back_porch = timing->h_back_porch >> 1;
115 timing->h_front_porch = timing->h_front_porch >> 1;
116 timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
117 }
118 }
119
get_horizontal_total(const struct dpu_hw_intf_timing_params * timing)120 static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
121 {
122 u32 active = timing->xres;
123 u32 inactive =
124 timing->h_back_porch + timing->h_front_porch +
125 timing->hsync_pulse_width;
126 return active + inactive;
127 }
128
get_vertical_total(const struct dpu_hw_intf_timing_params * timing)129 static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing)
130 {
131 u32 active = timing->yres;
132 u32 inactive =
133 timing->v_back_porch + timing->v_front_porch +
134 timing->vsync_pulse_width;
135 return active + inactive;
136 }
137
138 /*
139 * programmable_fetch_get_num_lines:
140 * Number of fetch lines in vertical front porch
141 * @timing: Pointer to the intf timing information for the requested mode
142 *
143 * Returns the number of fetch lines in vertical front porch at which mdp
144 * can start fetching the next frame.
145 *
146 * Number of needed prefetch lines is anything that cannot be absorbed in the
147 * start of frame time (back porch + vsync pulse width).
148 *
149 * Some panels have very large VFP, however we only need a total number of
150 * lines based on the chip worst case latencies.
151 */
programmable_fetch_get_num_lines(struct dpu_encoder_phys * phys_enc,const struct dpu_hw_intf_timing_params * timing)152 static u32 programmable_fetch_get_num_lines(
153 struct dpu_encoder_phys *phys_enc,
154 const struct dpu_hw_intf_timing_params *timing)
155 {
156 u32 worst_case_needed_lines =
157 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
158 u32 start_of_frame_lines =
159 timing->v_back_porch + timing->vsync_pulse_width;
160 u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
161 u32 actual_vfp_lines = 0;
162
163 /* Fetch must be outside active lines, otherwise undefined. */
164 if (start_of_frame_lines >= worst_case_needed_lines) {
165 DPU_DEBUG_VIDENC(phys_enc,
166 "prog fetch is not needed, large vbp+vsw\n");
167 actual_vfp_lines = 0;
168 } else if (timing->v_front_porch < needed_vfp_lines) {
169 /* Warn fetch needed, but not enough porch in panel config */
170 pr_warn_once
171 ("low vbp+vfp may lead to perf issues in some cases\n");
172 DPU_DEBUG_VIDENC(phys_enc,
173 "less vfp than fetch req, using entire vfp\n");
174 actual_vfp_lines = timing->v_front_porch;
175 } else {
176 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
177 actual_vfp_lines = needed_vfp_lines;
178 }
179
180 DPU_DEBUG_VIDENC(phys_enc,
181 "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
182 timing->v_front_porch, timing->v_back_porch,
183 timing->vsync_pulse_width);
184 DPU_DEBUG_VIDENC(phys_enc,
185 "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
186 worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
187
188 return actual_vfp_lines;
189 }
190
191 /*
192 * programmable_fetch_config: Programs HW to prefetch lines by offsetting
193 * the start of fetch into the vertical front porch for cases where the
194 * vsync pulse width and vertical back porch time is insufficient
195 *
196 * Gets # of lines to pre-fetch, then calculate VSYNC counter value.
197 * HW layer requires VSYNC counter of first pixel of tgt VFP line.
198 *
199 * @timing: Pointer to the intf timing information for the requested mode
200 */
programmable_fetch_config(struct dpu_encoder_phys * phys_enc,const struct dpu_hw_intf_timing_params * timing)201 static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
202 const struct dpu_hw_intf_timing_params *timing)
203 {
204 struct dpu_hw_intf_prog_fetch f = { 0 };
205 u32 vfp_fetch_lines = 0;
206 u32 horiz_total = 0;
207 u32 vert_total = 0;
208 u32 vfp_fetch_start_vsync_counter = 0;
209 unsigned long lock_flags;
210
211 if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
212 return;
213
214 vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
215 if (vfp_fetch_lines) {
216 vert_total = get_vertical_total(timing);
217 horiz_total = get_horizontal_total(timing);
218 vfp_fetch_start_vsync_counter =
219 (vert_total - vfp_fetch_lines) * horiz_total + 1;
220 f.enable = 1;
221 f.fetch_start = vfp_fetch_start_vsync_counter;
222 }
223
224 DPU_DEBUG_VIDENC(phys_enc,
225 "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
226 vfp_fetch_lines, vfp_fetch_start_vsync_counter);
227
228 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
229 phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
230 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
231 }
232
dpu_encoder_phys_vid_setup_timing_engine(struct dpu_encoder_phys * phys_enc)233 static void dpu_encoder_phys_vid_setup_timing_engine(
234 struct dpu_encoder_phys *phys_enc)
235 {
236 struct drm_display_mode mode;
237 struct dpu_hw_intf_timing_params timing_params = { 0 };
238 const struct dpu_format *fmt = NULL;
239 u32 fmt_fourcc = DRM_FORMAT_RGB888;
240 unsigned long lock_flags;
241 struct dpu_hw_intf_cfg intf_cfg = { 0 };
242
243 drm_mode_init(&mode, &phys_enc->cached_mode);
244
245 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) {
246 DPU_ERROR("invalid encoder %d\n", phys_enc != NULL);
247 return;
248 }
249
250 if (!phys_enc->hw_intf->ops.setup_timing_gen) {
251 DPU_ERROR("timing engine setup is not supported\n");
252 return;
253 }
254
255 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
256 drm_mode_debug_printmodeline(&mode);
257
258 if (phys_enc->split_role != ENC_ROLE_SOLO) {
259 mode.hdisplay >>= 1;
260 mode.htotal >>= 1;
261 mode.hsync_start >>= 1;
262 mode.hsync_end >>= 1;
263 mode.hskew >>= 1;
264
265 DPU_DEBUG_VIDENC(phys_enc,
266 "split_role %d, halve horizontal %d %d %d %d %d\n",
267 phys_enc->split_role,
268 mode.hdisplay, mode.htotal,
269 mode.hsync_start, mode.hsync_end,
270 mode.hskew);
271 }
272
273 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
274
275 fmt = dpu_get_dpu_format(fmt_fourcc);
276 DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
277
278 intf_cfg.intf = phys_enc->hw_intf->idx;
279 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
280 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
281 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
282 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
283 if (intf_cfg.mode_3d && phys_enc->hw_pp->merge_3d)
284 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
285
286 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
287 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
288 &timing_params, fmt);
289 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
290
291 /* setup which pp blk will connect to this intf */
292 if (phys_enc->hw_intf->ops.bind_pingpong_blk)
293 phys_enc->hw_intf->ops.bind_pingpong_blk(
294 phys_enc->hw_intf,
295 phys_enc->hw_pp->idx);
296
297 if (phys_enc->hw_pp->merge_3d)
298 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);
299
300 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
301
302 programmable_fetch_config(phys_enc, &timing_params);
303 }
304
dpu_encoder_phys_vid_vblank_irq(void * arg)305 static void dpu_encoder_phys_vid_vblank_irq(void *arg)
306 {
307 struct dpu_encoder_phys *phys_enc = arg;
308 struct dpu_hw_ctl *hw_ctl;
309 unsigned long lock_flags;
310 u32 flush_register = 0;
311
312 hw_ctl = phys_enc->hw_ctl;
313
314 DPU_ATRACE_BEGIN("vblank_irq");
315
316 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
317
318 atomic_read(&phys_enc->pending_kickoff_cnt);
319
320 /*
321 * only decrement the pending flush count if we've actually flushed
322 * hardware. due to sw irq latency, vblank may have already happened
323 * so we need to double-check with hw that it accepted the flush bits
324 */
325 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
326 if (hw_ctl->ops.get_flush_register)
327 flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
328
329 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
330 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
331 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
332
333 /* Signal any waiting atomic commit thread */
334 wake_up_all(&phys_enc->pending_kickoff_wq);
335
336 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
337 DPU_ENCODER_FRAME_EVENT_DONE);
338
339 DPU_ATRACE_END("vblank_irq");
340 }
341
dpu_encoder_phys_vid_underrun_irq(void * arg)342 static void dpu_encoder_phys_vid_underrun_irq(void *arg)
343 {
344 struct dpu_encoder_phys *phys_enc = arg;
345
346 dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);
347 }
348
dpu_encoder_phys_vid_needs_single_flush(struct dpu_encoder_phys * phys_enc)349 static bool dpu_encoder_phys_vid_needs_single_flush(
350 struct dpu_encoder_phys *phys_enc)
351 {
352 return phys_enc->split_role != ENC_ROLE_SOLO;
353 }
354
dpu_encoder_phys_vid_atomic_mode_set(struct dpu_encoder_phys * phys_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)355 static void dpu_encoder_phys_vid_atomic_mode_set(
356 struct dpu_encoder_phys *phys_enc,
357 struct drm_crtc_state *crtc_state,
358 struct drm_connector_state *conn_state)
359 {
360 phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
361
362 phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
363 }
364
dpu_encoder_phys_vid_control_vblank_irq(struct dpu_encoder_phys * phys_enc,bool enable)365 static int dpu_encoder_phys_vid_control_vblank_irq(
366 struct dpu_encoder_phys *phys_enc,
367 bool enable)
368 {
369 int ret = 0;
370 int refcount;
371
372 refcount = atomic_read(&phys_enc->vblank_refcount);
373
374 /* Slave encoders don't report vblank */
375 if (!dpu_encoder_phys_vid_is_master(phys_enc))
376 goto end;
377
378 /* protect against negative */
379 if (!enable && refcount == 0) {
380 ret = -EINVAL;
381 goto end;
382 }
383
384 DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
385 atomic_read(&phys_enc->vblank_refcount));
386
387 if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
388 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms,
389 phys_enc->irq[INTR_IDX_VSYNC],
390 dpu_encoder_phys_vid_vblank_irq,
391 phys_enc);
392 else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
393 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
394 phys_enc->irq[INTR_IDX_VSYNC]);
395
396 end:
397 if (ret) {
398 DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
399 DRMID(phys_enc->parent),
400 phys_enc->hw_intf->idx - INTF_0, ret, enable,
401 refcount);
402 }
403 return ret;
404 }
405
dpu_encoder_phys_vid_enable(struct dpu_encoder_phys * phys_enc)406 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
407 {
408 struct dpu_hw_ctl *ctl;
409
410 ctl = phys_enc->hw_ctl;
411
412 DPU_DEBUG_VIDENC(phys_enc, "\n");
413
414 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
415 return;
416
417 dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
418
419 dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
420
421 /*
422 * For single flush cases (dual-ctl or pp-split), skip setting the
423 * flush bit for the slave intf, since both intfs use same ctl
424 * and HW will only flush the master.
425 */
426 if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&
427 !dpu_encoder_phys_vid_is_master(phys_enc))
428 goto skip_flush;
429
430 ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
431 if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
432 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);
433
434 skip_flush:
435 DPU_DEBUG_VIDENC(phys_enc,
436 "update pending flush ctl %d intf %d\n",
437 ctl->idx - CTL_0, phys_enc->hw_intf->idx);
438
439 atomic_set(&phys_enc->underrun_cnt, 0);
440
441 /* ctl_flush & timing engine enable will be triggered by framework */
442 if (phys_enc->enable_state == DPU_ENC_DISABLED)
443 phys_enc->enable_state = DPU_ENC_ENABLING;
444 }
445
dpu_encoder_phys_vid_wait_for_tx_complete(struct dpu_encoder_phys * phys_enc)446 static int dpu_encoder_phys_vid_wait_for_tx_complete(
447 struct dpu_encoder_phys *phys_enc)
448 {
449 struct dpu_encoder_wait_info wait_info;
450 int ret;
451
452 wait_info.wq = &phys_enc->pending_kickoff_wq;
453 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
454 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
455
456 if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
457 return 0;
458 }
459
460 /* Wait for kickoff to complete */
461 ret = dpu_encoder_helper_wait_for_irq(phys_enc,
462 phys_enc->irq[INTR_IDX_VSYNC],
463 dpu_encoder_phys_vid_vblank_irq,
464 &wait_info);
465
466 if (ret == -ETIMEDOUT) {
467 dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
468 }
469
470 return ret;
471 }
472
dpu_encoder_phys_vid_wait_for_commit_done(struct dpu_encoder_phys * phys_enc)473 static int dpu_encoder_phys_vid_wait_for_commit_done(
474 struct dpu_encoder_phys *phys_enc)
475 {
476 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
477 int ret;
478
479 if (!hw_ctl)
480 return 0;
481
482 ret = wait_event_timeout(phys_enc->pending_kickoff_wq,
483 (hw_ctl->ops.get_flush_register(hw_ctl) == 0),
484 msecs_to_jiffies(50));
485 if (ret <= 0) {
486 DPU_ERROR("vblank timeout\n");
487 return -ETIMEDOUT;
488 }
489
490 return 0;
491 }
492
dpu_encoder_phys_vid_prepare_for_kickoff(struct dpu_encoder_phys * phys_enc)493 static void dpu_encoder_phys_vid_prepare_for_kickoff(
494 struct dpu_encoder_phys *phys_enc)
495 {
496 struct dpu_hw_ctl *ctl;
497 int rc;
498 struct drm_encoder *drm_enc;
499
500 drm_enc = phys_enc->parent;
501
502 ctl = phys_enc->hw_ctl;
503 if (!ctl->ops.wait_reset_status)
504 return;
505
506 /*
507 * hw supports hardware initiated ctl reset, so before we kickoff a new
508 * frame, need to check and wait for hw initiated ctl reset completion
509 */
510 rc = ctl->ops.wait_reset_status(ctl);
511 if (rc) {
512 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
513 ctl->idx, rc);
514 msm_disp_snapshot_state(drm_enc->dev);
515 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
516 phys_enc->irq[INTR_IDX_VSYNC]);
517 }
518 }
519
dpu_encoder_phys_vid_disable(struct dpu_encoder_phys * phys_enc)520 static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
521 {
522 unsigned long lock_flags;
523 int ret;
524 struct dpu_hw_intf_status intf_status = {0};
525
526 if (!phys_enc->parent || !phys_enc->parent->dev) {
527 DPU_ERROR("invalid encoder/device\n");
528 return;
529 }
530
531 if (!phys_enc->hw_intf) {
532 DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
533 phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
534 return;
535 }
536
537 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
538 return;
539
540 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
541 DPU_ERROR("already disabled\n");
542 return;
543 }
544
545 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
546 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
547 if (dpu_encoder_phys_vid_is_master(phys_enc))
548 dpu_encoder_phys_inc_pending(phys_enc);
549 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
550
551 /*
552 * Wait for a vsync so we know the ENABLE=0 latched before
553 * the (connector) source of the vsync's gets disabled,
554 * otherwise we end up in a funny state if we re-enable
555 * before the disable latches, which results that some of
556 * the settings changes for the new modeset (like new
557 * scanout buffer) don't latch properly..
558 */
559 if (dpu_encoder_phys_vid_is_master(phys_enc)) {
560 ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
561 if (ret) {
562 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
563 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
564 DRMID(phys_enc->parent),
565 phys_enc->hw_intf->idx - INTF_0, ret);
566 }
567 }
568
569 if (phys_enc->hw_intf && phys_enc->hw_intf->ops.get_status)
570 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &intf_status);
571
572 /*
573 * Wait for a vsync if timing en status is on after timing engine
574 * is disabled.
575 */
576 if (intf_status.is_en && dpu_encoder_phys_vid_is_master(phys_enc)) {
577 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
578 dpu_encoder_phys_inc_pending(phys_enc);
579 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
580 ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
581 if (ret) {
582 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
583 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
584 DRMID(phys_enc->parent),
585 phys_enc->hw_intf->idx - INTF_0, ret);
586 }
587 }
588
589 dpu_encoder_helper_phys_cleanup(phys_enc);
590 phys_enc->enable_state = DPU_ENC_DISABLED;
591 }
592
dpu_encoder_phys_vid_handle_post_kickoff(struct dpu_encoder_phys * phys_enc)593 static void dpu_encoder_phys_vid_handle_post_kickoff(
594 struct dpu_encoder_phys *phys_enc)
595 {
596 unsigned long lock_flags;
597
598 /*
599 * Video mode must flush CTL before enabling timing engine
600 * Video encoders need to turn on their interfaces now
601 */
602 if (phys_enc->enable_state == DPU_ENC_ENABLING) {
603 trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
604 phys_enc->hw_intf->idx - INTF_0);
605 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
606 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
607 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
608 phys_enc->enable_state = DPU_ENC_ENABLED;
609 }
610 }
611
dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys * phys_enc,bool enable)612 static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
613 bool enable)
614 {
615 int ret;
616
617 trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
618 phys_enc->hw_intf->idx - INTF_0,
619 enable,
620 atomic_read(&phys_enc->vblank_refcount));
621
622 if (enable) {
623 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
624 if (WARN_ON(ret))
625 return;
626
627 dpu_core_irq_register_callback(phys_enc->dpu_kms,
628 phys_enc->irq[INTR_IDX_UNDERRUN],
629 dpu_encoder_phys_vid_underrun_irq,
630 phys_enc);
631 } else {
632 dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
633 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
634 phys_enc->irq[INTR_IDX_UNDERRUN]);
635 }
636 }
637
dpu_encoder_phys_vid_get_line_count(struct dpu_encoder_phys * phys_enc)638 static int dpu_encoder_phys_vid_get_line_count(
639 struct dpu_encoder_phys *phys_enc)
640 {
641 if (!dpu_encoder_phys_vid_is_master(phys_enc))
642 return -EINVAL;
643
644 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
645 return -EINVAL;
646
647 return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
648 }
649
dpu_encoder_phys_vid_get_frame_count(struct dpu_encoder_phys * phys_enc)650 static int dpu_encoder_phys_vid_get_frame_count(
651 struct dpu_encoder_phys *phys_enc)
652 {
653 struct dpu_hw_intf_status s = {0};
654 u32 fetch_start = 0;
655 struct drm_display_mode mode;
656
657 drm_mode_init(&mode, &phys_enc->cached_mode);
658
659 if (!dpu_encoder_phys_vid_is_master(phys_enc))
660 return -EINVAL;
661
662 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status)
663 return -EINVAL;
664
665 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s);
666
667 if (s.is_prog_fetch_en && s.is_en) {
668 fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay);
669 if ((s.line_count > fetch_start) &&
670 (s.line_count <= mode.vtotal))
671 return s.frame_count + 1;
672 }
673
674 return s.frame_count;
675 }
676
dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops * ops)677 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
678 {
679 ops->is_master = dpu_encoder_phys_vid_is_master;
680 ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;
681 ops->enable = dpu_encoder_phys_vid_enable;
682 ops->disable = dpu_encoder_phys_vid_disable;
683 ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
684 ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
685 ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete;
686 ops->irq_control = dpu_encoder_phys_vid_irq_control;
687 ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
688 ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
689 ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
690 ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
691 ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count;
692 }
693
dpu_encoder_phys_vid_init(struct drm_device * dev,struct dpu_enc_phys_init_params * p)694 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,
695 struct dpu_enc_phys_init_params *p)
696 {
697 struct dpu_encoder_phys *phys_enc = NULL;
698
699 if (!p) {
700 DPU_ERROR("failed to create encoder due to invalid parameter\n");
701 return ERR_PTR(-EINVAL);
702 }
703
704 phys_enc = drmm_kzalloc(dev, sizeof(*phys_enc), GFP_KERNEL);
705 if (!phys_enc) {
706 DPU_ERROR("failed to create encoder due to memory allocation error\n");
707 return ERR_PTR(-ENOMEM);
708 }
709
710 DPU_DEBUG_VIDENC(phys_enc, "\n");
711
712 dpu_encoder_phys_init(phys_enc, p);
713
714 dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
715 phys_enc->intf_mode = INTF_MODE_VIDEO;
716
717 DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx);
718
719 return phys_enc;
720 }
721