1 /*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
44 #include "net/net.h"
45 #include "system/device_tree.h"
46 #include "system/numa.h"
47 #include "system/runstate.h"
48 #include "system/tpm.h"
49 #include "system/tcg.h"
50 #include "system/kvm.h"
51 #include "system/hvf.h"
52 #include "system/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/cutils.h"
57 #include "qemu/error-report.h"
58 #include "qemu/module.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/virtio/virtio-pci.h"
61 #include "hw/core/sysbus-fdt.h"
62 #include "hw/platform-bus.h"
63 #include "hw/qdev-properties.h"
64 #include "hw/arm/fdt.h"
65 #include "hw/intc/arm_gic.h"
66 #include "hw/intc/arm_gicv3_common.h"
67 #include "hw/intc/arm_gicv3_its_common.h"
68 #include "hw/irq.h"
69 #include "kvm_arm.h"
70 #include "hvf_arm.h"
71 #include "hw/firmware/smbios.h"
72 #include "qapi/visitor.h"
73 #include "qapi/qapi-visit-common.h"
74 #include "qobject/qlist.h"
75 #include "standard-headers/linux/input.h"
76 #include "hw/arm/smmuv3.h"
77 #include "hw/acpi/acpi.h"
78 #include "target/arm/cpu-qom.h"
79 #include "target/arm/internals.h"
80 #include "target/arm/multiprocessing.h"
81 #include "target/arm/gtimer.h"
82 #include "hw/mem/pc-dimm.h"
83 #include "hw/mem/nvdimm.h"
84 #include "hw/acpi/generic_event_device.h"
85 #include "hw/uefi/var-service-api.h"
86 #include "hw/virtio/virtio-md-pci.h"
87 #include "hw/virtio/virtio-iommu.h"
88 #include "hw/char/pl011.h"
89 #include "qemu/guest-random.h"
90
91 static GlobalProperty arm_virt_compat[] = {
92 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" },
93 };
94 static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat);
95
96 /*
97 * This cannot be called from the virt_machine_class_init() because
98 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
99 * only is called on virt non abstract class init.
100 */
arm_virt_compat_set(MachineClass * mc)101 static void arm_virt_compat_set(MachineClass *mc)
102 {
103 compat_props_add(mc->compat_props, arm_virt_compat,
104 arm_virt_compat_len);
105 }
106
107 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \
108 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \
109 ObjectClass *oc, \
110 void *data) \
111 { \
112 MachineClass *mc = MACHINE_CLASS(oc); \
113 arm_virt_compat_set(mc); \
114 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \
115 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \
116 MACHINE_VER_DEPRECATION(__VA_ARGS__); \
117 if (latest) { \
118 mc->alias = "virt"; \
119 } \
120 } \
121 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \
122 { \
123 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
124 .parent = TYPE_VIRT_MACHINE, \
125 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
126 }; \
127 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
128 { \
129 MACHINE_VER_DELETION(__VA_ARGS__); \
130 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \
131 } \
132 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__));
133
134 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
135 DEFINE_VIRT_MACHINE_IMPL(true, major, minor)
136 #define DEFINE_VIRT_MACHINE(major, minor) \
137 DEFINE_VIRT_MACHINE_IMPL(false, major, minor)
138
139
140 /* Number of external interrupt lines to configure the GIC with */
141 #define NUM_IRQS 256
142
143 #define PLATFORM_BUS_NUM_IRQS 64
144
145 /* Legacy RAM limit in GB (< version 4.0) */
146 #define LEGACY_RAMLIMIT_GB 255
147 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
148
149 /* Addresses and sizes of our components.
150 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
151 * 128MB..256MB is used for miscellaneous device I/O.
152 * 256MB..1GB is reserved for possible future PCI support (ie where the
153 * PCI memory window will go if we add a PCI host controller).
154 * 1GB and up is RAM (which may happily spill over into the
155 * high memory region beyond 4GB).
156 * This represents a compromise between how much RAM can be given to
157 * a 32 bit VM and leaving space for expansion and in particular for PCI.
158 * Note that devices should generally be placed at multiples of 0x10000,
159 * to accommodate guests using 64K pages.
160 */
161 static const MemMapEntry base_memmap[] = {
162 /* Space up to 0x8000000 is reserved for a boot ROM */
163 [VIRT_FLASH] = { 0, 0x08000000 },
164 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
165 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
166 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
167 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
168 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
169 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
170 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
171 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
172 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
173 /* This redistributor space allows up to 2*64kB*123 CPUs */
174 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
175 [VIRT_UART0] = { 0x09000000, 0x00001000 },
176 [VIRT_RTC] = { 0x09010000, 0x00001000 },
177 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
178 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
179 [VIRT_UART1] = { 0x09040000, 0x00001000 },
180 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
181 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
182 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
183 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
184 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
185 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
186 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
187 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
188 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
189 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
190 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
191 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
192 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
193 /* Actual RAM size depends on initial RAM and device memory settings */
194 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
195 };
196
197 /* Update the docs for highmem-mmio-size when changing this default */
198 #define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512
199 #define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB)
200
201 /*
202 * Highmem IO Regions: This memory map is floating, located after the RAM.
203 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
204 * top of the RAM, so that its base get the same alignment as the size,
205 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
206 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
207 * Note the extended_memmap is sized so that it eventually also includes the
208 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
209 * index of base_memmap).
210 *
211 * The memory map for these Highmem IO Regions can be in legacy or compact
212 * layout, depending on 'compact-highmem' property. With legacy layout, the
213 * PA space for one specific region is always reserved, even if the region
214 * has been disabled or doesn't fit into the PA space. However, the PA space
215 * for the region won't be reserved in these circumstances with compact layout.
216 *
217 * Note that the highmem-mmio-size property will update the high PCIE MMIO size
218 * field in this array.
219 */
220 static MemMapEntry extended_memmap[] = {
221 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
222 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
223 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
224 /* Second PCIe window */
225 [VIRT_HIGH_PCIE_MMIO] = { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE },
226 };
227
228 static const int a15irqmap[] = {
229 [VIRT_UART0] = 1,
230 [VIRT_RTC] = 2,
231 [VIRT_PCIE] = 3, /* ... to 6 */
232 [VIRT_GPIO] = 7,
233 [VIRT_UART1] = 8,
234 [VIRT_ACPI_GED] = 9,
235 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
236 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
237 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
238 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
239 };
240
create_randomness(MachineState * ms,const char * node)241 static void create_randomness(MachineState *ms, const char *node)
242 {
243 struct {
244 uint64_t kaslr;
245 uint8_t rng[32];
246 } seed;
247
248 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
249 return;
250 }
251 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
252 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
253 }
254
255 /*
256 * The CPU object always exposes the NS EL2 virt timer IRQ line,
257 * but we don't want to advertise it to the guest in the dtb or ACPI
258 * table unless it's really going to do something.
259 */
ns_el2_virt_timer_present(void)260 static bool ns_el2_virt_timer_present(void)
261 {
262 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
263 CPUARMState *env = &cpu->env;
264
265 return arm_feature(env, ARM_FEATURE_AARCH64) &&
266 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
267 }
268
create_fdt(VirtMachineState * vms)269 static void create_fdt(VirtMachineState *vms)
270 {
271 MachineState *ms = MACHINE(vms);
272 int nb_numa_nodes = ms->numa_state->num_nodes;
273 void *fdt = create_device_tree(&vms->fdt_size);
274
275 if (!fdt) {
276 error_report("create_device_tree() failed");
277 exit(1);
278 }
279
280 ms->fdt = fdt;
281
282 /* Header */
283 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
284 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
285 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
286 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
287
288 /*
289 * For QEMU, all DMA is coherent. Advertising this in the root node
290 * has two benefits:
291 *
292 * - It avoids potential bugs where we forget to mark a DMA
293 * capable device as being dma-coherent
294 * - It avoids spurious warnings from the Linux kernel about
295 * devices which can't do DMA at all
296 */
297 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0);
298
299 /* /chosen must exist for load_dtb to fill in necessary properties later */
300 qemu_fdt_add_subnode(fdt, "/chosen");
301 if (vms->dtb_randomness) {
302 create_randomness(ms, "/chosen");
303 }
304
305 if (vms->secure) {
306 qemu_fdt_add_subnode(fdt, "/secure-chosen");
307 if (vms->dtb_randomness) {
308 create_randomness(ms, "/secure-chosen");
309 }
310 }
311
312 qemu_fdt_add_subnode(fdt, "/aliases");
313
314 /* Clock node, for the benefit of the UART. The kernel device tree
315 * binding documentation claims the PL011 node clock properties are
316 * optional but in practice if you omit them the kernel refuses to
317 * probe for the device.
318 */
319 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
320 qemu_fdt_add_subnode(fdt, "/apb-pclk");
321 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
322 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
323 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
324 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
325 "clk24mhz");
326 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
327
328 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
329 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
330 uint32_t *matrix = g_malloc0(size);
331 int idx, i, j;
332
333 for (i = 0; i < nb_numa_nodes; i++) {
334 for (j = 0; j < nb_numa_nodes; j++) {
335 idx = (i * nb_numa_nodes + j) * 3;
336 matrix[idx + 0] = cpu_to_be32(i);
337 matrix[idx + 1] = cpu_to_be32(j);
338 matrix[idx + 2] =
339 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
340 }
341 }
342
343 qemu_fdt_add_subnode(fdt, "/distance-map");
344 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
345 "numa-distance-map-v1");
346 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
347 matrix, size);
348 g_free(matrix);
349 }
350 }
351
fdt_add_timer_nodes(const VirtMachineState * vms)352 static void fdt_add_timer_nodes(const VirtMachineState *vms)
353 {
354 /* On real hardware these interrupts are level-triggered.
355 * On KVM they were edge-triggered before host kernel version 4.4,
356 * and level-triggered afterwards.
357 * On emulated QEMU they are level-triggered.
358 *
359 * Getting the DTB info about them wrong is awkward for some
360 * guest kernels:
361 * pre-4.8 ignore the DT and leave the interrupt configured
362 * with whatever the GIC reset value (or the bootloader) left it at
363 * 4.8 before rc6 honour the incorrect data by programming it back
364 * into the GIC, causing problems
365 * 4.8rc6 and later ignore the DT and always write "level triggered"
366 * into the GIC
367 *
368 * For backwards-compatibility, virt-2.8 and earlier will continue
369 * to say these are edge-triggered, but later machines will report
370 * the correct information.
371 */
372 ARMCPU *armcpu;
373 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
374 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
375 MachineState *ms = MACHINE(vms);
376
377 if (vmc->claim_edge_triggered_timers) {
378 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
379 }
380
381 if (vms->gic_version == VIRT_GIC_VERSION_2) {
382 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
383 GIC_FDT_IRQ_PPI_CPU_WIDTH,
384 (1 << MACHINE(vms)->smp.cpus) - 1);
385 }
386
387 qemu_fdt_add_subnode(ms->fdt, "/timer");
388
389 armcpu = ARM_CPU(qemu_get_cpu(0));
390 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
391 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
392 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
393 compat, sizeof(compat));
394 } else {
395 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
396 "arm,armv7-timer");
397 }
398 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
399 if (vms->ns_el2_virt_timer_irq) {
400 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
401 GIC_FDT_IRQ_TYPE_PPI,
402 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
403 GIC_FDT_IRQ_TYPE_PPI,
404 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
405 GIC_FDT_IRQ_TYPE_PPI,
406 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
407 GIC_FDT_IRQ_TYPE_PPI,
408 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
409 GIC_FDT_IRQ_TYPE_PPI,
410 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
411 } else {
412 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
413 GIC_FDT_IRQ_TYPE_PPI,
414 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
415 GIC_FDT_IRQ_TYPE_PPI,
416 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
417 GIC_FDT_IRQ_TYPE_PPI,
418 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
419 GIC_FDT_IRQ_TYPE_PPI,
420 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
421 }
422 }
423
fdt_add_cpu_nodes(const VirtMachineState * vms)424 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
425 {
426 int cpu;
427 int addr_cells = 1;
428 const MachineState *ms = MACHINE(vms);
429 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
430 int smp_cpus = ms->smp.cpus;
431
432 /*
433 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
434 * On ARM v8 64-bit systems value should be set to 2,
435 * that corresponds to the MPIDR_EL1 register size.
436 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
437 * in the system, #address-cells can be set to 1, since
438 * MPIDR_EL1[63:32] bits are not used for CPUs
439 * identification.
440 *
441 * Here we actually don't know whether our system is 32- or 64-bit one.
442 * The simplest way to go is to examine affinity IDs of all our CPUs. If
443 * at least one of them has Aff3 populated, we set #address-cells to 2.
444 */
445 for (cpu = 0; cpu < smp_cpus; cpu++) {
446 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
447
448 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) {
449 addr_cells = 2;
450 break;
451 }
452 }
453
454 qemu_fdt_add_subnode(ms->fdt, "/cpus");
455 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
456 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
457
458 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
459 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
460 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
461 CPUState *cs = CPU(armcpu);
462
463 qemu_fdt_add_subnode(ms->fdt, nodename);
464 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
465 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
466 armcpu->dtb_compatible);
467
468 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
469 qemu_fdt_setprop_string(ms->fdt, nodename,
470 "enable-method", "psci");
471 }
472
473 if (addr_cells == 2) {
474 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
475 arm_cpu_mp_affinity(armcpu));
476 } else {
477 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
478 arm_cpu_mp_affinity(armcpu));
479 }
480
481 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
482 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
483 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
484 }
485
486 if (!vmc->no_cpu_topology) {
487 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
488 qemu_fdt_alloc_phandle(ms->fdt));
489 }
490
491 g_free(nodename);
492 }
493
494 if (!vmc->no_cpu_topology) {
495 /*
496 * Add vCPU topology description through fdt node cpu-map.
497 *
498 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
499 * In a SMP system, the hierarchy of CPUs can be defined through
500 * four entities that are used to describe the layout of CPUs in
501 * the system: socket/cluster/core/thread.
502 *
503 * A socket node represents the boundary of system physical package
504 * and its child nodes must be one or more cluster nodes. A system
505 * can contain several layers of clustering within a single physical
506 * package and cluster nodes can be contained in parent cluster nodes.
507 *
508 * Note: currently we only support one layer of clustering within
509 * each physical package.
510 */
511 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
512
513 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
514 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
515 char *map_path;
516
517 if (ms->smp.threads > 1) {
518 map_path = g_strdup_printf(
519 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
520 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
521 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
522 (cpu / ms->smp.threads) % ms->smp.cores,
523 cpu % ms->smp.threads);
524 } else {
525 map_path = g_strdup_printf(
526 "/cpus/cpu-map/socket%d/cluster%d/core%d",
527 cpu / (ms->smp.clusters * ms->smp.cores),
528 (cpu / ms->smp.cores) % ms->smp.clusters,
529 cpu % ms->smp.cores);
530 }
531 qemu_fdt_add_path(ms->fdt, map_path);
532 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
533
534 g_free(map_path);
535 g_free(cpu_path);
536 }
537 }
538 }
539
fdt_add_its_gic_node(VirtMachineState * vms)540 static void fdt_add_its_gic_node(VirtMachineState *vms)
541 {
542 char *nodename;
543 MachineState *ms = MACHINE(vms);
544
545 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
546 nodename = g_strdup_printf("/intc/its@%" PRIx64,
547 vms->memmap[VIRT_GIC_ITS].base);
548 qemu_fdt_add_subnode(ms->fdt, nodename);
549 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
550 "arm,gic-v3-its");
551 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
552 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
553 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
554 2, vms->memmap[VIRT_GIC_ITS].base,
555 2, vms->memmap[VIRT_GIC_ITS].size);
556 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
557 g_free(nodename);
558 }
559
fdt_add_v2m_gic_node(VirtMachineState * vms)560 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
561 {
562 MachineState *ms = MACHINE(vms);
563 char *nodename;
564
565 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
566 vms->memmap[VIRT_GIC_V2M].base);
567 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
568 qemu_fdt_add_subnode(ms->fdt, nodename);
569 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
570 "arm,gic-v2m-frame");
571 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
572 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
573 2, vms->memmap[VIRT_GIC_V2M].base,
574 2, vms->memmap[VIRT_GIC_V2M].size);
575 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
576 g_free(nodename);
577 }
578
fdt_add_gic_node(VirtMachineState * vms)579 static void fdt_add_gic_node(VirtMachineState *vms)
580 {
581 MachineState *ms = MACHINE(vms);
582 char *nodename;
583
584 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
585 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
586
587 nodename = g_strdup_printf("/intc@%" PRIx64,
588 vms->memmap[VIRT_GIC_DIST].base);
589 qemu_fdt_add_subnode(ms->fdt, nodename);
590 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
591 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
592 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
593 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
594 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
595 if (vms->gic_version != VIRT_GIC_VERSION_2) {
596 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
597
598 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
599 "arm,gic-v3");
600
601 qemu_fdt_setprop_cell(ms->fdt, nodename,
602 "#redistributor-regions", nb_redist_regions);
603
604 if (nb_redist_regions == 1) {
605 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
606 2, vms->memmap[VIRT_GIC_DIST].base,
607 2, vms->memmap[VIRT_GIC_DIST].size,
608 2, vms->memmap[VIRT_GIC_REDIST].base,
609 2, vms->memmap[VIRT_GIC_REDIST].size);
610 } else {
611 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
612 2, vms->memmap[VIRT_GIC_DIST].base,
613 2, vms->memmap[VIRT_GIC_DIST].size,
614 2, vms->memmap[VIRT_GIC_REDIST].base,
615 2, vms->memmap[VIRT_GIC_REDIST].size,
616 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
617 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
618 }
619
620 if (vms->virt) {
621 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
622 GIC_FDT_IRQ_TYPE_PPI,
623 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
624 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
625 }
626 } else {
627 /* 'cortex-a15-gic' means 'GIC v2' */
628 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
629 "arm,cortex-a15-gic");
630 if (!vms->virt) {
631 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
632 2, vms->memmap[VIRT_GIC_DIST].base,
633 2, vms->memmap[VIRT_GIC_DIST].size,
634 2, vms->memmap[VIRT_GIC_CPU].base,
635 2, vms->memmap[VIRT_GIC_CPU].size);
636 } else {
637 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
638 2, vms->memmap[VIRT_GIC_DIST].base,
639 2, vms->memmap[VIRT_GIC_DIST].size,
640 2, vms->memmap[VIRT_GIC_CPU].base,
641 2, vms->memmap[VIRT_GIC_CPU].size,
642 2, vms->memmap[VIRT_GIC_HYP].base,
643 2, vms->memmap[VIRT_GIC_HYP].size,
644 2, vms->memmap[VIRT_GIC_VCPU].base,
645 2, vms->memmap[VIRT_GIC_VCPU].size);
646 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
647 GIC_FDT_IRQ_TYPE_PPI,
648 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
649 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
650 }
651 }
652
653 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
654 g_free(nodename);
655 }
656
fdt_add_pmu_nodes(const VirtMachineState * vms)657 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
658 {
659 ARMCPU *armcpu = ARM_CPU(first_cpu);
660 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
661 MachineState *ms = MACHINE(vms);
662
663 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
664 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
665 return;
666 }
667
668 if (vms->gic_version == VIRT_GIC_VERSION_2) {
669 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
670 GIC_FDT_IRQ_PPI_CPU_WIDTH,
671 (1 << MACHINE(vms)->smp.cpus) - 1);
672 }
673
674 qemu_fdt_add_subnode(ms->fdt, "/pmu");
675 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
676 const char compat[] = "arm,armv8-pmuv3";
677 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
678 compat, sizeof(compat));
679 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
680 GIC_FDT_IRQ_TYPE_PPI,
681 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags);
682 }
683 }
684
create_acpi_ged(VirtMachineState * vms)685 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
686 {
687 DeviceState *dev;
688 MachineState *ms = MACHINE(vms);
689 int irq = vms->irqmap[VIRT_ACPI_GED];
690 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
691
692 if (ms->ram_slots) {
693 event |= ACPI_GED_MEM_HOTPLUG_EVT;
694 }
695
696 if (ms->nvdimms_state->is_enabled) {
697 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
698 }
699
700 dev = qdev_new(TYPE_ACPI_GED);
701 qdev_prop_set_uint32(dev, "ged-event", event);
702 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
703
704 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
705 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
706 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
707
708 return dev;
709 }
710
create_its(VirtMachineState * vms)711 static void create_its(VirtMachineState *vms)
712 {
713 const char *itsclass = its_class_name();
714 DeviceState *dev;
715
716 if (!strcmp(itsclass, "arm-gicv3-its")) {
717 if (!vms->tcg_its) {
718 itsclass = NULL;
719 }
720 }
721
722 if (!itsclass) {
723 /* Do nothing if not supported */
724 return;
725 }
726
727 dev = qdev_new(itsclass);
728
729 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
730 &error_abort);
731 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
732 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
733
734 fdt_add_its_gic_node(vms);
735 vms->msi_controller = VIRT_MSI_CTRL_ITS;
736 }
737
create_v2m(VirtMachineState * vms)738 static void create_v2m(VirtMachineState *vms)
739 {
740 int i;
741 int irq = vms->irqmap[VIRT_GIC_V2M];
742 DeviceState *dev;
743
744 dev = qdev_new("arm-gicv2m");
745 qdev_prop_set_uint32(dev, "base-spi", irq);
746 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
747 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
748 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
749
750 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
751 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
752 qdev_get_gpio_in(vms->gic, irq + i));
753 }
754
755 fdt_add_v2m_gic_node(vms);
756 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
757 }
758
759 /*
760 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
761 * It's permitted to have a configuration with NMI in the CPU (and thus the
762 * GICv3 CPU interface) but not in the distributor/redistributors, but it's
763 * not very useful.
764 */
gicv3_nmi_present(VirtMachineState * vms)765 static bool gicv3_nmi_present(VirtMachineState *vms)
766 {
767 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
768
769 return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) &&
770 (vms->gic_version != VIRT_GIC_VERSION_2);
771 }
772
create_gic(VirtMachineState * vms,MemoryRegion * mem)773 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
774 {
775 MachineState *ms = MACHINE(vms);
776 /* We create a standalone GIC */
777 SysBusDevice *gicbusdev;
778 const char *gictype;
779 int i;
780 unsigned int smp_cpus = ms->smp.cpus;
781 uint32_t nb_redist_regions = 0;
782 int revision;
783
784 if (vms->gic_version == VIRT_GIC_VERSION_2) {
785 gictype = gic_class_name();
786 } else {
787 gictype = gicv3_class_name();
788 }
789
790 switch (vms->gic_version) {
791 case VIRT_GIC_VERSION_2:
792 revision = 2;
793 break;
794 case VIRT_GIC_VERSION_3:
795 revision = 3;
796 break;
797 case VIRT_GIC_VERSION_4:
798 revision = 4;
799 break;
800 default:
801 g_assert_not_reached();
802 }
803 vms->gic = qdev_new(gictype);
804 qdev_prop_set_uint32(vms->gic, "revision", revision);
805 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
806 /* Note that the num-irq property counts both internal and external
807 * interrupts; there are always 32 of the former (mandated by GIC spec).
808 */
809 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
810 if (!kvm_irqchip_in_kernel()) {
811 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
812 }
813
814 if (vms->gic_version != VIRT_GIC_VERSION_2) {
815 QList *redist_region_count;
816 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
817 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
818
819 nb_redist_regions = virt_gicv3_redist_region_count(vms);
820
821 redist_region_count = qlist_new();
822 qlist_append_int(redist_region_count, redist0_count);
823 if (nb_redist_regions == 2) {
824 uint32_t redist1_capacity =
825 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
826
827 qlist_append_int(redist_region_count,
828 MIN(smp_cpus - redist0_count, redist1_capacity));
829 }
830 qdev_prop_set_array(vms->gic, "redist-region-count",
831 redist_region_count);
832
833 if (!kvm_irqchip_in_kernel()) {
834 if (vms->tcg_its) {
835 object_property_set_link(OBJECT(vms->gic), "sysmem",
836 OBJECT(mem), &error_fatal);
837 qdev_prop_set_bit(vms->gic, "has-lpi", true);
838 }
839 }
840 } else {
841 if (!kvm_irqchip_in_kernel()) {
842 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
843 vms->virt);
844 }
845 }
846
847 if (gicv3_nmi_present(vms)) {
848 qdev_prop_set_bit(vms->gic, "has-nmi", true);
849 }
850
851 gicbusdev = SYS_BUS_DEVICE(vms->gic);
852 sysbus_realize_and_unref(gicbusdev, &error_fatal);
853 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
854 if (vms->gic_version != VIRT_GIC_VERSION_2) {
855 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
856 if (nb_redist_regions == 2) {
857 sysbus_mmio_map(gicbusdev, 2,
858 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
859 }
860 } else {
861 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
862 if (vms->virt) {
863 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
864 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
865 }
866 }
867
868 /* Wire the outputs from each CPU's generic timer and the GICv3
869 * maintenance interrupt signal to the appropriate GIC PPI inputs,
870 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
871 * CPU's inputs.
872 */
873 for (i = 0; i < smp_cpus; i++) {
874 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
875 int intidbase = NUM_IRQS + i * GIC_INTERNAL;
876 /* Mapping from the output timer irq lines from the CPU to the
877 * GIC PPI inputs we use for the virt board.
878 */
879 const int timer_irq[] = {
880 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
881 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
882 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
883 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
884 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
885 [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
886 [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
887 };
888
889 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
890 qdev_connect_gpio_out(cpudev, irq,
891 qdev_get_gpio_in(vms->gic,
892 intidbase + timer_irq[irq]));
893 }
894
895 if (vms->gic_version != VIRT_GIC_VERSION_2) {
896 qemu_irq irq = qdev_get_gpio_in(vms->gic,
897 intidbase + ARCH_GIC_MAINT_IRQ);
898 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
899 0, irq);
900 } else if (vms->virt) {
901 qemu_irq irq = qdev_get_gpio_in(vms->gic,
902 intidbase + ARCH_GIC_MAINT_IRQ);
903 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
904 }
905
906 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
907 qdev_get_gpio_in(vms->gic, intidbase
908 + VIRTUAL_PMU_IRQ));
909
910 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
911 sysbus_connect_irq(gicbusdev, i + smp_cpus,
912 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
913 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
914 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
915 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
916 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
917
918 if (vms->gic_version != VIRT_GIC_VERSION_2) {
919 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,
920 qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
921 sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,
922 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
923 }
924 }
925
926 fdt_add_gic_node(vms);
927
928 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
929 create_its(vms);
930 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
931 create_v2m(vms);
932 }
933 }
934
create_uart(const VirtMachineState * vms,int uart,MemoryRegion * mem,Chardev * chr,bool secure)935 static void create_uart(const VirtMachineState *vms, int uart,
936 MemoryRegion *mem, Chardev *chr, bool secure)
937 {
938 char *nodename;
939 hwaddr base = vms->memmap[uart].base;
940 hwaddr size = vms->memmap[uart].size;
941 int irq = vms->irqmap[uart];
942 const char compat[] = "arm,pl011\0arm,primecell";
943 const char clocknames[] = "uartclk\0apb_pclk";
944 DeviceState *dev = qdev_new(TYPE_PL011);
945 SysBusDevice *s = SYS_BUS_DEVICE(dev);
946 MachineState *ms = MACHINE(vms);
947
948 qdev_prop_set_chr(dev, "chardev", chr);
949 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
950 memory_region_add_subregion(mem, base,
951 sysbus_mmio_get_region(s, 0));
952 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
953
954 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
955 qemu_fdt_add_subnode(ms->fdt, nodename);
956 /* Note that we can't use setprop_string because of the embedded NUL */
957 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
958 compat, sizeof(compat));
959 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
960 2, base, 2, size);
961 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
962 GIC_FDT_IRQ_TYPE_SPI, irq,
963 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
964 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
965 vms->clock_phandle, vms->clock_phandle);
966 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
967 clocknames, sizeof(clocknames));
968
969 if (uart == VIRT_UART0) {
970 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
971 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
972 } else {
973 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename);
974 }
975 if (secure) {
976 /* Mark as not usable by the normal world */
977 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
978 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
979
980 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
981 nodename);
982 }
983
984 g_free(nodename);
985 }
986
create_rtc(const VirtMachineState * vms)987 static void create_rtc(const VirtMachineState *vms)
988 {
989 char *nodename;
990 hwaddr base = vms->memmap[VIRT_RTC].base;
991 hwaddr size = vms->memmap[VIRT_RTC].size;
992 int irq = vms->irqmap[VIRT_RTC];
993 const char compat[] = "arm,pl031\0arm,primecell";
994 MachineState *ms = MACHINE(vms);
995
996 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
997
998 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
999 qemu_fdt_add_subnode(ms->fdt, nodename);
1000 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1001 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1002 2, base, 2, size);
1003 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1004 GIC_FDT_IRQ_TYPE_SPI, irq,
1005 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1006 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1007 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1008 g_free(nodename);
1009 }
1010
1011 static DeviceState *gpio_key_dev;
virt_powerdown_req(Notifier * n,void * opaque)1012 static void virt_powerdown_req(Notifier *n, void *opaque)
1013 {
1014 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
1015
1016 if (s->acpi_dev) {
1017 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
1018 } else {
1019 /* use gpio Pin for power button event */
1020 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
1021 }
1022 }
1023
create_gpio_keys(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1024 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
1025 uint32_t phandle)
1026 {
1027 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
1028 qdev_get_gpio_in(pl061_dev,
1029 GPIO_PIN_POWER_BUTTON));
1030
1031 qemu_fdt_add_subnode(fdt, "/gpio-keys");
1032 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
1033
1034 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
1035 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
1036 "label", "GPIO Key Poweroff");
1037 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
1038 KEY_POWER);
1039 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
1040 "gpios", phandle, GPIO_PIN_POWER_BUTTON, 0);
1041 }
1042
1043 #define SECURE_GPIO_POWEROFF 0
1044 #define SECURE_GPIO_RESET 1
1045
create_secure_gpio_pwr(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1046 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
1047 uint32_t phandle)
1048 {
1049 DeviceState *gpio_pwr_dev;
1050
1051 /* gpio-pwr */
1052 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
1053
1054 /* connect secure pl061 to gpio-pwr */
1055 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
1056 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
1057 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
1058 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
1059
1060 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
1061 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
1062 "gpio-poweroff");
1063 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
1064 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
1065 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
1066 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
1067 "okay");
1068
1069 qemu_fdt_add_subnode(fdt, "/gpio-restart");
1070 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
1071 "gpio-restart");
1072 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
1073 "gpios", phandle, SECURE_GPIO_RESET, 0);
1074 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
1075 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
1076 "okay");
1077 }
1078
create_gpio_devices(const VirtMachineState * vms,int gpio,MemoryRegion * mem)1079 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
1080 MemoryRegion *mem)
1081 {
1082 char *nodename;
1083 DeviceState *pl061_dev;
1084 hwaddr base = vms->memmap[gpio].base;
1085 hwaddr size = vms->memmap[gpio].size;
1086 int irq = vms->irqmap[gpio];
1087 const char compat[] = "arm,pl061\0arm,primecell";
1088 SysBusDevice *s;
1089 MachineState *ms = MACHINE(vms);
1090
1091 pl061_dev = qdev_new("pl061");
1092 /* Pull lines down to 0 if not driven by the PL061 */
1093 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
1094 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
1095 s = SYS_BUS_DEVICE(pl061_dev);
1096 sysbus_realize_and_unref(s, &error_fatal);
1097 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
1098 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1099
1100 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1101 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1102 qemu_fdt_add_subnode(ms->fdt, nodename);
1103 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1104 2, base, 2, size);
1105 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1106 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1107 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1108 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1109 GIC_FDT_IRQ_TYPE_SPI, irq,
1110 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1111 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1112 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1113 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1114
1115 if (gpio != VIRT_GPIO) {
1116 /* Mark as not usable by the normal world */
1117 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1118 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1119 }
1120 g_free(nodename);
1121
1122 /* Child gpio devices */
1123 if (gpio == VIRT_GPIO) {
1124 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1125 } else {
1126 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1127 }
1128 }
1129
create_virtio_devices(const VirtMachineState * vms)1130 static void create_virtio_devices(const VirtMachineState *vms)
1131 {
1132 int i;
1133 hwaddr size = vms->memmap[VIRT_MMIO].size;
1134 MachineState *ms = MACHINE(vms);
1135
1136 /* We create the transports in forwards order. Since qbus_realize()
1137 * prepends (not appends) new child buses, the incrementing loop below will
1138 * create a list of virtio-mmio buses with decreasing base addresses.
1139 *
1140 * When a -device option is processed from the command line,
1141 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1142 * order. The upshot is that -device options in increasing command line
1143 * order are mapped to virtio-mmio buses with decreasing base addresses.
1144 *
1145 * When this code was originally written, that arrangement ensured that the
1146 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1147 * the first -device on the command line. (The end-to-end order is a
1148 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1149 * guest kernel's name-to-address assignment strategy.)
1150 *
1151 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1152 * the message, if not necessarily the code, of commit 70161ff336.
1153 * Therefore the loop now establishes the inverse of the original intent.
1154 *
1155 * Unfortunately, we can't counteract the kernel change by reversing the
1156 * loop; it would break existing command lines.
1157 *
1158 * In any case, the kernel makes no guarantee about the stability of
1159 * enumeration order of virtio devices (as demonstrated by it changing
1160 * between kernel versions). For reliable and stable identification
1161 * of disks users must use UUIDs or similar mechanisms.
1162 */
1163 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1164 int irq = vms->irqmap[VIRT_MMIO] + i;
1165 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1166
1167 sysbus_create_simple("virtio-mmio", base,
1168 qdev_get_gpio_in(vms->gic, irq));
1169 }
1170
1171 /* We add dtb nodes in reverse order so that they appear in the finished
1172 * device tree lowest address first.
1173 *
1174 * Note that this mapping is independent of the loop above. The previous
1175 * loop influences virtio device to virtio transport assignment, whereas
1176 * this loop controls how virtio transports are laid out in the dtb.
1177 */
1178 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1179 char *nodename;
1180 int irq = vms->irqmap[VIRT_MMIO] + i;
1181 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1182
1183 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1184 qemu_fdt_add_subnode(ms->fdt, nodename);
1185 qemu_fdt_setprop_string(ms->fdt, nodename,
1186 "compatible", "virtio,mmio");
1187 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1188 2, base, 2, size);
1189 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1190 GIC_FDT_IRQ_TYPE_SPI, irq,
1191 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1192 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1193 g_free(nodename);
1194 }
1195 }
1196
1197 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1198
virt_flash_create1(VirtMachineState * vms,const char * name,const char * alias_prop_name)1199 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1200 const char *name,
1201 const char *alias_prop_name)
1202 {
1203 /*
1204 * Create a single flash device. We use the same parameters as
1205 * the flash devices on the Versatile Express board.
1206 */
1207 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1208
1209 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1210 qdev_prop_set_uint8(dev, "width", 4);
1211 qdev_prop_set_uint8(dev, "device-width", 2);
1212 qdev_prop_set_bit(dev, "big-endian", false);
1213 qdev_prop_set_uint16(dev, "id0", 0x89);
1214 qdev_prop_set_uint16(dev, "id1", 0x18);
1215 qdev_prop_set_uint16(dev, "id2", 0x00);
1216 qdev_prop_set_uint16(dev, "id3", 0x00);
1217 qdev_prop_set_string(dev, "name", name);
1218 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1219 object_property_add_alias(OBJECT(vms), alias_prop_name,
1220 OBJECT(dev), "drive");
1221 return PFLASH_CFI01(dev);
1222 }
1223
virt_flash_create(VirtMachineState * vms)1224 static void virt_flash_create(VirtMachineState *vms)
1225 {
1226 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1227 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1228 }
1229
virt_flash_map1(PFlashCFI01 * flash,hwaddr base,hwaddr size,MemoryRegion * sysmem)1230 static void virt_flash_map1(PFlashCFI01 *flash,
1231 hwaddr base, hwaddr size,
1232 MemoryRegion *sysmem)
1233 {
1234 DeviceState *dev = DEVICE(flash);
1235
1236 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1237 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1238 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1239 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1240
1241 memory_region_add_subregion(sysmem, base,
1242 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1243 0));
1244 }
1245
virt_flash_map(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1246 static void virt_flash_map(VirtMachineState *vms,
1247 MemoryRegion *sysmem,
1248 MemoryRegion *secure_sysmem)
1249 {
1250 /*
1251 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1252 * sysmem is the system memory space. secure_sysmem is the secure view
1253 * of the system, and the first flash device should be made visible only
1254 * there. The second flash device is visible to both secure and nonsecure.
1255 * If sysmem == secure_sysmem this means there is no separate Secure
1256 * address space and both flash devices are generally visible.
1257 */
1258 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1259 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1260
1261 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1262 secure_sysmem);
1263 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1264 sysmem);
1265 }
1266
virt_flash_fdt(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1267 static void virt_flash_fdt(VirtMachineState *vms,
1268 MemoryRegion *sysmem,
1269 MemoryRegion *secure_sysmem)
1270 {
1271 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1272 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1273 MachineState *ms = MACHINE(vms);
1274 char *nodename;
1275
1276 if (sysmem == secure_sysmem) {
1277 /* Report both flash devices as a single node in the DT */
1278 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1279 qemu_fdt_add_subnode(ms->fdt, nodename);
1280 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1281 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1282 2, flashbase, 2, flashsize,
1283 2, flashbase + flashsize, 2, flashsize);
1284 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1285 g_free(nodename);
1286 } else {
1287 /*
1288 * Report the devices as separate nodes so we can mark one as
1289 * only visible to the secure world.
1290 */
1291 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1292 qemu_fdt_add_subnode(ms->fdt, nodename);
1293 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1294 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1295 2, flashbase, 2, flashsize);
1296 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1297 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1298 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1299 g_free(nodename);
1300
1301 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1302 qemu_fdt_add_subnode(ms->fdt, nodename);
1303 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1304 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1305 2, flashbase + flashsize, 2, flashsize);
1306 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1307 g_free(nodename);
1308 }
1309 }
1310
virt_firmware_init(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1311 static bool virt_firmware_init(VirtMachineState *vms,
1312 MemoryRegion *sysmem,
1313 MemoryRegion *secure_sysmem)
1314 {
1315 int i;
1316 const char *bios_name;
1317 BlockBackend *pflash_blk0;
1318
1319 /* Map legacy -drive if=pflash to machine properties */
1320 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1321 pflash_cfi01_legacy_drive(vms->flash[i],
1322 drive_get(IF_PFLASH, 0, i));
1323 }
1324
1325 virt_flash_map(vms, sysmem, secure_sysmem);
1326
1327 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1328
1329 bios_name = MACHINE(vms)->firmware;
1330 if (bios_name) {
1331 char *fname;
1332 MemoryRegion *mr;
1333 int image_size;
1334
1335 if (pflash_blk0) {
1336 error_report("The contents of the first flash device may be "
1337 "specified with -bios or with -drive if=pflash... "
1338 "but you cannot use both options at once");
1339 exit(1);
1340 }
1341
1342 /* Fall back to -bios */
1343
1344 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1345 if (!fname) {
1346 error_report("Could not find ROM image '%s'", bios_name);
1347 exit(1);
1348 }
1349 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1350 image_size = load_image_mr(fname, mr);
1351 g_free(fname);
1352 if (image_size < 0) {
1353 error_report("Could not load ROM image '%s'", bios_name);
1354 exit(1);
1355 }
1356 }
1357
1358 return pflash_blk0 || bios_name;
1359 }
1360
create_fw_cfg(const VirtMachineState * vms,AddressSpace * as)1361 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1362 {
1363 MachineState *ms = MACHINE(vms);
1364 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1365 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1366 FWCfgState *fw_cfg;
1367 char *nodename;
1368
1369 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1370 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1371
1372 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1373 qemu_fdt_add_subnode(ms->fdt, nodename);
1374 qemu_fdt_setprop_string(ms->fdt, nodename,
1375 "compatible", "qemu,fw-cfg-mmio");
1376 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1377 2, base, 2, size);
1378 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1379 g_free(nodename);
1380 return fw_cfg;
1381 }
1382
create_pcie_irq_map(const MachineState * ms,uint32_t gic_phandle,int first_irq,const char * nodename)1383 static void create_pcie_irq_map(const MachineState *ms,
1384 uint32_t gic_phandle,
1385 int first_irq, const char *nodename)
1386 {
1387 int devfn, pin;
1388 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1389 uint32_t *irq_map = full_irq_map;
1390
1391 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1392 for (pin = 0; pin < 4; pin++) {
1393 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1394 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1395 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1396 int i;
1397
1398 uint32_t map[] = {
1399 devfn << 8, 0, 0, /* devfn */
1400 pin + 1, /* PCI pin */
1401 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1402
1403 /* Convert map to big endian */
1404 for (i = 0; i < 10; i++) {
1405 irq_map[i] = cpu_to_be32(map[i]);
1406 }
1407 irq_map += 10;
1408 }
1409 }
1410
1411 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1412 full_irq_map, sizeof(full_irq_map));
1413
1414 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1415 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1416 0, 0,
1417 0x7 /* PCI irq */);
1418 }
1419
create_smmu(const VirtMachineState * vms,PCIBus * bus)1420 static void create_smmu(const VirtMachineState *vms,
1421 PCIBus *bus)
1422 {
1423 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1424 char *node;
1425 const char compat[] = "arm,smmu-v3";
1426 int irq = vms->irqmap[VIRT_SMMU];
1427 int i;
1428 hwaddr base = vms->memmap[VIRT_SMMU].base;
1429 hwaddr size = vms->memmap[VIRT_SMMU].size;
1430 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1431 DeviceState *dev;
1432 MachineState *ms = MACHINE(vms);
1433
1434 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1435 return;
1436 }
1437
1438 dev = qdev_new(TYPE_ARM_SMMUV3);
1439
1440 if (!vmc->no_nested_smmu) {
1441 object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal);
1442 }
1443 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1444 &error_abort);
1445 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1446 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1447 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1448 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1449 qdev_get_gpio_in(vms->gic, irq + i));
1450 }
1451
1452 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1453 qemu_fdt_add_subnode(ms->fdt, node);
1454 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1455 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1456
1457 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1458 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1459 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1460 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1461 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1462
1463 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1464 sizeof(irq_names));
1465
1466 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1467
1468 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1469
1470 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1471 g_free(node);
1472 }
1473
create_virtio_iommu_dt_bindings(VirtMachineState * vms)1474 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1475 {
1476 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1477 uint16_t bdf = vms->virtio_iommu_bdf;
1478 MachineState *ms = MACHINE(vms);
1479 char *node;
1480
1481 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1482
1483 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1484 PCI_SLOT(bdf), PCI_FUNC(bdf));
1485 qemu_fdt_add_subnode(ms->fdt, node);
1486 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1487 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1488 1, bdf << 8, 1, 0, 1, 0,
1489 1, 0, 1, 0);
1490
1491 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1492 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1493 g_free(node);
1494
1495 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1496 0x0, vms->iommu_phandle, 0x0, bdf,
1497 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1498 }
1499
create_pcie(VirtMachineState * vms)1500 static void create_pcie(VirtMachineState *vms)
1501 {
1502 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1503 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1504 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1505 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1506 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1507 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1508 hwaddr base_ecam, size_ecam;
1509 hwaddr base = base_mmio;
1510 int nr_pcie_buses;
1511 int irq = vms->irqmap[VIRT_PCIE];
1512 MemoryRegion *mmio_alias;
1513 MemoryRegion *mmio_reg;
1514 MemoryRegion *ecam_alias;
1515 MemoryRegion *ecam_reg;
1516 DeviceState *dev;
1517 char *nodename;
1518 int i, ecam_id;
1519 PCIHostState *pci;
1520 MachineState *ms = MACHINE(vms);
1521 MachineClass *mc = MACHINE_GET_CLASS(ms);
1522
1523 dev = qdev_new(TYPE_GPEX_HOST);
1524 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1525
1526 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1527 base_ecam = vms->memmap[ecam_id].base;
1528 size_ecam = vms->memmap[ecam_id].size;
1529 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1530 /* Map only the first size_ecam bytes of ECAM space */
1531 ecam_alias = g_new0(MemoryRegion, 1);
1532 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1533 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1534 ecam_reg, 0, size_ecam);
1535 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1536
1537 /* Map the MMIO window into system address space so as to expose
1538 * the section of PCI MMIO space which starts at the same base address
1539 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1540 * the window).
1541 */
1542 mmio_alias = g_new0(MemoryRegion, 1);
1543 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1544 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1545 mmio_reg, base_mmio, size_mmio);
1546 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1547
1548 if (vms->highmem_mmio) {
1549 /* Map high MMIO space */
1550 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1551
1552 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1553 mmio_reg, base_mmio_high, size_mmio_high);
1554 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1555 high_mmio_alias);
1556 }
1557
1558 /* Map IO port space */
1559 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1560
1561 for (i = 0; i < PCI_NUM_PINS; i++) {
1562 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1563 qdev_get_gpio_in(vms->gic, irq + i));
1564 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1565 }
1566
1567 pci = PCI_HOST_BRIDGE(dev);
1568 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1569 vms->bus = pci->bus;
1570 if (vms->bus) {
1571 pci_init_nic_devices(pci->bus, mc->default_nic);
1572 }
1573
1574 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1575 qemu_fdt_add_subnode(ms->fdt, nodename);
1576 qemu_fdt_setprop_string(ms->fdt, nodename,
1577 "compatible", "pci-host-ecam-generic");
1578 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1579 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1580 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1581 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1582 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1583 nr_pcie_buses - 1);
1584 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1585
1586 if (vms->msi_phandle) {
1587 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1588 0, vms->msi_phandle, 0, 0x10000);
1589 }
1590
1591 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1592 2, base_ecam, 2, size_ecam);
1593
1594 if (vms->highmem_mmio) {
1595 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1596 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1597 2, base_pio, 2, size_pio,
1598 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1599 2, base_mmio, 2, size_mmio,
1600 1, FDT_PCI_RANGE_MMIO_64BIT,
1601 2, base_mmio_high,
1602 2, base_mmio_high, 2, size_mmio_high);
1603 } else {
1604 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1605 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1606 2, base_pio, 2, size_pio,
1607 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1608 2, base_mmio, 2, size_mmio);
1609 }
1610
1611 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1612 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1613
1614 if (vms->iommu) {
1615 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1616
1617 switch (vms->iommu) {
1618 case VIRT_IOMMU_SMMUV3:
1619 create_smmu(vms, vms->bus);
1620 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1621 0x0, vms->iommu_phandle, 0x0, 0x10000);
1622 break;
1623 default:
1624 g_assert_not_reached();
1625 }
1626 }
1627 }
1628
create_platform_bus(VirtMachineState * vms)1629 static void create_platform_bus(VirtMachineState *vms)
1630 {
1631 DeviceState *dev;
1632 SysBusDevice *s;
1633 int i;
1634 MemoryRegion *sysmem = get_system_memory();
1635
1636 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1637 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1638 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1639 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1640 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1641 vms->platform_bus_dev = dev;
1642
1643 s = SYS_BUS_DEVICE(dev);
1644 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1645 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1646 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1647 }
1648
1649 memory_region_add_subregion(sysmem,
1650 vms->memmap[VIRT_PLATFORM_BUS].base,
1651 sysbus_mmio_get_region(s, 0));
1652 }
1653
create_tag_ram(MemoryRegion * tag_sysmem,hwaddr base,hwaddr size,const char * name)1654 static void create_tag_ram(MemoryRegion *tag_sysmem,
1655 hwaddr base, hwaddr size,
1656 const char *name)
1657 {
1658 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1659
1660 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1661 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1662 }
1663
create_secure_ram(VirtMachineState * vms,MemoryRegion * secure_sysmem,MemoryRegion * secure_tag_sysmem)1664 static void create_secure_ram(VirtMachineState *vms,
1665 MemoryRegion *secure_sysmem,
1666 MemoryRegion *secure_tag_sysmem)
1667 {
1668 MemoryRegion *secram = g_new(MemoryRegion, 1);
1669 char *nodename;
1670 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1671 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1672 MachineState *ms = MACHINE(vms);
1673
1674 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1675 &error_fatal);
1676 memory_region_add_subregion(secure_sysmem, base, secram);
1677
1678 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1679 qemu_fdt_add_subnode(ms->fdt, nodename);
1680 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1681 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1682 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1683 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1684
1685 if (secure_tag_sysmem) {
1686 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1687 }
1688
1689 g_free(nodename);
1690 }
1691
machvirt_dtb(const struct arm_boot_info * binfo,int * fdt_size)1692 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1693 {
1694 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1695 bootinfo);
1696 MachineState *ms = MACHINE(board);
1697
1698
1699 *fdt_size = board->fdt_size;
1700 return ms->fdt;
1701 }
1702
virt_build_smbios(VirtMachineState * vms)1703 static void virt_build_smbios(VirtMachineState *vms)
1704 {
1705 MachineClass *mc = MACHINE_GET_CLASS(vms);
1706 MachineState *ms = MACHINE(vms);
1707 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1708 uint8_t *smbios_tables, *smbios_anchor;
1709 size_t smbios_tables_len, smbios_anchor_len;
1710 struct smbios_phys_mem_area mem_array;
1711 const char *product = "QEMU Virtual Machine";
1712
1713 if (kvm_enabled()) {
1714 product = "KVM Virtual Machine";
1715 }
1716
1717 smbios_set_defaults("QEMU", product,
1718 vmc->smbios_old_sys_ver ? "1.0" : mc->name);
1719
1720 /* build the array of physical mem area from base_memmap */
1721 mem_array.address = vms->memmap[VIRT_MEM].base;
1722 mem_array.length = ms->ram_size;
1723
1724 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1,
1725 &smbios_tables, &smbios_tables_len,
1726 &smbios_anchor, &smbios_anchor_len,
1727 &error_fatal);
1728
1729 if (smbios_anchor) {
1730 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1731 smbios_tables, smbios_tables_len);
1732 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1733 smbios_anchor, smbios_anchor_len);
1734 }
1735 }
1736
1737 static
virt_machine_done(Notifier * notifier,void * data)1738 void virt_machine_done(Notifier *notifier, void *data)
1739 {
1740 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1741 machine_done);
1742 MachineState *ms = MACHINE(vms);
1743 ARMCPU *cpu = ARM_CPU(first_cpu);
1744 struct arm_boot_info *info = &vms->bootinfo;
1745 AddressSpace *as = arm_boot_address_space(cpu, info);
1746
1747 /*
1748 * If the user provided a dtb, we assume the dynamic sysbus nodes
1749 * already are integrated there. This corresponds to a use case where
1750 * the dynamic sysbus nodes are complex and their generation is not yet
1751 * supported. In that case the user can take charge of the guest dt
1752 * while qemu takes charge of the qom stuff.
1753 */
1754 if (info->dtb_filename == NULL) {
1755 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1756 vms->memmap[VIRT_PLATFORM_BUS].base,
1757 vms->memmap[VIRT_PLATFORM_BUS].size,
1758 vms->irqmap[VIRT_PLATFORM_BUS]);
1759 }
1760 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) {
1761 exit(1);
1762 }
1763
1764 pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus,
1765 &error_abort);
1766
1767 virt_acpi_setup(vms);
1768 virt_build_smbios(vms);
1769 }
1770
virt_cpu_mp_affinity(VirtMachineState * vms,int idx)1771 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1772 {
1773 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1774 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1775
1776 if (!vmc->disallow_affinity_adjustment) {
1777 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1778 * GIC's target-list limitations. 32-bit KVM hosts currently
1779 * always create clusters of 4 CPUs, but that is expected to
1780 * change when they gain support for gicv3. When KVM is enabled
1781 * it will override the changes we make here, therefore our
1782 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1783 * and to improve SGI efficiency.
1784 */
1785 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1786 clustersz = GIC_TARGETLIST_BITS;
1787 } else {
1788 clustersz = GICV3_TARGETLIST_BITS;
1789 }
1790 }
1791 return arm_build_mp_affinity(idx, clustersz);
1792 }
1793
virt_get_high_memmap_enabled(VirtMachineState * vms,int index)1794 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
1795 int index)
1796 {
1797 bool *enabled_array[] = {
1798 &vms->highmem_redists,
1799 &vms->highmem_ecam,
1800 &vms->highmem_mmio,
1801 };
1802
1803 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1804 ARRAY_SIZE(enabled_array));
1805 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1806
1807 return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1808 }
1809
virt_set_high_memmap(VirtMachineState * vms,hwaddr base,int pa_bits)1810 static void virt_set_high_memmap(VirtMachineState *vms,
1811 hwaddr base, int pa_bits)
1812 {
1813 hwaddr region_base, region_size;
1814 bool *region_enabled, fits;
1815 int i;
1816
1817 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1818 region_enabled = virt_get_high_memmap_enabled(vms, i);
1819 region_base = ROUND_UP(base, extended_memmap[i].size);
1820 region_size = extended_memmap[i].size;
1821
1822 vms->memmap[i].base = region_base;
1823 vms->memmap[i].size = region_size;
1824
1825 /*
1826 * Check each device to see if it fits in the PA space,
1827 * moving highest_gpa as we go. For compatibility, move
1828 * highest_gpa for disabled fitting devices as well, if
1829 * the compact layout has been disabled.
1830 *
1831 * For each device that doesn't fit, disable it.
1832 */
1833 fits = (region_base + region_size) <= BIT_ULL(pa_bits);
1834 *region_enabled &= fits;
1835 if (vms->highmem_compact && !*region_enabled) {
1836 continue;
1837 }
1838
1839 base = region_base + region_size;
1840 if (fits) {
1841 vms->highest_gpa = base - 1;
1842 }
1843 }
1844 }
1845
virt_set_memmap(VirtMachineState * vms,int pa_bits)1846 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
1847 {
1848 MachineState *ms = MACHINE(vms);
1849 hwaddr base, device_memory_base, device_memory_size, memtop;
1850 int i;
1851
1852 vms->memmap = extended_memmap;
1853
1854 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1855 vms->memmap[i] = base_memmap[i];
1856 }
1857
1858 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1859 error_report("unsupported number of memory slots: %"PRIu64,
1860 ms->ram_slots);
1861 exit(EXIT_FAILURE);
1862 }
1863
1864 /*
1865 * !highmem is exactly the same as limiting the PA space to 32bit,
1866 * irrespective of the underlying capabilities of the HW.
1867 */
1868 if (!vms->highmem) {
1869 pa_bits = 32;
1870 }
1871
1872 /*
1873 * We compute the base of the high IO region depending on the
1874 * amount of initial and device memory. The device memory start/size
1875 * is aligned on 1GiB. We never put the high IO region below 256GiB
1876 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1877 * The device region size assumes 1GiB page max alignment per slot.
1878 */
1879 device_memory_base =
1880 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1881 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1882
1883 /* Base address of the high IO region */
1884 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1885 if (memtop > BIT_ULL(pa_bits)) {
1886 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
1887 pa_bits, memtop - BIT_ULL(pa_bits));
1888 exit(EXIT_FAILURE);
1889 }
1890 if (base < device_memory_base) {
1891 error_report("maxmem/slots too huge");
1892 exit(EXIT_FAILURE);
1893 }
1894 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1895 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1896 }
1897
1898 /* We know for sure that at least the memory fits in the PA space */
1899 vms->highest_gpa = memtop - 1;
1900
1901 virt_set_high_memmap(vms, base, pa_bits);
1902
1903 if (device_memory_size > 0) {
1904 machine_memory_devices_init(ms, device_memory_base, device_memory_size);
1905 }
1906 }
1907
finalize_gic_version_do(const char * accel_name,VirtGICType gic_version,int gics_supported,unsigned int max_cpus)1908 static VirtGICType finalize_gic_version_do(const char *accel_name,
1909 VirtGICType gic_version,
1910 int gics_supported,
1911 unsigned int max_cpus)
1912 {
1913 /* Convert host/max/nosel to GIC version number */
1914 switch (gic_version) {
1915 case VIRT_GIC_VERSION_HOST:
1916 if (!kvm_enabled()) {
1917 error_report("gic-version=host requires KVM");
1918 exit(1);
1919 }
1920
1921 /* For KVM, gic-version=host means gic-version=max */
1922 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
1923 gics_supported, max_cpus);
1924 case VIRT_GIC_VERSION_MAX:
1925 if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
1926 gic_version = VIRT_GIC_VERSION_4;
1927 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1928 gic_version = VIRT_GIC_VERSION_3;
1929 } else {
1930 gic_version = VIRT_GIC_VERSION_2;
1931 }
1932 break;
1933 case VIRT_GIC_VERSION_NOSEL:
1934 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
1935 max_cpus <= GIC_NCPU) {
1936 gic_version = VIRT_GIC_VERSION_2;
1937 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1938 /*
1939 * in case the host does not support v2 emulation or
1940 * the end-user requested more than 8 VCPUs we now default
1941 * to v3. In any case defaulting to v2 would be broken.
1942 */
1943 gic_version = VIRT_GIC_VERSION_3;
1944 } else if (max_cpus > GIC_NCPU) {
1945 error_report("%s only supports GICv2 emulation but more than 8 "
1946 "vcpus are requested", accel_name);
1947 exit(1);
1948 }
1949 break;
1950 case VIRT_GIC_VERSION_2:
1951 case VIRT_GIC_VERSION_3:
1952 case VIRT_GIC_VERSION_4:
1953 break;
1954 }
1955
1956 /* Check chosen version is effectively supported */
1957 switch (gic_version) {
1958 case VIRT_GIC_VERSION_2:
1959 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
1960 error_report("%s does not support GICv2 emulation", accel_name);
1961 exit(1);
1962 }
1963 break;
1964 case VIRT_GIC_VERSION_3:
1965 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
1966 error_report("%s does not support GICv3 emulation", accel_name);
1967 exit(1);
1968 }
1969 break;
1970 case VIRT_GIC_VERSION_4:
1971 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
1972 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1973 accel_name);
1974 exit(1);
1975 }
1976 break;
1977 default:
1978 error_report("logic error in finalize_gic_version");
1979 exit(1);
1980 break;
1981 }
1982
1983 return gic_version;
1984 }
1985
1986 /*
1987 * finalize_gic_version - Determines the final gic_version
1988 * according to the gic-version property
1989 *
1990 * Default GIC type is v2
1991 */
finalize_gic_version(VirtMachineState * vms)1992 static void finalize_gic_version(VirtMachineState *vms)
1993 {
1994 const char *accel_name = current_accel_name();
1995 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1996 int gics_supported = 0;
1997
1998 /* Determine which GIC versions the current environment supports */
1999 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
2000 int probe_bitmap = kvm_arm_vgic_probe();
2001
2002 if (!probe_bitmap) {
2003 error_report("Unable to determine GIC version supported by host");
2004 exit(1);
2005 }
2006
2007 if (probe_bitmap & KVM_ARM_VGIC_V2) {
2008 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2009 }
2010 if (probe_bitmap & KVM_ARM_VGIC_V3) {
2011 gics_supported |= VIRT_GIC_VERSION_3_MASK;
2012 }
2013 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
2014 /* KVM w/o kernel irqchip can only deal with GICv2 */
2015 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2016 accel_name = "KVM with kernel-irqchip=off";
2017 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
2018 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2019 if (module_object_class_by_name("arm-gicv3")) {
2020 gics_supported |= VIRT_GIC_VERSION_3_MASK;
2021 if (vms->virt) {
2022 /* GICv4 only makes sense if CPU has EL2 */
2023 gics_supported |= VIRT_GIC_VERSION_4_MASK;
2024 }
2025 }
2026 } else {
2027 error_report("Unsupported accelerator, can not determine GIC support");
2028 exit(1);
2029 }
2030
2031 /*
2032 * Then convert helpers like host/max to concrete GIC versions and ensure
2033 * the desired version is supported
2034 */
2035 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
2036 gics_supported, max_cpus);
2037 }
2038
2039 /*
2040 * virt_cpu_post_init() must be called after the CPUs have
2041 * been realized and the GIC has been created.
2042 */
virt_cpu_post_init(VirtMachineState * vms,MemoryRegion * sysmem)2043 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
2044 {
2045 int max_cpus = MACHINE(vms)->smp.max_cpus;
2046 bool aarch64, pmu, steal_time;
2047 CPUState *cpu;
2048
2049 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
2050 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
2051 steal_time = object_property_get_bool(OBJECT(first_cpu),
2052 "kvm-steal-time", NULL);
2053
2054 if (kvm_enabled()) {
2055 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
2056 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
2057
2058 if (steal_time) {
2059 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
2060 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
2061
2062 /* The memory region size must be a multiple of host page size. */
2063 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
2064
2065 if (pvtime_size > pvtime_reg_size) {
2066 error_report("pvtime requires a %" HWADDR_PRId
2067 " byte memory region for %d CPUs,"
2068 " but only %" HWADDR_PRId " has been reserved",
2069 pvtime_size, max_cpus, pvtime_reg_size);
2070 exit(1);
2071 }
2072
2073 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
2074 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
2075 }
2076
2077 CPU_FOREACH(cpu) {
2078 if (pmu) {
2079 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
2080 if (kvm_irqchip_in_kernel()) {
2081 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ);
2082 }
2083 kvm_arm_pmu_init(ARM_CPU(cpu));
2084 }
2085 if (steal_time) {
2086 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base
2087 + cpu->cpu_index
2088 * PVTIME_SIZE_PER_CPU);
2089 }
2090 }
2091 } else {
2092 if (aarch64 && vms->highmem) {
2093 int requested_pa_size = 64 - clz64(vms->highest_gpa);
2094 int pamax = arm_pamax(ARM_CPU(first_cpu));
2095
2096 if (pamax < requested_pa_size) {
2097 error_report("VCPU supports less PA bits (%d) than "
2098 "requested by the memory map (%d)",
2099 pamax, requested_pa_size);
2100 exit(1);
2101 }
2102 }
2103 }
2104 }
2105
machvirt_init(MachineState * machine)2106 static void machvirt_init(MachineState *machine)
2107 {
2108 VirtMachineState *vms = VIRT_MACHINE(machine);
2109 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
2110 MachineClass *mc = MACHINE_GET_CLASS(machine);
2111 const CPUArchIdList *possible_cpus;
2112 MemoryRegion *sysmem = get_system_memory();
2113 MemoryRegion *secure_sysmem = NULL;
2114 MemoryRegion *tag_sysmem = NULL;
2115 MemoryRegion *secure_tag_sysmem = NULL;
2116 int n, virt_max_cpus;
2117 bool firmware_loaded;
2118 bool aarch64 = true;
2119 bool has_ged = !vmc->no_ged;
2120 unsigned int smp_cpus = machine->smp.cpus;
2121 unsigned int max_cpus = machine->smp.max_cpus;
2122
2123 possible_cpus = mc->possible_cpu_arch_ids(machine);
2124
2125 /*
2126 * In accelerated mode, the memory map is computed earlier in kvm_type()
2127 * for Linux, or hvf_get_physical_address_range() for macOS to create a
2128 * VM with the right number of IPA bits.
2129 */
2130 if (!vms->memmap) {
2131 Object *cpuobj;
2132 ARMCPU *armcpu;
2133 int pa_bits;
2134
2135 /*
2136 * Instantiate a temporary CPU object to find out about what
2137 * we are about to deal with. Once this is done, get rid of
2138 * the object.
2139 */
2140 cpuobj = object_new(possible_cpus->cpus[0].type);
2141 armcpu = ARM_CPU(cpuobj);
2142
2143 pa_bits = arm_pamax(armcpu);
2144
2145 object_unref(cpuobj);
2146
2147 virt_set_memmap(vms, pa_bits);
2148 }
2149
2150 /* We can probe only here because during property set
2151 * KVM is not available yet
2152 */
2153 finalize_gic_version(vms);
2154
2155 if (vms->secure) {
2156 /*
2157 * The Secure view of the world is the same as the NonSecure,
2158 * but with a few extra devices. Create it as a container region
2159 * containing the system memory at low priority; any secure-only
2160 * devices go in at higher priority and take precedence.
2161 */
2162 secure_sysmem = g_new(MemoryRegion, 1);
2163 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2164 UINT64_MAX);
2165 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2166 }
2167
2168 firmware_loaded = virt_firmware_init(vms, sysmem,
2169 secure_sysmem ?: sysmem);
2170
2171 /* If we have an EL3 boot ROM then the assumption is that it will
2172 * implement PSCI itself, so disable QEMU's internal implementation
2173 * so it doesn't get in the way. Instead of starting secondary
2174 * CPUs in PSCI powerdown state we will start them all running and
2175 * let the boot ROM sort them out.
2176 * The usual case is that we do use QEMU's PSCI implementation;
2177 * if the guest has EL2 then we will use SMC as the conduit,
2178 * and otherwise we will use HVC (for backwards compatibility and
2179 * because if we're using KVM then we must use HVC).
2180 */
2181 if (vms->secure && firmware_loaded) {
2182 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2183 } else if (vms->virt) {
2184 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2185 } else {
2186 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2187 }
2188
2189 /*
2190 * The maximum number of CPUs depends on the GIC version, or on how
2191 * many redistributors we can fit into the memory map (which in turn
2192 * depends on whether this is a GICv3 or v4).
2193 */
2194 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2195 virt_max_cpus = GIC_NCPU;
2196 } else {
2197 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
2198 if (vms->highmem_redists) {
2199 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2200 }
2201 }
2202
2203 if (max_cpus > virt_max_cpus) {
2204 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2205 "supported by machine 'mach-virt' (%d)",
2206 max_cpus, virt_max_cpus);
2207 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2208 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2209 }
2210
2211 exit(1);
2212 }
2213
2214 if (vms->secure && (kvm_enabled() || hvf_enabled())) {
2215 error_report("mach-virt: %s does not support providing "
2216 "Security extensions (TrustZone) to the guest CPU",
2217 current_accel_name());
2218 exit(1);
2219 }
2220
2221 if (vms->virt && (kvm_enabled() || hvf_enabled())) {
2222 error_report("mach-virt: %s does not support providing "
2223 "Virtualization extensions to the guest CPU",
2224 current_accel_name());
2225 exit(1);
2226 }
2227
2228 if (vms->mte && hvf_enabled()) {
2229 error_report("mach-virt: %s does not support providing "
2230 "MTE to the guest CPU",
2231 current_accel_name());
2232 exit(1);
2233 }
2234
2235 create_fdt(vms);
2236
2237 assert(possible_cpus->len == max_cpus);
2238 for (n = 0; n < possible_cpus->len; n++) {
2239 Object *cpuobj;
2240 CPUState *cs;
2241
2242 if (n >= smp_cpus) {
2243 break;
2244 }
2245
2246 cpuobj = object_new(possible_cpus->cpus[n].type);
2247 object_property_set_int(cpuobj, "mp-affinity",
2248 possible_cpus->cpus[n].arch_id, NULL);
2249
2250 cs = CPU(cpuobj);
2251 cs->cpu_index = n;
2252
2253 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2254 &error_fatal);
2255
2256 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2257
2258 if (!vms->secure) {
2259 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2260 }
2261
2262 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2263 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2264 }
2265
2266 if (vmc->kvm_no_adjvtime &&
2267 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2268 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2269 }
2270
2271 if (vmc->no_kvm_steal_time &&
2272 object_property_find(cpuobj, "kvm-steal-time")) {
2273 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2274 }
2275
2276 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2277 object_property_set_bool(cpuobj, "pmu", false, NULL);
2278 }
2279
2280 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2281 object_property_set_bool(cpuobj, "lpa2", false, NULL);
2282 }
2283
2284 if (object_property_find(cpuobj, "reset-cbar")) {
2285 object_property_set_int(cpuobj, "reset-cbar",
2286 vms->memmap[VIRT_CPUPERIPHS].base,
2287 &error_abort);
2288 }
2289
2290 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2291 &error_abort);
2292 if (vms->secure) {
2293 object_property_set_link(cpuobj, "secure-memory",
2294 OBJECT(secure_sysmem), &error_abort);
2295 }
2296
2297 if (vms->mte) {
2298 if (tcg_enabled()) {
2299 /* Create the memory region only once, but link to all cpus. */
2300 if (!tag_sysmem) {
2301 /*
2302 * The property exists only if MemTag is supported.
2303 * If it is, we must allocate the ram to back that up.
2304 */
2305 if (!object_property_find(cpuobj, "tag-memory")) {
2306 error_report("MTE requested, but not supported "
2307 "by the guest CPU");
2308 exit(1);
2309 }
2310
2311 tag_sysmem = g_new(MemoryRegion, 1);
2312 memory_region_init(tag_sysmem, OBJECT(machine),
2313 "tag-memory", UINT64_MAX / 32);
2314
2315 if (vms->secure) {
2316 secure_tag_sysmem = g_new(MemoryRegion, 1);
2317 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2318 "secure-tag-memory",
2319 UINT64_MAX / 32);
2320
2321 /* As with ram, secure-tag takes precedence over tag. */
2322 memory_region_add_subregion_overlap(secure_tag_sysmem,
2323 0, tag_sysmem, -1);
2324 }
2325 }
2326
2327 object_property_set_link(cpuobj, "tag-memory",
2328 OBJECT(tag_sysmem), &error_abort);
2329 if (vms->secure) {
2330 object_property_set_link(cpuobj, "secure-tag-memory",
2331 OBJECT(secure_tag_sysmem),
2332 &error_abort);
2333 }
2334 } else if (kvm_enabled()) {
2335 if (!kvm_arm_mte_supported()) {
2336 error_report("MTE requested, but not supported by KVM");
2337 exit(1);
2338 }
2339 kvm_arm_enable_mte(cpuobj, &error_abort);
2340 } else {
2341 error_report("MTE requested, but not supported ");
2342 exit(1);
2343 }
2344 }
2345
2346 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2347 object_unref(cpuobj);
2348 }
2349
2350 /* Now we've created the CPUs we can see if they have the hypvirt timer */
2351 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
2352 !vmc->no_ns_el2_virt_timer_irq;
2353
2354 fdt_add_timer_nodes(vms);
2355 fdt_add_cpu_nodes(vms);
2356
2357 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2358 machine->ram);
2359
2360 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2361
2362 create_gic(vms, sysmem);
2363
2364 virt_cpu_post_init(vms, sysmem);
2365
2366 fdt_add_pmu_nodes(vms);
2367
2368 /*
2369 * The first UART always exists. If the security extensions are
2370 * enabled, the second UART also always exists. Otherwise, it only exists
2371 * if a backend is configured explicitly via '-serial <backend>'.
2372 * This avoids potentially breaking existing user setups that expect
2373 * only one NonSecure UART to be present (for instance, older EDK2
2374 * binaries).
2375 *
2376 * The nodes end up in the DTB in reverse order of creation, so we must
2377 * create UART0 last to ensure it appears as the first node in the DTB,
2378 * for compatibility with guest software that just iterates through the
2379 * DTB to find the first UART, as older versions of EDK2 do.
2380 * DTB readers that follow the spec, as Linux does, should honour the
2381 * aliases node information and /chosen/stdout-path regardless of
2382 * the order that nodes appear in the DTB.
2383 *
2384 * For similar back-compatibility reasons, if UART1 is the secure UART
2385 * we create it second (and so it appears first in the DTB), because
2386 * that's what QEMU has always done.
2387 */
2388 if (!vms->secure) {
2389 Chardev *serial1 = serial_hd(1);
2390
2391 if (serial1) {
2392 vms->second_ns_uart_present = true;
2393 create_uart(vms, VIRT_UART1, sysmem, serial1, false);
2394 }
2395 }
2396 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false);
2397 if (vms->secure) {
2398 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true);
2399 }
2400
2401 if (vms->secure) {
2402 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2403 }
2404
2405 if (tag_sysmem) {
2406 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2407 machine->ram_size, "mach-virt.tag");
2408 }
2409
2410 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2411
2412 create_rtc(vms);
2413
2414 create_pcie(vms);
2415
2416 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2417 vms->acpi_dev = create_acpi_ged(vms);
2418 } else {
2419 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2420 }
2421
2422 if (vms->secure && !vmc->no_secure_gpio) {
2423 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2424 }
2425
2426 /* connect powerdown request */
2427 vms->powerdown_notifier.notify = virt_powerdown_req;
2428 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2429
2430 /* Create mmio transports, so the user can create virtio backends
2431 * (which will be automatically plugged in to the transports). If
2432 * no backend is created the transport will just sit harmlessly idle.
2433 */
2434 create_virtio_devices(vms);
2435
2436 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2437 rom_set_fw(vms->fw_cfg);
2438
2439 create_platform_bus(vms);
2440
2441 if (machine->nvdimms_state->is_enabled) {
2442 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2443 .space_id = AML_AS_SYSTEM_MEMORY,
2444 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2445 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2446 };
2447
2448 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2449 arm_virt_nvdimm_acpi_dsmio,
2450 vms->fw_cfg, OBJECT(vms));
2451 }
2452
2453 vms->bootinfo.ram_size = machine->ram_size;
2454 vms->bootinfo.board_id = -1;
2455 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2456 vms->bootinfo.get_dtb = machvirt_dtb;
2457 vms->bootinfo.skip_dtb_autoload = true;
2458 vms->bootinfo.firmware_loaded = firmware_loaded;
2459 vms->bootinfo.psci_conduit = vms->psci_conduit;
2460 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2461
2462 vms->machine_done.notify = virt_machine_done;
2463 qemu_add_machine_init_done_notifier(&vms->machine_done);
2464 }
2465
virt_get_secure(Object * obj,Error ** errp)2466 static bool virt_get_secure(Object *obj, Error **errp)
2467 {
2468 VirtMachineState *vms = VIRT_MACHINE(obj);
2469
2470 return vms->secure;
2471 }
2472
virt_set_secure(Object * obj,bool value,Error ** errp)2473 static void virt_set_secure(Object *obj, bool value, Error **errp)
2474 {
2475 VirtMachineState *vms = VIRT_MACHINE(obj);
2476
2477 vms->secure = value;
2478 }
2479
virt_get_virt(Object * obj,Error ** errp)2480 static bool virt_get_virt(Object *obj, Error **errp)
2481 {
2482 VirtMachineState *vms = VIRT_MACHINE(obj);
2483
2484 return vms->virt;
2485 }
2486
virt_set_virt(Object * obj,bool value,Error ** errp)2487 static void virt_set_virt(Object *obj, bool value, Error **errp)
2488 {
2489 VirtMachineState *vms = VIRT_MACHINE(obj);
2490
2491 vms->virt = value;
2492 }
2493
virt_get_highmem(Object * obj,Error ** errp)2494 static bool virt_get_highmem(Object *obj, Error **errp)
2495 {
2496 VirtMachineState *vms = VIRT_MACHINE(obj);
2497
2498 return vms->highmem;
2499 }
2500
virt_set_highmem(Object * obj,bool value,Error ** errp)2501 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2502 {
2503 VirtMachineState *vms = VIRT_MACHINE(obj);
2504
2505 vms->highmem = value;
2506 }
2507
virt_get_compact_highmem(Object * obj,Error ** errp)2508 static bool virt_get_compact_highmem(Object *obj, Error **errp)
2509 {
2510 VirtMachineState *vms = VIRT_MACHINE(obj);
2511
2512 return vms->highmem_compact;
2513 }
2514
virt_set_compact_highmem(Object * obj,bool value,Error ** errp)2515 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
2516 {
2517 VirtMachineState *vms = VIRT_MACHINE(obj);
2518
2519 vms->highmem_compact = value;
2520 }
2521
virt_get_highmem_redists(Object * obj,Error ** errp)2522 static bool virt_get_highmem_redists(Object *obj, Error **errp)
2523 {
2524 VirtMachineState *vms = VIRT_MACHINE(obj);
2525
2526 return vms->highmem_redists;
2527 }
2528
virt_set_highmem_redists(Object * obj,bool value,Error ** errp)2529 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
2530 {
2531 VirtMachineState *vms = VIRT_MACHINE(obj);
2532
2533 vms->highmem_redists = value;
2534 }
2535
virt_get_highmem_ecam(Object * obj,Error ** errp)2536 static bool virt_get_highmem_ecam(Object *obj, Error **errp)
2537 {
2538 VirtMachineState *vms = VIRT_MACHINE(obj);
2539
2540 return vms->highmem_ecam;
2541 }
2542
virt_set_highmem_ecam(Object * obj,bool value,Error ** errp)2543 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
2544 {
2545 VirtMachineState *vms = VIRT_MACHINE(obj);
2546
2547 vms->highmem_ecam = value;
2548 }
2549
virt_get_highmem_mmio(Object * obj,Error ** errp)2550 static bool virt_get_highmem_mmio(Object *obj, Error **errp)
2551 {
2552 VirtMachineState *vms = VIRT_MACHINE(obj);
2553
2554 return vms->highmem_mmio;
2555 }
2556
virt_set_highmem_mmio(Object * obj,bool value,Error ** errp)2557 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
2558 {
2559 VirtMachineState *vms = VIRT_MACHINE(obj);
2560
2561 vms->highmem_mmio = value;
2562 }
2563
virt_get_highmem_mmio_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2564 static void virt_get_highmem_mmio_size(Object *obj, Visitor *v,
2565 const char *name, void *opaque,
2566 Error **errp)
2567 {
2568 uint64_t size = extended_memmap[VIRT_HIGH_PCIE_MMIO].size;
2569
2570 visit_type_size(v, name, &size, errp);
2571 }
2572
virt_set_highmem_mmio_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2573 static void virt_set_highmem_mmio_size(Object *obj, Visitor *v,
2574 const char *name, void *opaque,
2575 Error **errp)
2576 {
2577 uint64_t size;
2578
2579 if (!visit_type_size(v, name, &size, errp)) {
2580 return;
2581 }
2582
2583 if (!is_power_of_2(size)) {
2584 error_setg(errp, "highmem-mmio-size is not a power of 2");
2585 return;
2586 }
2587
2588 if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) {
2589 char *sz = size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE);
2590 error_setg(errp, "highmem-mmio-size cannot be set to a lower value "
2591 "than the default (%s)", sz);
2592 g_free(sz);
2593 return;
2594 }
2595
2596 extended_memmap[VIRT_HIGH_PCIE_MMIO].size = size;
2597 }
2598
virt_get_its(Object * obj,Error ** errp)2599 static bool virt_get_its(Object *obj, Error **errp)
2600 {
2601 VirtMachineState *vms = VIRT_MACHINE(obj);
2602
2603 return vms->its;
2604 }
2605
virt_set_its(Object * obj,bool value,Error ** errp)2606 static void virt_set_its(Object *obj, bool value, Error **errp)
2607 {
2608 VirtMachineState *vms = VIRT_MACHINE(obj);
2609
2610 vms->its = value;
2611 }
2612
virt_get_dtb_randomness(Object * obj,Error ** errp)2613 static bool virt_get_dtb_randomness(Object *obj, Error **errp)
2614 {
2615 VirtMachineState *vms = VIRT_MACHINE(obj);
2616
2617 return vms->dtb_randomness;
2618 }
2619
virt_set_dtb_randomness(Object * obj,bool value,Error ** errp)2620 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp)
2621 {
2622 VirtMachineState *vms = VIRT_MACHINE(obj);
2623
2624 vms->dtb_randomness = value;
2625 }
2626
virt_get_oem_id(Object * obj,Error ** errp)2627 static char *virt_get_oem_id(Object *obj, Error **errp)
2628 {
2629 VirtMachineState *vms = VIRT_MACHINE(obj);
2630
2631 return g_strdup(vms->oem_id);
2632 }
2633
virt_set_oem_id(Object * obj,const char * value,Error ** errp)2634 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2635 {
2636 VirtMachineState *vms = VIRT_MACHINE(obj);
2637 size_t len = strlen(value);
2638
2639 if (len > 6) {
2640 error_setg(errp,
2641 "User specified oem-id value is bigger than 6 bytes in size");
2642 return;
2643 }
2644
2645 strncpy(vms->oem_id, value, 6);
2646 }
2647
virt_get_oem_table_id(Object * obj,Error ** errp)2648 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2649 {
2650 VirtMachineState *vms = VIRT_MACHINE(obj);
2651
2652 return g_strdup(vms->oem_table_id);
2653 }
2654
virt_set_oem_table_id(Object * obj,const char * value,Error ** errp)2655 static void virt_set_oem_table_id(Object *obj, const char *value,
2656 Error **errp)
2657 {
2658 VirtMachineState *vms = VIRT_MACHINE(obj);
2659 size_t len = strlen(value);
2660
2661 if (len > 8) {
2662 error_setg(errp,
2663 "User specified oem-table-id value is bigger than 8 bytes in size");
2664 return;
2665 }
2666 strncpy(vms->oem_table_id, value, 8);
2667 }
2668
2669
virt_is_acpi_enabled(VirtMachineState * vms)2670 bool virt_is_acpi_enabled(VirtMachineState *vms)
2671 {
2672 if (vms->acpi == ON_OFF_AUTO_OFF) {
2673 return false;
2674 }
2675 return true;
2676 }
2677
virt_get_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2678 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2679 void *opaque, Error **errp)
2680 {
2681 VirtMachineState *vms = VIRT_MACHINE(obj);
2682 OnOffAuto acpi = vms->acpi;
2683
2684 visit_type_OnOffAuto(v, name, &acpi, errp);
2685 }
2686
virt_set_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2687 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2688 void *opaque, Error **errp)
2689 {
2690 VirtMachineState *vms = VIRT_MACHINE(obj);
2691
2692 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2693 }
2694
virt_get_ras(Object * obj,Error ** errp)2695 static bool virt_get_ras(Object *obj, Error **errp)
2696 {
2697 VirtMachineState *vms = VIRT_MACHINE(obj);
2698
2699 return vms->ras;
2700 }
2701
virt_set_ras(Object * obj,bool value,Error ** errp)2702 static void virt_set_ras(Object *obj, bool value, Error **errp)
2703 {
2704 VirtMachineState *vms = VIRT_MACHINE(obj);
2705
2706 vms->ras = value;
2707 }
2708
virt_get_mte(Object * obj,Error ** errp)2709 static bool virt_get_mte(Object *obj, Error **errp)
2710 {
2711 VirtMachineState *vms = VIRT_MACHINE(obj);
2712
2713 return vms->mte;
2714 }
2715
virt_set_mte(Object * obj,bool value,Error ** errp)2716 static void virt_set_mte(Object *obj, bool value, Error **errp)
2717 {
2718 VirtMachineState *vms = VIRT_MACHINE(obj);
2719
2720 vms->mte = value;
2721 }
2722
virt_get_gic_version(Object * obj,Error ** errp)2723 static char *virt_get_gic_version(Object *obj, Error **errp)
2724 {
2725 VirtMachineState *vms = VIRT_MACHINE(obj);
2726 const char *val;
2727
2728 switch (vms->gic_version) {
2729 case VIRT_GIC_VERSION_4:
2730 val = "4";
2731 break;
2732 case VIRT_GIC_VERSION_3:
2733 val = "3";
2734 break;
2735 default:
2736 val = "2";
2737 break;
2738 }
2739 return g_strdup(val);
2740 }
2741
virt_set_gic_version(Object * obj,const char * value,Error ** errp)2742 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2743 {
2744 VirtMachineState *vms = VIRT_MACHINE(obj);
2745
2746 if (!strcmp(value, "4")) {
2747 vms->gic_version = VIRT_GIC_VERSION_4;
2748 } else if (!strcmp(value, "3")) {
2749 vms->gic_version = VIRT_GIC_VERSION_3;
2750 } else if (!strcmp(value, "2")) {
2751 vms->gic_version = VIRT_GIC_VERSION_2;
2752 } else if (!strcmp(value, "host")) {
2753 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2754 } else if (!strcmp(value, "max")) {
2755 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2756 } else {
2757 error_setg(errp, "Invalid gic-version value");
2758 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2759 }
2760 }
2761
virt_get_iommu(Object * obj,Error ** errp)2762 static char *virt_get_iommu(Object *obj, Error **errp)
2763 {
2764 VirtMachineState *vms = VIRT_MACHINE(obj);
2765
2766 switch (vms->iommu) {
2767 case VIRT_IOMMU_NONE:
2768 return g_strdup("none");
2769 case VIRT_IOMMU_SMMUV3:
2770 return g_strdup("smmuv3");
2771 default:
2772 g_assert_not_reached();
2773 }
2774 }
2775
virt_set_iommu(Object * obj,const char * value,Error ** errp)2776 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2777 {
2778 VirtMachineState *vms = VIRT_MACHINE(obj);
2779
2780 if (!strcmp(value, "smmuv3")) {
2781 vms->iommu = VIRT_IOMMU_SMMUV3;
2782 } else if (!strcmp(value, "none")) {
2783 vms->iommu = VIRT_IOMMU_NONE;
2784 } else {
2785 error_setg(errp, "Invalid iommu value");
2786 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2787 }
2788 }
2789
virt_get_default_bus_bypass_iommu(Object * obj,Error ** errp)2790 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2791 {
2792 VirtMachineState *vms = VIRT_MACHINE(obj);
2793
2794 return vms->default_bus_bypass_iommu;
2795 }
2796
virt_set_default_bus_bypass_iommu(Object * obj,bool value,Error ** errp)2797 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2798 Error **errp)
2799 {
2800 VirtMachineState *vms = VIRT_MACHINE(obj);
2801
2802 vms->default_bus_bypass_iommu = value;
2803 }
2804
2805 static CpuInstanceProperties
virt_cpu_index_to_props(MachineState * ms,unsigned cpu_index)2806 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2807 {
2808 MachineClass *mc = MACHINE_GET_CLASS(ms);
2809 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2810
2811 assert(cpu_index < possible_cpus->len);
2812 return possible_cpus->cpus[cpu_index].props;
2813 }
2814
virt_get_default_cpu_node_id(const MachineState * ms,int idx)2815 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2816 {
2817 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2818
2819 return socket_id % ms->numa_state->num_nodes;
2820 }
2821
virt_possible_cpu_arch_ids(MachineState * ms)2822 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2823 {
2824 int n;
2825 unsigned int max_cpus = ms->smp.max_cpus;
2826 VirtMachineState *vms = VIRT_MACHINE(ms);
2827 MachineClass *mc = MACHINE_GET_CLASS(vms);
2828
2829 if (ms->possible_cpus) {
2830 assert(ms->possible_cpus->len == max_cpus);
2831 return ms->possible_cpus;
2832 }
2833
2834 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2835 sizeof(CPUArchId) * max_cpus);
2836 ms->possible_cpus->len = max_cpus;
2837 for (n = 0; n < ms->possible_cpus->len; n++) {
2838 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2839 ms->possible_cpus->cpus[n].arch_id =
2840 virt_cpu_mp_affinity(vms, n);
2841
2842 assert(!mc->smp_props.dies_supported);
2843 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2844 ms->possible_cpus->cpus[n].props.socket_id =
2845 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2846 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2847 ms->possible_cpus->cpus[n].props.cluster_id =
2848 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2849 ms->possible_cpus->cpus[n].props.has_core_id = true;
2850 ms->possible_cpus->cpus[n].props.core_id =
2851 (n / ms->smp.threads) % ms->smp.cores;
2852 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2853 ms->possible_cpus->cpus[n].props.thread_id =
2854 n % ms->smp.threads;
2855 }
2856 return ms->possible_cpus;
2857 }
2858
virt_memory_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2859 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2860 Error **errp)
2861 {
2862 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2863 const MachineState *ms = MACHINE(hotplug_dev);
2864 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2865
2866 if (!vms->acpi_dev) {
2867 error_setg(errp,
2868 "memory hotplug is not enabled: missing acpi-ged device");
2869 return;
2870 }
2871
2872 if (vms->mte) {
2873 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2874 return;
2875 }
2876
2877 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2878 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2879 return;
2880 }
2881
2882 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
2883 }
2884
virt_memory_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2885 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2886 DeviceState *dev, Error **errp)
2887 {
2888 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2889 MachineState *ms = MACHINE(hotplug_dev);
2890 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2891
2892 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2893
2894 if (is_nvdimm) {
2895 nvdimm_plug(ms->nvdimms_state);
2896 }
2897
2898 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2899 dev, &error_abort);
2900 }
2901
virt_machine_device_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2902 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2903 DeviceState *dev, Error **errp)
2904 {
2905 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2906
2907 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2908 virt_memory_pre_plug(hotplug_dev, dev, errp);
2909 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2910 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2911 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2912 hwaddr db_start = 0, db_end = 0;
2913 QList *reserved_regions;
2914 char *resv_prop_str;
2915
2916 if (vms->iommu != VIRT_IOMMU_NONE) {
2917 error_setg(errp, "virt machine does not support multiple IOMMUs");
2918 return;
2919 }
2920
2921 switch (vms->msi_controller) {
2922 case VIRT_MSI_CTRL_NONE:
2923 return;
2924 case VIRT_MSI_CTRL_ITS:
2925 /* GITS_TRANSLATER page */
2926 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2927 db_end = base_memmap[VIRT_GIC_ITS].base +
2928 base_memmap[VIRT_GIC_ITS].size - 1;
2929 break;
2930 case VIRT_MSI_CTRL_GICV2M:
2931 /* MSI_SETSPI_NS page */
2932 db_start = base_memmap[VIRT_GIC_V2M].base;
2933 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2934 break;
2935 }
2936 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2937 db_start, db_end,
2938 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2939
2940 reserved_regions = qlist_new();
2941 qlist_append_str(reserved_regions, resv_prop_str);
2942 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
2943 g_free(resv_prop_str);
2944 }
2945 }
2946
virt_machine_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2947 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2948 DeviceState *dev, Error **errp)
2949 {
2950 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2951
2952 if (vms->platform_bus_dev) {
2953 MachineClass *mc = MACHINE_GET_CLASS(vms);
2954
2955 if (device_is_dynamic_sysbus(mc, dev)) {
2956 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2957 SYS_BUS_DEVICE(dev));
2958 }
2959 }
2960
2961 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2962 virt_memory_plug(hotplug_dev, dev, errp);
2963 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2964 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2965 }
2966
2967 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2968 PCIDevice *pdev = PCI_DEVICE(dev);
2969
2970 vms->iommu = VIRT_IOMMU_VIRTIO;
2971 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2972 create_virtio_iommu_dt_bindings(vms);
2973 }
2974 }
2975
virt_dimm_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2976 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2977 DeviceState *dev, Error **errp)
2978 {
2979 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2980
2981 if (!vms->acpi_dev) {
2982 error_setg(errp,
2983 "memory hotplug is not enabled: missing acpi-ged device");
2984 return;
2985 }
2986
2987 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2988 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
2989 return;
2990 }
2991
2992 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2993 errp);
2994 }
2995
virt_dimm_unplug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2996 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2997 DeviceState *dev, Error **errp)
2998 {
2999 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3000 Error *local_err = NULL;
3001
3002 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
3003 if (local_err) {
3004 goto out;
3005 }
3006
3007 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
3008 qdev_unrealize(dev);
3009
3010 out:
3011 error_propagate(errp, local_err);
3012 }
3013
virt_machine_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3014 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
3015 DeviceState *dev, Error **errp)
3016 {
3017 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3018 virt_dimm_unplug_request(hotplug_dev, dev, errp);
3019 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
3020 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
3021 errp);
3022 } else {
3023 error_setg(errp, "device unplug request for unsupported device"
3024 " type: %s", object_get_typename(OBJECT(dev)));
3025 }
3026 }
3027
virt_machine_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3028 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
3029 DeviceState *dev, Error **errp)
3030 {
3031 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3032 virt_dimm_unplug(hotplug_dev, dev, errp);
3033 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
3034 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
3035 } else {
3036 error_setg(errp, "virt: device unplug for unsupported device"
3037 " type: %s", object_get_typename(OBJECT(dev)));
3038 }
3039 }
3040
virt_machine_get_hotplug_handler(MachineState * machine,DeviceState * dev)3041 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
3042 DeviceState *dev)
3043 {
3044 MachineClass *mc = MACHINE_GET_CLASS(machine);
3045
3046 if (device_is_dynamic_sysbus(mc, dev) ||
3047 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3048 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
3049 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
3050 return HOTPLUG_HANDLER(machine);
3051 }
3052 return NULL;
3053 }
3054
3055 /*
3056 * for arm64 kvm_type [7-0] encodes the requested number of bits
3057 * in the IPA address space
3058 */
virt_kvm_type(MachineState * ms,const char * type_str)3059 static int virt_kvm_type(MachineState *ms, const char *type_str)
3060 {
3061 VirtMachineState *vms = VIRT_MACHINE(ms);
3062 int max_vm_pa_size, requested_pa_size;
3063 bool fixed_ipa;
3064
3065 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
3066
3067 /* we freeze the memory map to compute the highest gpa */
3068 virt_set_memmap(vms, max_vm_pa_size);
3069
3070 requested_pa_size = 64 - clz64(vms->highest_gpa);
3071
3072 /*
3073 * KVM requires the IPA size to be at least 32 bits.
3074 */
3075 if (requested_pa_size < 32) {
3076 requested_pa_size = 32;
3077 }
3078
3079 if (requested_pa_size > max_vm_pa_size) {
3080 error_report("-m and ,maxmem option values "
3081 "require an IPA range (%d bits) larger than "
3082 "the one supported by the host (%d bits)",
3083 requested_pa_size, max_vm_pa_size);
3084 return -1;
3085 }
3086 /*
3087 * We return the requested PA log size, unless KVM only supports
3088 * the implicit legacy 40b IPA setting, in which case the kvm_type
3089 * must be 0.
3090 */
3091 return fixed_ipa ? 0 : requested_pa_size;
3092 }
3093
virt_hvf_get_physical_address_range(MachineState * ms)3094 static int virt_hvf_get_physical_address_range(MachineState *ms)
3095 {
3096 VirtMachineState *vms = VIRT_MACHINE(ms);
3097
3098 int default_ipa_size = hvf_arm_get_default_ipa_bit_size();
3099 int max_ipa_size = hvf_arm_get_max_ipa_bit_size();
3100
3101 /* We freeze the memory map to compute the highest gpa */
3102 virt_set_memmap(vms, max_ipa_size);
3103
3104 int requested_ipa_size = 64 - clz64(vms->highest_gpa);
3105
3106 /*
3107 * If we're <= the default IPA size just use the default.
3108 * If we're above the default but below the maximum, round up to
3109 * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only
3110 * returns values that are valid ARM PARange values.
3111 */
3112 if (requested_ipa_size <= default_ipa_size) {
3113 requested_ipa_size = default_ipa_size;
3114 } else if (requested_ipa_size <= max_ipa_size) {
3115 requested_ipa_size = max_ipa_size;
3116 } else {
3117 error_report("-m and ,maxmem option values "
3118 "require an IPA range (%d bits) larger than "
3119 "the one supported by the host (%d bits)",
3120 requested_ipa_size, max_ipa_size);
3121 return -1;
3122 }
3123
3124 return requested_ipa_size;
3125 }
3126
virt_machine_class_init(ObjectClass * oc,void * data)3127 static void virt_machine_class_init(ObjectClass *oc, void *data)
3128 {
3129 MachineClass *mc = MACHINE_CLASS(oc);
3130 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3131 static const char * const valid_cpu_types[] = {
3132 #ifdef CONFIG_TCG
3133 ARM_CPU_TYPE_NAME("cortex-a7"),
3134 ARM_CPU_TYPE_NAME("cortex-a15"),
3135 #ifdef TARGET_AARCH64
3136 ARM_CPU_TYPE_NAME("cortex-a35"),
3137 ARM_CPU_TYPE_NAME("cortex-a55"),
3138 ARM_CPU_TYPE_NAME("cortex-a72"),
3139 ARM_CPU_TYPE_NAME("cortex-a76"),
3140 ARM_CPU_TYPE_NAME("cortex-a710"),
3141 ARM_CPU_TYPE_NAME("a64fx"),
3142 ARM_CPU_TYPE_NAME("neoverse-n1"),
3143 ARM_CPU_TYPE_NAME("neoverse-v1"),
3144 ARM_CPU_TYPE_NAME("neoverse-n2"),
3145 #endif /* TARGET_AARCH64 */
3146 #endif /* CONFIG_TCG */
3147 #ifdef TARGET_AARCH64
3148 ARM_CPU_TYPE_NAME("cortex-a53"),
3149 ARM_CPU_TYPE_NAME("cortex-a57"),
3150 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3151 ARM_CPU_TYPE_NAME("host"),
3152 #endif /* CONFIG_KVM || CONFIG_HVF */
3153 #endif /* TARGET_AARCH64 */
3154 ARM_CPU_TYPE_NAME("max"),
3155 NULL
3156 };
3157
3158 mc->init = machvirt_init;
3159 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
3160 * The value may be reduced later when we have more information about the
3161 * configuration of the particular instance.
3162 */
3163 mc->max_cpus = 512;
3164 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
3165 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
3166 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
3167 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
3168 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS);
3169 #ifdef CONFIG_TPM
3170 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
3171 #endif
3172 mc->block_default_type = IF_VIRTIO;
3173 mc->no_cdrom = 1;
3174 mc->pci_allow_0_address = true;
3175 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3176 mc->minimum_page_bits = 12;
3177 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
3178 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
3179 #ifdef CONFIG_TCG
3180 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
3181 #else
3182 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
3183 #endif
3184 mc->valid_cpu_types = valid_cpu_types;
3185 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
3186 mc->kvm_type = virt_kvm_type;
3187 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
3188 assert(!mc->get_hotplug_handler);
3189 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
3190 hc->pre_plug = virt_machine_device_pre_plug_cb;
3191 hc->plug = virt_machine_device_plug_cb;
3192 hc->unplug_request = virt_machine_device_unplug_request_cb;
3193 hc->unplug = virt_machine_device_unplug_cb;
3194 mc->nvdimm_supported = true;
3195 mc->smp_props.clusters_supported = true;
3196 mc->auto_enable_numa_with_memhp = true;
3197 mc->auto_enable_numa_with_memdev = true;
3198 /* platform instead of architectural choice */
3199 mc->cpu_cluster_has_numa_boundary = true;
3200 mc->default_ram_id = "mach-virt.ram";
3201 mc->default_nic = "virtio-net-pci";
3202
3203 object_class_property_add(oc, "acpi", "OnOffAuto",
3204 virt_get_acpi, virt_set_acpi,
3205 NULL, NULL);
3206 object_class_property_set_description(oc, "acpi",
3207 "Enable ACPI");
3208 object_class_property_add_bool(oc, "secure", virt_get_secure,
3209 virt_set_secure);
3210 object_class_property_set_description(oc, "secure",
3211 "Set on/off to enable/disable the ARM "
3212 "Security Extensions (TrustZone)");
3213
3214 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
3215 virt_set_virt);
3216 object_class_property_set_description(oc, "virtualization",
3217 "Set on/off to enable/disable emulating a "
3218 "guest CPU which implements the ARM "
3219 "Virtualization Extensions");
3220
3221 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
3222 virt_set_highmem);
3223 object_class_property_set_description(oc, "highmem",
3224 "Set on/off to enable/disable using "
3225 "physical address space above 32 bits");
3226
3227 object_class_property_add_bool(oc, "compact-highmem",
3228 virt_get_compact_highmem,
3229 virt_set_compact_highmem);
3230 object_class_property_set_description(oc, "compact-highmem",
3231 "Set on/off to enable/disable compact "
3232 "layout for high memory regions");
3233
3234 object_class_property_add_bool(oc, "highmem-redists",
3235 virt_get_highmem_redists,
3236 virt_set_highmem_redists);
3237 object_class_property_set_description(oc, "highmem-redists",
3238 "Set on/off to enable/disable high "
3239 "memory region for GICv3 or GICv4 "
3240 "redistributor");
3241
3242 object_class_property_add_bool(oc, "highmem-ecam",
3243 virt_get_highmem_ecam,
3244 virt_set_highmem_ecam);
3245 object_class_property_set_description(oc, "highmem-ecam",
3246 "Set on/off to enable/disable high "
3247 "memory region for PCI ECAM");
3248
3249 object_class_property_add_bool(oc, "highmem-mmio",
3250 virt_get_highmem_mmio,
3251 virt_set_highmem_mmio);
3252 object_class_property_set_description(oc, "highmem-mmio",
3253 "Set on/off to enable/disable high "
3254 "memory region for PCI MMIO");
3255
3256 object_class_property_add(oc, "highmem-mmio-size", "size",
3257 virt_get_highmem_mmio_size,
3258 virt_set_highmem_mmio_size,
3259 NULL, NULL);
3260 object_class_property_set_description(oc, "highmem-mmio-size",
3261 "Set the high memory region size "
3262 "for PCI MMIO");
3263
3264 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3265 virt_set_gic_version);
3266 object_class_property_set_description(oc, "gic-version",
3267 "Set GIC version. "
3268 "Valid values are 2, 3, 4, host and max");
3269
3270 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
3271 object_class_property_set_description(oc, "iommu",
3272 "Set the IOMMU type. "
3273 "Valid values are none and smmuv3");
3274
3275 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3276 virt_get_default_bus_bypass_iommu,
3277 virt_set_default_bus_bypass_iommu);
3278 object_class_property_set_description(oc, "default-bus-bypass-iommu",
3279 "Set on/off to enable/disable "
3280 "bypass_iommu for default root bus");
3281
3282 object_class_property_add_bool(oc, "ras", virt_get_ras,
3283 virt_set_ras);
3284 object_class_property_set_description(oc, "ras",
3285 "Set on/off to enable/disable reporting host memory errors "
3286 "to a KVM guest using ACPI and guest external abort exceptions");
3287
3288 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
3289 object_class_property_set_description(oc, "mte",
3290 "Set on/off to enable/disable emulating a "
3291 "guest CPU which implements the ARM "
3292 "Memory Tagging Extension");
3293
3294 object_class_property_add_bool(oc, "its", virt_get_its,
3295 virt_set_its);
3296 object_class_property_set_description(oc, "its",
3297 "Set on/off to enable/disable "
3298 "ITS instantiation");
3299
3300 object_class_property_add_bool(oc, "dtb-randomness",
3301 virt_get_dtb_randomness,
3302 virt_set_dtb_randomness);
3303 object_class_property_set_description(oc, "dtb-randomness",
3304 "Set off to disable passing random or "
3305 "non-deterministic dtb nodes to guest");
3306
3307 object_class_property_add_bool(oc, "dtb-kaslr-seed",
3308 virt_get_dtb_randomness,
3309 virt_set_dtb_randomness);
3310 object_class_property_set_description(oc, "dtb-kaslr-seed",
3311 "Deprecated synonym of dtb-randomness");
3312
3313 object_class_property_add_str(oc, "x-oem-id",
3314 virt_get_oem_id,
3315 virt_set_oem_id);
3316 object_class_property_set_description(oc, "x-oem-id",
3317 "Override the default value of field OEMID "
3318 "in ACPI table header."
3319 "The string may be up to 6 bytes in size");
3320
3321
3322 object_class_property_add_str(oc, "x-oem-table-id",
3323 virt_get_oem_table_id,
3324 virt_set_oem_table_id);
3325 object_class_property_set_description(oc, "x-oem-table-id",
3326 "Override the default value of field OEM Table ID "
3327 "in ACPI table header."
3328 "The string may be up to 8 bytes in size");
3329
3330 }
3331
virt_instance_init(Object * obj)3332 static void virt_instance_init(Object *obj)
3333 {
3334 VirtMachineState *vms = VIRT_MACHINE(obj);
3335 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
3336
3337 /* EL3 is disabled by default on virt: this makes us consistent
3338 * between KVM and TCG for this board, and it also allows us to
3339 * boot UEFI blobs which assume no TrustZone support.
3340 */
3341 vms->secure = false;
3342
3343 /* EL2 is also disabled by default, for similar reasons */
3344 vms->virt = false;
3345
3346 /* High memory is enabled by default */
3347 vms->highmem = true;
3348 vms->highmem_compact = !vmc->no_highmem_compact;
3349 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3350
3351 vms->highmem_ecam = !vmc->no_highmem_ecam;
3352 vms->highmem_mmio = true;
3353 vms->highmem_redists = true;
3354
3355 if (vmc->no_its) {
3356 vms->its = false;
3357 } else {
3358 /* Default allows ITS instantiation */
3359 vms->its = true;
3360
3361 if (vmc->no_tcg_its) {
3362 vms->tcg_its = false;
3363 } else {
3364 vms->tcg_its = true;
3365 }
3366 }
3367
3368 /* Default disallows iommu instantiation */
3369 vms->iommu = VIRT_IOMMU_NONE;
3370
3371 /* The default root bus is attached to iommu by default */
3372 vms->default_bus_bypass_iommu = false;
3373
3374 /* Default disallows RAS instantiation */
3375 vms->ras = false;
3376
3377 /* MTE is disabled by default. */
3378 vms->mte = false;
3379
3380 /* Supply kaslr-seed and rng-seed by default */
3381 vms->dtb_randomness = true;
3382
3383 vms->irqmap = a15irqmap;
3384
3385 virt_flash_create(vms);
3386
3387 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3388 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3389 }
3390
3391 static const TypeInfo virt_machine_info = {
3392 .name = TYPE_VIRT_MACHINE,
3393 .parent = TYPE_MACHINE,
3394 .abstract = true,
3395 .instance_size = sizeof(VirtMachineState),
3396 .class_size = sizeof(VirtMachineClass),
3397 .class_init = virt_machine_class_init,
3398 .instance_init = virt_instance_init,
3399 .interfaces = (InterfaceInfo[]) {
3400 { TYPE_HOTPLUG_HANDLER },
3401 { }
3402 },
3403 };
3404
machvirt_machine_init(void)3405 static void machvirt_machine_init(void)
3406 {
3407 type_register_static(&virt_machine_info);
3408 }
3409 type_init(machvirt_machine_init);
3410
virt_machine_10_0_options(MachineClass * mc)3411 static void virt_machine_10_0_options(MachineClass *mc)
3412 {
3413 }
3414 DEFINE_VIRT_MACHINE_AS_LATEST(10, 0)
3415
virt_machine_9_2_options(MachineClass * mc)3416 static void virt_machine_9_2_options(MachineClass *mc)
3417 {
3418 virt_machine_10_0_options(mc);
3419 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len);
3420 }
3421 DEFINE_VIRT_MACHINE(9, 2)
3422
virt_machine_9_1_options(MachineClass * mc)3423 static void virt_machine_9_1_options(MachineClass *mc)
3424 {
3425 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3426
3427 virt_machine_9_2_options(mc);
3428 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len);
3429 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */
3430 vmc->no_nested_smmu = true;
3431 }
3432 DEFINE_VIRT_MACHINE(9, 1)
3433
virt_machine_9_0_options(MachineClass * mc)3434 static void virt_machine_9_0_options(MachineClass *mc)
3435 {
3436 virt_machine_9_1_options(mc);
3437 mc->smbios_memory_device_size = 16 * GiB;
3438 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len);
3439 }
3440 DEFINE_VIRT_MACHINE(9, 0)
3441
virt_machine_8_2_options(MachineClass * mc)3442 static void virt_machine_8_2_options(MachineClass *mc)
3443 {
3444 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3445
3446 virt_machine_9_0_options(mc);
3447 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
3448 /*
3449 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
3450 * earlier machines. (Exposing it tickles a bug in older EDK2
3451 * guest BIOS binaries.)
3452 */
3453 vmc->no_ns_el2_virt_timer_irq = true;
3454 }
3455 DEFINE_VIRT_MACHINE(8, 2)
3456
virt_machine_8_1_options(MachineClass * mc)3457 static void virt_machine_8_1_options(MachineClass *mc)
3458 {
3459 virt_machine_8_2_options(mc);
3460 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
3461 }
3462 DEFINE_VIRT_MACHINE(8, 1)
3463
virt_machine_8_0_options(MachineClass * mc)3464 static void virt_machine_8_0_options(MachineClass *mc)
3465 {
3466 virt_machine_8_1_options(mc);
3467 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3468 }
3469 DEFINE_VIRT_MACHINE(8, 0)
3470
virt_machine_7_2_options(MachineClass * mc)3471 static void virt_machine_7_2_options(MachineClass *mc)
3472 {
3473 virt_machine_8_0_options(mc);
3474 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3475 }
3476 DEFINE_VIRT_MACHINE(7, 2)
3477
virt_machine_7_1_options(MachineClass * mc)3478 static void virt_machine_7_1_options(MachineClass *mc)
3479 {
3480 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3481
3482 virt_machine_7_2_options(mc);
3483 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3484 /* Compact layout for high memory regions was introduced with 7.2 */
3485 vmc->no_highmem_compact = true;
3486 }
3487 DEFINE_VIRT_MACHINE(7, 1)
3488
virt_machine_7_0_options(MachineClass * mc)3489 static void virt_machine_7_0_options(MachineClass *mc)
3490 {
3491 virt_machine_7_1_options(mc);
3492 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3493 }
3494 DEFINE_VIRT_MACHINE(7, 0)
3495
virt_machine_6_2_options(MachineClass * mc)3496 static void virt_machine_6_2_options(MachineClass *mc)
3497 {
3498 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3499
3500 virt_machine_7_0_options(mc);
3501 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3502 vmc->no_tcg_lpa2 = true;
3503 }
3504 DEFINE_VIRT_MACHINE(6, 2)
3505
virt_machine_6_1_options(MachineClass * mc)3506 static void virt_machine_6_1_options(MachineClass *mc)
3507 {
3508 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3509
3510 virt_machine_6_2_options(mc);
3511 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3512 mc->smp_props.prefer_sockets = true;
3513 vmc->no_cpu_topology = true;
3514
3515 /* qemu ITS was introduced with 6.2 */
3516 vmc->no_tcg_its = true;
3517 }
3518 DEFINE_VIRT_MACHINE(6, 1)
3519
virt_machine_6_0_options(MachineClass * mc)3520 static void virt_machine_6_0_options(MachineClass *mc)
3521 {
3522 virt_machine_6_1_options(mc);
3523 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3524 }
3525 DEFINE_VIRT_MACHINE(6, 0)
3526
virt_machine_5_2_options(MachineClass * mc)3527 static void virt_machine_5_2_options(MachineClass *mc)
3528 {
3529 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3530
3531 virt_machine_6_0_options(mc);
3532 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3533 vmc->no_secure_gpio = true;
3534 }
3535 DEFINE_VIRT_MACHINE(5, 2)
3536
virt_machine_5_1_options(MachineClass * mc)3537 static void virt_machine_5_1_options(MachineClass *mc)
3538 {
3539 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3540
3541 virt_machine_5_2_options(mc);
3542 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3543 vmc->no_kvm_steal_time = true;
3544 }
3545 DEFINE_VIRT_MACHINE(5, 1)
3546
virt_machine_5_0_options(MachineClass * mc)3547 static void virt_machine_5_0_options(MachineClass *mc)
3548 {
3549 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3550
3551 virt_machine_5_1_options(mc);
3552 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3553 mc->numa_mem_supported = true;
3554 vmc->acpi_expose_flash = true;
3555 mc->auto_enable_numa_with_memdev = false;
3556 }
3557 DEFINE_VIRT_MACHINE(5, 0)
3558
virt_machine_4_2_options(MachineClass * mc)3559 static void virt_machine_4_2_options(MachineClass *mc)
3560 {
3561 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3562
3563 virt_machine_5_0_options(mc);
3564 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3565 vmc->kvm_no_adjvtime = true;
3566 }
3567 DEFINE_VIRT_MACHINE(4, 2)
3568
virt_machine_4_1_options(MachineClass * mc)3569 static void virt_machine_4_1_options(MachineClass *mc)
3570 {
3571 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3572
3573 virt_machine_4_2_options(mc);
3574 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3575 vmc->no_ged = true;
3576 mc->auto_enable_numa_with_memhp = false;
3577 }
3578 DEFINE_VIRT_MACHINE(4, 1)
3579
virt_machine_4_0_options(MachineClass * mc)3580 static void virt_machine_4_0_options(MachineClass *mc)
3581 {
3582 virt_machine_4_1_options(mc);
3583 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
3584 }
3585 DEFINE_VIRT_MACHINE(4, 0)
3586
virt_machine_3_1_options(MachineClass * mc)3587 static void virt_machine_3_1_options(MachineClass *mc)
3588 {
3589 virt_machine_4_0_options(mc);
3590 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
3591 }
3592 DEFINE_VIRT_MACHINE(3, 1)
3593
virt_machine_3_0_options(MachineClass * mc)3594 static void virt_machine_3_0_options(MachineClass *mc)
3595 {
3596 virt_machine_3_1_options(mc);
3597 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
3598 }
3599 DEFINE_VIRT_MACHINE(3, 0)
3600
virt_machine_2_12_options(MachineClass * mc)3601 static void virt_machine_2_12_options(MachineClass *mc)
3602 {
3603 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3604
3605 virt_machine_3_0_options(mc);
3606 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
3607 vmc->no_highmem_ecam = true;
3608 mc->max_cpus = 255;
3609 }
3610 DEFINE_VIRT_MACHINE(2, 12)
3611
virt_machine_2_11_options(MachineClass * mc)3612 static void virt_machine_2_11_options(MachineClass *mc)
3613 {
3614 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3615
3616 virt_machine_2_12_options(mc);
3617 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
3618 vmc->smbios_old_sys_ver = true;
3619 }
3620 DEFINE_VIRT_MACHINE(2, 11)
3621
virt_machine_2_10_options(MachineClass * mc)3622 static void virt_machine_2_10_options(MachineClass *mc)
3623 {
3624 virt_machine_2_11_options(mc);
3625 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
3626 /* before 2.11 we never faulted accesses to bad addresses */
3627 mc->ignore_memory_transaction_failures = true;
3628 }
3629 DEFINE_VIRT_MACHINE(2, 10)
3630
virt_machine_2_9_options(MachineClass * mc)3631 static void virt_machine_2_9_options(MachineClass *mc)
3632 {
3633 virt_machine_2_10_options(mc);
3634 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
3635 }
3636 DEFINE_VIRT_MACHINE(2, 9)
3637
virt_machine_2_8_options(MachineClass * mc)3638 static void virt_machine_2_8_options(MachineClass *mc)
3639 {
3640 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3641
3642 virt_machine_2_9_options(mc);
3643 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3644 /* For 2.8 and earlier we falsely claimed in the DT that
3645 * our timers were edge-triggered, not level-triggered.
3646 */
3647 vmc->claim_edge_triggered_timers = true;
3648 }
3649 DEFINE_VIRT_MACHINE(2, 8)
3650
virt_machine_2_7_options(MachineClass * mc)3651 static void virt_machine_2_7_options(MachineClass *mc)
3652 {
3653 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3654
3655 virt_machine_2_8_options(mc);
3656 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3657 /* ITS was introduced with 2.8 */
3658 vmc->no_its = true;
3659 /* Stick with 1K pages for migration compatibility */
3660 mc->minimum_page_bits = 0;
3661 }
3662 DEFINE_VIRT_MACHINE(2, 7)
3663
virt_machine_2_6_options(MachineClass * mc)3664 static void virt_machine_2_6_options(MachineClass *mc)
3665 {
3666 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3667
3668 virt_machine_2_7_options(mc);
3669 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3670 vmc->disallow_affinity_adjustment = true;
3671 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3672 vmc->no_pmu = true;
3673 }
3674 DEFINE_VIRT_MACHINE(2, 6)
3675