1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/module.h>
25
26 #ifdef CONFIG_X86
27 #include <asm/hypervisor.h>
28 #endif
29
30 #include <drm/drm_drv.h>
31 #include <xen/xen.h>
32
33 #include "amdgpu.h"
34 #include "amdgpu_ras.h"
35 #include "amdgpu_reset.h"
36 #include "vi.h"
37 #include "soc15.h"
38 #include "nv.h"
39
40 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
41 do { \
42 vf2pf_info->ucode_info[ucode].id = ucode; \
43 vf2pf_info->ucode_info[ucode].version = ver; \
44 } while (0)
45
amdgpu_virt_mmio_blocked(struct amdgpu_device * adev)46 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
47 {
48 /* By now all MMIO pages except mailbox are blocked */
49 /* if blocking is enabled in hypervisor. Choose the */
50 /* SCRATCH_REG0 to test. */
51 return RREG32_NO_KIQ(0xc040) == 0xffffffff;
52 }
53
amdgpu_virt_init_setting(struct amdgpu_device * adev)54 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
55 {
56 struct drm_device *ddev = adev_to_drm(adev);
57
58 /* enable virtual display */
59 if (adev->asic_type != CHIP_ALDEBARAN &&
60 adev->asic_type != CHIP_ARCTURUS &&
61 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) {
62 if (adev->mode_info.num_crtc == 0)
63 adev->mode_info.num_crtc = 1;
64 adev->enable_virtual_display = true;
65 }
66 ddev->driver_features &= ~DRIVER_ATOMIC;
67 adev->cg_flags = 0;
68 adev->pg_flags = 0;
69
70 /* Reduce kcq number to 2 to reduce latency */
71 if (amdgpu_num_kcq == -1)
72 amdgpu_num_kcq = 2;
73 }
74
amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device * adev,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)75 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
76 uint32_t reg0, uint32_t reg1,
77 uint32_t ref, uint32_t mask)
78 {
79 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
80 struct amdgpu_ring *ring = &kiq->ring;
81 signed long r, cnt = 0;
82 unsigned long flags;
83 uint32_t seq;
84
85 if (adev->mes.ring.sched.ready) {
86 amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,
87 ref, mask);
88 return;
89 }
90
91 spin_lock_irqsave(&kiq->ring_lock, flags);
92 amdgpu_ring_alloc(ring, 32);
93 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
94 ref, mask);
95 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
96 if (r)
97 goto failed_undo;
98
99 amdgpu_ring_commit(ring);
100 spin_unlock_irqrestore(&kiq->ring_lock, flags);
101
102 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
103
104 /* don't wait anymore for IRQ context */
105 if (r < 1 && in_interrupt())
106 goto failed_kiq;
107
108 might_sleep();
109 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
110
111 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
112 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
113 }
114
115 if (cnt > MAX_KIQ_REG_TRY)
116 goto failed_kiq;
117
118 return;
119
120 failed_undo:
121 amdgpu_ring_undo(ring);
122 spin_unlock_irqrestore(&kiq->ring_lock, flags);
123 failed_kiq:
124 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);
125 }
126
127 /**
128 * amdgpu_virt_request_full_gpu() - request full gpu access
129 * @adev: amdgpu device.
130 * @init: is driver init time.
131 * When start to init/fini driver, first need to request full gpu access.
132 * Return: Zero if request success, otherwise will return error.
133 */
amdgpu_virt_request_full_gpu(struct amdgpu_device * adev,bool init)134 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
135 {
136 struct amdgpu_virt *virt = &adev->virt;
137 int r;
138
139 if (virt->ops && virt->ops->req_full_gpu) {
140 r = virt->ops->req_full_gpu(adev, init);
141 if (r) {
142 adev->no_hw_access = true;
143 return r;
144 }
145
146 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
147 }
148
149 return 0;
150 }
151
152 /**
153 * amdgpu_virt_release_full_gpu() - release full gpu access
154 * @adev: amdgpu device.
155 * @init: is driver init time.
156 * When finishing driver init/fini, need to release full gpu access.
157 * Return: Zero if release success, otherwise will returen error.
158 */
amdgpu_virt_release_full_gpu(struct amdgpu_device * adev,bool init)159 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
160 {
161 struct amdgpu_virt *virt = &adev->virt;
162 int r;
163
164 if (virt->ops && virt->ops->rel_full_gpu) {
165 r = virt->ops->rel_full_gpu(adev, init);
166 if (r)
167 return r;
168
169 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
170 }
171 return 0;
172 }
173
174 /**
175 * amdgpu_virt_reset_gpu() - reset gpu
176 * @adev: amdgpu device.
177 * Send reset command to GPU hypervisor to reset GPU that VM is using
178 * Return: Zero if reset success, otherwise will return error.
179 */
amdgpu_virt_reset_gpu(struct amdgpu_device * adev)180 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
181 {
182 struct amdgpu_virt *virt = &adev->virt;
183 int r;
184
185 if (virt->ops && virt->ops->reset_gpu) {
186 r = virt->ops->reset_gpu(adev);
187 if (r)
188 return r;
189
190 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
191 }
192
193 return 0;
194 }
195
amdgpu_virt_request_init_data(struct amdgpu_device * adev)196 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
197 {
198 struct amdgpu_virt *virt = &adev->virt;
199
200 if (virt->ops && virt->ops->req_init_data)
201 virt->ops->req_init_data(adev);
202
203 if (adev->virt.req_init_data_ver > 0)
204 DRM_INFO("host supports REQ_INIT_DATA handshake\n");
205 else
206 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");
207 }
208
209 /**
210 * amdgpu_virt_wait_reset() - wait for reset gpu completed
211 * @adev: amdgpu device.
212 * Wait for GPU reset completed.
213 * Return: Zero if reset success, otherwise will return error.
214 */
amdgpu_virt_wait_reset(struct amdgpu_device * adev)215 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
216 {
217 struct amdgpu_virt *virt = &adev->virt;
218
219 if (!virt->ops || !virt->ops->wait_reset)
220 return -EINVAL;
221
222 return virt->ops->wait_reset(adev);
223 }
224
225 /**
226 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
227 * @adev: amdgpu device.
228 * MM table is used by UVD and VCE for its initialization
229 * Return: Zero if allocate success.
230 */
amdgpu_virt_alloc_mm_table(struct amdgpu_device * adev)231 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
232 {
233 int r;
234
235 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
236 return 0;
237
238 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
239 AMDGPU_GEM_DOMAIN_VRAM |
240 AMDGPU_GEM_DOMAIN_GTT,
241 &adev->virt.mm_table.bo,
242 &adev->virt.mm_table.gpu_addr,
243 (void *)&adev->virt.mm_table.cpu_addr);
244 if (r) {
245 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
246 return r;
247 }
248
249 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
250 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
251 adev->virt.mm_table.gpu_addr,
252 adev->virt.mm_table.cpu_addr);
253 return 0;
254 }
255
256 /**
257 * amdgpu_virt_free_mm_table() - free mm table memory
258 * @adev: amdgpu device.
259 * Free MM table memory
260 */
amdgpu_virt_free_mm_table(struct amdgpu_device * adev)261 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
262 {
263 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
264 return;
265
266 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
267 &adev->virt.mm_table.gpu_addr,
268 (void *)&adev->virt.mm_table.cpu_addr);
269 adev->virt.mm_table.gpu_addr = 0;
270 }
271
272
amd_sriov_msg_checksum(void * obj,unsigned long obj_size,unsigned int key,unsigned int checksum)273 unsigned int amd_sriov_msg_checksum(void *obj,
274 unsigned long obj_size,
275 unsigned int key,
276 unsigned int checksum)
277 {
278 unsigned int ret = key;
279 unsigned long i = 0;
280 unsigned char *pos;
281
282 pos = (char *)obj;
283 /* calculate checksum */
284 for (i = 0; i < obj_size; ++i)
285 ret += *(pos + i);
286 /* minus the checksum itself */
287 pos = (char *)&checksum;
288 for (i = 0; i < sizeof(checksum); ++i)
289 ret -= *(pos + i);
290 return ret;
291 }
292
amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device * adev)293 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)
294 {
295 struct amdgpu_virt *virt = &adev->virt;
296 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data;
297 /* GPU will be marked bad on host if bp count more then 10,
298 * so alloc 512 is enough.
299 */
300 unsigned int align_space = 512;
301 void *bps = NULL;
302 struct amdgpu_bo **bps_bo = NULL;
303
304 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL);
305 if (!*data)
306 goto data_failure;
307
308 bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL);
309 if (!bps)
310 goto bps_failure;
311
312 bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL);
313 if (!bps_bo)
314 goto bps_bo_failure;
315
316 (*data)->bps = bps;
317 (*data)->bps_bo = bps_bo;
318 (*data)->count = 0;
319 (*data)->last_reserved = 0;
320
321 virt->ras_init_done = true;
322
323 return 0;
324
325 bps_bo_failure:
326 kfree(bps);
327 bps_failure:
328 kfree(*data);
329 data_failure:
330 return -ENOMEM;
331 }
332
amdgpu_virt_ras_release_bp(struct amdgpu_device * adev)333 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)
334 {
335 struct amdgpu_virt *virt = &adev->virt;
336 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
337 struct amdgpu_bo *bo;
338 int i;
339
340 if (!data)
341 return;
342
343 for (i = data->last_reserved - 1; i >= 0; i--) {
344 bo = data->bps_bo[i];
345 amdgpu_bo_free_kernel(&bo, NULL, NULL);
346 data->bps_bo[i] = bo;
347 data->last_reserved = i;
348 }
349 }
350
amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device * adev)351 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)
352 {
353 struct amdgpu_virt *virt = &adev->virt;
354 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
355
356 virt->ras_init_done = false;
357
358 if (!data)
359 return;
360
361 amdgpu_virt_ras_release_bp(adev);
362
363 kfree(data->bps);
364 kfree(data->bps_bo);
365 kfree(data);
366 virt->virt_eh_data = NULL;
367 }
368
amdgpu_virt_ras_add_bps(struct amdgpu_device * adev,struct eeprom_table_record * bps,int pages)369 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,
370 struct eeprom_table_record *bps, int pages)
371 {
372 struct amdgpu_virt *virt = &adev->virt;
373 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
374
375 if (!data)
376 return;
377
378 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
379 data->count += pages;
380 }
381
amdgpu_virt_ras_reserve_bps(struct amdgpu_device * adev)382 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
383 {
384 struct amdgpu_virt *virt = &adev->virt;
385 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
386 struct amdgpu_bo *bo = NULL;
387 uint64_t bp;
388 int i;
389
390 if (!data)
391 return;
392
393 for (i = data->last_reserved; i < data->count; i++) {
394 bp = data->bps[i].retired_page;
395
396 /* There are two cases of reserve error should be ignored:
397 * 1) a ras bad page has been allocated (used by someone);
398 * 2) a ras bad page has been reserved (duplicate error injection
399 * for one page);
400 */
401 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
402 AMDGPU_GPU_PAGE_SIZE,
403 &bo, NULL))
404 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);
405
406 data->bps_bo[i] = bo;
407 data->last_reserved = i + 1;
408 bo = NULL;
409 }
410 }
411
amdgpu_virt_ras_check_bad_page(struct amdgpu_device * adev,uint64_t retired_page)412 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
413 uint64_t retired_page)
414 {
415 struct amdgpu_virt *virt = &adev->virt;
416 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
417 int i;
418
419 if (!data)
420 return true;
421
422 for (i = 0; i < data->count; i++)
423 if (retired_page == data->bps[i].retired_page)
424 return true;
425
426 return false;
427 }
428
amdgpu_virt_add_bad_page(struct amdgpu_device * adev,uint64_t bp_block_offset,uint32_t bp_block_size)429 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
430 uint64_t bp_block_offset, uint32_t bp_block_size)
431 {
432 struct eeprom_table_record bp;
433 uint64_t retired_page;
434 uint32_t bp_idx, bp_cnt;
435 void *vram_usage_va = NULL;
436
437 if (adev->mman.fw_vram_usage_va)
438 vram_usage_va = adev->mman.fw_vram_usage_va;
439 else
440 vram_usage_va = adev->mman.drv_vram_usage_va;
441
442 if (bp_block_size) {
443 bp_cnt = bp_block_size / sizeof(uint64_t);
444 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
445 retired_page = *(uint64_t *)(vram_usage_va +
446 bp_block_offset + bp_idx * sizeof(uint64_t));
447 bp.retired_page = retired_page;
448
449 if (amdgpu_virt_ras_check_bad_page(adev, retired_page))
450 continue;
451
452 amdgpu_virt_ras_add_bps(adev, &bp, 1);
453
454 amdgpu_virt_ras_reserve_bps(adev);
455 }
456 }
457 }
458
amdgpu_virt_read_pf2vf_data(struct amdgpu_device * adev)459 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
460 {
461 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;
462 uint32_t checksum;
463 uint32_t checkval;
464
465 uint32_t i;
466 uint32_t tmp;
467
468 if (adev->virt.fw_reserve.p_pf2vf == NULL)
469 return -EINVAL;
470
471 if (pf2vf_info->size > 1024) {
472 dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info->size);
473 return -EINVAL;
474 }
475
476 switch (pf2vf_info->version) {
477 case 1:
478 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum;
479 checkval = amd_sriov_msg_checksum(
480 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
481 adev->virt.fw_reserve.checksum_key, checksum);
482 if (checksum != checkval) {
483 dev_err(adev->dev,
484 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n",
485 checksum, checkval);
486 return -EINVAL;
487 }
488
489 adev->virt.gim_feature =
490 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags;
491 break;
492 case 2:
493 /* TODO: missing key, need to add it later */
494 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum;
495 checkval = amd_sriov_msg_checksum(
496 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
497 0, checksum);
498 if (checksum != checkval) {
499 dev_err(adev->dev,
500 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n",
501 checksum, checkval);
502 return -EINVAL;
503 }
504
505 adev->virt.vf2pf_update_interval_ms =
506 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms;
507 adev->virt.gim_feature =
508 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all;
509 adev->virt.reg_access =
510 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all;
511
512 adev->virt.decode_max_dimension_pixels = 0;
513 adev->virt.decode_max_frame_pixels = 0;
514 adev->virt.encode_max_dimension_pixels = 0;
515 adev->virt.encode_max_frame_pixels = 0;
516 adev->virt.is_mm_bw_enabled = false;
517 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) {
518 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels;
519 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);
520
521 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels;
522 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);
523
524 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels;
525 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);
526
527 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels;
528 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);
529 }
530 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))
531 adev->virt.is_mm_bw_enabled = true;
532
533 adev->unique_id =
534 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid;
535 break;
536 default:
537 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version);
538 return -EINVAL;
539 }
540
541 /* correct too large or too little interval value */
542 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)
543 adev->virt.vf2pf_update_interval_ms = 2000;
544
545 return 0;
546 }
547
amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device * adev)548 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)
549 {
550 struct amd_sriov_msg_vf2pf_info *vf2pf_info;
551 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
552
553 if (adev->virt.fw_reserve.p_vf2pf == NULL)
554 return;
555
556 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version);
557 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version);
558 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version);
559 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version);
560 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version);
561 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version);
562 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version);
563 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);
564 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);
565 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
566 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version);
567 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version);
568 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version);
569 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD,
570 adev->psp.asd_context.bin_desc.fw_version);
571 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS,
572 adev->psp.ras_context.context.bin_desc.fw_version);
573 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI,
574 adev->psp.xgmi_context.context.bin_desc.fw_version);
575 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version);
576 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version);
577 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version);
578 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version);
579 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version);
580 }
581
amdgpu_virt_write_vf2pf_data(struct amdgpu_device * adev)582 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)
583 {
584 struct amd_sriov_msg_vf2pf_info *vf2pf_info;
585
586 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
587
588 if (adev->virt.fw_reserve.p_vf2pf == NULL)
589 return -EINVAL;
590
591 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info));
592
593 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info);
594 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER;
595
596 #ifdef MODULE
597 if (THIS_MODULE->version != NULL)
598 strcpy(vf2pf_info->driver_version, THIS_MODULE->version);
599 else
600 #endif
601 strcpy(vf2pf_info->driver_version, "N/A");
602
603 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all
604 vf2pf_info->driver_cert = 0;
605 vf2pf_info->os_info.all = 0;
606
607 vf2pf_info->fb_usage =
608 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20;
609 vf2pf_info->fb_vis_usage =
610 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20;
611 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;
612 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;
613
614 amdgpu_virt_populate_vf2pf_ucode_info(adev);
615
616 /* TODO: read dynamic info */
617 vf2pf_info->gfx_usage = 0;
618 vf2pf_info->compute_usage = 0;
619 vf2pf_info->encode_usage = 0;
620 vf2pf_info->decode_usage = 0;
621
622 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr;
623 vf2pf_info->checksum =
624 amd_sriov_msg_checksum(
625 vf2pf_info, sizeof(*vf2pf_info), 0, 0);
626
627 return 0;
628 }
629
amdgpu_virt_update_vf2pf_work_item(struct work_struct * work)630 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
631 {
632 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);
633 int ret;
634
635 ret = amdgpu_virt_read_pf2vf_data(adev);
636 if (ret) {
637 adev->virt.vf2pf_update_retry_cnt++;
638 if ((adev->virt.vf2pf_update_retry_cnt >= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) &&
639 amdgpu_sriov_runtime(adev) && !amdgpu_in_reset(adev)) {
640 if (amdgpu_reset_domain_schedule(adev->reset_domain,
641 &adev->virt.flr_work))
642 return;
643 else
644 dev_err(adev->dev, "Failed to queue work! at %s", __func__);
645 }
646
647 goto out;
648 }
649
650 adev->virt.vf2pf_update_retry_cnt = 0;
651 amdgpu_virt_write_vf2pf_data(adev);
652
653 out:
654 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
655 }
656
amdgpu_virt_fini_data_exchange(struct amdgpu_device * adev)657 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)
658 {
659 if (adev->virt.vf2pf_update_interval_ms != 0) {
660 DRM_INFO("clean up the vf2pf work item\n");
661 cancel_delayed_work_sync(&adev->virt.vf2pf_work);
662 adev->virt.vf2pf_update_interval_ms = 0;
663 }
664 }
665
amdgpu_virt_init_data_exchange(struct amdgpu_device * adev)666 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
667 {
668 adev->virt.fw_reserve.p_pf2vf = NULL;
669 adev->virt.fw_reserve.p_vf2pf = NULL;
670 adev->virt.vf2pf_update_interval_ms = 0;
671 adev->virt.vf2pf_update_retry_cnt = 0;
672
673 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) {
674 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!");
675 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {
676 /* go through this logic in ip_init and reset to init workqueue*/
677 amdgpu_virt_exchange_data(adev);
678
679 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
680 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));
681 } else if (adev->bios != NULL) {
682 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/
683 adev->virt.fw_reserve.p_pf2vf =
684 (struct amd_sriov_msg_pf2vf_info_header *)
685 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
686
687 amdgpu_virt_read_pf2vf_data(adev);
688 }
689 }
690
691
amdgpu_virt_exchange_data(struct amdgpu_device * adev)692 void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
693 {
694 uint64_t bp_block_offset = 0;
695 uint32_t bp_block_size = 0;
696 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
697
698 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {
699 if (adev->mman.fw_vram_usage_va) {
700 adev->virt.fw_reserve.p_pf2vf =
701 (struct amd_sriov_msg_pf2vf_info_header *)
702 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
703 adev->virt.fw_reserve.p_vf2pf =
704 (struct amd_sriov_msg_vf2pf_info_header *)
705 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
706 } else if (adev->mman.drv_vram_usage_va) {
707 adev->virt.fw_reserve.p_pf2vf =
708 (struct amd_sriov_msg_pf2vf_info_header *)
709 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
710 adev->virt.fw_reserve.p_vf2pf =
711 (struct amd_sriov_msg_vf2pf_info_header *)
712 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
713 }
714
715 amdgpu_virt_read_pf2vf_data(adev);
716 amdgpu_virt_write_vf2pf_data(adev);
717
718 /* bad page handling for version 2 */
719 if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
720 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;
721
722 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) |
723 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000);
724 bp_block_size = pf2vf_v2->bp_block_size;
725
726 if (bp_block_size && !adev->virt.ras_init_done)
727 amdgpu_virt_init_ras_err_handler_data(adev);
728
729 if (adev->virt.ras_init_done)
730 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
731 }
732 }
733 }
734
amdgpu_detect_virtualization(struct amdgpu_device * adev)735 void amdgpu_detect_virtualization(struct amdgpu_device *adev)
736 {
737 uint32_t reg;
738
739 switch (adev->asic_type) {
740 case CHIP_TONGA:
741 case CHIP_FIJI:
742 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
743 break;
744 case CHIP_VEGA10:
745 case CHIP_VEGA20:
746 case CHIP_NAVI10:
747 case CHIP_NAVI12:
748 case CHIP_SIENNA_CICHLID:
749 case CHIP_ARCTURUS:
750 case CHIP_ALDEBARAN:
751 case CHIP_IP_DISCOVERY:
752 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
753 break;
754 default: /* other chip doesn't support SRIOV */
755 reg = 0;
756 break;
757 }
758
759 if (reg & 1)
760 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
761
762 if (reg & 0x80000000)
763 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
764
765 if (!reg) {
766 /* passthrough mode exclus sriov mod */
767 if (is_virtual_machine() && !xen_initial_domain())
768 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
769 }
770
771 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
772 /* VF MMIO access (except mailbox range) from CPU
773 * will be blocked during sriov runtime
774 */
775 adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;
776
777 /* we have the ability to check now */
778 if (amdgpu_sriov_vf(adev)) {
779 switch (adev->asic_type) {
780 case CHIP_TONGA:
781 case CHIP_FIJI:
782 vi_set_virt_ops(adev);
783 break;
784 case CHIP_VEGA10:
785 soc15_set_virt_ops(adev);
786 #ifdef CONFIG_X86
787 /* not send GPU_INIT_DATA with MS_HYPERV*/
788 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV))
789 #endif
790 /* send a dummy GPU_INIT_DATA request to host on vega10 */
791 amdgpu_virt_request_init_data(adev);
792 break;
793 case CHIP_VEGA20:
794 case CHIP_ARCTURUS:
795 case CHIP_ALDEBARAN:
796 soc15_set_virt_ops(adev);
797 break;
798 case CHIP_NAVI10:
799 case CHIP_NAVI12:
800 case CHIP_SIENNA_CICHLID:
801 case CHIP_IP_DISCOVERY:
802 nv_set_virt_ops(adev);
803 /* try send GPU_INIT_DATA request to host */
804 amdgpu_virt_request_init_data(adev);
805 break;
806 default: /* other chip doesn't support SRIOV */
807 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type);
808 break;
809 }
810 }
811 }
812
amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device * adev)813 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
814 {
815 return amdgpu_sriov_is_debug(adev) ? true : false;
816 }
817
amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device * adev)818 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
819 {
820 return amdgpu_sriov_is_normal(adev) ? true : false;
821 }
822
amdgpu_virt_enable_access_debugfs(struct amdgpu_device * adev)823 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
824 {
825 if (!amdgpu_sriov_vf(adev) ||
826 amdgpu_virt_access_debugfs_is_kiq(adev))
827 return 0;
828
829 if (amdgpu_virt_access_debugfs_is_mmio(adev))
830 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
831 else
832 return -EPERM;
833
834 return 0;
835 }
836
amdgpu_virt_disable_access_debugfs(struct amdgpu_device * adev)837 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)
838 {
839 if (amdgpu_sriov_vf(adev))
840 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
841 }
842
amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device * adev)843 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)
844 {
845 enum amdgpu_sriov_vf_mode mode;
846
847 if (amdgpu_sriov_vf(adev)) {
848 if (amdgpu_sriov_is_pp_one_vf(adev))
849 mode = SRIOV_VF_MODE_ONE_VF;
850 else
851 mode = SRIOV_VF_MODE_MULTI_VF;
852 } else {
853 mode = SRIOV_VF_MODE_BARE_METAL;
854 }
855
856 return mode;
857 }
858
amdgpu_virt_post_reset(struct amdgpu_device * adev)859 void amdgpu_virt_post_reset(struct amdgpu_device *adev)
860 {
861 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) {
862 /* force set to GFXOFF state after reset,
863 * to avoid some invalid operation before GC enable
864 */
865 adev->gfx.is_poweron = false;
866 }
867 }
868
amdgpu_virt_fw_load_skip_check(struct amdgpu_device * adev,uint32_t ucode_id)869 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)
870 {
871 switch (adev->ip_versions[MP0_HWIP][0]) {
872 case IP_VERSION(13, 0, 0):
873 /* no vf autoload, white list */
874 if (ucode_id == AMDGPU_UCODE_ID_VCN1 ||
875 ucode_id == AMDGPU_UCODE_ID_VCN)
876 return false;
877 else
878 return true;
879 case IP_VERSION(11, 0, 9):
880 case IP_VERSION(11, 0, 7):
881 /* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */
882 if (ucode_id == AMDGPU_UCODE_ID_RLC_G
883 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
884 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
885 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
886 || ucode_id == AMDGPU_UCODE_ID_SMC)
887 return true;
888 else
889 return false;
890 case IP_VERSION(13, 0, 10):
891 /* white list */
892 if (ucode_id == AMDGPU_UCODE_ID_CAP
893 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP
894 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME
895 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC
896 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK
897 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK
898 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK
899 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK
900 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK
901 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK
902 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK
903 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK
904 || ucode_id == AMDGPU_UCODE_ID_CP_MES
905 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA
906 || ucode_id == AMDGPU_UCODE_ID_CP_MES1
907 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA
908 || ucode_id == AMDGPU_UCODE_ID_VCN1
909 || ucode_id == AMDGPU_UCODE_ID_VCN)
910 return false;
911 else
912 return true;
913 default:
914 /* lagacy black list */
915 if (ucode_id == AMDGPU_UCODE_ID_SDMA0
916 || ucode_id == AMDGPU_UCODE_ID_SDMA1
917 || ucode_id == AMDGPU_UCODE_ID_SDMA2
918 || ucode_id == AMDGPU_UCODE_ID_SDMA3
919 || ucode_id == AMDGPU_UCODE_ID_SDMA4
920 || ucode_id == AMDGPU_UCODE_ID_SDMA5
921 || ucode_id == AMDGPU_UCODE_ID_SDMA6
922 || ucode_id == AMDGPU_UCODE_ID_SDMA7
923 || ucode_id == AMDGPU_UCODE_ID_RLC_G
924 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
925 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
926 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
927 || ucode_id == AMDGPU_UCODE_ID_SMC)
928 return true;
929 else
930 return false;
931 }
932 }
933
amdgpu_virt_update_sriov_video_codec(struct amdgpu_device * adev,struct amdgpu_video_codec_info * encode,uint32_t encode_array_size,struct amdgpu_video_codec_info * decode,uint32_t decode_array_size)934 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
935 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
936 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)
937 {
938 uint32_t i;
939
940 if (!adev->virt.is_mm_bw_enabled)
941 return;
942
943 if (encode) {
944 for (i = 0; i < encode_array_size; i++) {
945 encode[i].max_width = adev->virt.encode_max_dimension_pixels;
946 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels;
947 if (encode[i].max_width > 0)
948 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width;
949 else
950 encode[i].max_height = 0;
951 }
952 }
953
954 if (decode) {
955 for (i = 0; i < decode_array_size; i++) {
956 decode[i].max_width = adev->virt.decode_max_dimension_pixels;
957 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels;
958 if (decode[i].max_width > 0)
959 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width;
960 else
961 decode[i].max_height = 0;
962 }
963 }
964 }
965
amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device * adev,u32 acc_flags,u32 hwip,bool write,u32 * rlcg_flag)966 static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
967 u32 acc_flags, u32 hwip,
968 bool write, u32 *rlcg_flag)
969 {
970 bool ret = false;
971
972 switch (hwip) {
973 case GC_HWIP:
974 if (amdgpu_sriov_reg_indirect_gc(adev)) {
975 *rlcg_flag =
976 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ;
977 ret = true;
978 /* only in new version, AMDGPU_REGS_NO_KIQ and
979 * AMDGPU_REGS_RLC are enabled simultaneously */
980 } else if ((acc_flags & AMDGPU_REGS_RLC) &&
981 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
982 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY;
983 ret = true;
984 }
985 break;
986 case MMHUB_HWIP:
987 if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
988 (acc_flags & AMDGPU_REGS_RLC) && write) {
989 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE;
990 ret = true;
991 }
992 break;
993 default:
994 break;
995 }
996 return ret;
997 }
998
amdgpu_virt_rlcg_reg_rw(struct amdgpu_device * adev,u32 offset,u32 v,u32 flag,u32 xcc_id)999 static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)
1000 {
1001 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
1002 uint32_t timeout = 50000;
1003 uint32_t i, tmp;
1004 uint32_t ret = 0;
1005 void *scratch_reg0;
1006 void *scratch_reg1;
1007 void *scratch_reg2;
1008 void *scratch_reg3;
1009 void *spare_int;
1010
1011 if (!adev->gfx.rlc.rlcg_reg_access_supported) {
1012 dev_err(adev->dev,
1013 "indirect registers access through rlcg is not available\n");
1014 return 0;
1015 }
1016
1017 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) {
1018 dev_err(adev->dev, "invalid xcc\n");
1019 return 0;
1020 }
1021
1022 if (amdgpu_device_skip_hw_access(adev))
1023 return 0;
1024
1025 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id];
1026 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;
1027 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
1028 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
1029 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
1030
1031 mutex_lock(&adev->virt.rlcg_reg_lock);
1032
1033 if (reg_access_ctrl->spare_int)
1034 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
1035
1036 if (offset == reg_access_ctrl->grbm_cntl) {
1037 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */
1038 writel(v, scratch_reg2);
1039 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
1040 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1041 } else if (offset == reg_access_ctrl->grbm_idx) {
1042 /* if the target reg offset is grbm_idx, write to scratch_reg3 */
1043 writel(v, scratch_reg3);
1044 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
1045 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1046 } else {
1047 /*
1048 * SCRATCH_REG0 = read/write value
1049 * SCRATCH_REG1[30:28] = command
1050 * SCRATCH_REG1[19:0] = address in dword
1051 * SCRATCH_REG1[26:24] = Error reporting
1052 */
1053 writel(v, scratch_reg0);
1054 writel((offset | flag), scratch_reg1);
1055 if (reg_access_ctrl->spare_int)
1056 writel(1, spare_int);
1057
1058 for (i = 0; i < timeout; i++) {
1059 tmp = readl(scratch_reg1);
1060 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK))
1061 break;
1062 udelay(10);
1063 }
1064
1065 if (i >= timeout) {
1066 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) {
1067 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) {
1068 dev_err(adev->dev,
1069 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset);
1070 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) {
1071 dev_err(adev->dev,
1072 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset);
1073 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) {
1074 dev_err(adev->dev,
1075 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset);
1076 } else {
1077 dev_err(adev->dev,
1078 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset);
1079 }
1080 } else {
1081 dev_err(adev->dev,
1082 "timeout: rlcg faled to program reg: 0x%05x\n", offset);
1083 }
1084 }
1085 }
1086
1087 ret = readl(scratch_reg0);
1088
1089 mutex_unlock(&adev->virt.rlcg_reg_lock);
1090
1091 return ret;
1092 }
1093
amdgpu_sriov_wreg(struct amdgpu_device * adev,u32 offset,u32 value,u32 acc_flags,u32 hwip,u32 xcc_id)1094 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
1095 u32 offset, u32 value,
1096 u32 acc_flags, u32 hwip, u32 xcc_id)
1097 {
1098 u32 rlcg_flag;
1099
1100 if (amdgpu_device_skip_hw_access(adev))
1101 return;
1102
1103 if (!amdgpu_sriov_runtime(adev) &&
1104 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
1105 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id);
1106 return;
1107 }
1108
1109 if (acc_flags & AMDGPU_REGS_NO_KIQ)
1110 WREG32_NO_KIQ(offset, value);
1111 else
1112 WREG32(offset, value);
1113 }
1114
amdgpu_sriov_rreg(struct amdgpu_device * adev,u32 offset,u32 acc_flags,u32 hwip,u32 xcc_id)1115 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
1116 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id)
1117 {
1118 u32 rlcg_flag;
1119
1120 if (amdgpu_device_skip_hw_access(adev))
1121 return 0;
1122
1123 if (!amdgpu_sriov_runtime(adev) &&
1124 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
1125 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id);
1126
1127 if (acc_flags & AMDGPU_REGS_NO_KIQ)
1128 return RREG32_NO_KIQ(offset);
1129 else
1130 return RREG32(offset);
1131 }
1132