xref: /openbmc/u-boot/arch/arm/mach-davinci/include/mach/ddr2_defs.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1  /* SPDX-License-Identifier: GPL-2.0+ */
2  /*
3   * Copyright (C) 2011
4   * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5   */
6  #ifndef _DV_DDR2_DEFS_H_
7  #define _DV_DDR2_DEFS_H_
8  
9  /*
10   * DDR2 Memory Ctrl Register structure
11   * See sprueh7d.pdf for more details.
12   */
13  struct dv_ddr2_regs_ctrl {
14  	unsigned char	rsvd0[4];	/* 0x00 */
15  	unsigned int	sdrstat;	/* 0x04 */
16  	unsigned int	sdbcr;		/* 0x08 */
17  	unsigned int	sdrcr;		/* 0x0C */
18  	unsigned int	sdtimr;		/* 0x10 */
19  	unsigned int	sdtimr2;	/* 0x14 */
20  	unsigned char	rsvd1[4];	/* 0x18 */
21  	unsigned int	sdbcr2;		/* 0x1C */
22  	unsigned int	pbbpr;		/* 0x20 */
23  	unsigned char	rsvd2[156];	/* 0x24 */
24  	unsigned int	irr;		/* 0xC0 */
25  	unsigned int	imr;		/* 0xC4 */
26  	unsigned int	imsr;		/* 0xC8 */
27  	unsigned int	imcr;		/* 0xCC */
28  	unsigned char	rsvd3[20];	/* 0xD0 */
29  	unsigned int	ddrphycr;	/* 0xE4 */
30  	unsigned int	ddrphycr2;	/* 0xE8 */
31  	unsigned char	rsvd4[4];	/* 0xEC */
32  };
33  
34  #define DV_DDR_PHY_PWRDNEN		0x40
35  #define DV_DDR_PHY_EXT_STRBEN	0x80
36  #define DV_DDR_PHY_RD_LATENCY_SHIFT	0
37  
38  #define DV_DDR_SDTMR1_RFC_SHIFT	25
39  #define DV_DDR_SDTMR1_RP_SHIFT	22
40  #define DV_DDR_SDTMR1_RCD_SHIFT	19
41  #define DV_DDR_SDTMR1_WR_SHIFT	16
42  #define DV_DDR_SDTMR1_RAS_SHIFT	11
43  #define DV_DDR_SDTMR1_RC_SHIFT	6
44  #define DV_DDR_SDTMR1_RRD_SHIFT	3
45  #define DV_DDR_SDTMR1_WTR_SHIFT	0
46  
47  #define DV_DDR_SDTMR2_RASMAX_SHIFT	27
48  #define DV_DDR_SDTMR2_XP_SHIFT	25
49  #define DV_DDR_SDTMR2_ODT_SHIFT	23
50  #define DV_DDR_SDTMR2_XSNR_SHIFT	16
51  #define DV_DDR_SDTMR2_XSRD_SHIFT	8
52  #define DV_DDR_SDTMR2_RTP_SHIFT	5
53  #define DV_DDR_SDTMR2_CKE_SHIFT	0
54  
55  #define DV_DDR_SDCR_DDR2TERM1_SHIFT	27
56  #define DV_DDR_SDCR_IBANK_POS_SHIFT	26
57  #define DV_DDR_SDCR_MSDRAMEN_SHIFT	25
58  #define DV_DDR_SDCR_DDRDRIVE1_SHIFT	24
59  #define DV_DDR_SDCR_BOOTUNLOCK_SHIFT	23
60  #define DV_DDR_SDCR_DDR_DDQS_SHIFT	22
61  #define DV_DDR_SDCR_DDR2EN_SHIFT	20
62  #define DV_DDR_SDCR_DDRDRIVE0_SHIFT	18
63  #define DV_DDR_SDCR_DDREN_SHIFT	17
64  #define DV_DDR_SDCR_SDRAMEN_SHIFT	16
65  #define DV_DDR_SDCR_TIMUNLOCK_SHIFT	15
66  #define DV_DDR_SDCR_BUS_WIDTH_SHIFT	14
67  #define DV_DDR_SDCR_CL_SHIFT		9
68  #define DV_DDR_SDCR_IBANK_SHIFT	4
69  #define DV_DDR_SDCR_PAGESIZE_SHIFT	0
70  
71  #define DV_DDR_SDRCR_LPMODEN	(1 << 31)
72  #define DV_DDR_SDRCR_MCLKSTOPEN	(1 << 30)
73  
74  #define DV_DDR_SRCR_LPMODEN_SHIFT	31
75  #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT	30
76  
77  #define DV_DDR_BOOTUNLOCK	(1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
78  #define DV_DDR_TIMUNLOCK	(1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
79  
80  #define dv_ddr2_regs_ctrl \
81  	((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
82  
83  #endif /* _DV_DDR2_DEFS_H_ */
84