1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn31_resource.h"
35
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
38
39 #include "dml/dcn30/dcn30_fpu.h"
40
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn30/dcn30_hubbub.h"
43 #include "dcn31/dcn31_hubbub.h"
44 #include "dcn30/dcn30_mpc.h"
45 #include "dcn31/dcn31_hubp.h"
46 #include "irq/dcn31/irq_service_dcn31.h"
47 #include "dcn30/dcn30_dpp.h"
48 #include "dcn31/dcn31_optc.h"
49 #include "dcn20/dcn20_hwseq.h"
50 #include "dcn30/dcn30_hwseq.h"
51 #include "dce110/dce110_hw_sequencer.h"
52 #include "dcn30/dcn30_opp.h"
53 #include "dcn20/dcn20_dsc.h"
54 #include "dcn30/dcn30_vpg.h"
55 #include "dcn30/dcn30_afmt.h"
56 #include "dcn30/dcn30_dio_stream_encoder.h"
57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
59 #include "dcn31/dcn31_apg.h"
60 #include "dcn31/dcn31_dio_link_encoder.h"
61 #include "dcn31/dcn31_vpg.h"
62 #include "dcn31/dcn31_afmt.h"
63 #include "dce/dce_clock_source.h"
64 #include "dce/dce_audio.h"
65 #include "dce/dce_hwseq.h"
66 #include "clk_mgr.h"
67 #include "virtual/virtual_stream_encoder.h"
68 #include "dce110/dce110_resource.h"
69 #include "dml/display_mode_vba.h"
70 #include "dml/dcn31/dcn31_fpu.h"
71 #include "dcn31/dcn31_dccg.h"
72 #include "dcn10/dcn10_resource.h"
73 #include "dcn31_panel_cntl.h"
74
75 #include "dcn30/dcn30_dwb.h"
76 #include "dcn30/dcn30_mmhubbub.h"
77
78 // TODO: change include headers /amd/include/asic_reg after upstream
79 #include "yellow_carp_offset.h"
80 #include "dcn/dcn_3_1_2_offset.h"
81 #include "dcn/dcn_3_1_2_sh_mask.h"
82 #include "nbio/nbio_7_2_0_offset.h"
83 #include "dpcs/dpcs_4_2_0_offset.h"
84 #include "dpcs/dpcs_4_2_0_sh_mask.h"
85 #include "mmhub/mmhub_2_3_0_offset.h"
86 #include "mmhub/mmhub_2_3_0_sh_mask.h"
87
88
89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
93
94 #include "reg_helper.h"
95 #include "dce/dmub_abm.h"
96 #include "dce/dmub_psr.h"
97 #include "dce/dce_aux.h"
98 #include "dce/dce_i2c.h"
99 #include "dce/dmub_replay.h"
100
101 #include "dml/dcn30/display_mode_vba_30.h"
102 #include "vm_helper.h"
103 #include "dcn20/dcn20_vmid.h"
104
105 #include "link_enc_cfg.h"
106
107 #define DC_LOGGER_INIT(logger)
108
109 enum dcn31_clk_src_array_id {
110 DCN31_CLK_SRC_PLL0,
111 DCN31_CLK_SRC_PLL1,
112 DCN31_CLK_SRC_PLL2,
113 DCN31_CLK_SRC_PLL3,
114 DCN31_CLK_SRC_PLL4,
115 DCN30_CLK_SRC_TOTAL
116 };
117
118 /* begin *********************
119 * macros to expend register list macro defined in HW object header file
120 */
121
122 /* DCN */
123 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
124
125 #define BASE(seg) BASE_INNER(seg)
126
127 #define SR(reg_name)\
128 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
129 reg ## reg_name
130
131 #define SRI(reg_name, block, id)\
132 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
133 reg ## block ## id ## _ ## reg_name
134
135 #define SRI2(reg_name, block, id)\
136 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
137 reg ## reg_name
138
139 #define SRIR(var_name, reg_name, block, id)\
140 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 reg ## block ## id ## _ ## reg_name
142
143 #define SRII(reg_name, block, id)\
144 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
145 reg ## block ## id ## _ ## reg_name
146
147 #define SRII_MPC_RMU(reg_name, block, id)\
148 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 reg ## block ## id ## _ ## reg_name
150
151 #define SRII_DWB(reg_name, temp_name, block, id)\
152 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
153 reg ## block ## id ## _ ## temp_name
154
155 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
156 .field_name = reg_name ## __ ## field_name ## post_fix
157
158 #define DCCG_SRII(reg_name, block, id)\
159 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
160 reg ## block ## id ## _ ## reg_name
161
162 #define VUPDATE_SRII(reg_name, block, id)\
163 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
164 reg ## reg_name ## _ ## block ## id
165
166 /* NBIO */
167 #define NBIO_BASE_INNER(seg) \
168 NBIO_BASE__INST0_SEG ## seg
169
170 #define NBIO_BASE(seg) \
171 NBIO_BASE_INNER(seg)
172
173 #define NBIO_SR(reg_name)\
174 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
175 regBIF_BX1_ ## reg_name
176
177 /* MMHUB */
178 #define MMHUB_BASE_INNER(seg) \
179 MMHUB_BASE__INST0_SEG ## seg
180
181 #define MMHUB_BASE(seg) \
182 MMHUB_BASE_INNER(seg)
183
184 #define MMHUB_SR(reg_name)\
185 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
186 mm ## reg_name
187
188 /* CLOCK */
189 #define CLK_BASE_INNER(seg) \
190 CLK_BASE__INST0_SEG ## seg
191
192 #define CLK_BASE(seg) \
193 CLK_BASE_INNER(seg)
194
195 #define CLK_SRI(reg_name, block, inst)\
196 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
197 reg ## block ## _ ## inst ## _ ## reg_name
198
199
200 static const struct bios_registers bios_regs = {
201 NBIO_SR(BIOS_SCRATCH_3),
202 NBIO_SR(BIOS_SCRATCH_6)
203 };
204
205 #define clk_src_regs(index, pllid)\
206 [index] = {\
207 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
208 }
209
210 static const struct dce110_clk_src_regs clk_src_regs[] = {
211 clk_src_regs(0, A),
212 clk_src_regs(1, B),
213 clk_src_regs(2, C),
214 clk_src_regs(3, D),
215 clk_src_regs(4, E)
216 };
217 /*pll_id being rempped in dmub, in driver it is logical instance*/
218 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
219 clk_src_regs(0, A),
220 clk_src_regs(1, B),
221 clk_src_regs(2, F),
222 clk_src_regs(3, G),
223 clk_src_regs(4, E)
224 };
225
226 static const struct dce110_clk_src_shift cs_shift = {
227 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
228 };
229
230 static const struct dce110_clk_src_mask cs_mask = {
231 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
232 };
233
234 #define abm_regs(id)\
235 [id] = {\
236 ABM_DCN302_REG_LIST(id)\
237 }
238
239 static const struct dce_abm_registers abm_regs[] = {
240 abm_regs(0),
241 abm_regs(1),
242 abm_regs(2),
243 abm_regs(3),
244 };
245
246 static const struct dce_abm_shift abm_shift = {
247 ABM_MASK_SH_LIST_DCN30(__SHIFT)
248 };
249
250 static const struct dce_abm_mask abm_mask = {
251 ABM_MASK_SH_LIST_DCN30(_MASK)
252 };
253
254 #define audio_regs(id)\
255 [id] = {\
256 AUD_COMMON_REG_LIST(id)\
257 }
258
259 static const struct dce_audio_registers audio_regs[] = {
260 audio_regs(0),
261 audio_regs(1),
262 audio_regs(2),
263 audio_regs(3),
264 audio_regs(4),
265 audio_regs(5),
266 audio_regs(6)
267 };
268
269 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
270 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
271 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
272 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
273
274 static const struct dce_audio_shift audio_shift = {
275 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
276 };
277
278 static const struct dce_audio_mask audio_mask = {
279 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
280 };
281
282 #define vpg_regs(id)\
283 [id] = {\
284 VPG_DCN31_REG_LIST(id)\
285 }
286
287 static const struct dcn31_vpg_registers vpg_regs[] = {
288 vpg_regs(0),
289 vpg_regs(1),
290 vpg_regs(2),
291 vpg_regs(3),
292 vpg_regs(4),
293 vpg_regs(5),
294 vpg_regs(6),
295 vpg_regs(7),
296 vpg_regs(8),
297 vpg_regs(9),
298 };
299
300 static const struct dcn31_vpg_shift vpg_shift = {
301 DCN31_VPG_MASK_SH_LIST(__SHIFT)
302 };
303
304 static const struct dcn31_vpg_mask vpg_mask = {
305 DCN31_VPG_MASK_SH_LIST(_MASK)
306 };
307
308 #define afmt_regs(id)\
309 [id] = {\
310 AFMT_DCN31_REG_LIST(id)\
311 }
312
313 static const struct dcn31_afmt_registers afmt_regs[] = {
314 afmt_regs(0),
315 afmt_regs(1),
316 afmt_regs(2),
317 afmt_regs(3),
318 afmt_regs(4),
319 afmt_regs(5)
320 };
321
322 static const struct dcn31_afmt_shift afmt_shift = {
323 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
324 };
325
326 static const struct dcn31_afmt_mask afmt_mask = {
327 DCN31_AFMT_MASK_SH_LIST(_MASK)
328 };
329
330 #define apg_regs(id)\
331 [id] = {\
332 APG_DCN31_REG_LIST(id)\
333 }
334
335 static const struct dcn31_apg_registers apg_regs[] = {
336 apg_regs(0),
337 apg_regs(1),
338 apg_regs(2),
339 apg_regs(3)
340 };
341
342 static const struct dcn31_apg_shift apg_shift = {
343 DCN31_APG_MASK_SH_LIST(__SHIFT)
344 };
345
346 static const struct dcn31_apg_mask apg_mask = {
347 DCN31_APG_MASK_SH_LIST(_MASK)
348 };
349
350 #define stream_enc_regs(id)\
351 [id] = {\
352 SE_DCN3_REG_LIST(id)\
353 }
354
355 /* Some encoders won't be initialized here - but they're logical, not physical. */
356 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
357 stream_enc_regs(0),
358 stream_enc_regs(1),
359 stream_enc_regs(2),
360 stream_enc_regs(3),
361 stream_enc_regs(4)
362 };
363
364 static const struct dcn10_stream_encoder_shift se_shift = {
365 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
366 };
367
368 static const struct dcn10_stream_encoder_mask se_mask = {
369 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
370 };
371
372
373 #define aux_regs(id)\
374 [id] = {\
375 DCN2_AUX_REG_LIST(id)\
376 }
377
378 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
379 aux_regs(0),
380 aux_regs(1),
381 aux_regs(2),
382 aux_regs(3),
383 aux_regs(4)
384 };
385
386 #define hpd_regs(id)\
387 [id] = {\
388 HPD_REG_LIST(id)\
389 }
390
391 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
392 hpd_regs(0),
393 hpd_regs(1),
394 hpd_regs(2),
395 hpd_regs(3),
396 hpd_regs(4)
397 };
398
399 #define link_regs(id, phyid)\
400 [id] = {\
401 LE_DCN31_REG_LIST(id), \
402 UNIPHY_DCN2_REG_LIST(phyid), \
403 DPCS_DCN31_REG_LIST(id), \
404 }
405
406 static const struct dce110_aux_registers_shift aux_shift = {
407 DCN_AUX_MASK_SH_LIST(__SHIFT)
408 };
409
410 static const struct dce110_aux_registers_mask aux_mask = {
411 DCN_AUX_MASK_SH_LIST(_MASK)
412 };
413
414 static const struct dcn10_link_enc_registers link_enc_regs[] = {
415 link_regs(0, A),
416 link_regs(1, B),
417 link_regs(2, C),
418 link_regs(3, D),
419 link_regs(4, E)
420 };
421
422 static const struct dcn10_link_enc_shift le_shift = {
423 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
424 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
425 };
426
427 static const struct dcn10_link_enc_mask le_mask = {
428 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
429 DPCS_DCN31_MASK_SH_LIST(_MASK)
430 };
431
432 #define hpo_dp_stream_encoder_reg_list(id)\
433 [id] = {\
434 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
435 }
436
437 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
438 hpo_dp_stream_encoder_reg_list(0),
439 hpo_dp_stream_encoder_reg_list(1),
440 hpo_dp_stream_encoder_reg_list(2),
441 hpo_dp_stream_encoder_reg_list(3),
442 };
443
444 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
445 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
446 };
447
448 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
449 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
450 };
451
452 #define hpo_dp_link_encoder_reg_list(id)\
453 [id] = {\
454 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
455 DCN3_1_RDPCSTX_REG_LIST(0),\
456 DCN3_1_RDPCSTX_REG_LIST(1),\
457 DCN3_1_RDPCSTX_REG_LIST(2),\
458 DCN3_1_RDPCSTX_REG_LIST(3),\
459 DCN3_1_RDPCSTX_REG_LIST(4)\
460 }
461
462 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
463 hpo_dp_link_encoder_reg_list(0),
464 hpo_dp_link_encoder_reg_list(1),
465 };
466
467 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
468 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
469 };
470
471 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
472 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
473 };
474
475 #define dpp_regs(id)\
476 [id] = {\
477 DPP_REG_LIST_DCN30(id),\
478 }
479
480 static const struct dcn3_dpp_registers dpp_regs[] = {
481 dpp_regs(0),
482 dpp_regs(1),
483 dpp_regs(2),
484 dpp_regs(3)
485 };
486
487 static const struct dcn3_dpp_shift tf_shift = {
488 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
489 };
490
491 static const struct dcn3_dpp_mask tf_mask = {
492 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
493 };
494
495 #define opp_regs(id)\
496 [id] = {\
497 OPP_REG_LIST_DCN30(id),\
498 }
499
500 static const struct dcn20_opp_registers opp_regs[] = {
501 opp_regs(0),
502 opp_regs(1),
503 opp_regs(2),
504 opp_regs(3)
505 };
506
507 static const struct dcn20_opp_shift opp_shift = {
508 OPP_MASK_SH_LIST_DCN20(__SHIFT)
509 };
510
511 static const struct dcn20_opp_mask opp_mask = {
512 OPP_MASK_SH_LIST_DCN20(_MASK)
513 };
514
515 #define aux_engine_regs(id)\
516 [id] = {\
517 AUX_COMMON_REG_LIST0(id), \
518 .AUXN_IMPCAL = 0, \
519 .AUXP_IMPCAL = 0, \
520 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
521 }
522
523 static const struct dce110_aux_registers aux_engine_regs[] = {
524 aux_engine_regs(0),
525 aux_engine_regs(1),
526 aux_engine_regs(2),
527 aux_engine_regs(3),
528 aux_engine_regs(4)
529 };
530
531 #define dwbc_regs_dcn3(id)\
532 [id] = {\
533 DWBC_COMMON_REG_LIST_DCN30(id),\
534 }
535
536 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
537 dwbc_regs_dcn3(0),
538 };
539
540 static const struct dcn30_dwbc_shift dwbc30_shift = {
541 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
542 };
543
544 static const struct dcn30_dwbc_mask dwbc30_mask = {
545 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
546 };
547
548 #define mcif_wb_regs_dcn3(id)\
549 [id] = {\
550 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
551 }
552
553 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
554 mcif_wb_regs_dcn3(0)
555 };
556
557 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
558 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
559 };
560
561 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
562 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
563 };
564
565 #define dsc_regsDCN20(id)\
566 [id] = {\
567 DSC_REG_LIST_DCN20(id)\
568 }
569
570 static const struct dcn20_dsc_registers dsc_regs[] = {
571 dsc_regsDCN20(0),
572 dsc_regsDCN20(1),
573 dsc_regsDCN20(2)
574 };
575
576 static const struct dcn20_dsc_shift dsc_shift = {
577 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
578 };
579
580 static const struct dcn20_dsc_mask dsc_mask = {
581 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
582 };
583
584 static const struct dcn30_mpc_registers mpc_regs = {
585 MPC_REG_LIST_DCN3_0(0),
586 MPC_REG_LIST_DCN3_0(1),
587 MPC_REG_LIST_DCN3_0(2),
588 MPC_REG_LIST_DCN3_0(3),
589 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
590 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
591 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
592 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
593 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
594 MPC_RMU_REG_LIST_DCN3AG(0),
595 MPC_RMU_REG_LIST_DCN3AG(1),
596 //MPC_RMU_REG_LIST_DCN3AG(2),
597 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
598 };
599
600 static const struct dcn30_mpc_shift mpc_shift = {
601 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
602 };
603
604 static const struct dcn30_mpc_mask mpc_mask = {
605 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
606 };
607
608 #define optc_regs(id)\
609 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
610
611 static const struct dcn_optc_registers optc_regs[] = {
612 optc_regs(0),
613 optc_regs(1),
614 optc_regs(2),
615 optc_regs(3)
616 };
617
618 static const struct dcn_optc_shift optc_shift = {
619 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
620 };
621
622 static const struct dcn_optc_mask optc_mask = {
623 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
624 };
625
626 #define hubp_regs(id)\
627 [id] = {\
628 HUBP_REG_LIST_DCN30(id)\
629 }
630
631 static const struct dcn_hubp2_registers hubp_regs[] = {
632 hubp_regs(0),
633 hubp_regs(1),
634 hubp_regs(2),
635 hubp_regs(3)
636 };
637
638
639 static const struct dcn_hubp2_shift hubp_shift = {
640 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
641 };
642
643 static const struct dcn_hubp2_mask hubp_mask = {
644 HUBP_MASK_SH_LIST_DCN31(_MASK)
645 };
646 static const struct dcn_hubbub_registers hubbub_reg = {
647 HUBBUB_REG_LIST_DCN31(0)
648 };
649
650 static const struct dcn_hubbub_shift hubbub_shift = {
651 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
652 };
653
654 static const struct dcn_hubbub_mask hubbub_mask = {
655 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
656 };
657
658 static const struct dccg_registers dccg_regs = {
659 DCCG_REG_LIST_DCN31()
660 };
661
662 static const struct dccg_shift dccg_shift = {
663 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
664 };
665
666 static const struct dccg_mask dccg_mask = {
667 DCCG_MASK_SH_LIST_DCN31(_MASK)
668 };
669
670
671 #define SRII2(reg_name_pre, reg_name_post, id)\
672 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
673 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
674 reg ## reg_name_pre ## id ## _ ## reg_name_post
675
676
677 #define HWSEQ_DCN31_REG_LIST()\
678 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
679 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
680 SR(DIO_MEM_PWR_CTRL), \
681 SR(ODM_MEM_PWR_CTRL3), \
682 SR(DMU_MEM_PWR_CNTL), \
683 SR(MMHUBBUB_MEM_PWR_CNTL), \
684 SR(DCCG_GATE_DISABLE_CNTL), \
685 SR(DCCG_GATE_DISABLE_CNTL2), \
686 SR(DCFCLK_CNTL),\
687 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
688 SRII(PIXEL_RATE_CNTL, OTG, 0), \
689 SRII(PIXEL_RATE_CNTL, OTG, 1),\
690 SRII(PIXEL_RATE_CNTL, OTG, 2),\
691 SRII(PIXEL_RATE_CNTL, OTG, 3),\
692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
696 SR(MICROSECOND_TIME_BASE_DIV), \
697 SR(MILLISECOND_TIME_BASE_DIV), \
698 SR(DISPCLK_FREQ_CHANGE_CNTL), \
699 SR(RBBMIF_TIMEOUT_DIS), \
700 SR(RBBMIF_TIMEOUT_DIS_2), \
701 SR(DCHUBBUB_CRC_CTRL), \
702 SR(DPP_TOP0_DPP_CRC_CTRL), \
703 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
704 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
705 SR(MPC_CRC_CTRL), \
706 SR(MPC_CRC_RESULT_GB), \
707 SR(MPC_CRC_RESULT_C), \
708 SR(MPC_CRC_RESULT_AR), \
709 SR(DOMAIN0_PG_CONFIG), \
710 SR(DOMAIN1_PG_CONFIG), \
711 SR(DOMAIN2_PG_CONFIG), \
712 SR(DOMAIN3_PG_CONFIG), \
713 SR(DOMAIN16_PG_CONFIG), \
714 SR(DOMAIN17_PG_CONFIG), \
715 SR(DOMAIN18_PG_CONFIG), \
716 SR(DOMAIN0_PG_STATUS), \
717 SR(DOMAIN1_PG_STATUS), \
718 SR(DOMAIN2_PG_STATUS), \
719 SR(DOMAIN3_PG_STATUS), \
720 SR(DOMAIN16_PG_STATUS), \
721 SR(DOMAIN17_PG_STATUS), \
722 SR(DOMAIN18_PG_STATUS), \
723 SR(D1VGA_CONTROL), \
724 SR(D2VGA_CONTROL), \
725 SR(D3VGA_CONTROL), \
726 SR(D4VGA_CONTROL), \
727 SR(D5VGA_CONTROL), \
728 SR(D6VGA_CONTROL), \
729 SR(DC_IP_REQUEST_CNTL), \
730 SR(AZALIA_AUDIO_DTO), \
731 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
732 SR(HPO_TOP_HW_CONTROL)
733
734 static const struct dce_hwseq_registers hwseq_reg = {
735 HWSEQ_DCN31_REG_LIST()
736 };
737
738 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
739 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
740 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
741 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
742 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
743 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
744 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
745 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
746 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
747 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
748 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
749 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
750 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
751 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
752 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
753 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
754 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
755 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
756 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
757 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
758 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
759 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
760 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
761 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
762 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
763 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
764 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
765 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
766 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
767 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
768 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
769 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
770 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
771 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
772
773 static const struct dce_hwseq_shift hwseq_shift = {
774 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
775 };
776
777 static const struct dce_hwseq_mask hwseq_mask = {
778 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
779 };
780 #define vmid_regs(id)\
781 [id] = {\
782 DCN20_VMID_REG_LIST(id)\
783 }
784
785 static const struct dcn_vmid_registers vmid_regs[] = {
786 vmid_regs(0),
787 vmid_regs(1),
788 vmid_regs(2),
789 vmid_regs(3),
790 vmid_regs(4),
791 vmid_regs(5),
792 vmid_regs(6),
793 vmid_regs(7),
794 vmid_regs(8),
795 vmid_regs(9),
796 vmid_regs(10),
797 vmid_regs(11),
798 vmid_regs(12),
799 vmid_regs(13),
800 vmid_regs(14),
801 vmid_regs(15)
802 };
803
804 static const struct dcn20_vmid_shift vmid_shifts = {
805 DCN20_VMID_MASK_SH_LIST(__SHIFT)
806 };
807
808 static const struct dcn20_vmid_mask vmid_masks = {
809 DCN20_VMID_MASK_SH_LIST(_MASK)
810 };
811
812 static const struct resource_caps res_cap_dcn31 = {
813 .num_timing_generator = 4,
814 .num_opp = 4,
815 .num_video_plane = 4,
816 .num_audio = 5,
817 .num_stream_encoder = 5,
818 .num_dig_link_enc = 5,
819 .num_hpo_dp_stream_encoder = 4,
820 .num_hpo_dp_link_encoder = 2,
821 .num_pll = 5,
822 .num_dwb = 1,
823 .num_ddc = 5,
824 .num_vmid = 16,
825 .num_mpc_3dlut = 2,
826 .num_dsc = 3,
827 };
828
829 static const struct dc_plane_cap plane_cap = {
830 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
831 .per_pixel_alpha = true,
832
833 .pixel_format_support = {
834 .argb8888 = true,
835 .nv12 = true,
836 .fp16 = true,
837 .p010 = true,
838 .ayuv = false,
839 },
840
841 .max_upscale_factor = {
842 .argb8888 = 16000,
843 .nv12 = 16000,
844 .fp16 = 16000
845 },
846
847 // 6:1 downscaling ratio: 1000/6 = 166.666
848 .max_downscale_factor = {
849 .argb8888 = 167,
850 .nv12 = 167,
851 .fp16 = 167
852 },
853 64,
854 64
855 };
856
857 static const struct dc_debug_options debug_defaults_drv = {
858 .disable_dmcu = true,
859 .force_abm_enable = false,
860 .timing_trace = false,
861 .clock_trace = true,
862 .disable_pplib_clock_request = false,
863 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
864 .force_single_disp_pipe_split = false,
865 .disable_dcc = DCC_ENABLE,
866 .vsr_support = true,
867 .performance_trace = false,
868 .max_downscale_src_width = 4096,/*upto true 4K*/
869 .disable_pplib_wm_range = false,
870 .scl_reset_length10 = true,
871 .sanity_checks = true,
872 .underflow_assert_delay_us = 0xFFFFFFFF,
873 .dwb_fi_phase = -1, // -1 = disable,
874 .dmub_command_table = true,
875 .pstate_enabled = true,
876 .use_max_lb = true,
877 .enable_mem_low_power = {
878 .bits = {
879 .vga = true,
880 .i2c = true,
881 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
882 .dscl = true,
883 .cm = true,
884 .mpc = true,
885 .optc = true,
886 .vpg = true,
887 .afmt = true,
888 }
889 },
890 .disable_z10 = true,
891 .enable_legacy_fast_update = true,
892 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
893 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
894 };
895
896 static const struct dc_panel_config panel_config_defaults = {
897 .psr = {
898 .disable_psr = false,
899 .disallow_psrsu = false,
900 .disallow_replay = false,
901 },
902 .ilr = {
903 .optimize_edp_link_rate = true,
904 },
905 };
906
dcn31_dpp_destroy(struct dpp ** dpp)907 static void dcn31_dpp_destroy(struct dpp **dpp)
908 {
909 kfree(TO_DCN20_DPP(*dpp));
910 *dpp = NULL;
911 }
912
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)913 static struct dpp *dcn31_dpp_create(
914 struct dc_context *ctx,
915 uint32_t inst)
916 {
917 struct dcn3_dpp *dpp =
918 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
919
920 if (!dpp)
921 return NULL;
922
923 if (dpp3_construct(dpp, ctx, inst,
924 &dpp_regs[inst], &tf_shift, &tf_mask))
925 return &dpp->base;
926
927 BREAK_TO_DEBUGGER();
928 kfree(dpp);
929 return NULL;
930 }
931
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)932 static struct output_pixel_processor *dcn31_opp_create(
933 struct dc_context *ctx, uint32_t inst)
934 {
935 struct dcn20_opp *opp =
936 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
937
938 if (!opp) {
939 BREAK_TO_DEBUGGER();
940 return NULL;
941 }
942
943 dcn20_opp_construct(opp, ctx, inst,
944 &opp_regs[inst], &opp_shift, &opp_mask);
945 return &opp->base;
946 }
947
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)948 static struct dce_aux *dcn31_aux_engine_create(
949 struct dc_context *ctx,
950 uint32_t inst)
951 {
952 struct aux_engine_dce110 *aux_engine =
953 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
954
955 if (!aux_engine)
956 return NULL;
957
958 dce110_aux_engine_construct(aux_engine, ctx, inst,
959 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
960 &aux_engine_regs[inst],
961 &aux_mask,
962 &aux_shift,
963 ctx->dc->caps.extended_aux_timeout_support);
964
965 return &aux_engine->base;
966 }
967 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
968
969 static const struct dce_i2c_registers i2c_hw_regs[] = {
970 i2c_inst_regs(1),
971 i2c_inst_regs(2),
972 i2c_inst_regs(3),
973 i2c_inst_regs(4),
974 i2c_inst_regs(5),
975 };
976
977 static const struct dce_i2c_shift i2c_shifts = {
978 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
979 };
980
981 static const struct dce_i2c_mask i2c_masks = {
982 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
983 };
984
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)985 static struct dce_i2c_hw *dcn31_i2c_hw_create(
986 struct dc_context *ctx,
987 uint32_t inst)
988 {
989 struct dce_i2c_hw *dce_i2c_hw =
990 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
991
992 if (!dce_i2c_hw)
993 return NULL;
994
995 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
996 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
997
998 return dce_i2c_hw;
999 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1000 static struct mpc *dcn31_mpc_create(
1001 struct dc_context *ctx,
1002 int num_mpcc,
1003 int num_rmu)
1004 {
1005 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1006 GFP_KERNEL);
1007
1008 if (!mpc30)
1009 return NULL;
1010
1011 dcn30_mpc_construct(mpc30, ctx,
1012 &mpc_regs,
1013 &mpc_shift,
1014 &mpc_mask,
1015 num_mpcc,
1016 num_rmu);
1017
1018 return &mpc30->base;
1019 }
1020
dcn31_hubbub_create(struct dc_context * ctx)1021 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1022 {
1023 int i;
1024
1025 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1026 GFP_KERNEL);
1027
1028 if (!hubbub3)
1029 return NULL;
1030
1031 hubbub31_construct(hubbub3, ctx,
1032 &hubbub_reg,
1033 &hubbub_shift,
1034 &hubbub_mask,
1035 dcn3_1_ip.det_buffer_size_kbytes,
1036 dcn3_1_ip.pixel_chunk_size_kbytes,
1037 dcn3_1_ip.config_return_buffer_size_in_kbytes);
1038
1039
1040 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1041 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1042
1043 vmid->ctx = ctx;
1044
1045 vmid->regs = &vmid_regs[i];
1046 vmid->shifts = &vmid_shifts;
1047 vmid->masks = &vmid_masks;
1048 }
1049
1050 return &hubbub3->base;
1051 }
1052
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1053 static struct timing_generator *dcn31_timing_generator_create(
1054 struct dc_context *ctx,
1055 uint32_t instance)
1056 {
1057 struct optc *tgn10 =
1058 kzalloc(sizeof(struct optc), GFP_KERNEL);
1059
1060 if (!tgn10)
1061 return NULL;
1062
1063 tgn10->base.inst = instance;
1064 tgn10->base.ctx = ctx;
1065
1066 tgn10->tg_regs = &optc_regs[instance];
1067 tgn10->tg_shift = &optc_shift;
1068 tgn10->tg_mask = &optc_mask;
1069
1070 dcn31_timing_generator_init(tgn10);
1071
1072 return &tgn10->base;
1073 }
1074
1075 static const struct encoder_feature_support link_enc_feature = {
1076 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1077 .max_hdmi_pixel_clock = 600000,
1078 .hdmi_ycbcr420_supported = true,
1079 .dp_ycbcr420_supported = true,
1080 .fec_supported = true,
1081 .flags.bits.IS_HBR2_CAPABLE = true,
1082 .flags.bits.IS_HBR3_CAPABLE = true,
1083 .flags.bits.IS_TPS3_CAPABLE = true,
1084 .flags.bits.IS_TPS4_CAPABLE = true
1085 };
1086
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1087 static struct link_encoder *dcn31_link_encoder_create(
1088 struct dc_context *ctx,
1089 const struct encoder_init_data *enc_init_data)
1090 {
1091 struct dcn20_link_encoder *enc20 =
1092 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1093
1094 if (!enc20)
1095 return NULL;
1096
1097 dcn31_link_encoder_construct(enc20,
1098 enc_init_data,
1099 &link_enc_feature,
1100 &link_enc_regs[enc_init_data->transmitter],
1101 &link_enc_aux_regs[enc_init_data->channel - 1],
1102 &link_enc_hpd_regs[enc_init_data->hpd_source],
1103 &le_shift,
1104 &le_mask);
1105
1106 return &enc20->enc10.base;
1107 }
1108
1109 /* Create a minimal link encoder object not associated with a particular
1110 * physical connector.
1111 * resource_funcs.link_enc_create_minimal
1112 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1113 static struct link_encoder *dcn31_link_enc_create_minimal(
1114 struct dc_context *ctx, enum engine_id eng_id)
1115 {
1116 struct dcn20_link_encoder *enc20;
1117
1118 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1119 return NULL;
1120
1121 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1122 if (!enc20)
1123 return NULL;
1124
1125 dcn31_link_encoder_construct_minimal(
1126 enc20,
1127 ctx,
1128 &link_enc_feature,
1129 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1130 eng_id);
1131
1132 return &enc20->enc10.base;
1133 }
1134
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1135 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1136 {
1137 struct dcn31_panel_cntl *panel_cntl =
1138 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1139
1140 if (!panel_cntl)
1141 return NULL;
1142
1143 dcn31_panel_cntl_construct(panel_cntl, init_data);
1144
1145 return &panel_cntl->base;
1146 }
1147
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1148 static void read_dce_straps(
1149 struct dc_context *ctx,
1150 struct resource_straps *straps)
1151 {
1152 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1153 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1154
1155 }
1156
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1157 static struct audio *dcn31_create_audio(
1158 struct dc_context *ctx, unsigned int inst)
1159 {
1160 return dce_audio_create(ctx, inst,
1161 &audio_regs[inst], &audio_shift, &audio_mask);
1162 }
1163
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1164 static struct vpg *dcn31_vpg_create(
1165 struct dc_context *ctx,
1166 uint32_t inst)
1167 {
1168 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1169
1170 if (!vpg31)
1171 return NULL;
1172
1173 vpg31_construct(vpg31, ctx, inst,
1174 &vpg_regs[inst],
1175 &vpg_shift,
1176 &vpg_mask);
1177
1178 return &vpg31->base;
1179 }
1180
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1181 static struct afmt *dcn31_afmt_create(
1182 struct dc_context *ctx,
1183 uint32_t inst)
1184 {
1185 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1186
1187 if (!afmt31)
1188 return NULL;
1189
1190 afmt31_construct(afmt31, ctx, inst,
1191 &afmt_regs[inst],
1192 &afmt_shift,
1193 &afmt_mask);
1194
1195 // Light sleep by default, no need to power down here
1196
1197 return &afmt31->base;
1198 }
1199
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1200 static struct apg *dcn31_apg_create(
1201 struct dc_context *ctx,
1202 uint32_t inst)
1203 {
1204 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1205
1206 if (!apg31)
1207 return NULL;
1208
1209 apg31_construct(apg31, ctx, inst,
1210 &apg_regs[inst],
1211 &apg_shift,
1212 &apg_mask);
1213
1214 return &apg31->base;
1215 }
1216
dcn31_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1217 static struct stream_encoder *dcn31_stream_encoder_create(
1218 enum engine_id eng_id,
1219 struct dc_context *ctx)
1220 {
1221 struct dcn10_stream_encoder *enc1;
1222 struct vpg *vpg;
1223 struct afmt *afmt;
1224 int vpg_inst;
1225 int afmt_inst;
1226
1227 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1228 if (eng_id <= ENGINE_ID_DIGF) {
1229 vpg_inst = eng_id;
1230 afmt_inst = eng_id;
1231 } else
1232 return NULL;
1233
1234 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1235 vpg = dcn31_vpg_create(ctx, vpg_inst);
1236 afmt = dcn31_afmt_create(ctx, afmt_inst);
1237
1238 if (!enc1 || !vpg || !afmt) {
1239 kfree(enc1);
1240 kfree(vpg);
1241 kfree(afmt);
1242 return NULL;
1243 }
1244
1245 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1246 eng_id, vpg, afmt,
1247 &stream_enc_regs[eng_id],
1248 &se_shift, &se_mask);
1249
1250 return &enc1->base;
1251 }
1252
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1253 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1254 enum engine_id eng_id,
1255 struct dc_context *ctx)
1256 {
1257 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1258 struct vpg *vpg;
1259 struct apg *apg;
1260 uint32_t hpo_dp_inst;
1261 uint32_t vpg_inst;
1262 uint32_t apg_inst;
1263
1264 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1265 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1266
1267 /* Mapping of VPG register blocks to HPO DP block instance:
1268 * VPG[6] -> HPO_DP[0]
1269 * VPG[7] -> HPO_DP[1]
1270 * VPG[8] -> HPO_DP[2]
1271 * VPG[9] -> HPO_DP[3]
1272 */
1273 vpg_inst = hpo_dp_inst + 6;
1274
1275 /* Mapping of APG register blocks to HPO DP block instance:
1276 * APG[0] -> HPO_DP[0]
1277 * APG[1] -> HPO_DP[1]
1278 * APG[2] -> HPO_DP[2]
1279 * APG[3] -> HPO_DP[3]
1280 */
1281 apg_inst = hpo_dp_inst;
1282
1283 /* allocate HPO stream encoder and create VPG sub-block */
1284 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1285 vpg = dcn31_vpg_create(ctx, vpg_inst);
1286 apg = dcn31_apg_create(ctx, apg_inst);
1287
1288 if (!hpo_dp_enc31 || !vpg || !apg) {
1289 kfree(hpo_dp_enc31);
1290 kfree(vpg);
1291 kfree(apg);
1292 return NULL;
1293 }
1294
1295 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1296 hpo_dp_inst, eng_id, vpg, apg,
1297 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1298 &hpo_dp_se_shift, &hpo_dp_se_mask);
1299
1300 return &hpo_dp_enc31->base;
1301 }
1302
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1303 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1304 uint8_t inst,
1305 struct dc_context *ctx)
1306 {
1307 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1308
1309 /* allocate HPO link encoder */
1310 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1311 if (!hpo_dp_enc31)
1312 return NULL; /* out of memory */
1313
1314 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1315 &hpo_dp_link_enc_regs[inst],
1316 &hpo_dp_le_shift, &hpo_dp_le_mask);
1317
1318 return &hpo_dp_enc31->base;
1319 }
1320
dcn31_hwseq_create(struct dc_context * ctx)1321 static struct dce_hwseq *dcn31_hwseq_create(
1322 struct dc_context *ctx)
1323 {
1324 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1325
1326 if (hws) {
1327 hws->ctx = ctx;
1328 hws->regs = &hwseq_reg;
1329 hws->shifts = &hwseq_shift;
1330 hws->masks = &hwseq_mask;
1331 }
1332 return hws;
1333 }
1334 static const struct resource_create_funcs res_create_funcs = {
1335 .read_dce_straps = read_dce_straps,
1336 .create_audio = dcn31_create_audio,
1337 .create_stream_encoder = dcn31_stream_encoder_create,
1338 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1339 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1340 .create_hwseq = dcn31_hwseq_create,
1341 };
1342
dcn31_resource_destruct(struct dcn31_resource_pool * pool)1343 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1344 {
1345 unsigned int i;
1346
1347 for (i = 0; i < pool->base.stream_enc_count; i++) {
1348 if (pool->base.stream_enc[i] != NULL) {
1349 if (pool->base.stream_enc[i]->vpg != NULL) {
1350 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1351 pool->base.stream_enc[i]->vpg = NULL;
1352 }
1353 if (pool->base.stream_enc[i]->afmt != NULL) {
1354 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1355 pool->base.stream_enc[i]->afmt = NULL;
1356 }
1357 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1358 pool->base.stream_enc[i] = NULL;
1359 }
1360 }
1361
1362 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1363 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1364 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1365 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1366 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1367 }
1368 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1369 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1370 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1371 }
1372 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1373 pool->base.hpo_dp_stream_enc[i] = NULL;
1374 }
1375 }
1376
1377 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1378 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1379 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1380 pool->base.hpo_dp_link_enc[i] = NULL;
1381 }
1382 }
1383
1384 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1385 if (pool->base.dscs[i] != NULL)
1386 dcn20_dsc_destroy(&pool->base.dscs[i]);
1387 }
1388
1389 if (pool->base.mpc != NULL) {
1390 kfree(TO_DCN20_MPC(pool->base.mpc));
1391 pool->base.mpc = NULL;
1392 }
1393 if (pool->base.hubbub != NULL) {
1394 kfree(pool->base.hubbub);
1395 pool->base.hubbub = NULL;
1396 }
1397 for (i = 0; i < pool->base.pipe_count; i++) {
1398 if (pool->base.dpps[i] != NULL)
1399 dcn31_dpp_destroy(&pool->base.dpps[i]);
1400
1401 if (pool->base.ipps[i] != NULL)
1402 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1403
1404 if (pool->base.hubps[i] != NULL) {
1405 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1406 pool->base.hubps[i] = NULL;
1407 }
1408
1409 if (pool->base.irqs != NULL) {
1410 dal_irq_service_destroy(&pool->base.irqs);
1411 }
1412 }
1413
1414 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1415 if (pool->base.engines[i] != NULL)
1416 dce110_engine_destroy(&pool->base.engines[i]);
1417 if (pool->base.hw_i2cs[i] != NULL) {
1418 kfree(pool->base.hw_i2cs[i]);
1419 pool->base.hw_i2cs[i] = NULL;
1420 }
1421 if (pool->base.sw_i2cs[i] != NULL) {
1422 kfree(pool->base.sw_i2cs[i]);
1423 pool->base.sw_i2cs[i] = NULL;
1424 }
1425 }
1426
1427 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1428 if (pool->base.opps[i] != NULL)
1429 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1430 }
1431
1432 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1433 if (pool->base.timing_generators[i] != NULL) {
1434 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1435 pool->base.timing_generators[i] = NULL;
1436 }
1437 }
1438
1439 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1440 if (pool->base.dwbc[i] != NULL) {
1441 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1442 pool->base.dwbc[i] = NULL;
1443 }
1444 if (pool->base.mcif_wb[i] != NULL) {
1445 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1446 pool->base.mcif_wb[i] = NULL;
1447 }
1448 }
1449
1450 for (i = 0; i < pool->base.audio_count; i++) {
1451 if (pool->base.audios[i])
1452 dce_aud_destroy(&pool->base.audios[i]);
1453 }
1454
1455 for (i = 0; i < pool->base.clk_src_count; i++) {
1456 if (pool->base.clock_sources[i] != NULL) {
1457 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1458 pool->base.clock_sources[i] = NULL;
1459 }
1460 }
1461
1462 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1463 if (pool->base.mpc_lut[i] != NULL) {
1464 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1465 pool->base.mpc_lut[i] = NULL;
1466 }
1467 if (pool->base.mpc_shaper[i] != NULL) {
1468 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1469 pool->base.mpc_shaper[i] = NULL;
1470 }
1471 }
1472
1473 if (pool->base.dp_clock_source != NULL) {
1474 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1475 pool->base.dp_clock_source = NULL;
1476 }
1477
1478 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1479 if (pool->base.multiple_abms[i] != NULL)
1480 dce_abm_destroy(&pool->base.multiple_abms[i]);
1481 }
1482
1483 if (pool->base.psr != NULL)
1484 dmub_psr_destroy(&pool->base.psr);
1485
1486 if (pool->base.replay != NULL)
1487 dmub_replay_destroy(&pool->base.replay);
1488
1489 if (pool->base.dccg != NULL)
1490 dcn_dccg_destroy(&pool->base.dccg);
1491 }
1492
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1493 static struct hubp *dcn31_hubp_create(
1494 struct dc_context *ctx,
1495 uint32_t inst)
1496 {
1497 struct dcn20_hubp *hubp2 =
1498 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1499
1500 if (!hubp2)
1501 return NULL;
1502
1503 if (hubp31_construct(hubp2, ctx, inst,
1504 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1505 return &hubp2->base;
1506
1507 BREAK_TO_DEBUGGER();
1508 kfree(hubp2);
1509 return NULL;
1510 }
1511
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1512 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1513 {
1514 int i;
1515 uint32_t pipe_count = pool->res_cap->num_dwb;
1516
1517 for (i = 0; i < pipe_count; i++) {
1518 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1519 GFP_KERNEL);
1520
1521 if (!dwbc30) {
1522 dm_error("DC: failed to create dwbc30!\n");
1523 return false;
1524 }
1525
1526 dcn30_dwbc_construct(dwbc30, ctx,
1527 &dwbc30_regs[i],
1528 &dwbc30_shift,
1529 &dwbc30_mask,
1530 i);
1531
1532 pool->dwbc[i] = &dwbc30->base;
1533 }
1534 return true;
1535 }
1536
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1537 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1538 {
1539 int i;
1540 uint32_t pipe_count = pool->res_cap->num_dwb;
1541
1542 for (i = 0; i < pipe_count; i++) {
1543 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1544 GFP_KERNEL);
1545
1546 if (!mcif_wb30) {
1547 dm_error("DC: failed to create mcif_wb30!\n");
1548 return false;
1549 }
1550
1551 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1552 &mcif_wb30_regs[i],
1553 &mcif_wb30_shift,
1554 &mcif_wb30_mask,
1555 i);
1556
1557 pool->mcif_wb[i] = &mcif_wb30->base;
1558 }
1559 return true;
1560 }
1561
dcn31_dsc_create(struct dc_context * ctx,uint32_t inst)1562 static struct display_stream_compressor *dcn31_dsc_create(
1563 struct dc_context *ctx, uint32_t inst)
1564 {
1565 struct dcn20_dsc *dsc =
1566 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1567
1568 if (!dsc) {
1569 BREAK_TO_DEBUGGER();
1570 return NULL;
1571 }
1572
1573 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1574 return &dsc->base;
1575 }
1576
dcn31_destroy_resource_pool(struct resource_pool ** pool)1577 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1578 {
1579 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1580
1581 dcn31_resource_destruct(dcn31_pool);
1582 kfree(dcn31_pool);
1583 *pool = NULL;
1584 }
1585
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1586 static struct clock_source *dcn31_clock_source_create(
1587 struct dc_context *ctx,
1588 struct dc_bios *bios,
1589 enum clock_source_id id,
1590 const struct dce110_clk_src_regs *regs,
1591 bool dp_clk_src)
1592 {
1593 struct dce110_clk_src *clk_src =
1594 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1595
1596 if (!clk_src)
1597 return NULL;
1598
1599 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1600 regs, &cs_shift, &cs_mask)) {
1601 clk_src->base.dp_clk_src = dp_clk_src;
1602 return &clk_src->base;
1603 }
1604
1605 kfree(clk_src);
1606 BREAK_TO_DEBUGGER();
1607 return NULL;
1608 }
1609
is_dual_plane(enum surface_pixel_format format)1610 static bool is_dual_plane(enum surface_pixel_format format)
1611 {
1612 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1613 }
1614
dcn31x_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1615 int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
1616 struct dc_state *context,
1617 display_e2e_pipe_params_st *pipes,
1618 bool fast_validate)
1619 {
1620 uint32_t pipe_cnt;
1621 int i;
1622
1623 dc_assert_fp_enabled();
1624
1625 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1626
1627 for (i = 0; i < pipe_cnt; i++) {
1628 pipes[i].pipe.src.gpuvm = 1;
1629 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {
1630 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1631 pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;
1632 } else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
1633 pipes[i].pipe.src.hostvm = false;
1634 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
1635 pipes[i].pipe.src.hostvm = true;
1636 }
1637 return pipe_cnt;
1638 }
1639
dcn31_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1640 int dcn31_populate_dml_pipes_from_context(
1641 struct dc *dc, struct dc_state *context,
1642 display_e2e_pipe_params_st *pipes,
1643 bool fast_validate)
1644 {
1645 int i, pipe_cnt;
1646 struct resource_context *res_ctx = &context->res_ctx;
1647 struct pipe_ctx *pipe;
1648 bool upscaled = false;
1649
1650 DC_FP_START();
1651 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1652 DC_FP_END();
1653
1654 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1655 struct dc_crtc_timing *timing;
1656
1657 if (!res_ctx->pipe_ctx[i].stream)
1658 continue;
1659 pipe = &res_ctx->pipe_ctx[i];
1660 timing = &pipe->stream->timing;
1661 if (pipe->plane_state &&
1662 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1663 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1664 upscaled = true;
1665
1666 /*
1667 * Immediate flip can be set dynamically after enabling the plane.
1668 * We need to require support for immediate flip or underflow can be
1669 * intermittently experienced depending on peak b/w requirements.
1670 */
1671 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1672 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1673 pipes[pipe_cnt].pipe.src.gpuvm = true;
1674 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1675 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1676 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1677 DC_FP_START();
1678 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1679 DC_FP_END();
1680
1681
1682 if (pipes[pipe_cnt].dout.dsc_enable) {
1683 switch (timing->display_color_depth) {
1684 case COLOR_DEPTH_888:
1685 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1686 break;
1687 case COLOR_DEPTH_101010:
1688 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1689 break;
1690 case COLOR_DEPTH_121212:
1691 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1692 break;
1693 default:
1694 ASSERT(0);
1695 break;
1696 }
1697 }
1698
1699 pipe_cnt++;
1700 }
1701 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1702 dc->config.enable_4to1MPC = false;
1703 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1704 if (is_dual_plane(pipe->plane_state->format)
1705 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1706 dc->config.enable_4to1MPC = true;
1707 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1708 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1709 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1710 pipes[0].pipe.src.unbounded_req_mode = true;
1711 }
1712 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1713 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1714 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1715 } else if (context->stream_count >= 3 && upscaled) {
1716 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1717 }
1718
1719 return pipe_cnt;
1720 }
1721
dcn31_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1722 void dcn31_calculate_wm_and_dlg(
1723 struct dc *dc, struct dc_state *context,
1724 display_e2e_pipe_params_st *pipes,
1725 int pipe_cnt,
1726 int vlevel)
1727 {
1728 DC_FP_START();
1729 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1730 DC_FP_END();
1731 }
1732
1733 void
dcn31_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)1734 dcn31_populate_dml_writeback_from_context(struct dc *dc,
1735 struct resource_context *res_ctx,
1736 display_e2e_pipe_params_st *pipes)
1737 {
1738 DC_FP_START();
1739 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1740 DC_FP_END();
1741 }
1742
1743 void
dcn31_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1744 dcn31_set_mcif_arb_params(struct dc *dc,
1745 struct dc_state *context,
1746 display_e2e_pipe_params_st *pipes,
1747 int pipe_cnt)
1748 {
1749 DC_FP_START();
1750 dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1751 DC_FP_END();
1752 }
1753
dcn31_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1754 bool dcn31_validate_bandwidth(struct dc *dc,
1755 struct dc_state *context,
1756 bool fast_validate)
1757 {
1758 bool out = false;
1759
1760 BW_VAL_TRACE_SETUP();
1761
1762 int vlevel = 0;
1763 int pipe_cnt = 0;
1764 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1765 DC_LOGGER_INIT(dc->ctx->logger);
1766
1767 BW_VAL_TRACE_COUNT();
1768
1769 if (!pipes)
1770 goto validate_fail;
1771
1772 DC_FP_START();
1773 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
1774 DC_FP_END();
1775
1776 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
1777 if (pipe_cnt == 0)
1778 fast_validate = false;
1779
1780 if (!out)
1781 goto validate_fail;
1782
1783 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1784
1785 if (fast_validate) {
1786 BW_VAL_TRACE_SKIP(fast);
1787 goto validate_out;
1788 }
1789 if (dc->res_pool->funcs->calculate_wm_and_dlg)
1790 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1791
1792 BW_VAL_TRACE_END_WATERMARKS();
1793
1794 goto validate_out;
1795
1796 validate_fail:
1797 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1798 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1799
1800 BW_VAL_TRACE_SKIP(fail);
1801 out = false;
1802
1803 validate_out:
1804 kfree(pipes);
1805
1806 BW_VAL_TRACE_FINISH();
1807
1808 return out;
1809 }
1810
dcn31_get_panel_config_defaults(struct dc_panel_config * panel_config)1811 static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config)
1812 {
1813 *panel_config = panel_config_defaults;
1814 }
1815
1816 static struct dc_cap_funcs cap_funcs = {
1817 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1818 };
1819
1820 static struct resource_funcs dcn31_res_pool_funcs = {
1821 .destroy = dcn31_destroy_resource_pool,
1822 .link_enc_create = dcn31_link_encoder_create,
1823 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1824 .link_encs_assign = link_enc_cfg_link_encs_assign,
1825 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1826 .panel_cntl_create = dcn31_panel_cntl_create,
1827 .validate_bandwidth = dcn31_validate_bandwidth,
1828 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1829 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1830 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
1831 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1832 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1833 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1834 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1835 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1836 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1837 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1838 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1839 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1840 .update_bw_bounding_box = dcn31_update_bw_bounding_box,
1841 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1842 .get_panel_config_defaults = dcn31_get_panel_config_defaults,
1843 };
1844
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1845 static struct clock_source *dcn30_clock_source_create(
1846 struct dc_context *ctx,
1847 struct dc_bios *bios,
1848 enum clock_source_id id,
1849 const struct dce110_clk_src_regs *regs,
1850 bool dp_clk_src)
1851 {
1852 struct dce110_clk_src *clk_src =
1853 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1854
1855 if (!clk_src)
1856 return NULL;
1857
1858 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1859 regs, &cs_shift, &cs_mask)) {
1860 clk_src->base.dp_clk_src = dp_clk_src;
1861 return &clk_src->base;
1862 }
1863
1864 BREAK_TO_DEBUGGER();
1865 return NULL;
1866 }
1867
dcn31_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn31_resource_pool * pool)1868 static bool dcn31_resource_construct(
1869 uint8_t num_virtual_links,
1870 struct dc *dc,
1871 struct dcn31_resource_pool *pool)
1872 {
1873 int i;
1874 struct dc_context *ctx = dc->ctx;
1875 struct irq_service_init_data init_data;
1876
1877 ctx->dc_bios->regs = &bios_regs;
1878
1879 pool->base.res_cap = &res_cap_dcn31;
1880
1881 pool->base.funcs = &dcn31_res_pool_funcs;
1882
1883 /*************************************************
1884 * Resource + asic cap harcoding *
1885 *************************************************/
1886 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1887 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1888 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1889 dc->caps.max_downscale_ratio = 600;
1890 dc->caps.i2c_speed_in_khz = 100;
1891 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1892 dc->caps.max_cursor_size = 256;
1893 dc->caps.min_horizontal_blanking_period = 80;
1894 dc->caps.dmdata_alloc_size = 2048;
1895
1896 dc->caps.max_slave_planes = 2;
1897 dc->caps.max_slave_yuv_planes = 2;
1898 dc->caps.max_slave_rgb_planes = 2;
1899 dc->caps.post_blend_color_processing = true;
1900 dc->caps.force_dp_tps4_for_cp2520 = true;
1901 if (dc->config.forceHBR2CP2520)
1902 dc->caps.force_dp_tps4_for_cp2520 = false;
1903 dc->caps.dp_hpo = true;
1904 dc->caps.dp_hdmi21_pcon_support = true;
1905 dc->caps.edp_dsc_support = true;
1906 dc->caps.extended_aux_timeout_support = true;
1907 dc->caps.dmcub_support = true;
1908 dc->caps.is_apu = true;
1909 dc->caps.zstate_support = true;
1910
1911 /* Color pipeline capabilities */
1912 dc->caps.color.dpp.dcn_arch = 1;
1913 dc->caps.color.dpp.input_lut_shared = 0;
1914 dc->caps.color.dpp.icsc = 1;
1915 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1916 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1917 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1918 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1919 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1920 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1921 dc->caps.color.dpp.post_csc = 1;
1922 dc->caps.color.dpp.gamma_corr = 1;
1923 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1924
1925 dc->caps.color.dpp.hw_3d_lut = 1;
1926 dc->caps.color.dpp.ogam_ram = 1;
1927 // no OGAM ROM on DCN301
1928 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1929 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1930 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1931 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1932 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1933 dc->caps.color.dpp.ocsc = 0;
1934
1935 dc->caps.color.mpc.gamut_remap = 1;
1936 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1937 dc->caps.color.mpc.ogam_ram = 1;
1938 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1939 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1940 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1941 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1942 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1943 dc->caps.color.mpc.ocsc = 1;
1944
1945 dc->config.use_old_fixed_vs_sequence = true;
1946
1947 /* Use pipe context based otg sync logic */
1948 dc->config.use_pipe_ctx_sync_logic = true;
1949
1950 /* read VBIOS LTTPR caps */
1951 {
1952 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1953 enum bp_result bp_query_result;
1954 uint8_t is_vbios_lttpr_enable = 0;
1955
1956 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1957 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1958 }
1959
1960 /* interop bit is implicit */
1961 {
1962 dc->caps.vbios_lttpr_aware = true;
1963 }
1964 }
1965
1966 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1967 dc->debug = debug_defaults_drv;
1968
1969 // Init the vm_helper
1970 if (dc->vm_helper)
1971 vm_helper_init(dc->vm_helper, 16);
1972
1973 /*************************************************
1974 * Create resources *
1975 *************************************************/
1976
1977 /* Clock Sources for Pixel Clock*/
1978 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1979 dcn30_clock_source_create(ctx, ctx->dc_bios,
1980 CLOCK_SOURCE_COMBO_PHY_PLL0,
1981 &clk_src_regs[0], false);
1982 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1983 dcn30_clock_source_create(ctx, ctx->dc_bios,
1984 CLOCK_SOURCE_COMBO_PHY_PLL1,
1985 &clk_src_regs[1], false);
1986 /*move phypllx_pixclk_resync to dmub next*/
1987 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
1988 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1989 dcn30_clock_source_create(ctx, ctx->dc_bios,
1990 CLOCK_SOURCE_COMBO_PHY_PLL2,
1991 &clk_src_regs_b0[2], false);
1992 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1993 dcn30_clock_source_create(ctx, ctx->dc_bios,
1994 CLOCK_SOURCE_COMBO_PHY_PLL3,
1995 &clk_src_regs_b0[3], false);
1996 } else {
1997 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1998 dcn30_clock_source_create(ctx, ctx->dc_bios,
1999 CLOCK_SOURCE_COMBO_PHY_PLL2,
2000 &clk_src_regs[2], false);
2001 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2002 dcn30_clock_source_create(ctx, ctx->dc_bios,
2003 CLOCK_SOURCE_COMBO_PHY_PLL3,
2004 &clk_src_regs[3], false);
2005 }
2006
2007 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2008 dcn30_clock_source_create(ctx, ctx->dc_bios,
2009 CLOCK_SOURCE_COMBO_PHY_PLL4,
2010 &clk_src_regs[4], false);
2011
2012 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2013
2014 /* todo: not reuse phy_pll registers */
2015 pool->base.dp_clock_source =
2016 dcn31_clock_source_create(ctx, ctx->dc_bios,
2017 CLOCK_SOURCE_ID_DP_DTO,
2018 &clk_src_regs[0], true);
2019
2020 for (i = 0; i < pool->base.clk_src_count; i++) {
2021 if (pool->base.clock_sources[i] == NULL) {
2022 dm_error("DC: failed to create clock sources!\n");
2023 BREAK_TO_DEBUGGER();
2024 goto create_fail;
2025 }
2026 }
2027
2028 /* TODO: DCCG */
2029 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2030 if (pool->base.dccg == NULL) {
2031 dm_error("DC: failed to create dccg!\n");
2032 BREAK_TO_DEBUGGER();
2033 goto create_fail;
2034 }
2035
2036 /* TODO: IRQ */
2037 init_data.ctx = dc->ctx;
2038 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2039 if (!pool->base.irqs)
2040 goto create_fail;
2041
2042 /* HUBBUB */
2043 pool->base.hubbub = dcn31_hubbub_create(ctx);
2044 if (pool->base.hubbub == NULL) {
2045 BREAK_TO_DEBUGGER();
2046 dm_error("DC: failed to create hubbub!\n");
2047 goto create_fail;
2048 }
2049
2050 /* HUBPs, DPPs, OPPs and TGs */
2051 for (i = 0; i < pool->base.pipe_count; i++) {
2052 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2053 if (pool->base.hubps[i] == NULL) {
2054 BREAK_TO_DEBUGGER();
2055 dm_error(
2056 "DC: failed to create hubps!\n");
2057 goto create_fail;
2058 }
2059
2060 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2061 if (pool->base.dpps[i] == NULL) {
2062 BREAK_TO_DEBUGGER();
2063 dm_error(
2064 "DC: failed to create dpps!\n");
2065 goto create_fail;
2066 }
2067 }
2068
2069 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2070 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2071 if (pool->base.opps[i] == NULL) {
2072 BREAK_TO_DEBUGGER();
2073 dm_error(
2074 "DC: failed to create output pixel processor!\n");
2075 goto create_fail;
2076 }
2077 }
2078
2079 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2080 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2081 ctx, i);
2082 if (pool->base.timing_generators[i] == NULL) {
2083 BREAK_TO_DEBUGGER();
2084 dm_error("DC: failed to create tg!\n");
2085 goto create_fail;
2086 }
2087 }
2088 pool->base.timing_generator_count = i;
2089
2090 /* PSR */
2091 pool->base.psr = dmub_psr_create(ctx);
2092 if (pool->base.psr == NULL) {
2093 dm_error("DC: failed to create psr obj!\n");
2094 BREAK_TO_DEBUGGER();
2095 goto create_fail;
2096 }
2097
2098 /* Replay */
2099 pool->base.replay = dmub_replay_create(ctx);
2100 if (pool->base.replay == NULL) {
2101 dm_error("DC: failed to create replay obj!\n");
2102 BREAK_TO_DEBUGGER();
2103 goto create_fail;
2104 }
2105
2106 /* ABM */
2107 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2108 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2109 &abm_regs[i],
2110 &abm_shift,
2111 &abm_mask);
2112 if (pool->base.multiple_abms[i] == NULL) {
2113 dm_error("DC: failed to create abm for pipe %d!\n", i);
2114 BREAK_TO_DEBUGGER();
2115 goto create_fail;
2116 }
2117 }
2118
2119 /* MPC and DSC */
2120 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2121 if (pool->base.mpc == NULL) {
2122 BREAK_TO_DEBUGGER();
2123 dm_error("DC: failed to create mpc!\n");
2124 goto create_fail;
2125 }
2126
2127 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2128 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2129 if (pool->base.dscs[i] == NULL) {
2130 BREAK_TO_DEBUGGER();
2131 dm_error("DC: failed to create display stream compressor %d!\n", i);
2132 goto create_fail;
2133 }
2134 }
2135
2136 /* DWB and MMHUBBUB */
2137 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2138 BREAK_TO_DEBUGGER();
2139 dm_error("DC: failed to create dwbc!\n");
2140 goto create_fail;
2141 }
2142
2143 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2144 BREAK_TO_DEBUGGER();
2145 dm_error("DC: failed to create mcif_wb!\n");
2146 goto create_fail;
2147 }
2148
2149 /* AUX and I2C */
2150 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2151 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2152 if (pool->base.engines[i] == NULL) {
2153 BREAK_TO_DEBUGGER();
2154 dm_error(
2155 "DC:failed to create aux engine!!\n");
2156 goto create_fail;
2157 }
2158 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2159 if (pool->base.hw_i2cs[i] == NULL) {
2160 BREAK_TO_DEBUGGER();
2161 dm_error(
2162 "DC:failed to create hw i2c!!\n");
2163 goto create_fail;
2164 }
2165 pool->base.sw_i2cs[i] = NULL;
2166 }
2167
2168 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2169 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2170 !dc->debug.dpia_debug.bits.disable_dpia) {
2171 /* YELLOW CARP B0 has 4 DPIA's */
2172 pool->base.usb4_dpia_count = 4;
2173 }
2174
2175 if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1)
2176 pool->base.usb4_dpia_count = 4;
2177
2178 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2179 if (!resource_construct(num_virtual_links, dc, &pool->base,
2180 &res_create_funcs))
2181 goto create_fail;
2182
2183 /* HW Sequencer and Plane caps */
2184 dcn31_hw_sequencer_construct(dc);
2185
2186 dc->caps.max_planes = pool->base.pipe_count;
2187
2188 for (i = 0; i < dc->caps.max_planes; ++i)
2189 dc->caps.planes[i] = plane_cap;
2190
2191 dc->cap_funcs = cap_funcs;
2192
2193 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2194
2195 return true;
2196
2197 create_fail:
2198 dcn31_resource_destruct(pool);
2199
2200 return false;
2201 }
2202
dcn31_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2203 struct resource_pool *dcn31_create_resource_pool(
2204 const struct dc_init_data *init_data,
2205 struct dc *dc)
2206 {
2207 struct dcn31_resource_pool *pool =
2208 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2209
2210 if (!pool)
2211 return NULL;
2212
2213 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2214 return &pool->base;
2215
2216 BREAK_TO_DEBUGGER();
2217 kfree(pool);
2218 return NULL;
2219 }
2220