1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/device.h>
25 #include <linux/export.h>
26 #include <linux/err.h>
27 #include <linux/fs.h>
28 #include <linux/file.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/compat.h>
33 #include <uapi/linux/kfd_ioctl.h>
34 #include <linux/time.h>
35 #include <linux/mm.h>
36 #include <linux/mman.h>
37 #include <linux/ptrace.h>
38 #include <linux/dma-buf.h>
39 #include <linux/fdtable.h>
40 #include <linux/processor.h>
41 #include "kfd_priv.h"
42 #include "kfd_device_queue_manager.h"
43 #include "kfd_svm.h"
44 #include "amdgpu_amdkfd.h"
45 #include "kfd_smi_events.h"
46 #include "amdgpu_dma_buf.h"
47 #include "kfd_debug.h"
48
49 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
50 static int kfd_open(struct inode *, struct file *);
51 static int kfd_release(struct inode *, struct file *);
52 static int kfd_mmap(struct file *, struct vm_area_struct *);
53
54 static const char kfd_dev_name[] = "kfd";
55
56 static const struct file_operations kfd_fops = {
57 .owner = THIS_MODULE,
58 .unlocked_ioctl = kfd_ioctl,
59 .compat_ioctl = compat_ptr_ioctl,
60 .open = kfd_open,
61 .release = kfd_release,
62 .mmap = kfd_mmap,
63 };
64
65 static int kfd_char_dev_major = -1;
66 static struct class *kfd_class;
67 struct device *kfd_device;
68
kfd_lock_pdd_by_id(struct kfd_process * p,__u32 gpu_id)69 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id)
70 {
71 struct kfd_process_device *pdd;
72
73 mutex_lock(&p->mutex);
74 pdd = kfd_process_device_data_by_id(p, gpu_id);
75
76 if (pdd)
77 return pdd;
78
79 mutex_unlock(&p->mutex);
80 return NULL;
81 }
82
kfd_unlock_pdd(struct kfd_process_device * pdd)83 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd)
84 {
85 mutex_unlock(&pdd->process->mutex);
86 }
87
kfd_chardev_init(void)88 int kfd_chardev_init(void)
89 {
90 int err = 0;
91
92 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
93 err = kfd_char_dev_major;
94 if (err < 0)
95 goto err_register_chrdev;
96
97 kfd_class = class_create(kfd_dev_name);
98 err = PTR_ERR(kfd_class);
99 if (IS_ERR(kfd_class))
100 goto err_class_create;
101
102 kfd_device = device_create(kfd_class, NULL,
103 MKDEV(kfd_char_dev_major, 0),
104 NULL, kfd_dev_name);
105 err = PTR_ERR(kfd_device);
106 if (IS_ERR(kfd_device))
107 goto err_device_create;
108
109 return 0;
110
111 err_device_create:
112 class_destroy(kfd_class);
113 err_class_create:
114 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
115 err_register_chrdev:
116 return err;
117 }
118
kfd_chardev_exit(void)119 void kfd_chardev_exit(void)
120 {
121 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
122 class_destroy(kfd_class);
123 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
124 kfd_device = NULL;
125 }
126
127
kfd_open(struct inode * inode,struct file * filep)128 static int kfd_open(struct inode *inode, struct file *filep)
129 {
130 struct kfd_process *process;
131 bool is_32bit_user_mode;
132
133 if (iminor(inode) != 0)
134 return -ENODEV;
135
136 is_32bit_user_mode = in_compat_syscall();
137
138 if (is_32bit_user_mode) {
139 dev_warn(kfd_device,
140 "Process %d (32-bit) failed to open /dev/kfd\n"
141 "32-bit processes are not supported by amdkfd\n",
142 current->pid);
143 return -EPERM;
144 }
145
146 process = kfd_create_process(current);
147 if (IS_ERR(process))
148 return PTR_ERR(process);
149
150 if (kfd_process_init_cwsr_apu(process, filep)) {
151 kfd_unref_process(process);
152 return -EFAULT;
153 }
154
155 /* filep now owns the reference returned by kfd_create_process */
156 filep->private_data = process;
157
158 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
159 process->pasid, process->is_32bit_user_mode);
160
161 return 0;
162 }
163
kfd_release(struct inode * inode,struct file * filep)164 static int kfd_release(struct inode *inode, struct file *filep)
165 {
166 struct kfd_process *process = filep->private_data;
167
168 if (process)
169 kfd_unref_process(process);
170
171 return 0;
172 }
173
kfd_ioctl_get_version(struct file * filep,struct kfd_process * p,void * data)174 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
175 void *data)
176 {
177 struct kfd_ioctl_get_version_args *args = data;
178
179 args->major_version = KFD_IOCTL_MAJOR_VERSION;
180 args->minor_version = KFD_IOCTL_MINOR_VERSION;
181
182 return 0;
183 }
184
set_queue_properties_from_user(struct queue_properties * q_properties,struct kfd_ioctl_create_queue_args * args)185 static int set_queue_properties_from_user(struct queue_properties *q_properties,
186 struct kfd_ioctl_create_queue_args *args)
187 {
188 /*
189 * Repurpose queue percentage to accommodate new features:
190 * bit 0-7: queue percentage
191 * bit 8-15: pm4_target_xcc
192 */
193 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
194 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
195 return -EINVAL;
196 }
197
198 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
199 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
200 return -EINVAL;
201 }
202
203 if ((args->ring_base_address) &&
204 (!access_ok((const void __user *) args->ring_base_address,
205 sizeof(uint64_t)))) {
206 pr_err("Can't access ring base address\n");
207 return -EFAULT;
208 }
209
210 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
211 pr_err("Ring size must be a power of 2 or 0\n");
212 return -EINVAL;
213 }
214
215 if (args->ring_size < KFD_MIN_QUEUE_RING_SIZE) {
216 args->ring_size = KFD_MIN_QUEUE_RING_SIZE;
217 pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE");
218 }
219
220 if (!access_ok((const void __user *) args->read_pointer_address,
221 sizeof(uint32_t))) {
222 pr_err("Can't access read pointer\n");
223 return -EFAULT;
224 }
225
226 if (!access_ok((const void __user *) args->write_pointer_address,
227 sizeof(uint32_t))) {
228 pr_err("Can't access write pointer\n");
229 return -EFAULT;
230 }
231
232 if (args->eop_buffer_address &&
233 !access_ok((const void __user *) args->eop_buffer_address,
234 sizeof(uint32_t))) {
235 pr_debug("Can't access eop buffer");
236 return -EFAULT;
237 }
238
239 if (args->ctx_save_restore_address &&
240 !access_ok((const void __user *) args->ctx_save_restore_address,
241 sizeof(uint32_t))) {
242 pr_debug("Can't access ctx save restore buffer");
243 return -EFAULT;
244 }
245
246 q_properties->is_interop = false;
247 q_properties->is_gws = false;
248 q_properties->queue_percent = args->queue_percentage & 0xFF;
249 /* bit 8-15 are repurposed to be PM4 target XCC */
250 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
251 q_properties->priority = args->queue_priority;
252 q_properties->queue_address = args->ring_base_address;
253 q_properties->queue_size = args->ring_size;
254 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
255 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
256 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
257 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
258 q_properties->ctx_save_restore_area_address =
259 args->ctx_save_restore_address;
260 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
261 q_properties->ctl_stack_size = args->ctl_stack_size;
262 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
263 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
264 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
265 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
266 q_properties->type = KFD_QUEUE_TYPE_SDMA;
267 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
268 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI;
269 else
270 return -ENOTSUPP;
271
272 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
273 q_properties->format = KFD_QUEUE_FORMAT_AQL;
274 else
275 q_properties->format = KFD_QUEUE_FORMAT_PM4;
276
277 pr_debug("Queue Percentage: %d, %d\n",
278 q_properties->queue_percent, args->queue_percentage);
279
280 pr_debug("Queue Priority: %d, %d\n",
281 q_properties->priority, args->queue_priority);
282
283 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
284 q_properties->queue_address, args->ring_base_address);
285
286 pr_debug("Queue Size: 0x%llX, %u\n",
287 q_properties->queue_size, args->ring_size);
288
289 pr_debug("Queue r/w Pointers: %px, %px\n",
290 q_properties->read_ptr,
291 q_properties->write_ptr);
292
293 pr_debug("Queue Format: %d\n", q_properties->format);
294
295 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
296
297 pr_debug("Queue CTX save area: 0x%llX\n",
298 q_properties->ctx_save_restore_area_address);
299
300 return 0;
301 }
302
kfd_ioctl_create_queue(struct file * filep,struct kfd_process * p,void * data)303 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
304 void *data)
305 {
306 struct kfd_ioctl_create_queue_args *args = data;
307 struct kfd_node *dev;
308 int err = 0;
309 unsigned int queue_id;
310 struct kfd_process_device *pdd;
311 struct queue_properties q_properties;
312 uint32_t doorbell_offset_in_process = 0;
313 struct amdgpu_bo *wptr_bo = NULL;
314
315 memset(&q_properties, 0, sizeof(struct queue_properties));
316
317 pr_debug("Creating queue ioctl\n");
318
319 err = set_queue_properties_from_user(&q_properties, args);
320 if (err)
321 return err;
322
323 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
324
325 mutex_lock(&p->mutex);
326
327 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
328 if (!pdd) {
329 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
330 err = -EINVAL;
331 goto err_pdd;
332 }
333 dev = pdd->dev;
334
335 pdd = kfd_bind_process_to_device(dev, p);
336 if (IS_ERR(pdd)) {
337 err = -ESRCH;
338 goto err_bind_process;
339 }
340
341 if (!pdd->qpd.proc_doorbells) {
342 err = kfd_alloc_process_doorbells(dev->kfd, pdd);
343 if (err) {
344 pr_debug("failed to allocate process doorbells\n");
345 goto err_bind_process;
346 }
347 }
348
349 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
350 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
351 */
352 if (dev->kfd->shared_resources.enable_mes &&
353 ((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK)
354 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) {
355 struct amdgpu_bo_va_mapping *wptr_mapping;
356 struct amdgpu_vm *wptr_vm;
357
358 wptr_vm = drm_priv_to_vm(pdd->drm_priv);
359 err = amdgpu_bo_reserve(wptr_vm->root.bo, false);
360 if (err)
361 goto err_wptr_map_gart;
362
363 wptr_mapping = amdgpu_vm_bo_lookup_mapping(
364 wptr_vm, args->write_pointer_address >> PAGE_SHIFT);
365 amdgpu_bo_unreserve(wptr_vm->root.bo);
366 if (!wptr_mapping) {
367 pr_err("Failed to lookup wptr bo\n");
368 err = -EINVAL;
369 goto err_wptr_map_gart;
370 }
371
372 wptr_bo = wptr_mapping->bo_va->base.bo;
373 if (wptr_bo->tbo.base.size > PAGE_SIZE) {
374 pr_err("Requested GART mapping for wptr bo larger than one page\n");
375 err = -EINVAL;
376 goto err_wptr_map_gart;
377 }
378
379 err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
380 if (err) {
381 pr_err("Failed to map wptr bo to GART\n");
382 goto err_wptr_map_gart;
383 }
384 }
385
386 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
387 p->pasid,
388 dev->id);
389
390 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo,
391 NULL, NULL, NULL, &doorbell_offset_in_process);
392 if (err != 0)
393 goto err_create_queue;
394
395 args->queue_id = queue_id;
396
397
398 /* Return gpu_id as doorbell offset for mmap usage */
399 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
400 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
401 if (KFD_IS_SOC15(dev))
402 /* On SOC15 ASICs, include the doorbell offset within the
403 * process doorbell frame, which is 2 pages.
404 */
405 args->doorbell_offset |= doorbell_offset_in_process;
406
407 mutex_unlock(&p->mutex);
408
409 pr_debug("Queue id %d was created successfully\n", args->queue_id);
410
411 pr_debug("Ring buffer address == 0x%016llX\n",
412 args->ring_base_address);
413
414 pr_debug("Read ptr address == 0x%016llX\n",
415 args->read_pointer_address);
416
417 pr_debug("Write ptr address == 0x%016llX\n",
418 args->write_pointer_address);
419
420 kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, NULL, 0);
421 return 0;
422
423 err_create_queue:
424 if (wptr_bo)
425 amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&wptr_bo);
426 err_wptr_map_gart:
427 err_bind_process:
428 err_pdd:
429 mutex_unlock(&p->mutex);
430 return err;
431 }
432
kfd_ioctl_destroy_queue(struct file * filp,struct kfd_process * p,void * data)433 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
434 void *data)
435 {
436 int retval;
437 struct kfd_ioctl_destroy_queue_args *args = data;
438
439 pr_debug("Destroying queue id %d for pasid 0x%x\n",
440 args->queue_id,
441 p->pasid);
442
443 mutex_lock(&p->mutex);
444
445 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
446
447 mutex_unlock(&p->mutex);
448 return retval;
449 }
450
kfd_ioctl_update_queue(struct file * filp,struct kfd_process * p,void * data)451 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
452 void *data)
453 {
454 int retval;
455 struct kfd_ioctl_update_queue_args *args = data;
456 struct queue_properties properties;
457
458 /*
459 * Repurpose queue percentage to accommodate new features:
460 * bit 0-7: queue percentage
461 * bit 8-15: pm4_target_xcc
462 */
463 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
464 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
465 return -EINVAL;
466 }
467
468 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
469 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
470 return -EINVAL;
471 }
472
473 if ((args->ring_base_address) &&
474 (!access_ok((const void __user *) args->ring_base_address,
475 sizeof(uint64_t)))) {
476 pr_err("Can't access ring base address\n");
477 return -EFAULT;
478 }
479
480 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
481 pr_err("Ring size must be a power of 2 or 0\n");
482 return -EINVAL;
483 }
484
485 if (args->ring_size < KFD_MIN_QUEUE_RING_SIZE) {
486 args->ring_size = KFD_MIN_QUEUE_RING_SIZE;
487 pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE");
488 }
489
490 properties.queue_address = args->ring_base_address;
491 properties.queue_size = args->ring_size;
492 properties.queue_percent = args->queue_percentage & 0xFF;
493 /* bit 8-15 are repurposed to be PM4 target XCC */
494 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
495 properties.priority = args->queue_priority;
496
497 pr_debug("Updating queue id %d for pasid 0x%x\n",
498 args->queue_id, p->pasid);
499
500 mutex_lock(&p->mutex);
501
502 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties);
503
504 mutex_unlock(&p->mutex);
505
506 return retval;
507 }
508
kfd_ioctl_set_cu_mask(struct file * filp,struct kfd_process * p,void * data)509 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,
510 void *data)
511 {
512 int retval;
513 const int max_num_cus = 1024;
514 struct kfd_ioctl_set_cu_mask_args *args = data;
515 struct mqd_update_info minfo = {0};
516 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
517 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
518
519 if ((args->num_cu_mask % 32) != 0) {
520 pr_debug("num_cu_mask 0x%x must be a multiple of 32",
521 args->num_cu_mask);
522 return -EINVAL;
523 }
524
525 minfo.cu_mask.count = args->num_cu_mask;
526 if (minfo.cu_mask.count == 0) {
527 pr_debug("CU mask cannot be 0");
528 return -EINVAL;
529 }
530
531 /* To prevent an unreasonably large CU mask size, set an arbitrary
532 * limit of max_num_cus bits. We can then just drop any CU mask bits
533 * past max_num_cus bits and just use the first max_num_cus bits.
534 */
535 if (minfo.cu_mask.count > max_num_cus) {
536 pr_debug("CU mask cannot be greater than 1024 bits");
537 minfo.cu_mask.count = max_num_cus;
538 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
539 }
540
541 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL);
542 if (!minfo.cu_mask.ptr)
543 return -ENOMEM;
544
545 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size);
546 if (retval) {
547 pr_debug("Could not copy CU mask from userspace");
548 retval = -EFAULT;
549 goto out;
550 }
551
552 mutex_lock(&p->mutex);
553
554 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo);
555
556 mutex_unlock(&p->mutex);
557
558 out:
559 kfree(minfo.cu_mask.ptr);
560 return retval;
561 }
562
kfd_ioctl_get_queue_wave_state(struct file * filep,struct kfd_process * p,void * data)563 static int kfd_ioctl_get_queue_wave_state(struct file *filep,
564 struct kfd_process *p, void *data)
565 {
566 struct kfd_ioctl_get_queue_wave_state_args *args = data;
567 int r;
568
569 mutex_lock(&p->mutex);
570
571 r = pqm_get_wave_state(&p->pqm, args->queue_id,
572 (void __user *)args->ctl_stack_address,
573 &args->ctl_stack_used_size,
574 &args->save_area_used_size);
575
576 mutex_unlock(&p->mutex);
577
578 return r;
579 }
580
kfd_ioctl_set_memory_policy(struct file * filep,struct kfd_process * p,void * data)581 static int kfd_ioctl_set_memory_policy(struct file *filep,
582 struct kfd_process *p, void *data)
583 {
584 struct kfd_ioctl_set_memory_policy_args *args = data;
585 int err = 0;
586 struct kfd_process_device *pdd;
587 enum cache_policy default_policy, alternate_policy;
588
589 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
590 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
591 return -EINVAL;
592 }
593
594 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
595 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
596 return -EINVAL;
597 }
598
599 mutex_lock(&p->mutex);
600 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
601 if (!pdd) {
602 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
603 err = -EINVAL;
604 goto err_pdd;
605 }
606
607 pdd = kfd_bind_process_to_device(pdd->dev, p);
608 if (IS_ERR(pdd)) {
609 err = -ESRCH;
610 goto out;
611 }
612
613 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
614 ? cache_policy_coherent : cache_policy_noncoherent;
615
616 alternate_policy =
617 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
618 ? cache_policy_coherent : cache_policy_noncoherent;
619
620 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm,
621 &pdd->qpd,
622 default_policy,
623 alternate_policy,
624 (void __user *)args->alternate_aperture_base,
625 args->alternate_aperture_size))
626 err = -EINVAL;
627
628 out:
629 err_pdd:
630 mutex_unlock(&p->mutex);
631
632 return err;
633 }
634
kfd_ioctl_set_trap_handler(struct file * filep,struct kfd_process * p,void * data)635 static int kfd_ioctl_set_trap_handler(struct file *filep,
636 struct kfd_process *p, void *data)
637 {
638 struct kfd_ioctl_set_trap_handler_args *args = data;
639 int err = 0;
640 struct kfd_process_device *pdd;
641
642 mutex_lock(&p->mutex);
643
644 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
645 if (!pdd) {
646 err = -EINVAL;
647 goto err_pdd;
648 }
649
650 pdd = kfd_bind_process_to_device(pdd->dev, p);
651 if (IS_ERR(pdd)) {
652 err = -ESRCH;
653 goto out;
654 }
655
656 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr);
657
658 out:
659 err_pdd:
660 mutex_unlock(&p->mutex);
661
662 return err;
663 }
664
kfd_ioctl_dbg_register(struct file * filep,struct kfd_process * p,void * data)665 static int kfd_ioctl_dbg_register(struct file *filep,
666 struct kfd_process *p, void *data)
667 {
668 return -EPERM;
669 }
670
kfd_ioctl_dbg_unregister(struct file * filep,struct kfd_process * p,void * data)671 static int kfd_ioctl_dbg_unregister(struct file *filep,
672 struct kfd_process *p, void *data)
673 {
674 return -EPERM;
675 }
676
kfd_ioctl_dbg_address_watch(struct file * filep,struct kfd_process * p,void * data)677 static int kfd_ioctl_dbg_address_watch(struct file *filep,
678 struct kfd_process *p, void *data)
679 {
680 return -EPERM;
681 }
682
683 /* Parse and generate fixed size data structure for wave control */
kfd_ioctl_dbg_wave_control(struct file * filep,struct kfd_process * p,void * data)684 static int kfd_ioctl_dbg_wave_control(struct file *filep,
685 struct kfd_process *p, void *data)
686 {
687 return -EPERM;
688 }
689
kfd_ioctl_get_clock_counters(struct file * filep,struct kfd_process * p,void * data)690 static int kfd_ioctl_get_clock_counters(struct file *filep,
691 struct kfd_process *p, void *data)
692 {
693 struct kfd_ioctl_get_clock_counters_args *args = data;
694 struct kfd_process_device *pdd;
695
696 mutex_lock(&p->mutex);
697 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
698 mutex_unlock(&p->mutex);
699 if (pdd)
700 /* Reading GPU clock counter from KGD */
701 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev);
702 else
703 /* Node without GPU resource */
704 args->gpu_clock_counter = 0;
705
706 /* No access to rdtsc. Using raw monotonic time */
707 args->cpu_clock_counter = ktime_get_raw_ns();
708 args->system_clock_counter = ktime_get_boottime_ns();
709
710 /* Since the counter is in nano-seconds we use 1GHz frequency */
711 args->system_clock_freq = 1000000000;
712
713 return 0;
714 }
715
716
kfd_ioctl_get_process_apertures(struct file * filp,struct kfd_process * p,void * data)717 static int kfd_ioctl_get_process_apertures(struct file *filp,
718 struct kfd_process *p, void *data)
719 {
720 struct kfd_ioctl_get_process_apertures_args *args = data;
721 struct kfd_process_device_apertures *pAperture;
722 int i;
723
724 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
725
726 args->num_of_nodes = 0;
727
728 mutex_lock(&p->mutex);
729 /* Run over all pdd of the process */
730 for (i = 0; i < p->n_pdds; i++) {
731 struct kfd_process_device *pdd = p->pdds[i];
732
733 pAperture =
734 &args->process_apertures[args->num_of_nodes];
735 pAperture->gpu_id = pdd->dev->id;
736 pAperture->lds_base = pdd->lds_base;
737 pAperture->lds_limit = pdd->lds_limit;
738 pAperture->gpuvm_base = pdd->gpuvm_base;
739 pAperture->gpuvm_limit = pdd->gpuvm_limit;
740 pAperture->scratch_base = pdd->scratch_base;
741 pAperture->scratch_limit = pdd->scratch_limit;
742
743 dev_dbg(kfd_device,
744 "node id %u\n", args->num_of_nodes);
745 dev_dbg(kfd_device,
746 "gpu id %u\n", pdd->dev->id);
747 dev_dbg(kfd_device,
748 "lds_base %llX\n", pdd->lds_base);
749 dev_dbg(kfd_device,
750 "lds_limit %llX\n", pdd->lds_limit);
751 dev_dbg(kfd_device,
752 "gpuvm_base %llX\n", pdd->gpuvm_base);
753 dev_dbg(kfd_device,
754 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
755 dev_dbg(kfd_device,
756 "scratch_base %llX\n", pdd->scratch_base);
757 dev_dbg(kfd_device,
758 "scratch_limit %llX\n", pdd->scratch_limit);
759
760 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS)
761 break;
762 }
763 mutex_unlock(&p->mutex);
764
765 return 0;
766 }
767
kfd_ioctl_get_process_apertures_new(struct file * filp,struct kfd_process * p,void * data)768 static int kfd_ioctl_get_process_apertures_new(struct file *filp,
769 struct kfd_process *p, void *data)
770 {
771 struct kfd_ioctl_get_process_apertures_new_args *args = data;
772 struct kfd_process_device_apertures *pa;
773 int ret;
774 int i;
775
776 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
777
778 if (args->num_of_nodes == 0) {
779 /* Return number of nodes, so that user space can alloacate
780 * sufficient memory
781 */
782 mutex_lock(&p->mutex);
783 args->num_of_nodes = p->n_pdds;
784 goto out_unlock;
785 }
786
787 /* Fill in process-aperture information for all available
788 * nodes, but not more than args->num_of_nodes as that is
789 * the amount of memory allocated by user
790 */
791 pa = kcalloc(args->num_of_nodes, sizeof(struct kfd_process_device_apertures),
792 GFP_KERNEL);
793 if (!pa)
794 return -ENOMEM;
795
796 mutex_lock(&p->mutex);
797
798 if (!p->n_pdds) {
799 args->num_of_nodes = 0;
800 kfree(pa);
801 goto out_unlock;
802 }
803
804 /* Run over all pdd of the process */
805 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) {
806 struct kfd_process_device *pdd = p->pdds[i];
807
808 pa[i].gpu_id = pdd->dev->id;
809 pa[i].lds_base = pdd->lds_base;
810 pa[i].lds_limit = pdd->lds_limit;
811 pa[i].gpuvm_base = pdd->gpuvm_base;
812 pa[i].gpuvm_limit = pdd->gpuvm_limit;
813 pa[i].scratch_base = pdd->scratch_base;
814 pa[i].scratch_limit = pdd->scratch_limit;
815
816 dev_dbg(kfd_device,
817 "gpu id %u\n", pdd->dev->id);
818 dev_dbg(kfd_device,
819 "lds_base %llX\n", pdd->lds_base);
820 dev_dbg(kfd_device,
821 "lds_limit %llX\n", pdd->lds_limit);
822 dev_dbg(kfd_device,
823 "gpuvm_base %llX\n", pdd->gpuvm_base);
824 dev_dbg(kfd_device,
825 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
826 dev_dbg(kfd_device,
827 "scratch_base %llX\n", pdd->scratch_base);
828 dev_dbg(kfd_device,
829 "scratch_limit %llX\n", pdd->scratch_limit);
830 }
831 mutex_unlock(&p->mutex);
832
833 args->num_of_nodes = i;
834 ret = copy_to_user(
835 (void __user *)args->kfd_process_device_apertures_ptr,
836 pa,
837 (i * sizeof(struct kfd_process_device_apertures)));
838 kfree(pa);
839 return ret ? -EFAULT : 0;
840
841 out_unlock:
842 mutex_unlock(&p->mutex);
843 return 0;
844 }
845
kfd_ioctl_create_event(struct file * filp,struct kfd_process * p,void * data)846 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
847 void *data)
848 {
849 struct kfd_ioctl_create_event_args *args = data;
850 int err;
851
852 /* For dGPUs the event page is allocated in user mode. The
853 * handle is passed to KFD with the first call to this IOCTL
854 * through the event_page_offset field.
855 */
856 if (args->event_page_offset) {
857 mutex_lock(&p->mutex);
858 err = kfd_kmap_event_page(p, args->event_page_offset);
859 mutex_unlock(&p->mutex);
860 if (err)
861 return err;
862 }
863
864 err = kfd_event_create(filp, p, args->event_type,
865 args->auto_reset != 0, args->node_id,
866 &args->event_id, &args->event_trigger_data,
867 &args->event_page_offset,
868 &args->event_slot_index);
869
870 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__);
871 return err;
872 }
873
kfd_ioctl_destroy_event(struct file * filp,struct kfd_process * p,void * data)874 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
875 void *data)
876 {
877 struct kfd_ioctl_destroy_event_args *args = data;
878
879 return kfd_event_destroy(p, args->event_id);
880 }
881
kfd_ioctl_set_event(struct file * filp,struct kfd_process * p,void * data)882 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
883 void *data)
884 {
885 struct kfd_ioctl_set_event_args *args = data;
886
887 return kfd_set_event(p, args->event_id);
888 }
889
kfd_ioctl_reset_event(struct file * filp,struct kfd_process * p,void * data)890 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
891 void *data)
892 {
893 struct kfd_ioctl_reset_event_args *args = data;
894
895 return kfd_reset_event(p, args->event_id);
896 }
897
kfd_ioctl_wait_events(struct file * filp,struct kfd_process * p,void * data)898 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
899 void *data)
900 {
901 struct kfd_ioctl_wait_events_args *args = data;
902
903 return kfd_wait_on_events(p, args->num_events,
904 (void __user *)args->events_ptr,
905 (args->wait_for_all != 0),
906 &args->timeout, &args->wait_result);
907 }
kfd_ioctl_set_scratch_backing_va(struct file * filep,struct kfd_process * p,void * data)908 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
909 struct kfd_process *p, void *data)
910 {
911 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
912 struct kfd_process_device *pdd;
913 struct kfd_node *dev;
914 long err;
915
916 mutex_lock(&p->mutex);
917 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
918 if (!pdd) {
919 err = -EINVAL;
920 goto err_pdd;
921 }
922 dev = pdd->dev;
923
924 pdd = kfd_bind_process_to_device(dev, p);
925 if (IS_ERR(pdd)) {
926 err = PTR_ERR(pdd);
927 goto bind_process_to_device_fail;
928 }
929
930 pdd->qpd.sh_hidden_private_base = args->va_addr;
931
932 mutex_unlock(&p->mutex);
933
934 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
935 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va)
936 dev->kfd2kgd->set_scratch_backing_va(
937 dev->adev, args->va_addr, pdd->qpd.vmid);
938
939 return 0;
940
941 bind_process_to_device_fail:
942 err_pdd:
943 mutex_unlock(&p->mutex);
944 return err;
945 }
946
kfd_ioctl_get_tile_config(struct file * filep,struct kfd_process * p,void * data)947 static int kfd_ioctl_get_tile_config(struct file *filep,
948 struct kfd_process *p, void *data)
949 {
950 struct kfd_ioctl_get_tile_config_args *args = data;
951 struct kfd_process_device *pdd;
952 struct tile_config config;
953 int err = 0;
954
955 mutex_lock(&p->mutex);
956 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
957 mutex_unlock(&p->mutex);
958 if (!pdd)
959 return -EINVAL;
960
961 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config);
962
963 args->gb_addr_config = config.gb_addr_config;
964 args->num_banks = config.num_banks;
965 args->num_ranks = config.num_ranks;
966
967 if (args->num_tile_configs > config.num_tile_configs)
968 args->num_tile_configs = config.num_tile_configs;
969 err = copy_to_user((void __user *)args->tile_config_ptr,
970 config.tile_config_ptr,
971 args->num_tile_configs * sizeof(uint32_t));
972 if (err) {
973 args->num_tile_configs = 0;
974 return -EFAULT;
975 }
976
977 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
978 args->num_macro_tile_configs =
979 config.num_macro_tile_configs;
980 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
981 config.macro_tile_config_ptr,
982 args->num_macro_tile_configs * sizeof(uint32_t));
983 if (err) {
984 args->num_macro_tile_configs = 0;
985 return -EFAULT;
986 }
987
988 return 0;
989 }
990
kfd_ioctl_acquire_vm(struct file * filep,struct kfd_process * p,void * data)991 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
992 void *data)
993 {
994 struct kfd_ioctl_acquire_vm_args *args = data;
995 struct kfd_process_device *pdd;
996 struct file *drm_file;
997 int ret;
998
999 drm_file = fget(args->drm_fd);
1000 if (!drm_file)
1001 return -EINVAL;
1002
1003 mutex_lock(&p->mutex);
1004 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1005 if (!pdd) {
1006 ret = -EINVAL;
1007 goto err_pdd;
1008 }
1009
1010 if (pdd->drm_file) {
1011 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
1012 goto err_drm_file;
1013 }
1014
1015 ret = kfd_process_device_init_vm(pdd, drm_file);
1016 if (ret)
1017 goto err_unlock;
1018
1019 /* On success, the PDD keeps the drm_file reference */
1020 mutex_unlock(&p->mutex);
1021
1022 return 0;
1023
1024 err_unlock:
1025 err_pdd:
1026 err_drm_file:
1027 mutex_unlock(&p->mutex);
1028 fput(drm_file);
1029 return ret;
1030 }
1031
kfd_dev_is_large_bar(struct kfd_node * dev)1032 bool kfd_dev_is_large_bar(struct kfd_node *dev)
1033 {
1034 if (debug_largebar) {
1035 pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1036 return true;
1037 }
1038
1039 if (dev->local_mem_info.local_mem_size_private == 0 &&
1040 dev->local_mem_info.local_mem_size_public > 0)
1041 return true;
1042
1043 if (dev->local_mem_info.local_mem_size_public == 0 &&
1044 dev->kfd->adev->gmc.is_app_apu) {
1045 pr_debug("APP APU, Consider like a large bar system\n");
1046 return true;
1047 }
1048
1049 return false;
1050 }
1051
kfd_ioctl_get_available_memory(struct file * filep,struct kfd_process * p,void * data)1052 static int kfd_ioctl_get_available_memory(struct file *filep,
1053 struct kfd_process *p, void *data)
1054 {
1055 struct kfd_ioctl_get_available_memory_args *args = data;
1056 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id);
1057
1058 if (!pdd)
1059 return -EINVAL;
1060 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev,
1061 pdd->dev->node_id);
1062 kfd_unlock_pdd(pdd);
1063 return 0;
1064 }
1065
kfd_ioctl_alloc_memory_of_gpu(struct file * filep,struct kfd_process * p,void * data)1066 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1067 struct kfd_process *p, void *data)
1068 {
1069 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1070 struct kfd_process_device *pdd;
1071 void *mem;
1072 struct kfd_node *dev;
1073 int idr_handle;
1074 long err;
1075 uint64_t offset = args->mmap_offset;
1076 uint32_t flags = args->flags;
1077
1078 if (args->size == 0)
1079 return -EINVAL;
1080
1081 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1082 /* Flush pending deferred work to avoid racing with deferred actions
1083 * from previous memory map changes (e.g. munmap).
1084 */
1085 svm_range_list_lock_and_flush_work(&p->svms, current->mm);
1086 mutex_lock(&p->svms.lock);
1087 mmap_write_unlock(current->mm);
1088 if (interval_tree_iter_first(&p->svms.objects,
1089 args->va_addr >> PAGE_SHIFT,
1090 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) {
1091 pr_err("Address: 0x%llx already allocated by SVM\n",
1092 args->va_addr);
1093 mutex_unlock(&p->svms.lock);
1094 return -EADDRINUSE;
1095 }
1096
1097 /* When register user buffer check if it has been registered by svm by
1098 * buffer cpu virtual address.
1099 */
1100 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) &&
1101 interval_tree_iter_first(&p->svms.objects,
1102 args->mmap_offset >> PAGE_SHIFT,
1103 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) {
1104 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n",
1105 args->mmap_offset);
1106 mutex_unlock(&p->svms.lock);
1107 return -EADDRINUSE;
1108 }
1109
1110 mutex_unlock(&p->svms.lock);
1111 #endif
1112 mutex_lock(&p->mutex);
1113 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1114 if (!pdd) {
1115 err = -EINVAL;
1116 goto err_pdd;
1117 }
1118
1119 dev = pdd->dev;
1120
1121 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1122 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1123 !kfd_dev_is_large_bar(dev)) {
1124 pr_err("Alloc host visible vram on small bar is not allowed\n");
1125 err = -EINVAL;
1126 goto err_large_bar;
1127 }
1128
1129 pdd = kfd_bind_process_to_device(dev, p);
1130 if (IS_ERR(pdd)) {
1131 err = PTR_ERR(pdd);
1132 goto err_unlock;
1133 }
1134
1135 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
1136 if (args->size != kfd_doorbell_process_slice(dev->kfd)) {
1137 err = -EINVAL;
1138 goto err_unlock;
1139 }
1140 offset = kfd_get_process_doorbells(pdd);
1141 if (!offset) {
1142 err = -ENOMEM;
1143 goto err_unlock;
1144 }
1145 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1146 if (args->size != PAGE_SIZE) {
1147 err = -EINVAL;
1148 goto err_unlock;
1149 }
1150 offset = dev->adev->rmmio_remap.bus_addr;
1151 if (!offset || (PAGE_SIZE > 4096)) {
1152 err = -ENOMEM;
1153 goto err_unlock;
1154 }
1155 }
1156
1157 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1158 dev->adev, args->va_addr, args->size,
1159 pdd->drm_priv, (struct kgd_mem **) &mem, &offset,
1160 flags, false);
1161
1162 if (err)
1163 goto err_unlock;
1164
1165 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1166 if (idr_handle < 0) {
1167 err = -EFAULT;
1168 goto err_free;
1169 }
1170
1171 /* Update the VRAM usage count */
1172 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1173 uint64_t size = args->size;
1174
1175 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM)
1176 size >>= 1;
1177 atomic64_add(PAGE_ALIGN(size), &pdd->vram_usage);
1178 }
1179
1180 mutex_unlock(&p->mutex);
1181
1182 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1183 args->mmap_offset = offset;
1184
1185 /* MMIO is mapped through kfd device
1186 * Generate a kfd mmap offset
1187 */
1188 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1189 args->mmap_offset = KFD_MMAP_TYPE_MMIO
1190 | KFD_MMAP_GPU_ID(args->gpu_id);
1191
1192 return 0;
1193
1194 err_free:
1195 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem,
1196 pdd->drm_priv, NULL);
1197 err_unlock:
1198 err_pdd:
1199 err_large_bar:
1200 mutex_unlock(&p->mutex);
1201 return err;
1202 }
1203
kfd_ioctl_free_memory_of_gpu(struct file * filep,struct kfd_process * p,void * data)1204 static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1205 struct kfd_process *p, void *data)
1206 {
1207 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1208 struct kfd_process_device *pdd;
1209 void *mem;
1210 int ret;
1211 uint64_t size = 0;
1212
1213 mutex_lock(&p->mutex);
1214 /*
1215 * Safeguard to prevent user space from freeing signal BO.
1216 * It will be freed at process termination.
1217 */
1218 if (p->signal_handle && (p->signal_handle == args->handle)) {
1219 pr_err("Free signal BO is not allowed\n");
1220 ret = -EPERM;
1221 goto err_unlock;
1222 }
1223
1224 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1225 if (!pdd) {
1226 pr_err("Process device data doesn't exist\n");
1227 ret = -EINVAL;
1228 goto err_pdd;
1229 }
1230
1231 mem = kfd_process_device_translate_handle(
1232 pdd, GET_IDR_HANDLE(args->handle));
1233 if (!mem) {
1234 ret = -EINVAL;
1235 goto err_unlock;
1236 }
1237
1238 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev,
1239 (struct kgd_mem *)mem, pdd->drm_priv, &size);
1240
1241 /* If freeing the buffer failed, leave the handle in place for
1242 * clean-up during process tear-down.
1243 */
1244 if (!ret)
1245 kfd_process_device_remove_obj_handle(
1246 pdd, GET_IDR_HANDLE(args->handle));
1247
1248 atomic64_sub(size, &pdd->vram_usage);
1249
1250 err_unlock:
1251 err_pdd:
1252 mutex_unlock(&p->mutex);
1253 return ret;
1254 }
1255
kfd_ioctl_map_memory_to_gpu(struct file * filep,struct kfd_process * p,void * data)1256 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1257 struct kfd_process *p, void *data)
1258 {
1259 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1260 struct kfd_process_device *pdd, *peer_pdd;
1261 void *mem;
1262 struct kfd_node *dev;
1263 long err = 0;
1264 int i;
1265 uint32_t *devices_arr = NULL;
1266
1267 if (!args->n_devices) {
1268 pr_debug("Device IDs array empty\n");
1269 return -EINVAL;
1270 }
1271 if (args->n_success > args->n_devices) {
1272 pr_debug("n_success exceeds n_devices\n");
1273 return -EINVAL;
1274 }
1275
1276 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1277 GFP_KERNEL);
1278 if (!devices_arr)
1279 return -ENOMEM;
1280
1281 err = copy_from_user(devices_arr,
1282 (void __user *)args->device_ids_array_ptr,
1283 args->n_devices * sizeof(*devices_arr));
1284 if (err != 0) {
1285 err = -EFAULT;
1286 goto copy_from_user_failed;
1287 }
1288
1289 mutex_lock(&p->mutex);
1290 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1291 if (!pdd) {
1292 err = -EINVAL;
1293 goto get_process_device_data_failed;
1294 }
1295 dev = pdd->dev;
1296
1297 pdd = kfd_bind_process_to_device(dev, p);
1298 if (IS_ERR(pdd)) {
1299 err = PTR_ERR(pdd);
1300 goto bind_process_to_device_failed;
1301 }
1302
1303 mem = kfd_process_device_translate_handle(pdd,
1304 GET_IDR_HANDLE(args->handle));
1305 if (!mem) {
1306 err = -ENOMEM;
1307 goto get_mem_obj_from_handle_failed;
1308 }
1309
1310 for (i = args->n_success; i < args->n_devices; i++) {
1311 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1312 if (!peer_pdd) {
1313 pr_debug("Getting device by id failed for 0x%x\n",
1314 devices_arr[i]);
1315 err = -EINVAL;
1316 goto get_mem_obj_from_handle_failed;
1317 }
1318
1319 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p);
1320 if (IS_ERR(peer_pdd)) {
1321 err = PTR_ERR(peer_pdd);
1322 goto get_mem_obj_from_handle_failed;
1323 }
1324
1325 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1326 peer_pdd->dev->adev, (struct kgd_mem *)mem,
1327 peer_pdd->drm_priv);
1328 if (err) {
1329 struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
1330
1331 dev_err(dev->adev->dev,
1332 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n",
1333 pci_domain_nr(pdev->bus),
1334 pdev->bus->number,
1335 PCI_SLOT(pdev->devfn),
1336 PCI_FUNC(pdev->devfn),
1337 ((struct kgd_mem *)mem)->domain);
1338 goto map_memory_to_gpu_failed;
1339 }
1340 args->n_success = i+1;
1341 }
1342
1343 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true);
1344 if (err) {
1345 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1346 goto sync_memory_failed;
1347 }
1348
1349 mutex_unlock(&p->mutex);
1350
1351 /* Flush TLBs after waiting for the page table updates to complete */
1352 for (i = 0; i < args->n_devices; i++) {
1353 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1354 if (WARN_ON_ONCE(!peer_pdd))
1355 continue;
1356 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
1357 }
1358 kfree(devices_arr);
1359
1360 return err;
1361
1362 get_process_device_data_failed:
1363 bind_process_to_device_failed:
1364 get_mem_obj_from_handle_failed:
1365 map_memory_to_gpu_failed:
1366 sync_memory_failed:
1367 mutex_unlock(&p->mutex);
1368 copy_from_user_failed:
1369 kfree(devices_arr);
1370
1371 return err;
1372 }
1373
kfd_ioctl_unmap_memory_from_gpu(struct file * filep,struct kfd_process * p,void * data)1374 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1375 struct kfd_process *p, void *data)
1376 {
1377 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1378 struct kfd_process_device *pdd, *peer_pdd;
1379 void *mem;
1380 long err = 0;
1381 uint32_t *devices_arr = NULL, i;
1382 bool flush_tlb;
1383
1384 if (!args->n_devices) {
1385 pr_debug("Device IDs array empty\n");
1386 return -EINVAL;
1387 }
1388 if (args->n_success > args->n_devices) {
1389 pr_debug("n_success exceeds n_devices\n");
1390 return -EINVAL;
1391 }
1392
1393 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1394 GFP_KERNEL);
1395 if (!devices_arr)
1396 return -ENOMEM;
1397
1398 err = copy_from_user(devices_arr,
1399 (void __user *)args->device_ids_array_ptr,
1400 args->n_devices * sizeof(*devices_arr));
1401 if (err != 0) {
1402 err = -EFAULT;
1403 goto copy_from_user_failed;
1404 }
1405
1406 mutex_lock(&p->mutex);
1407 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1408 if (!pdd) {
1409 err = -EINVAL;
1410 goto bind_process_to_device_failed;
1411 }
1412
1413 mem = kfd_process_device_translate_handle(pdd,
1414 GET_IDR_HANDLE(args->handle));
1415 if (!mem) {
1416 err = -ENOMEM;
1417 goto get_mem_obj_from_handle_failed;
1418 }
1419
1420 for (i = args->n_success; i < args->n_devices; i++) {
1421 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1422 if (!peer_pdd) {
1423 err = -EINVAL;
1424 goto get_mem_obj_from_handle_failed;
1425 }
1426 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1427 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv);
1428 if (err) {
1429 pr_err("Failed to unmap from gpu %d/%d\n",
1430 i, args->n_devices);
1431 goto unmap_memory_from_gpu_failed;
1432 }
1433 args->n_success = i+1;
1434 }
1435
1436 flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd);
1437 if (flush_tlb) {
1438 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev,
1439 (struct kgd_mem *) mem, true);
1440 if (err) {
1441 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1442 goto sync_memory_failed;
1443 }
1444 }
1445
1446 /* Flush TLBs after waiting for the page table updates to complete */
1447 for (i = 0; i < args->n_devices; i++) {
1448 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1449 if (WARN_ON_ONCE(!peer_pdd))
1450 continue;
1451 if (flush_tlb)
1452 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
1453
1454 /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */
1455 err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv);
1456 if (err)
1457 goto sync_memory_failed;
1458 }
1459
1460 mutex_unlock(&p->mutex);
1461
1462 kfree(devices_arr);
1463
1464 return 0;
1465
1466 bind_process_to_device_failed:
1467 get_mem_obj_from_handle_failed:
1468 unmap_memory_from_gpu_failed:
1469 sync_memory_failed:
1470 mutex_unlock(&p->mutex);
1471 copy_from_user_failed:
1472 kfree(devices_arr);
1473 return err;
1474 }
1475
kfd_ioctl_alloc_queue_gws(struct file * filep,struct kfd_process * p,void * data)1476 static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1477 struct kfd_process *p, void *data)
1478 {
1479 int retval;
1480 struct kfd_ioctl_alloc_queue_gws_args *args = data;
1481 struct queue *q;
1482 struct kfd_node *dev;
1483
1484 mutex_lock(&p->mutex);
1485 q = pqm_get_user_queue(&p->pqm, args->queue_id);
1486
1487 if (q) {
1488 dev = q->device;
1489 } else {
1490 retval = -EINVAL;
1491 goto out_unlock;
1492 }
1493
1494 if (!dev->gws) {
1495 retval = -ENODEV;
1496 goto out_unlock;
1497 }
1498
1499 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
1500 retval = -ENODEV;
1501 goto out_unlock;
1502 }
1503
1504 if (p->debug_trap_enabled && (!kfd_dbg_has_gws_support(dev) ||
1505 kfd_dbg_has_cwsr_workaround(dev))) {
1506 retval = -EBUSY;
1507 goto out_unlock;
1508 }
1509
1510 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1511 mutex_unlock(&p->mutex);
1512
1513 args->first_gws = 0;
1514 return retval;
1515
1516 out_unlock:
1517 mutex_unlock(&p->mutex);
1518 return retval;
1519 }
1520
kfd_ioctl_get_dmabuf_info(struct file * filep,struct kfd_process * p,void * data)1521 static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1522 struct kfd_process *p, void *data)
1523 {
1524 struct kfd_ioctl_get_dmabuf_info_args *args = data;
1525 struct kfd_node *dev = NULL;
1526 struct amdgpu_device *dmabuf_adev;
1527 void *metadata_buffer = NULL;
1528 uint32_t flags;
1529 int8_t xcp_id;
1530 unsigned int i;
1531 int r;
1532
1533 /* Find a KFD GPU device that supports the get_dmabuf_info query */
1534 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
1535 if (dev && !kfd_devcgroup_check_permission(dev))
1536 break;
1537 if (!dev)
1538 return -EINVAL;
1539
1540 if (args->metadata_ptr) {
1541 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1542 if (!metadata_buffer)
1543 return -ENOMEM;
1544 }
1545
1546 /* Get dmabuf info from KGD */
1547 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd,
1548 &dmabuf_adev, &args->size,
1549 metadata_buffer, args->metadata_size,
1550 &args->metadata_size, &flags, &xcp_id);
1551 if (r)
1552 goto exit;
1553
1554 if (xcp_id >= 0)
1555 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id;
1556 else
1557 args->gpu_id = dev->id;
1558 args->flags = flags;
1559
1560 /* Copy metadata buffer to user mode */
1561 if (metadata_buffer) {
1562 r = copy_to_user((void __user *)args->metadata_ptr,
1563 metadata_buffer, args->metadata_size);
1564 if (r != 0)
1565 r = -EFAULT;
1566 }
1567
1568 exit:
1569 kfree(metadata_buffer);
1570
1571 return r;
1572 }
1573
kfd_ioctl_import_dmabuf(struct file * filep,struct kfd_process * p,void * data)1574 static int kfd_ioctl_import_dmabuf(struct file *filep,
1575 struct kfd_process *p, void *data)
1576 {
1577 struct kfd_ioctl_import_dmabuf_args *args = data;
1578 struct kfd_process_device *pdd;
1579 struct dma_buf *dmabuf;
1580 int idr_handle;
1581 uint64_t size;
1582 void *mem;
1583 int r;
1584
1585 dmabuf = dma_buf_get(args->dmabuf_fd);
1586 if (IS_ERR(dmabuf))
1587 return PTR_ERR(dmabuf);
1588
1589 mutex_lock(&p->mutex);
1590 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1591 if (!pdd) {
1592 r = -EINVAL;
1593 goto err_unlock;
1594 }
1595
1596 pdd = kfd_bind_process_to_device(pdd->dev, p);
1597 if (IS_ERR(pdd)) {
1598 r = PTR_ERR(pdd);
1599 goto err_unlock;
1600 }
1601
1602 r = amdgpu_amdkfd_gpuvm_import_dmabuf(pdd->dev->adev, dmabuf,
1603 args->va_addr, pdd->drm_priv,
1604 (struct kgd_mem **)&mem, &size,
1605 NULL);
1606 if (r)
1607 goto err_unlock;
1608
1609 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1610 if (idr_handle < 0) {
1611 r = -EFAULT;
1612 goto err_free;
1613 }
1614
1615 mutex_unlock(&p->mutex);
1616 dma_buf_put(dmabuf);
1617
1618 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1619
1620 return 0;
1621
1622 err_free:
1623 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem,
1624 pdd->drm_priv, NULL);
1625 err_unlock:
1626 mutex_unlock(&p->mutex);
1627 dma_buf_put(dmabuf);
1628 return r;
1629 }
1630
kfd_ioctl_export_dmabuf(struct file * filep,struct kfd_process * p,void * data)1631 static int kfd_ioctl_export_dmabuf(struct file *filep,
1632 struct kfd_process *p, void *data)
1633 {
1634 struct kfd_ioctl_export_dmabuf_args *args = data;
1635 struct kfd_process_device *pdd;
1636 struct dma_buf *dmabuf;
1637 struct kfd_node *dev;
1638 void *mem;
1639 int ret = 0;
1640
1641 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1642 if (!dev)
1643 return -EINVAL;
1644
1645 mutex_lock(&p->mutex);
1646
1647 pdd = kfd_get_process_device_data(dev, p);
1648 if (!pdd) {
1649 ret = -EINVAL;
1650 goto err_unlock;
1651 }
1652
1653 mem = kfd_process_device_translate_handle(pdd,
1654 GET_IDR_HANDLE(args->handle));
1655 if (!mem) {
1656 ret = -EINVAL;
1657 goto err_unlock;
1658 }
1659
1660 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf);
1661 mutex_unlock(&p->mutex);
1662 if (ret)
1663 goto err_out;
1664
1665 ret = dma_buf_fd(dmabuf, args->flags);
1666 if (ret < 0) {
1667 dma_buf_put(dmabuf);
1668 goto err_out;
1669 }
1670 /* dma_buf_fd assigns the reference count to the fd, no need to
1671 * put the reference here.
1672 */
1673 args->dmabuf_fd = ret;
1674
1675 return 0;
1676
1677 err_unlock:
1678 mutex_unlock(&p->mutex);
1679 err_out:
1680 return ret;
1681 }
1682
1683 /* Handle requests for watching SMI events */
kfd_ioctl_smi_events(struct file * filep,struct kfd_process * p,void * data)1684 static int kfd_ioctl_smi_events(struct file *filep,
1685 struct kfd_process *p, void *data)
1686 {
1687 struct kfd_ioctl_smi_events_args *args = data;
1688 struct kfd_process_device *pdd;
1689
1690 mutex_lock(&p->mutex);
1691
1692 pdd = kfd_process_device_data_by_id(p, args->gpuid);
1693 mutex_unlock(&p->mutex);
1694 if (!pdd)
1695 return -EINVAL;
1696
1697 return kfd_smi_event_open(pdd->dev, &args->anon_fd);
1698 }
1699
1700 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1701
kfd_ioctl_set_xnack_mode(struct file * filep,struct kfd_process * p,void * data)1702 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1703 struct kfd_process *p, void *data)
1704 {
1705 struct kfd_ioctl_set_xnack_mode_args *args = data;
1706 int r = 0;
1707
1708 mutex_lock(&p->mutex);
1709 if (args->xnack_enabled >= 0) {
1710 if (!list_empty(&p->pqm.queues)) {
1711 pr_debug("Process has user queues running\n");
1712 r = -EBUSY;
1713 goto out_unlock;
1714 }
1715
1716 if (p->xnack_enabled == args->xnack_enabled)
1717 goto out_unlock;
1718
1719 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) {
1720 r = -EPERM;
1721 goto out_unlock;
1722 }
1723
1724 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled);
1725 } else {
1726 args->xnack_enabled = p->xnack_enabled;
1727 }
1728
1729 out_unlock:
1730 mutex_unlock(&p->mutex);
1731
1732 return r;
1733 }
1734
kfd_ioctl_svm(struct file * filep,struct kfd_process * p,void * data)1735 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1736 {
1737 struct kfd_ioctl_svm_args *args = data;
1738 int r = 0;
1739
1740 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n",
1741 args->start_addr, args->size, args->op, args->nattr);
1742
1743 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK))
1744 return -EINVAL;
1745 if (!args->start_addr || !args->size)
1746 return -EINVAL;
1747
1748 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr,
1749 args->attrs);
1750
1751 return r;
1752 }
1753 #else
kfd_ioctl_set_xnack_mode(struct file * filep,struct kfd_process * p,void * data)1754 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1755 struct kfd_process *p, void *data)
1756 {
1757 return -EPERM;
1758 }
kfd_ioctl_svm(struct file * filep,struct kfd_process * p,void * data)1759 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1760 {
1761 return -EPERM;
1762 }
1763 #endif
1764
criu_checkpoint_process(struct kfd_process * p,uint8_t __user * user_priv_data,uint64_t * priv_offset)1765 static int criu_checkpoint_process(struct kfd_process *p,
1766 uint8_t __user *user_priv_data,
1767 uint64_t *priv_offset)
1768 {
1769 struct kfd_criu_process_priv_data process_priv;
1770 int ret;
1771
1772 memset(&process_priv, 0, sizeof(process_priv));
1773
1774 process_priv.version = KFD_CRIU_PRIV_VERSION;
1775 /* For CR, we don't consider negative xnack mode which is used for
1776 * querying without changing it, here 0 simply means disabled and 1
1777 * means enabled so retry for finding a valid PTE.
1778 */
1779 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0;
1780
1781 ret = copy_to_user(user_priv_data + *priv_offset,
1782 &process_priv, sizeof(process_priv));
1783
1784 if (ret) {
1785 pr_err("Failed to copy process information to user\n");
1786 ret = -EFAULT;
1787 }
1788
1789 *priv_offset += sizeof(process_priv);
1790 return ret;
1791 }
1792
criu_checkpoint_devices(struct kfd_process * p,uint32_t num_devices,uint8_t __user * user_addr,uint8_t __user * user_priv_data,uint64_t * priv_offset)1793 static int criu_checkpoint_devices(struct kfd_process *p,
1794 uint32_t num_devices,
1795 uint8_t __user *user_addr,
1796 uint8_t __user *user_priv_data,
1797 uint64_t *priv_offset)
1798 {
1799 struct kfd_criu_device_priv_data *device_priv = NULL;
1800 struct kfd_criu_device_bucket *device_buckets = NULL;
1801 int ret = 0, i;
1802
1803 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL);
1804 if (!device_buckets) {
1805 ret = -ENOMEM;
1806 goto exit;
1807 }
1808
1809 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL);
1810 if (!device_priv) {
1811 ret = -ENOMEM;
1812 goto exit;
1813 }
1814
1815 for (i = 0; i < num_devices; i++) {
1816 struct kfd_process_device *pdd = p->pdds[i];
1817
1818 device_buckets[i].user_gpu_id = pdd->user_gpu_id;
1819 device_buckets[i].actual_gpu_id = pdd->dev->id;
1820
1821 /*
1822 * priv_data does not contain useful information for now and is reserved for
1823 * future use, so we do not set its contents.
1824 */
1825 }
1826
1827 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets));
1828 if (ret) {
1829 pr_err("Failed to copy device information to user\n");
1830 ret = -EFAULT;
1831 goto exit;
1832 }
1833
1834 ret = copy_to_user(user_priv_data + *priv_offset,
1835 device_priv,
1836 num_devices * sizeof(*device_priv));
1837 if (ret) {
1838 pr_err("Failed to copy device information to user\n");
1839 ret = -EFAULT;
1840 }
1841 *priv_offset += num_devices * sizeof(*device_priv);
1842
1843 exit:
1844 kvfree(device_buckets);
1845 kvfree(device_priv);
1846 return ret;
1847 }
1848
get_process_num_bos(struct kfd_process * p)1849 static uint32_t get_process_num_bos(struct kfd_process *p)
1850 {
1851 uint32_t num_of_bos = 0;
1852 int i;
1853
1854 /* Run over all PDDs of the process */
1855 for (i = 0; i < p->n_pdds; i++) {
1856 struct kfd_process_device *pdd = p->pdds[i];
1857 void *mem;
1858 int id;
1859
1860 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1861 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
1862
1863 if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base)
1864 num_of_bos++;
1865 }
1866 }
1867 return num_of_bos;
1868 }
1869
criu_get_prime_handle(struct kgd_mem * mem,int flags,u32 * shared_fd)1870 static int criu_get_prime_handle(struct kgd_mem *mem, int flags,
1871 u32 *shared_fd)
1872 {
1873 struct dma_buf *dmabuf;
1874 int ret;
1875
1876 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf);
1877 if (ret) {
1878 pr_err("dmabuf export failed for the BO\n");
1879 return ret;
1880 }
1881
1882 ret = dma_buf_fd(dmabuf, flags);
1883 if (ret < 0) {
1884 pr_err("dmabuf create fd failed, ret:%d\n", ret);
1885 goto out_free_dmabuf;
1886 }
1887
1888 *shared_fd = ret;
1889 return 0;
1890
1891 out_free_dmabuf:
1892 dma_buf_put(dmabuf);
1893 return ret;
1894 }
1895
criu_checkpoint_bos(struct kfd_process * p,uint32_t num_bos,uint8_t __user * user_bos,uint8_t __user * user_priv_data,uint64_t * priv_offset)1896 static int criu_checkpoint_bos(struct kfd_process *p,
1897 uint32_t num_bos,
1898 uint8_t __user *user_bos,
1899 uint8_t __user *user_priv_data,
1900 uint64_t *priv_offset)
1901 {
1902 struct kfd_criu_bo_bucket *bo_buckets;
1903 struct kfd_criu_bo_priv_data *bo_privs;
1904 int ret = 0, pdd_index, bo_index = 0, id;
1905 void *mem;
1906
1907 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL);
1908 if (!bo_buckets)
1909 return -ENOMEM;
1910
1911 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL);
1912 if (!bo_privs) {
1913 ret = -ENOMEM;
1914 goto exit;
1915 }
1916
1917 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
1918 struct kfd_process_device *pdd = p->pdds[pdd_index];
1919 struct amdgpu_bo *dumper_bo;
1920 struct kgd_mem *kgd_mem;
1921
1922 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1923 struct kfd_criu_bo_bucket *bo_bucket;
1924 struct kfd_criu_bo_priv_data *bo_priv;
1925 int i, dev_idx = 0;
1926
1927 if (!mem) {
1928 ret = -ENOMEM;
1929 goto exit;
1930 }
1931
1932 kgd_mem = (struct kgd_mem *)mem;
1933 dumper_bo = kgd_mem->bo;
1934
1935 /* Skip checkpointing BOs that are used for Trap handler
1936 * code and state. Currently, these BOs have a VA that
1937 * is less GPUVM Base
1938 */
1939 if (kgd_mem->va && kgd_mem->va <= pdd->gpuvm_base)
1940 continue;
1941
1942 bo_bucket = &bo_buckets[bo_index];
1943 bo_priv = &bo_privs[bo_index];
1944
1945 bo_bucket->gpu_id = pdd->user_gpu_id;
1946 bo_bucket->addr = (uint64_t)kgd_mem->va;
1947 bo_bucket->size = amdgpu_bo_size(dumper_bo);
1948 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags;
1949 bo_priv->idr_handle = id;
1950
1951 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1952 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo,
1953 &bo_priv->user_addr);
1954 if (ret) {
1955 pr_err("Failed to obtain user address for user-pointer bo\n");
1956 goto exit;
1957 }
1958 }
1959 if (bo_bucket->alloc_flags
1960 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
1961 ret = criu_get_prime_handle(kgd_mem,
1962 bo_bucket->alloc_flags &
1963 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0,
1964 &bo_bucket->dmabuf_fd);
1965 if (ret)
1966 goto exit;
1967 } else {
1968 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
1969 }
1970
1971 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
1972 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL |
1973 KFD_MMAP_GPU_ID(pdd->dev->id);
1974 else if (bo_bucket->alloc_flags &
1975 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1976 bo_bucket->offset = KFD_MMAP_TYPE_MMIO |
1977 KFD_MMAP_GPU_ID(pdd->dev->id);
1978 else
1979 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo);
1980
1981 for (i = 0; i < p->n_pdds; i++) {
1982 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->dev->adev, kgd_mem))
1983 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id;
1984 }
1985
1986 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n"
1987 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x",
1988 bo_bucket->size,
1989 bo_bucket->addr,
1990 bo_bucket->offset,
1991 bo_bucket->gpu_id,
1992 bo_bucket->alloc_flags,
1993 bo_priv->idr_handle);
1994 bo_index++;
1995 }
1996 }
1997
1998 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets));
1999 if (ret) {
2000 pr_err("Failed to copy BO information to user\n");
2001 ret = -EFAULT;
2002 goto exit;
2003 }
2004
2005 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs));
2006 if (ret) {
2007 pr_err("Failed to copy BO priv information to user\n");
2008 ret = -EFAULT;
2009 goto exit;
2010 }
2011
2012 *priv_offset += num_bos * sizeof(*bo_privs);
2013
2014 exit:
2015 while (ret && bo_index--) {
2016 if (bo_buckets[bo_index].alloc_flags
2017 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
2018 close_fd(bo_buckets[bo_index].dmabuf_fd);
2019 }
2020
2021 kvfree(bo_buckets);
2022 kvfree(bo_privs);
2023 return ret;
2024 }
2025
criu_get_process_object_info(struct kfd_process * p,uint32_t * num_devices,uint32_t * num_bos,uint32_t * num_objects,uint64_t * objs_priv_size)2026 static int criu_get_process_object_info(struct kfd_process *p,
2027 uint32_t *num_devices,
2028 uint32_t *num_bos,
2029 uint32_t *num_objects,
2030 uint64_t *objs_priv_size)
2031 {
2032 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size;
2033 uint32_t num_queues, num_events, num_svm_ranges;
2034 int ret;
2035
2036 *num_devices = p->n_pdds;
2037 *num_bos = get_process_num_bos(p);
2038
2039 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size);
2040 if (ret)
2041 return ret;
2042
2043 num_events = kfd_get_num_events(p);
2044
2045 ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size);
2046 if (ret)
2047 return ret;
2048
2049 *num_objects = num_queues + num_events + num_svm_ranges;
2050
2051 if (objs_priv_size) {
2052 priv_size = sizeof(struct kfd_criu_process_priv_data);
2053 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data);
2054 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data);
2055 priv_size += queues_priv_data_size;
2056 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data);
2057 priv_size += svm_priv_data_size;
2058 *objs_priv_size = priv_size;
2059 }
2060 return 0;
2061 }
2062
criu_checkpoint(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2063 static int criu_checkpoint(struct file *filep,
2064 struct kfd_process *p,
2065 struct kfd_ioctl_criu_args *args)
2066 {
2067 int ret;
2068 uint32_t num_devices, num_bos, num_objects;
2069 uint64_t priv_size, priv_offset = 0, bo_priv_offset;
2070
2071 if (!args->devices || !args->bos || !args->priv_data)
2072 return -EINVAL;
2073
2074 mutex_lock(&p->mutex);
2075
2076 if (!p->n_pdds) {
2077 pr_err("No pdd for given process\n");
2078 ret = -ENODEV;
2079 goto exit_unlock;
2080 }
2081
2082 /* Confirm all process queues are evicted */
2083 if (!p->queues_paused) {
2084 pr_err("Cannot dump process when queues are not in evicted state\n");
2085 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */
2086 ret = -EINVAL;
2087 goto exit_unlock;
2088 }
2089
2090 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size);
2091 if (ret)
2092 goto exit_unlock;
2093
2094 if (num_devices != args->num_devices ||
2095 num_bos != args->num_bos ||
2096 num_objects != args->num_objects ||
2097 priv_size != args->priv_data_size) {
2098
2099 ret = -EINVAL;
2100 goto exit_unlock;
2101 }
2102
2103 /* each function will store private data inside priv_data and adjust priv_offset */
2104 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset);
2105 if (ret)
2106 goto exit_unlock;
2107
2108 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices,
2109 (uint8_t __user *)args->priv_data, &priv_offset);
2110 if (ret)
2111 goto exit_unlock;
2112
2113 /* Leave room for BOs in the private data. They need to be restored
2114 * before events, but we checkpoint them last to simplify the error
2115 * handling.
2116 */
2117 bo_priv_offset = priv_offset;
2118 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data);
2119
2120 if (num_objects) {
2121 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
2122 &priv_offset);
2123 if (ret)
2124 goto exit_unlock;
2125
2126 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
2127 &priv_offset);
2128 if (ret)
2129 goto exit_unlock;
2130
2131 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
2132 if (ret)
2133 goto exit_unlock;
2134 }
2135
2136 /* This must be the last thing in this function that can fail.
2137 * Otherwise we leak dmabuf file descriptors.
2138 */
2139 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
2140 (uint8_t __user *)args->priv_data, &bo_priv_offset);
2141
2142 exit_unlock:
2143 mutex_unlock(&p->mutex);
2144 if (ret)
2145 pr_err("Failed to dump CRIU ret:%d\n", ret);
2146 else
2147 pr_debug("CRIU dump ret:%d\n", ret);
2148
2149 return ret;
2150 }
2151
criu_restore_process(struct kfd_process * p,struct kfd_ioctl_criu_args * args,uint64_t * priv_offset,uint64_t max_priv_data_size)2152 static int criu_restore_process(struct kfd_process *p,
2153 struct kfd_ioctl_criu_args *args,
2154 uint64_t *priv_offset,
2155 uint64_t max_priv_data_size)
2156 {
2157 int ret = 0;
2158 struct kfd_criu_process_priv_data process_priv;
2159
2160 if (*priv_offset + sizeof(process_priv) > max_priv_data_size)
2161 return -EINVAL;
2162
2163 ret = copy_from_user(&process_priv,
2164 (void __user *)(args->priv_data + *priv_offset),
2165 sizeof(process_priv));
2166 if (ret) {
2167 pr_err("Failed to copy process private information from user\n");
2168 ret = -EFAULT;
2169 goto exit;
2170 }
2171 *priv_offset += sizeof(process_priv);
2172
2173 if (process_priv.version != KFD_CRIU_PRIV_VERSION) {
2174 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n",
2175 process_priv.version, KFD_CRIU_PRIV_VERSION);
2176 return -EINVAL;
2177 }
2178
2179 pr_debug("Setting XNACK mode\n");
2180 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) {
2181 pr_err("xnack mode cannot be set\n");
2182 ret = -EPERM;
2183 goto exit;
2184 } else {
2185 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode);
2186 p->xnack_enabled = process_priv.xnack_mode;
2187 }
2188
2189 exit:
2190 return ret;
2191 }
2192
criu_restore_devices(struct kfd_process * p,struct kfd_ioctl_criu_args * args,uint64_t * priv_offset,uint64_t max_priv_data_size)2193 static int criu_restore_devices(struct kfd_process *p,
2194 struct kfd_ioctl_criu_args *args,
2195 uint64_t *priv_offset,
2196 uint64_t max_priv_data_size)
2197 {
2198 struct kfd_criu_device_bucket *device_buckets;
2199 struct kfd_criu_device_priv_data *device_privs;
2200 int ret = 0;
2201 uint32_t i;
2202
2203 if (args->num_devices != p->n_pdds)
2204 return -EINVAL;
2205
2206 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size)
2207 return -EINVAL;
2208
2209 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL);
2210 if (!device_buckets)
2211 return -ENOMEM;
2212
2213 ret = copy_from_user(device_buckets, (void __user *)args->devices,
2214 args->num_devices * sizeof(*device_buckets));
2215 if (ret) {
2216 pr_err("Failed to copy devices buckets from user\n");
2217 ret = -EFAULT;
2218 goto exit;
2219 }
2220
2221 for (i = 0; i < args->num_devices; i++) {
2222 struct kfd_node *dev;
2223 struct kfd_process_device *pdd;
2224 struct file *drm_file;
2225
2226 /* device private data is not currently used */
2227
2228 if (!device_buckets[i].user_gpu_id) {
2229 pr_err("Invalid user gpu_id\n");
2230 ret = -EINVAL;
2231 goto exit;
2232 }
2233
2234 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id);
2235 if (!dev) {
2236 pr_err("Failed to find device with gpu_id = %x\n",
2237 device_buckets[i].actual_gpu_id);
2238 ret = -EINVAL;
2239 goto exit;
2240 }
2241
2242 pdd = kfd_get_process_device_data(dev, p);
2243 if (!pdd) {
2244 pr_err("Failed to get pdd for gpu_id = %x\n",
2245 device_buckets[i].actual_gpu_id);
2246 ret = -EINVAL;
2247 goto exit;
2248 }
2249 pdd->user_gpu_id = device_buckets[i].user_gpu_id;
2250
2251 drm_file = fget(device_buckets[i].drm_fd);
2252 if (!drm_file) {
2253 pr_err("Invalid render node file descriptor sent from plugin (%d)\n",
2254 device_buckets[i].drm_fd);
2255 ret = -EINVAL;
2256 goto exit;
2257 }
2258
2259 if (pdd->drm_file) {
2260 ret = -EINVAL;
2261 goto exit;
2262 }
2263
2264 /* create the vm using render nodes for kfd pdd */
2265 if (kfd_process_device_init_vm(pdd, drm_file)) {
2266 pr_err("could not init vm for given pdd\n");
2267 /* On success, the PDD keeps the drm_file reference */
2268 fput(drm_file);
2269 ret = -EINVAL;
2270 goto exit;
2271 }
2272 /*
2273 * pdd now already has the vm bound to render node so below api won't create a new
2274 * exclusive kfd mapping but use existing one with renderDXXX but is still needed
2275 * for iommu v2 binding and runtime pm.
2276 */
2277 pdd = kfd_bind_process_to_device(dev, p);
2278 if (IS_ERR(pdd)) {
2279 ret = PTR_ERR(pdd);
2280 goto exit;
2281 }
2282
2283 if (!pdd->qpd.proc_doorbells) {
2284 ret = kfd_alloc_process_doorbells(dev->kfd, pdd);
2285 if (ret)
2286 goto exit;
2287 }
2288 }
2289
2290 /*
2291 * We are not copying device private data from user as we are not using the data for now,
2292 * but we still adjust for its private data.
2293 */
2294 *priv_offset += args->num_devices * sizeof(*device_privs);
2295
2296 exit:
2297 kfree(device_buckets);
2298 return ret;
2299 }
2300
criu_restore_memory_of_gpu(struct kfd_process_device * pdd,struct kfd_criu_bo_bucket * bo_bucket,struct kfd_criu_bo_priv_data * bo_priv,struct kgd_mem ** kgd_mem)2301 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,
2302 struct kfd_criu_bo_bucket *bo_bucket,
2303 struct kfd_criu_bo_priv_data *bo_priv,
2304 struct kgd_mem **kgd_mem)
2305 {
2306 int idr_handle;
2307 int ret;
2308 const bool criu_resume = true;
2309 u64 offset;
2310
2311 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
2312 if (bo_bucket->size !=
2313 kfd_doorbell_process_slice(pdd->dev->kfd))
2314 return -EINVAL;
2315
2316 offset = kfd_get_process_doorbells(pdd);
2317 if (!offset)
2318 return -ENOMEM;
2319 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2320 /* MMIO BOs need remapped bus address */
2321 if (bo_bucket->size != PAGE_SIZE) {
2322 pr_err("Invalid page size\n");
2323 return -EINVAL;
2324 }
2325 offset = pdd->dev->adev->rmmio_remap.bus_addr;
2326 if (!offset || (PAGE_SIZE > 4096)) {
2327 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
2328 return -ENOMEM;
2329 }
2330 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
2331 offset = bo_priv->user_addr;
2332 }
2333 /* Create the BO */
2334 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr,
2335 bo_bucket->size, pdd->drm_priv, kgd_mem,
2336 &offset, bo_bucket->alloc_flags, criu_resume);
2337 if (ret) {
2338 pr_err("Could not create the BO\n");
2339 return ret;
2340 }
2341 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n",
2342 bo_bucket->size, bo_bucket->addr, offset);
2343
2344 /* Restore previous IDR handle */
2345 pr_debug("Restoring old IDR handle for the BO");
2346 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle,
2347 bo_priv->idr_handle + 1, GFP_KERNEL);
2348
2349 if (idr_handle < 0) {
2350 pr_err("Could not allocate idr\n");
2351 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv,
2352 NULL);
2353 return -ENOMEM;
2354 }
2355
2356 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
2357 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id);
2358 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2359 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id);
2360 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
2361 bo_bucket->restored_offset = offset;
2362 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
2363 bo_bucket->restored_offset = offset;
2364 /* Update the VRAM usage count */
2365 atomic64_add(bo_bucket->size, &pdd->vram_usage);
2366 }
2367 return 0;
2368 }
2369
criu_restore_bo(struct kfd_process * p,struct kfd_criu_bo_bucket * bo_bucket,struct kfd_criu_bo_priv_data * bo_priv)2370 static int criu_restore_bo(struct kfd_process *p,
2371 struct kfd_criu_bo_bucket *bo_bucket,
2372 struct kfd_criu_bo_priv_data *bo_priv)
2373 {
2374 struct kfd_process_device *pdd;
2375 struct kgd_mem *kgd_mem;
2376 int ret;
2377 int j;
2378
2379 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n",
2380 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags,
2381 bo_priv->idr_handle);
2382
2383 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id);
2384 if (!pdd) {
2385 pr_err("Failed to get pdd\n");
2386 return -ENODEV;
2387 }
2388
2389 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem);
2390 if (ret)
2391 return ret;
2392
2393 /* now map these BOs to GPU/s */
2394 for (j = 0; j < p->n_pdds; j++) {
2395 struct kfd_node *peer;
2396 struct kfd_process_device *peer_pdd;
2397
2398 if (!bo_priv->mapped_gpuids[j])
2399 break;
2400
2401 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]);
2402 if (!peer_pdd)
2403 return -EINVAL;
2404
2405 peer = peer_pdd->dev;
2406
2407 peer_pdd = kfd_bind_process_to_device(peer, p);
2408 if (IS_ERR(peer_pdd))
2409 return PTR_ERR(peer_pdd);
2410
2411 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem,
2412 peer_pdd->drm_priv);
2413 if (ret) {
2414 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds);
2415 return ret;
2416 }
2417 }
2418
2419 pr_debug("map memory was successful for the BO\n");
2420 /* create the dmabuf object and export the bo */
2421 if (bo_bucket->alloc_flags
2422 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
2423 ret = criu_get_prime_handle(kgd_mem, DRM_RDWR,
2424 &bo_bucket->dmabuf_fd);
2425 if (ret)
2426 return ret;
2427 } else {
2428 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
2429 }
2430
2431 return 0;
2432 }
2433
criu_restore_bos(struct kfd_process * p,struct kfd_ioctl_criu_args * args,uint64_t * priv_offset,uint64_t max_priv_data_size)2434 static int criu_restore_bos(struct kfd_process *p,
2435 struct kfd_ioctl_criu_args *args,
2436 uint64_t *priv_offset,
2437 uint64_t max_priv_data_size)
2438 {
2439 struct kfd_criu_bo_bucket *bo_buckets = NULL;
2440 struct kfd_criu_bo_priv_data *bo_privs = NULL;
2441 int ret = 0;
2442 uint32_t i = 0;
2443
2444 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size)
2445 return -EINVAL;
2446
2447 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */
2448 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info);
2449
2450 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL);
2451 if (!bo_buckets)
2452 return -ENOMEM;
2453
2454 ret = copy_from_user(bo_buckets, (void __user *)args->bos,
2455 args->num_bos * sizeof(*bo_buckets));
2456 if (ret) {
2457 pr_err("Failed to copy BOs information from user\n");
2458 ret = -EFAULT;
2459 goto exit;
2460 }
2461
2462 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL);
2463 if (!bo_privs) {
2464 ret = -ENOMEM;
2465 goto exit;
2466 }
2467
2468 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset,
2469 args->num_bos * sizeof(*bo_privs));
2470 if (ret) {
2471 pr_err("Failed to copy BOs information from user\n");
2472 ret = -EFAULT;
2473 goto exit;
2474 }
2475 *priv_offset += args->num_bos * sizeof(*bo_privs);
2476
2477 /* Create and map new BOs */
2478 for (; i < args->num_bos; i++) {
2479 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]);
2480 if (ret) {
2481 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret);
2482 goto exit;
2483 }
2484 } /* done */
2485
2486 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */
2487 ret = copy_to_user((void __user *)args->bos,
2488 bo_buckets,
2489 (args->num_bos * sizeof(*bo_buckets)));
2490 if (ret)
2491 ret = -EFAULT;
2492
2493 exit:
2494 while (ret && i--) {
2495 if (bo_buckets[i].alloc_flags
2496 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
2497 close_fd(bo_buckets[i].dmabuf_fd);
2498 }
2499 kvfree(bo_buckets);
2500 kvfree(bo_privs);
2501 return ret;
2502 }
2503
criu_restore_objects(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args,uint64_t * priv_offset,uint64_t max_priv_data_size)2504 static int criu_restore_objects(struct file *filep,
2505 struct kfd_process *p,
2506 struct kfd_ioctl_criu_args *args,
2507 uint64_t *priv_offset,
2508 uint64_t max_priv_data_size)
2509 {
2510 int ret = 0;
2511 uint32_t i;
2512
2513 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type));
2514 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type));
2515 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type));
2516
2517 for (i = 0; i < args->num_objects; i++) {
2518 uint32_t object_type;
2519
2520 if (*priv_offset + sizeof(object_type) > max_priv_data_size) {
2521 pr_err("Invalid private data size\n");
2522 return -EINVAL;
2523 }
2524
2525 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset));
2526 if (ret) {
2527 pr_err("Failed to copy private information from user\n");
2528 goto exit;
2529 }
2530
2531 switch (object_type) {
2532 case KFD_CRIU_OBJECT_TYPE_QUEUE:
2533 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data,
2534 priv_offset, max_priv_data_size);
2535 if (ret)
2536 goto exit;
2537 break;
2538 case KFD_CRIU_OBJECT_TYPE_EVENT:
2539 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data,
2540 priv_offset, max_priv_data_size);
2541 if (ret)
2542 goto exit;
2543 break;
2544 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE:
2545 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data,
2546 priv_offset, max_priv_data_size);
2547 if (ret)
2548 goto exit;
2549 break;
2550 default:
2551 pr_err("Invalid object type:%u at index:%d\n", object_type, i);
2552 ret = -EINVAL;
2553 goto exit;
2554 }
2555 }
2556 exit:
2557 return ret;
2558 }
2559
criu_restore(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2560 static int criu_restore(struct file *filep,
2561 struct kfd_process *p,
2562 struct kfd_ioctl_criu_args *args)
2563 {
2564 uint64_t priv_offset = 0;
2565 int ret = 0;
2566
2567 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n",
2568 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size);
2569
2570 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size ||
2571 !args->num_devices || !args->num_bos)
2572 return -EINVAL;
2573
2574 mutex_lock(&p->mutex);
2575
2576 /*
2577 * Set the process to evicted state to avoid running any new queues before all the memory
2578 * mappings are ready.
2579 */
2580 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE);
2581 if (ret)
2582 goto exit_unlock;
2583
2584 /* Each function will adjust priv_offset based on how many bytes they consumed */
2585 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size);
2586 if (ret)
2587 goto exit_unlock;
2588
2589 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size);
2590 if (ret)
2591 goto exit_unlock;
2592
2593 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size);
2594 if (ret)
2595 goto exit_unlock;
2596
2597 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size);
2598 if (ret)
2599 goto exit_unlock;
2600
2601 if (priv_offset != args->priv_data_size) {
2602 pr_err("Invalid private data size\n");
2603 ret = -EINVAL;
2604 }
2605
2606 exit_unlock:
2607 mutex_unlock(&p->mutex);
2608 if (ret)
2609 pr_err("Failed to restore CRIU ret:%d\n", ret);
2610 else
2611 pr_debug("CRIU restore successful\n");
2612
2613 return ret;
2614 }
2615
criu_unpause(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2616 static int criu_unpause(struct file *filep,
2617 struct kfd_process *p,
2618 struct kfd_ioctl_criu_args *args)
2619 {
2620 int ret;
2621
2622 mutex_lock(&p->mutex);
2623
2624 if (!p->queues_paused) {
2625 mutex_unlock(&p->mutex);
2626 return -EINVAL;
2627 }
2628
2629 ret = kfd_process_restore_queues(p);
2630 if (ret)
2631 pr_err("Failed to unpause queues ret:%d\n", ret);
2632 else
2633 p->queues_paused = false;
2634
2635 mutex_unlock(&p->mutex);
2636
2637 return ret;
2638 }
2639
criu_resume(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2640 static int criu_resume(struct file *filep,
2641 struct kfd_process *p,
2642 struct kfd_ioctl_criu_args *args)
2643 {
2644 struct kfd_process *target = NULL;
2645 struct pid *pid = NULL;
2646 int ret = 0;
2647
2648 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__,
2649 args->pid);
2650
2651 pid = find_get_pid(args->pid);
2652 if (!pid) {
2653 pr_err("Cannot find pid info for %i\n", args->pid);
2654 return -ESRCH;
2655 }
2656
2657 pr_debug("calling kfd_lookup_process_by_pid\n");
2658 target = kfd_lookup_process_by_pid(pid);
2659
2660 put_pid(pid);
2661
2662 if (!target) {
2663 pr_debug("Cannot find process info for %i\n", args->pid);
2664 return -ESRCH;
2665 }
2666
2667 mutex_lock(&target->mutex);
2668 ret = kfd_criu_resume_svm(target);
2669 if (ret) {
2670 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid);
2671 goto exit;
2672 }
2673
2674 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info);
2675 if (ret)
2676 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid);
2677
2678 exit:
2679 mutex_unlock(&target->mutex);
2680
2681 kfd_unref_process(target);
2682 return ret;
2683 }
2684
criu_process_info(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2685 static int criu_process_info(struct file *filep,
2686 struct kfd_process *p,
2687 struct kfd_ioctl_criu_args *args)
2688 {
2689 int ret = 0;
2690
2691 mutex_lock(&p->mutex);
2692
2693 if (!p->n_pdds) {
2694 pr_err("No pdd for given process\n");
2695 ret = -ENODEV;
2696 goto err_unlock;
2697 }
2698
2699 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT);
2700 if (ret)
2701 goto err_unlock;
2702
2703 p->queues_paused = true;
2704
2705 args->pid = task_pid_nr_ns(p->lead_thread,
2706 task_active_pid_ns(p->lead_thread));
2707
2708 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos,
2709 &args->num_objects, &args->priv_data_size);
2710 if (ret)
2711 goto err_unlock;
2712
2713 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n",
2714 args->num_devices, args->num_bos, args->num_objects,
2715 args->priv_data_size);
2716
2717 err_unlock:
2718 if (ret) {
2719 kfd_process_restore_queues(p);
2720 p->queues_paused = false;
2721 }
2722 mutex_unlock(&p->mutex);
2723 return ret;
2724 }
2725
kfd_ioctl_criu(struct file * filep,struct kfd_process * p,void * data)2726 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data)
2727 {
2728 struct kfd_ioctl_criu_args *args = data;
2729 int ret;
2730
2731 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op);
2732 switch (args->op) {
2733 case KFD_CRIU_OP_PROCESS_INFO:
2734 ret = criu_process_info(filep, p, args);
2735 break;
2736 case KFD_CRIU_OP_CHECKPOINT:
2737 ret = criu_checkpoint(filep, p, args);
2738 break;
2739 case KFD_CRIU_OP_UNPAUSE:
2740 ret = criu_unpause(filep, p, args);
2741 break;
2742 case KFD_CRIU_OP_RESTORE:
2743 ret = criu_restore(filep, p, args);
2744 break;
2745 case KFD_CRIU_OP_RESUME:
2746 ret = criu_resume(filep, p, args);
2747 break;
2748 default:
2749 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op);
2750 ret = -EINVAL;
2751 break;
2752 }
2753
2754 if (ret)
2755 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret);
2756
2757 return ret;
2758 }
2759
runtime_enable(struct kfd_process * p,uint64_t r_debug,bool enable_ttmp_setup)2760 static int runtime_enable(struct kfd_process *p, uint64_t r_debug,
2761 bool enable_ttmp_setup)
2762 {
2763 int i = 0, ret = 0;
2764
2765 if (p->is_runtime_retry)
2766 goto retry;
2767
2768 if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED)
2769 return -EBUSY;
2770
2771 for (i = 0; i < p->n_pdds; i++) {
2772 struct kfd_process_device *pdd = p->pdds[i];
2773
2774 if (pdd->qpd.queue_count)
2775 return -EEXIST;
2776
2777 /*
2778 * Setup TTMPs by default.
2779 * Note that this call must remain here for MES ADD QUEUE to
2780 * skip_process_ctx_clear unconditionally as the first call to
2781 * SET_SHADER_DEBUGGER clears any stale process context data
2782 * saved in MES.
2783 */
2784 if (pdd->dev->kfd->shared_resources.enable_mes)
2785 kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev));
2786 }
2787
2788 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED;
2789 p->runtime_info.r_debug = r_debug;
2790 p->runtime_info.ttmp_setup = enable_ttmp_setup;
2791
2792 if (p->runtime_info.ttmp_setup) {
2793 for (i = 0; i < p->n_pdds; i++) {
2794 struct kfd_process_device *pdd = p->pdds[i];
2795
2796 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) {
2797 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
2798 pdd->dev->kfd2kgd->enable_debug_trap(
2799 pdd->dev->adev,
2800 true,
2801 pdd->dev->vm_info.last_vmid_kfd);
2802 } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2803 pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap(
2804 pdd->dev->adev,
2805 false,
2806 0);
2807 }
2808 }
2809 }
2810
2811 retry:
2812 if (p->debug_trap_enabled) {
2813 if (!p->is_runtime_retry) {
2814 kfd_dbg_trap_activate(p);
2815 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2816 p, NULL, 0, false, NULL, 0);
2817 }
2818
2819 mutex_unlock(&p->mutex);
2820 ret = down_interruptible(&p->runtime_enable_sema);
2821 mutex_lock(&p->mutex);
2822
2823 p->is_runtime_retry = !!ret;
2824 }
2825
2826 return ret;
2827 }
2828
runtime_disable(struct kfd_process * p)2829 static int runtime_disable(struct kfd_process *p)
2830 {
2831 int i = 0, ret;
2832 bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED;
2833
2834 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED;
2835 p->runtime_info.r_debug = 0;
2836
2837 if (p->debug_trap_enabled) {
2838 if (was_enabled)
2839 kfd_dbg_trap_deactivate(p, false, 0);
2840
2841 if (!p->is_runtime_retry)
2842 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2843 p, NULL, 0, false, NULL, 0);
2844
2845 mutex_unlock(&p->mutex);
2846 ret = down_interruptible(&p->runtime_enable_sema);
2847 mutex_lock(&p->mutex);
2848
2849 p->is_runtime_retry = !!ret;
2850 if (ret)
2851 return ret;
2852 }
2853
2854 if (was_enabled && p->runtime_info.ttmp_setup) {
2855 for (i = 0; i < p->n_pdds; i++) {
2856 struct kfd_process_device *pdd = p->pdds[i];
2857
2858 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev))
2859 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
2860 }
2861 }
2862
2863 p->runtime_info.ttmp_setup = false;
2864
2865 /* disable ttmp setup */
2866 for (i = 0; i < p->n_pdds; i++) {
2867 struct kfd_process_device *pdd = p->pdds[i];
2868
2869 if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2870 pdd->spi_dbg_override =
2871 pdd->dev->kfd2kgd->disable_debug_trap(
2872 pdd->dev->adev,
2873 false,
2874 pdd->dev->vm_info.last_vmid_kfd);
2875
2876 if (!pdd->dev->kfd->shared_resources.enable_mes)
2877 debug_refresh_runlist(pdd->dev->dqm);
2878 else
2879 kfd_dbg_set_mes_debug_mode(pdd,
2880 !kfd_dbg_has_cwsr_workaround(pdd->dev));
2881 }
2882 }
2883
2884 return 0;
2885 }
2886
kfd_ioctl_runtime_enable(struct file * filep,struct kfd_process * p,void * data)2887 static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data)
2888 {
2889 struct kfd_ioctl_runtime_enable_args *args = data;
2890 int r;
2891
2892 mutex_lock(&p->mutex);
2893
2894 if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK)
2895 r = runtime_enable(p, args->r_debug,
2896 !!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK));
2897 else
2898 r = runtime_disable(p);
2899
2900 mutex_unlock(&p->mutex);
2901
2902 return r;
2903 }
2904
kfd_ioctl_set_debug_trap(struct file * filep,struct kfd_process * p,void * data)2905 static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, void *data)
2906 {
2907 struct kfd_ioctl_dbg_trap_args *args = data;
2908 struct task_struct *thread = NULL;
2909 struct mm_struct *mm = NULL;
2910 struct pid *pid = NULL;
2911 struct kfd_process *target = NULL;
2912 struct kfd_process_device *pdd = NULL;
2913 int r = 0;
2914
2915 if (sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2916 pr_err("Debugging does not support sched_policy %i", sched_policy);
2917 return -EINVAL;
2918 }
2919
2920 pid = find_get_pid(args->pid);
2921 if (!pid) {
2922 pr_debug("Cannot find pid info for %i\n", args->pid);
2923 r = -ESRCH;
2924 goto out;
2925 }
2926
2927 thread = get_pid_task(pid, PIDTYPE_PID);
2928 if (!thread) {
2929 r = -ESRCH;
2930 goto out;
2931 }
2932
2933 mm = get_task_mm(thread);
2934 if (!mm) {
2935 r = -ESRCH;
2936 goto out;
2937 }
2938
2939 if (args->op == KFD_IOC_DBG_TRAP_ENABLE) {
2940 bool create_process;
2941
2942 rcu_read_lock();
2943 create_process = thread && thread != current && ptrace_parent(thread) == current;
2944 rcu_read_unlock();
2945
2946 target = create_process ? kfd_create_process(thread) :
2947 kfd_lookup_process_by_pid(pid);
2948 } else {
2949 target = kfd_lookup_process_by_pid(pid);
2950 }
2951
2952 if (IS_ERR_OR_NULL(target)) {
2953 pr_debug("Cannot find process PID %i to debug\n", args->pid);
2954 r = target ? PTR_ERR(target) : -ESRCH;
2955 goto out;
2956 }
2957
2958 /* Check if target is still PTRACED. */
2959 rcu_read_lock();
2960 if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE
2961 && ptrace_parent(target->lead_thread) != current) {
2962 pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid);
2963 r = -EPERM;
2964 }
2965 rcu_read_unlock();
2966
2967 if (r)
2968 goto out;
2969
2970 mutex_lock(&target->mutex);
2971
2972 if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) {
2973 pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op);
2974 r = -EINVAL;
2975 goto unlock_out;
2976 }
2977
2978 if (target->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_ENABLED &&
2979 (args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE ||
2980 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE ||
2981 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES ||
2982 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES ||
2983 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2984 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH ||
2985 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) {
2986 r = -EPERM;
2987 goto unlock_out;
2988 }
2989
2990 if (args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2991 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH) {
2992 int user_gpu_id = kfd_process_get_user_gpu_id(target,
2993 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ?
2994 args->set_node_address_watch.gpu_id :
2995 args->clear_node_address_watch.gpu_id);
2996
2997 pdd = kfd_process_device_data_by_id(target, user_gpu_id);
2998 if (user_gpu_id == -EINVAL || !pdd) {
2999 r = -ENODEV;
3000 goto unlock_out;
3001 }
3002 }
3003
3004 switch (args->op) {
3005 case KFD_IOC_DBG_TRAP_ENABLE:
3006 if (target != p)
3007 target->debugger_process = p;
3008
3009 r = kfd_dbg_trap_enable(target,
3010 args->enable.dbg_fd,
3011 (void __user *)args->enable.rinfo_ptr,
3012 &args->enable.rinfo_size);
3013 if (!r)
3014 target->exception_enable_mask = args->enable.exception_mask;
3015
3016 break;
3017 case KFD_IOC_DBG_TRAP_DISABLE:
3018 r = kfd_dbg_trap_disable(target);
3019 break;
3020 case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT:
3021 r = kfd_dbg_send_exception_to_runtime(target,
3022 args->send_runtime_event.gpu_id,
3023 args->send_runtime_event.queue_id,
3024 args->send_runtime_event.exception_mask);
3025 break;
3026 case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED:
3027 kfd_dbg_set_enabled_debug_exception_mask(target,
3028 args->set_exceptions_enabled.exception_mask);
3029 break;
3030 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
3031 r = kfd_dbg_trap_set_wave_launch_override(target,
3032 args->launch_override.override_mode,
3033 args->launch_override.enable_mask,
3034 args->launch_override.support_request_mask,
3035 &args->launch_override.enable_mask,
3036 &args->launch_override.support_request_mask);
3037 break;
3038 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
3039 r = kfd_dbg_trap_set_wave_launch_mode(target,
3040 args->launch_mode.launch_mode);
3041 break;
3042 case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES:
3043 r = suspend_queues(target,
3044 args->suspend_queues.num_queues,
3045 args->suspend_queues.grace_period,
3046 args->suspend_queues.exception_mask,
3047 (uint32_t *)args->suspend_queues.queue_array_ptr);
3048
3049 break;
3050 case KFD_IOC_DBG_TRAP_RESUME_QUEUES:
3051 r = resume_queues(target, args->resume_queues.num_queues,
3052 (uint32_t *)args->resume_queues.queue_array_ptr);
3053 break;
3054 case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH:
3055 r = kfd_dbg_trap_set_dev_address_watch(pdd,
3056 args->set_node_address_watch.address,
3057 args->set_node_address_watch.mask,
3058 &args->set_node_address_watch.id,
3059 args->set_node_address_watch.mode);
3060 break;
3061 case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH:
3062 r = kfd_dbg_trap_clear_dev_address_watch(pdd,
3063 args->clear_node_address_watch.id);
3064 break;
3065 case KFD_IOC_DBG_TRAP_SET_FLAGS:
3066 r = kfd_dbg_trap_set_flags(target, &args->set_flags.flags);
3067 break;
3068 case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
3069 r = kfd_dbg_ev_query_debug_event(target,
3070 &args->query_debug_event.queue_id,
3071 &args->query_debug_event.gpu_id,
3072 args->query_debug_event.exception_mask,
3073 &args->query_debug_event.exception_mask);
3074 break;
3075 case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO:
3076 r = kfd_dbg_trap_query_exception_info(target,
3077 args->query_exception_info.source_id,
3078 args->query_exception_info.exception_code,
3079 args->query_exception_info.clear_exception,
3080 (void __user *)args->query_exception_info.info_ptr,
3081 &args->query_exception_info.info_size);
3082 break;
3083 case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
3084 r = pqm_get_queue_snapshot(&target->pqm,
3085 args->queue_snapshot.exception_mask,
3086 (void __user *)args->queue_snapshot.snapshot_buf_ptr,
3087 &args->queue_snapshot.num_queues,
3088 &args->queue_snapshot.entry_size);
3089 break;
3090 case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT:
3091 r = kfd_dbg_trap_device_snapshot(target,
3092 args->device_snapshot.exception_mask,
3093 (void __user *)args->device_snapshot.snapshot_buf_ptr,
3094 &args->device_snapshot.num_devices,
3095 &args->device_snapshot.entry_size);
3096 break;
3097 default:
3098 pr_err("Invalid option: %i\n", args->op);
3099 r = -EINVAL;
3100 }
3101
3102 unlock_out:
3103 mutex_unlock(&target->mutex);
3104
3105 out:
3106 if (thread)
3107 put_task_struct(thread);
3108
3109 if (mm)
3110 mmput(mm);
3111
3112 if (pid)
3113 put_pid(pid);
3114
3115 if (target)
3116 kfd_unref_process(target);
3117
3118 return r;
3119 }
3120
3121 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
3122 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
3123 .cmd_drv = 0, .name = #ioctl}
3124
3125 /** Ioctl table */
3126 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
3127 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
3128 kfd_ioctl_get_version, 0),
3129
3130 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
3131 kfd_ioctl_create_queue, 0),
3132
3133 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
3134 kfd_ioctl_destroy_queue, 0),
3135
3136 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
3137 kfd_ioctl_set_memory_policy, 0),
3138
3139 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
3140 kfd_ioctl_get_clock_counters, 0),
3141
3142 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
3143 kfd_ioctl_get_process_apertures, 0),
3144
3145 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
3146 kfd_ioctl_update_queue, 0),
3147
3148 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
3149 kfd_ioctl_create_event, 0),
3150
3151 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
3152 kfd_ioctl_destroy_event, 0),
3153
3154 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
3155 kfd_ioctl_set_event, 0),
3156
3157 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
3158 kfd_ioctl_reset_event, 0),
3159
3160 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
3161 kfd_ioctl_wait_events, 0),
3162
3163 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED,
3164 kfd_ioctl_dbg_register, 0),
3165
3166 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED,
3167 kfd_ioctl_dbg_unregister, 0),
3168
3169 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED,
3170 kfd_ioctl_dbg_address_watch, 0),
3171
3172 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED,
3173 kfd_ioctl_dbg_wave_control, 0),
3174
3175 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
3176 kfd_ioctl_set_scratch_backing_va, 0),
3177
3178 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
3179 kfd_ioctl_get_tile_config, 0),
3180
3181 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
3182 kfd_ioctl_set_trap_handler, 0),
3183
3184 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
3185 kfd_ioctl_get_process_apertures_new, 0),
3186
3187 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
3188 kfd_ioctl_acquire_vm, 0),
3189
3190 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
3191 kfd_ioctl_alloc_memory_of_gpu, 0),
3192
3193 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
3194 kfd_ioctl_free_memory_of_gpu, 0),
3195
3196 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
3197 kfd_ioctl_map_memory_to_gpu, 0),
3198
3199 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
3200 kfd_ioctl_unmap_memory_from_gpu, 0),
3201
3202 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
3203 kfd_ioctl_set_cu_mask, 0),
3204
3205 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
3206 kfd_ioctl_get_queue_wave_state, 0),
3207
3208 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO,
3209 kfd_ioctl_get_dmabuf_info, 0),
3210
3211 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
3212 kfd_ioctl_import_dmabuf, 0),
3213
3214 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
3215 kfd_ioctl_alloc_queue_gws, 0),
3216
3217 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
3218 kfd_ioctl_smi_events, 0),
3219
3220 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0),
3221
3222 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
3223 kfd_ioctl_set_xnack_mode, 0),
3224
3225 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP,
3226 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE),
3227
3228 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY,
3229 kfd_ioctl_get_available_memory, 0),
3230
3231 AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF,
3232 kfd_ioctl_export_dmabuf, 0),
3233
3234 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE,
3235 kfd_ioctl_runtime_enable, 0),
3236
3237 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP,
3238 kfd_ioctl_set_debug_trap, 0),
3239 };
3240
3241 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
3242
kfd_ioctl(struct file * filep,unsigned int cmd,unsigned long arg)3243 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
3244 {
3245 struct kfd_process *process;
3246 amdkfd_ioctl_t *func;
3247 const struct amdkfd_ioctl_desc *ioctl = NULL;
3248 unsigned int nr = _IOC_NR(cmd);
3249 char stack_kdata[128];
3250 char *kdata = NULL;
3251 unsigned int usize, asize;
3252 int retcode = -EINVAL;
3253 bool ptrace_attached = false;
3254
3255 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
3256 goto err_i1;
3257
3258 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
3259 u32 amdkfd_size;
3260
3261 ioctl = &amdkfd_ioctls[nr];
3262
3263 amdkfd_size = _IOC_SIZE(ioctl->cmd);
3264 usize = asize = _IOC_SIZE(cmd);
3265 if (amdkfd_size > asize)
3266 asize = amdkfd_size;
3267
3268 cmd = ioctl->cmd;
3269 } else
3270 goto err_i1;
3271
3272 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
3273
3274 /* Get the process struct from the filep. Only the process
3275 * that opened /dev/kfd can use the file descriptor. Child
3276 * processes need to create their own KFD device context.
3277 */
3278 process = filep->private_data;
3279
3280 rcu_read_lock();
3281 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) &&
3282 ptrace_parent(process->lead_thread) == current)
3283 ptrace_attached = true;
3284 rcu_read_unlock();
3285
3286 if (process->lead_thread != current->group_leader
3287 && !ptrace_attached) {
3288 dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
3289 retcode = -EBADF;
3290 goto err_i1;
3291 }
3292
3293 /* Do not trust userspace, use our own definition */
3294 func = ioctl->func;
3295
3296 if (unlikely(!func)) {
3297 dev_dbg(kfd_device, "no function\n");
3298 retcode = -EINVAL;
3299 goto err_i1;
3300 }
3301
3302 /*
3303 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support
3304 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a
3305 * more priviledged access.
3306 */
3307 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) {
3308 if (!capable(CAP_CHECKPOINT_RESTORE) &&
3309 !capable(CAP_SYS_ADMIN)) {
3310 retcode = -EACCES;
3311 goto err_i1;
3312 }
3313 }
3314
3315 if (cmd & (IOC_IN | IOC_OUT)) {
3316 if (asize <= sizeof(stack_kdata)) {
3317 kdata = stack_kdata;
3318 } else {
3319 kdata = kmalloc(asize, GFP_KERNEL);
3320 if (!kdata) {
3321 retcode = -ENOMEM;
3322 goto err_i1;
3323 }
3324 }
3325 if (asize > usize)
3326 memset(kdata + usize, 0, asize - usize);
3327 }
3328
3329 if (cmd & IOC_IN) {
3330 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
3331 retcode = -EFAULT;
3332 goto err_i1;
3333 }
3334 } else if (cmd & IOC_OUT) {
3335 memset(kdata, 0, usize);
3336 }
3337
3338 retcode = func(filep, process, kdata);
3339
3340 if (cmd & IOC_OUT)
3341 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
3342 retcode = -EFAULT;
3343
3344 err_i1:
3345 if (!ioctl)
3346 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
3347 task_pid_nr(current), cmd, nr);
3348
3349 if (kdata != stack_kdata)
3350 kfree(kdata);
3351
3352 if (retcode)
3353 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n",
3354 nr, arg, retcode);
3355
3356 return retcode;
3357 }
3358
kfd_mmio_mmap(struct kfd_node * dev,struct kfd_process * process,struct vm_area_struct * vma)3359 static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process,
3360 struct vm_area_struct *vma)
3361 {
3362 phys_addr_t address;
3363
3364 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3365 return -EINVAL;
3366
3367 if (PAGE_SIZE > 4096)
3368 return -EINVAL;
3369
3370 address = dev->adev->rmmio_remap.bus_addr;
3371
3372 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
3373 VM_DONTDUMP | VM_PFNMAP);
3374
3375 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3376
3377 pr_debug("pasid 0x%x mapping mmio page\n"
3378 " target user address == 0x%08llX\n"
3379 " physical address == 0x%08llX\n"
3380 " vm_flags == 0x%04lX\n"
3381 " size == 0x%04lX\n",
3382 process->pasid, (unsigned long long) vma->vm_start,
3383 address, vma->vm_flags, PAGE_SIZE);
3384
3385 return io_remap_pfn_range(vma,
3386 vma->vm_start,
3387 address >> PAGE_SHIFT,
3388 PAGE_SIZE,
3389 vma->vm_page_prot);
3390 }
3391
3392
kfd_mmap(struct file * filp,struct vm_area_struct * vma)3393 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
3394 {
3395 struct kfd_process *process;
3396 struct kfd_node *dev = NULL;
3397 unsigned long mmap_offset;
3398 unsigned int gpu_id;
3399
3400 process = kfd_get_process(current);
3401 if (IS_ERR(process))
3402 return PTR_ERR(process);
3403
3404 mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
3405 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
3406 if (gpu_id)
3407 dev = kfd_device_by_id(gpu_id);
3408
3409 switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
3410 case KFD_MMAP_TYPE_DOORBELL:
3411 if (!dev)
3412 return -ENODEV;
3413 return kfd_doorbell_mmap(dev, process, vma);
3414
3415 case KFD_MMAP_TYPE_EVENTS:
3416 return kfd_event_mmap(process, vma);
3417
3418 case KFD_MMAP_TYPE_RESERVED_MEM:
3419 if (!dev)
3420 return -ENODEV;
3421 return kfd_reserved_mem_mmap(dev, process, vma);
3422 case KFD_MMAP_TYPE_MMIO:
3423 if (!dev)
3424 return -ENODEV;
3425 return kfd_mmio_mmap(dev, process, vma);
3426 }
3427
3428 return -EFAULT;
3429 }
3430