1 /*
2 * Sparc CPU init helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "qemu/module.h"
24 #include "qemu/qemu-print.h"
25 #include "exec/exec-all.h"
26 #include "hw/qdev-properties.h"
27 #include "qapi/visitor.h"
28 #include "tcg/tcg.h"
29 #include "fpu/softfloat.h"
30
31 //#define DEBUG_FEATURES
32
sparc_cpu_reset_hold(Object * obj,ResetType type)33 static void sparc_cpu_reset_hold(Object *obj, ResetType type)
34 {
35 CPUState *cs = CPU(obj);
36 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
37 CPUSPARCState *env = cpu_env(cs);
38
39 if (scc->parent_phases.hold) {
40 scc->parent_phases.hold(obj, type);
41 }
42
43 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
44 env->cwp = 0;
45 #ifndef TARGET_SPARC64
46 env->wim = 1;
47 #endif
48 env->regwptr = env->regbase + (env->cwp * 16);
49 #if defined(CONFIG_USER_ONLY)
50 #ifdef TARGET_SPARC64
51 env->cleanwin = env->nwindows - 2;
52 env->cansave = env->nwindows - 2;
53 env->pstate = PS_RMO | PS_PEF | PS_IE;
54 env->asi = 0x82; /* Primary no-fault */
55 #endif
56 #else
57 #if !defined(TARGET_SPARC64)
58 env->psret = 0;
59 env->psrs = 1;
60 env->psrps = 1;
61 #endif
62 #ifdef TARGET_SPARC64
63 env->pstate = PS_PRIV | PS_RED | PS_PEF;
64 if (!cpu_has_hypervisor(env)) {
65 env->pstate |= PS_AG;
66 }
67 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
68 env->tl = env->maxtl;
69 env->gl = 2;
70 cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
71 env->lsu = 0;
72 #else
73 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
74 env->mmuregs[0] |= env->def.mmu_bm;
75 #endif
76 env->pc = 0;
77 env->npc = env->pc + 4;
78 #endif
79 env->cache_control = 0;
80 cpu_put_fsr(env, 0);
81 }
82
83 #ifndef CONFIG_USER_ONLY
sparc_cpu_exec_interrupt(CPUState * cs,int interrupt_request)84 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
85 {
86 if (interrupt_request & CPU_INTERRUPT_HARD) {
87 CPUSPARCState *env = cpu_env(cs);
88
89 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
90 int pil = env->interrupt_index & 0xf;
91 int type = env->interrupt_index & 0xf0;
92
93 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
94 cs->exception_index = env->interrupt_index;
95 sparc_cpu_do_interrupt(cs);
96 return true;
97 }
98 }
99 }
100 return false;
101 }
102 #endif /* !CONFIG_USER_ONLY */
103
cpu_sparc_disas_set_info(CPUState * cpu,disassemble_info * info)104 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
105 {
106 info->print_insn = print_insn_sparc;
107 #ifdef TARGET_SPARC64
108 info->mach = bfd_mach_sparc_v9b;
109 #endif
110 }
111
112 static void
cpu_add_feat_as_prop(const char * typename,const char * name,const char * val)113 cpu_add_feat_as_prop(const char *typename, const char *name, const char *val)
114 {
115 GlobalProperty *prop = g_new0(typeof(*prop), 1);
116 prop->driver = typename;
117 prop->property = g_strdup(name);
118 prop->value = g_strdup(val);
119 qdev_prop_register_global(prop);
120 }
121
122 /* Parse "+feature,-feature,feature=foo" CPU feature string */
sparc_cpu_parse_features(const char * typename,char * features,Error ** errp)123 static void sparc_cpu_parse_features(const char *typename, char *features,
124 Error **errp)
125 {
126 GList *l, *plus_features = NULL, *minus_features = NULL;
127 char *featurestr; /* Single 'key=value" string being parsed */
128 static bool cpu_globals_initialized;
129
130 if (cpu_globals_initialized) {
131 return;
132 }
133 cpu_globals_initialized = true;
134
135 if (!features) {
136 return;
137 }
138
139 for (featurestr = strtok(features, ",");
140 featurestr;
141 featurestr = strtok(NULL, ",")) {
142 const char *name;
143 const char *val = NULL;
144 char *eq = NULL;
145
146 /* Compatibility syntax: */
147 if (featurestr[0] == '+') {
148 plus_features = g_list_append(plus_features,
149 g_strdup(featurestr + 1));
150 continue;
151 } else if (featurestr[0] == '-') {
152 minus_features = g_list_append(minus_features,
153 g_strdup(featurestr + 1));
154 continue;
155 }
156
157 eq = strchr(featurestr, '=');
158 name = featurestr;
159 if (eq) {
160 *eq++ = 0;
161 val = eq;
162
163 /*
164 * Temporarily, only +feat/-feat will be supported
165 * for boolean properties until we remove the
166 * minus-overrides-plus semantics and just follow
167 * the order options appear on the command-line.
168 *
169 * TODO: warn if user is relying on minus-override-plus semantics
170 * TODO: remove minus-override-plus semantics after
171 * warning for a few releases
172 */
173 if (!strcasecmp(val, "on") ||
174 !strcasecmp(val, "off") ||
175 !strcasecmp(val, "true") ||
176 !strcasecmp(val, "false")) {
177 error_setg(errp, "Boolean properties in format %s=%s"
178 " are not supported", name, val);
179 return;
180 }
181 } else {
182 error_setg(errp, "Unsupported property format: %s", name);
183 return;
184 }
185 cpu_add_feat_as_prop(typename, name, val);
186 }
187
188 for (l = plus_features; l; l = l->next) {
189 const char *name = l->data;
190 cpu_add_feat_as_prop(typename, name, "on");
191 }
192 g_list_free_full(plus_features, g_free);
193
194 for (l = minus_features; l; l = l->next) {
195 const char *name = l->data;
196 cpu_add_feat_as_prop(typename, name, "off");
197 }
198 g_list_free_full(minus_features, g_free);
199 }
200
cpu_sparc_set_id(CPUSPARCState * env,unsigned int cpu)201 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
202 {
203 #if !defined(TARGET_SPARC64)
204 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
205 #endif
206 }
207
208 static const sparc_def_t sparc_defs[] = {
209 #ifdef TARGET_SPARC64
210 {
211 .name = "Fujitsu-Sparc64",
212 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
213 .fpu_version = 0x00000000,
214 .mmu_version = mmu_us_12,
215 .nwindows = 4,
216 .maxtl = 4,
217 .features = CPU_DEFAULT_FEATURES,
218 },
219 {
220 .name = "Fujitsu-Sparc64-III",
221 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
222 .fpu_version = 0x00000000,
223 .mmu_version = mmu_us_12,
224 .nwindows = 5,
225 .maxtl = 4,
226 .features = CPU_DEFAULT_FEATURES,
227 },
228 {
229 .name = "Fujitsu-Sparc64-IV",
230 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
231 .fpu_version = 0x00000000,
232 .mmu_version = mmu_us_12,
233 .nwindows = 8,
234 .maxtl = 5,
235 .features = CPU_DEFAULT_FEATURES,
236 },
237 {
238 .name = "Fujitsu-Sparc64-V",
239 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
240 .fpu_version = 0x00000000,
241 .mmu_version = mmu_us_12,
242 .nwindows = 8,
243 .maxtl = 5,
244 .features = CPU_DEFAULT_FEATURES,
245 },
246 {
247 .name = "TI-UltraSparc-I",
248 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
249 .fpu_version = 0x00000000,
250 .mmu_version = mmu_us_12,
251 .nwindows = 8,
252 .maxtl = 5,
253 .features = CPU_DEFAULT_FEATURES,
254 },
255 {
256 .name = "TI-UltraSparc-II",
257 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
258 .fpu_version = 0x00000000,
259 .mmu_version = mmu_us_12,
260 .nwindows = 8,
261 .maxtl = 5,
262 .features = CPU_DEFAULT_FEATURES,
263 },
264 {
265 .name = "TI-UltraSparc-IIi",
266 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
267 .fpu_version = 0x00000000,
268 .mmu_version = mmu_us_12,
269 .nwindows = 8,
270 .maxtl = 5,
271 .features = CPU_DEFAULT_FEATURES,
272 },
273 {
274 .name = "TI-UltraSparc-IIe",
275 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
276 .fpu_version = 0x00000000,
277 .mmu_version = mmu_us_12,
278 .nwindows = 8,
279 .maxtl = 5,
280 .features = CPU_DEFAULT_FEATURES,
281 },
282 {
283 .name = "Sun-UltraSparc-III",
284 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
285 .fpu_version = 0x00000000,
286 .mmu_version = mmu_us_12,
287 .nwindows = 8,
288 .maxtl = 5,
289 .features = CPU_DEFAULT_FEATURES,
290 },
291 {
292 .name = "Sun-UltraSparc-III-Cu",
293 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
294 .fpu_version = 0x00000000,
295 .mmu_version = mmu_us_3,
296 .nwindows = 8,
297 .maxtl = 5,
298 .features = CPU_DEFAULT_FEATURES,
299 },
300 {
301 .name = "Sun-UltraSparc-IIIi",
302 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
303 .fpu_version = 0x00000000,
304 .mmu_version = mmu_us_12,
305 .nwindows = 8,
306 .maxtl = 5,
307 .features = CPU_DEFAULT_FEATURES,
308 },
309 {
310 .name = "Sun-UltraSparc-IV",
311 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
312 .fpu_version = 0x00000000,
313 .mmu_version = mmu_us_4,
314 .nwindows = 8,
315 .maxtl = 5,
316 .features = CPU_DEFAULT_FEATURES,
317 },
318 {
319 .name = "Sun-UltraSparc-IV-plus",
320 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
321 .fpu_version = 0x00000000,
322 .mmu_version = mmu_us_12,
323 .nwindows = 8,
324 .maxtl = 5,
325 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
326 },
327 {
328 .name = "Sun-UltraSparc-IIIi-plus",
329 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
330 .fpu_version = 0x00000000,
331 .mmu_version = mmu_us_3,
332 .nwindows = 8,
333 .maxtl = 5,
334 .features = CPU_DEFAULT_FEATURES,
335 },
336 {
337 .name = "Sun-UltraSparc-T1",
338 /* defined in sparc_ifu_fdp.v and ctu.h */
339 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
340 .fpu_version = 0x00000000,
341 .mmu_version = mmu_sun4v,
342 .nwindows = 8,
343 .maxtl = 6,
344 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
345 | CPU_FEATURE_GL,
346 },
347 {
348 .name = "Sun-UltraSparc-T2",
349 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
350 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
351 .fpu_version = 0x00000000,
352 .mmu_version = mmu_sun4v,
353 .nwindows = 8,
354 .maxtl = 6,
355 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
356 | CPU_FEATURE_GL,
357 },
358 {
359 .name = "NEC-UltraSparc-I",
360 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
361 .fpu_version = 0x00000000,
362 .mmu_version = mmu_us_12,
363 .nwindows = 8,
364 .maxtl = 5,
365 .features = CPU_DEFAULT_FEATURES,
366 },
367 #else
368 {
369 .name = "Fujitsu-MB86904",
370 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
371 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
372 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
373 .mmu_bm = 0x00004000,
374 .mmu_ctpr_mask = 0x00ffffc0,
375 .mmu_cxr_mask = 0x000000ff,
376 .mmu_sfsr_mask = 0x00016fff,
377 .mmu_trcr_mask = 0x00ffffff,
378 .nwindows = 8,
379 .features = CPU_DEFAULT_FEATURES,
380 },
381 {
382 .name = "Fujitsu-MB86907",
383 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
384 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
385 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
386 .mmu_bm = 0x00004000,
387 .mmu_ctpr_mask = 0xffffffc0,
388 .mmu_cxr_mask = 0x000000ff,
389 .mmu_sfsr_mask = 0x00016fff,
390 .mmu_trcr_mask = 0xffffffff,
391 .nwindows = 8,
392 .features = CPU_DEFAULT_FEATURES,
393 },
394 {
395 .name = "TI-MicroSparc-I",
396 .iu_version = 0x41000000,
397 .fpu_version = 4 << FSR_VER_SHIFT,
398 .mmu_version = 0x41000000,
399 .mmu_bm = 0x00004000,
400 .mmu_ctpr_mask = 0x007ffff0,
401 .mmu_cxr_mask = 0x0000003f,
402 .mmu_sfsr_mask = 0x00016fff,
403 .mmu_trcr_mask = 0x0000003f,
404 .nwindows = 7,
405 .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV,
406 },
407 {
408 .name = "TI-MicroSparc-II",
409 .iu_version = 0x42000000,
410 .fpu_version = 4 << FSR_VER_SHIFT,
411 .mmu_version = 0x02000000,
412 .mmu_bm = 0x00004000,
413 .mmu_ctpr_mask = 0x00ffffc0,
414 .mmu_cxr_mask = 0x000000ff,
415 .mmu_sfsr_mask = 0x00016fff,
416 .mmu_trcr_mask = 0x00ffffff,
417 .nwindows = 8,
418 .features = CPU_DEFAULT_FEATURES,
419 },
420 {
421 .name = "TI-MicroSparc-IIep",
422 .iu_version = 0x42000000,
423 .fpu_version = 4 << FSR_VER_SHIFT,
424 .mmu_version = 0x04000000,
425 .mmu_bm = 0x00004000,
426 .mmu_ctpr_mask = 0x00ffffc0,
427 .mmu_cxr_mask = 0x000000ff,
428 .mmu_sfsr_mask = 0x00016bff,
429 .mmu_trcr_mask = 0x00ffffff,
430 .nwindows = 8,
431 .features = CPU_DEFAULT_FEATURES,
432 },
433 {
434 .name = "TI-SuperSparc-40", /* STP1020NPGA */
435 .iu_version = 0x41000000, /* SuperSPARC 2.x */
436 .fpu_version = 0 << FSR_VER_SHIFT,
437 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
438 .mmu_bm = 0x00002000,
439 .mmu_ctpr_mask = 0xffffffc0,
440 .mmu_cxr_mask = 0x0000ffff,
441 .mmu_sfsr_mask = 0xffffffff,
442 .mmu_trcr_mask = 0xffffffff,
443 .nwindows = 8,
444 .features = CPU_DEFAULT_FEATURES,
445 },
446 {
447 .name = "TI-SuperSparc-50", /* STP1020PGA */
448 .iu_version = 0x40000000, /* SuperSPARC 3.x */
449 .fpu_version = 0 << FSR_VER_SHIFT,
450 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
451 .mmu_bm = 0x00002000,
452 .mmu_ctpr_mask = 0xffffffc0,
453 .mmu_cxr_mask = 0x0000ffff,
454 .mmu_sfsr_mask = 0xffffffff,
455 .mmu_trcr_mask = 0xffffffff,
456 .nwindows = 8,
457 .features = CPU_DEFAULT_FEATURES,
458 },
459 {
460 .name = "TI-SuperSparc-51",
461 .iu_version = 0x40000000, /* SuperSPARC 3.x */
462 .fpu_version = 0 << FSR_VER_SHIFT,
463 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
464 .mmu_bm = 0x00002000,
465 .mmu_ctpr_mask = 0xffffffc0,
466 .mmu_cxr_mask = 0x0000ffff,
467 .mmu_sfsr_mask = 0xffffffff,
468 .mmu_trcr_mask = 0xffffffff,
469 .mxcc_version = 0x00000104,
470 .nwindows = 8,
471 .features = CPU_DEFAULT_FEATURES,
472 },
473 {
474 .name = "TI-SuperSparc-60", /* STP1020APGA */
475 .iu_version = 0x40000000, /* SuperSPARC 3.x */
476 .fpu_version = 0 << FSR_VER_SHIFT,
477 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
478 .mmu_bm = 0x00002000,
479 .mmu_ctpr_mask = 0xffffffc0,
480 .mmu_cxr_mask = 0x0000ffff,
481 .mmu_sfsr_mask = 0xffffffff,
482 .mmu_trcr_mask = 0xffffffff,
483 .nwindows = 8,
484 .features = CPU_DEFAULT_FEATURES,
485 },
486 {
487 .name = "TI-SuperSparc-61",
488 .iu_version = 0x44000000, /* SuperSPARC 3.x */
489 .fpu_version = 0 << FSR_VER_SHIFT,
490 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
491 .mmu_bm = 0x00002000,
492 .mmu_ctpr_mask = 0xffffffc0,
493 .mmu_cxr_mask = 0x0000ffff,
494 .mmu_sfsr_mask = 0xffffffff,
495 .mmu_trcr_mask = 0xffffffff,
496 .mxcc_version = 0x00000104,
497 .nwindows = 8,
498 .features = CPU_DEFAULT_FEATURES,
499 },
500 {
501 .name = "TI-SuperSparc-II",
502 .iu_version = 0x40000000, /* SuperSPARC II 1.x */
503 .fpu_version = 0 << FSR_VER_SHIFT,
504 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
505 .mmu_bm = 0x00002000,
506 .mmu_ctpr_mask = 0xffffffc0,
507 .mmu_cxr_mask = 0x0000ffff,
508 .mmu_sfsr_mask = 0xffffffff,
509 .mmu_trcr_mask = 0xffffffff,
510 .mxcc_version = 0x00000104,
511 .nwindows = 8,
512 .features = CPU_DEFAULT_FEATURES,
513 },
514 {
515 .name = "LEON2",
516 .iu_version = 0xf2000000,
517 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
518 .mmu_version = 0xf2000000,
519 .mmu_bm = 0x00004000,
520 .mmu_ctpr_mask = 0x007ffff0,
521 .mmu_cxr_mask = 0x0000003f,
522 .mmu_sfsr_mask = 0xffffffff,
523 .mmu_trcr_mask = 0xffffffff,
524 .nwindows = 8,
525 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
526 },
527 {
528 .name = "LEON3",
529 .iu_version = 0xf3000000,
530 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
531 .mmu_version = 0xf3000000,
532 .mmu_bm = 0x00000000,
533 .mmu_ctpr_mask = 0xfffffffc,
534 .mmu_cxr_mask = 0x000000ff,
535 .mmu_sfsr_mask = 0xffffffff,
536 .mmu_trcr_mask = 0xffffffff,
537 .nwindows = 8,
538 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
539 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
540 CPU_FEATURE_CASA,
541 },
542 #endif
543 };
544
545 /* This must match sparc_cpu_properties[]. */
546 static const char * const feature_name[] = {
547 [CPU_FEATURE_BIT_FLOAT128] = "float128",
548 #ifdef TARGET_SPARC64
549 [CPU_FEATURE_BIT_CMT] = "cmt",
550 [CPU_FEATURE_BIT_GL] = "gl",
551 [CPU_FEATURE_BIT_HYPV] = "hypv",
552 [CPU_FEATURE_BIT_VIS1] = "vis1",
553 [CPU_FEATURE_BIT_VIS2] = "vis2",
554 [CPU_FEATURE_BIT_FMAF] = "fmaf",
555 [CPU_FEATURE_BIT_VIS3] = "vis3",
556 [CPU_FEATURE_BIT_IMA] = "ima",
557 [CPU_FEATURE_BIT_VIS4] = "vis4",
558 #else
559 [CPU_FEATURE_BIT_MUL] = "mul",
560 [CPU_FEATURE_BIT_DIV] = "div",
561 [CPU_FEATURE_BIT_FSMULD] = "fsmuld",
562 #endif
563 };
564
print_features(uint32_t features,const char * prefix)565 static void print_features(uint32_t features, const char *prefix)
566 {
567 unsigned int i;
568
569 for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
570 if (feature_name[i] && (features & (1 << i))) {
571 if (prefix) {
572 qemu_printf("%s", prefix);
573 }
574 qemu_printf("%s ", feature_name[i]);
575 }
576 }
577 }
578
sparc_cpu_list(void)579 void sparc_cpu_list(void)
580 {
581 unsigned int i;
582
583 qemu_printf("Available CPU types:\n");
584 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
585 qemu_printf(" %-20s (IU " TARGET_FMT_lx
586 " FPU %08x MMU %08x NWINS %d) ",
587 sparc_defs[i].name,
588 sparc_defs[i].iu_version,
589 sparc_defs[i].fpu_version,
590 sparc_defs[i].mmu_version,
591 sparc_defs[i].nwindows);
592 print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
593 print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
594 qemu_printf("\n");
595 }
596 qemu_printf("Default CPU feature flags (use '-' to remove): ");
597 print_features(CPU_DEFAULT_FEATURES, NULL);
598 qemu_printf("\n");
599 qemu_printf("Available CPU feature flags (use '+' to add): ");
600 print_features(~CPU_DEFAULT_FEATURES, NULL);
601 qemu_printf("\n");
602 qemu_printf("Numerical features (use '=' to set): iu_version "
603 "fpu_version mmu_version nwindows\n");
604 }
605
cpu_print_cc(FILE * f,uint32_t cc)606 static void cpu_print_cc(FILE *f, uint32_t cc)
607 {
608 qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
609 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
610 cc & PSR_CARRY ? 'C' : '-');
611 }
612
613 #ifdef TARGET_SPARC64
614 #define REGS_PER_LINE 4
615 #else
616 #define REGS_PER_LINE 8
617 #endif
618
sparc_cpu_dump_state(CPUState * cs,FILE * f,int flags)619 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
620 {
621 CPUSPARCState *env = cpu_env(cs);
622 int i, x;
623
624 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
625 env->npc);
626
627 for (i = 0; i < 8; i++) {
628 if (i % REGS_PER_LINE == 0) {
629 qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
630 }
631 qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
632 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
633 qemu_fprintf(f, "\n");
634 }
635 }
636 for (x = 0; x < 3; x++) {
637 for (i = 0; i < 8; i++) {
638 if (i % REGS_PER_LINE == 0) {
639 qemu_fprintf(f, "%%%c%d-%d: ",
640 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
641 i, i + REGS_PER_LINE - 1);
642 }
643 qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
644 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
645 qemu_fprintf(f, "\n");
646 }
647 }
648 }
649
650 if (flags & CPU_DUMP_FPU) {
651 for (i = 0; i < TARGET_DPREGS; i++) {
652 if ((i & 3) == 0) {
653 qemu_fprintf(f, "%%f%02d: ", i * 2);
654 }
655 qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
656 if ((i & 3) == 3) {
657 qemu_fprintf(f, "\n");
658 }
659 }
660 }
661
662 #ifdef TARGET_SPARC64
663 qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
664 (unsigned)cpu_get_ccr(env));
665 cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
666 qemu_fprintf(f, " xcc: ");
667 cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
668 qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl,
669 env->psrpil, env->gl);
670 qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: "
671 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba);
672 qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
673 "cleanwin: %d cwp: %d\n",
674 env->cansave, env->canrestore, env->otherwin, env->wstate,
675 env->cleanwin, env->nwindows - 1 - env->cwp);
676 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n",
677 cpu_get_fsr(env), env->y, env->fprs);
678
679 #else
680 qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
681 cpu_print_cc(f, cpu_get_psr(env));
682 qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
683 env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
684 env->wim);
685 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
686 cpu_get_fsr(env), env->y);
687 #endif
688 qemu_fprintf(f, "\n");
689 }
690
sparc_cpu_set_pc(CPUState * cs,vaddr value)691 static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
692 {
693 SPARCCPU *cpu = SPARC_CPU(cs);
694
695 cpu->env.pc = value;
696 cpu->env.npc = value + 4;
697 }
698
sparc_cpu_get_pc(CPUState * cs)699 static vaddr sparc_cpu_get_pc(CPUState *cs)
700 {
701 SPARCCPU *cpu = SPARC_CPU(cs);
702
703 return cpu->env.pc;
704 }
705
sparc_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)706 static void sparc_cpu_synchronize_from_tb(CPUState *cs,
707 const TranslationBlock *tb)
708 {
709 SPARCCPU *cpu = SPARC_CPU(cs);
710
711 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
712 cpu->env.pc = tb->pc;
713 cpu->env.npc = tb->cs_base;
714 }
715
sparc_cpu_has_work(CPUState * cs)716 static bool sparc_cpu_has_work(CPUState *cs)
717 {
718 return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
719 cpu_interrupts_enabled(cpu_env(cs));
720 }
721
sparc_cpu_mmu_index(CPUState * cs,bool ifetch)722 static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
723 {
724 CPUSPARCState *env = cpu_env(cs);
725
726 #ifndef TARGET_SPARC64
727 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
728 return MMU_PHYS_IDX;
729 } else {
730 return env->psrs;
731 }
732 #else
733 /* IMMU or DMMU disabled. */
734 if (ifetch
735 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
736 : (env->lsu & DMMU_E) == 0) {
737 return MMU_PHYS_IDX;
738 } else if (cpu_hypervisor_mode(env)) {
739 return MMU_PHYS_IDX;
740 } else if (env->tl > 0) {
741 return MMU_NUCLEUS_IDX;
742 } else if (cpu_supervisor_mode(env)) {
743 return MMU_KERNEL_IDX;
744 } else {
745 return MMU_USER_IDX;
746 }
747 #endif
748 }
749
sparc_cpu_type_name(const char * cpu_model)750 static char *sparc_cpu_type_name(const char *cpu_model)
751 {
752 char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model);
753 char *s = name;
754
755 /* SPARC cpu model names happen to have whitespaces,
756 * as type names shouldn't have spaces replace them with '-'
757 */
758 while ((s = strchr(s, ' '))) {
759 *s = '-';
760 }
761
762 return name;
763 }
764
sparc_cpu_class_by_name(const char * cpu_model)765 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model)
766 {
767 ObjectClass *oc;
768 char *typename;
769
770 typename = sparc_cpu_type_name(cpu_model);
771
772 /* Fix up legacy names with '+' in it */
773 if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) {
774 g_free(typename);
775 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus"));
776 } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi+"))) {
777 g_free(typename);
778 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plus"));
779 }
780
781 oc = object_class_by_name(typename);
782 g_free(typename);
783 return oc;
784 }
785
sparc_cpu_realizefn(DeviceState * dev,Error ** errp)786 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
787 {
788 CPUState *cs = CPU(dev);
789 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
790 Error *local_err = NULL;
791 CPUSPARCState *env = cpu_env(cs);
792
793 #if defined(CONFIG_USER_ONLY)
794 /* We are emulating the kernel, which will trap and emulate float128. */
795 env->def.features |= CPU_FEATURE_FLOAT128;
796 #endif
797
798 env->version = env->def.iu_version;
799 env->nwindows = env->def.nwindows;
800 #if !defined(TARGET_SPARC64)
801 env->mmuregs[0] |= env->def.mmu_version;
802 cpu_sparc_set_id(env, 0);
803 env->mxccregs[7] |= env->def.mxcc_version;
804 #else
805 env->mmu_version = env->def.mmu_version;
806 env->maxtl = env->def.maxtl;
807 env->version |= env->def.maxtl << 8;
808 env->version |= env->def.nwindows - 1;
809 #endif
810
811 /*
812 * Prefer SNaN over QNaN, order B then A. It's OK to do this in realize
813 * rather than reset, because fp_status is after 'end_reset_fields' in
814 * the CPU state struct so it won't get zeroed on reset.
815 */
816 set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
817
818 cpu_exec_realizefn(cs, &local_err);
819 if (local_err != NULL) {
820 error_propagate(errp, local_err);
821 return;
822 }
823
824 qemu_init_vcpu(cs);
825
826 scc->parent_realize(dev, errp);
827 }
828
sparc_cpu_initfn(Object * obj)829 static void sparc_cpu_initfn(Object *obj)
830 {
831 SPARCCPU *cpu = SPARC_CPU(obj);
832 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
833 CPUSPARCState *env = &cpu->env;
834
835 if (scc->cpu_def) {
836 env->def = *scc->cpu_def;
837 }
838 }
839
sparc_get_nwindows(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)840 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name,
841 void *opaque, Error **errp)
842 {
843 SPARCCPU *cpu = SPARC_CPU(obj);
844 int64_t value = cpu->env.def.nwindows;
845
846 visit_type_int(v, name, &value, errp);
847 }
848
sparc_set_nwindows(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)849 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name,
850 void *opaque, Error **errp)
851 {
852 const int64_t min = MIN_NWINDOWS;
853 const int64_t max = MAX_NWINDOWS;
854 SPARCCPU *cpu = SPARC_CPU(obj);
855 int64_t value;
856
857 if (!visit_type_int(v, name, &value, errp)) {
858 return;
859 }
860
861 if (value < min || value > max) {
862 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
863 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
864 object_get_typename(obj), name ? name : "null",
865 value, min, max);
866 return;
867 }
868 cpu->env.def.nwindows = value;
869 }
870
871 static PropertyInfo qdev_prop_nwindows = {
872 .name = "int",
873 .get = sparc_get_nwindows,
874 .set = sparc_set_nwindows,
875 };
876
877 /* This must match feature_name[]. */
878 static Property sparc_cpu_properties[] = {
879 DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features,
880 CPU_FEATURE_BIT_FLOAT128, false),
881 #ifdef TARGET_SPARC64
882 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features,
883 CPU_FEATURE_BIT_CMT, false),
884 DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features,
885 CPU_FEATURE_BIT_GL, false),
886 DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features,
887 CPU_FEATURE_BIT_HYPV, false),
888 DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features,
889 CPU_FEATURE_BIT_VIS1, false),
890 DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features,
891 CPU_FEATURE_BIT_VIS2, false),
892 DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features,
893 CPU_FEATURE_BIT_FMAF, false),
894 DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features,
895 CPU_FEATURE_BIT_VIS3, false),
896 DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features,
897 CPU_FEATURE_BIT_IMA, false),
898 DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features,
899 CPU_FEATURE_BIT_VIS4, false),
900 #else
901 DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features,
902 CPU_FEATURE_BIT_MUL, false),
903 DEFINE_PROP_BIT("div", SPARCCPU, env.def.features,
904 CPU_FEATURE_BIT_DIV, false),
905 DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features,
906 CPU_FEATURE_BIT_FSMULD, false),
907 #endif
908 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
909 qdev_prop_uint64, target_ulong),
910 DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
911 DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
912 DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows,
913 qdev_prop_nwindows, uint32_t),
914 DEFINE_PROP_END_OF_LIST()
915 };
916
917 #ifndef CONFIG_USER_ONLY
918 #include "hw/core/sysemu-cpu-ops.h"
919
920 static const struct SysemuCPUOps sparc_sysemu_ops = {
921 .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
922 .legacy_vmsd = &vmstate_sparc_cpu,
923 };
924 #endif
925
926 #ifdef CONFIG_TCG
927 #include "hw/core/tcg-cpu-ops.h"
928
929 static const TCGCPUOps sparc_tcg_ops = {
930 .initialize = sparc_tcg_init,
931 .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
932 .restore_state_to_opc = sparc_restore_state_to_opc,
933
934 #ifndef CONFIG_USER_ONLY
935 .tlb_fill = sparc_cpu_tlb_fill,
936 .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
937 .cpu_exec_halt = sparc_cpu_has_work,
938 .do_interrupt = sparc_cpu_do_interrupt,
939 .do_transaction_failed = sparc_cpu_do_transaction_failed,
940 .do_unaligned_access = sparc_cpu_do_unaligned_access,
941 #endif /* !CONFIG_USER_ONLY */
942 };
943 #endif /* CONFIG_TCG */
944
sparc_cpu_class_init(ObjectClass * oc,void * data)945 static void sparc_cpu_class_init(ObjectClass *oc, void *data)
946 {
947 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
948 CPUClass *cc = CPU_CLASS(oc);
949 DeviceClass *dc = DEVICE_CLASS(oc);
950 ResettableClass *rc = RESETTABLE_CLASS(oc);
951
952 device_class_set_parent_realize(dc, sparc_cpu_realizefn,
953 &scc->parent_realize);
954 device_class_set_props(dc, sparc_cpu_properties);
955
956 resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL,
957 &scc->parent_phases);
958
959 cc->class_by_name = sparc_cpu_class_by_name;
960 cc->parse_features = sparc_cpu_parse_features;
961 cc->has_work = sparc_cpu_has_work;
962 cc->mmu_index = sparc_cpu_mmu_index;
963 cc->dump_state = sparc_cpu_dump_state;
964 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
965 cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
966 #endif
967 cc->set_pc = sparc_cpu_set_pc;
968 cc->get_pc = sparc_cpu_get_pc;
969 cc->gdb_read_register = sparc_cpu_gdb_read_register;
970 cc->gdb_write_register = sparc_cpu_gdb_write_register;
971 #ifndef CONFIG_USER_ONLY
972 cc->sysemu_ops = &sparc_sysemu_ops;
973 #endif
974 cc->disas_set_info = cpu_sparc_disas_set_info;
975
976 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
977 cc->gdb_num_core_regs = 86;
978 #else
979 cc->gdb_num_core_regs = 72;
980 #endif
981 cc->tcg_ops = &sparc_tcg_ops;
982 }
983
984 static const TypeInfo sparc_cpu_type_info = {
985 .name = TYPE_SPARC_CPU,
986 .parent = TYPE_CPU,
987 .instance_size = sizeof(SPARCCPU),
988 .instance_align = __alignof(SPARCCPU),
989 .instance_init = sparc_cpu_initfn,
990 .abstract = true,
991 .class_size = sizeof(SPARCCPUClass),
992 .class_init = sparc_cpu_class_init,
993 };
994
sparc_cpu_cpudef_class_init(ObjectClass * oc,void * data)995 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
996 {
997 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
998 scc->cpu_def = data;
999 }
1000
sparc_register_cpudef_type(const struct sparc_def_t * def)1001 static void sparc_register_cpudef_type(const struct sparc_def_t *def)
1002 {
1003 char *typename = sparc_cpu_type_name(def->name);
1004 TypeInfo ti = {
1005 .name = typename,
1006 .parent = TYPE_SPARC_CPU,
1007 .class_init = sparc_cpu_cpudef_class_init,
1008 .class_data = (void *)def,
1009 };
1010
1011 type_register(&ti);
1012 g_free(typename);
1013 }
1014
sparc_cpu_register_types(void)1015 static void sparc_cpu_register_types(void)
1016 {
1017 int i;
1018
1019 type_register_static(&sparc_cpu_type_info);
1020 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1021 sparc_register_cpudef_type(&sparc_defs[i]);
1022 }
1023 }
1024
1025 type_init(sparc_cpu_register_types)
1026