1 /*
2 * Host code generation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21
22 #include "trace.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg.h"
26 #if defined(CONFIG_USER_ONLY)
27 #include "qemu.h"
28 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
29 #include <sys/param.h>
30 #if __FreeBSD_version >= 700104
31 #define HAVE_KINFO_GETVMMAP
32 #define sigqueue sigqueue_freebsd /* avoid redefinition */
33 #include <sys/proc.h>
34 #include <machine/profile.h>
35 #define _KERNEL
36 #include <sys/user.h>
37 #undef _KERNEL
38 #undef sigqueue
39 #include <libutil.h>
40 #endif
41 #endif
42 #else
43 #include "exec/ram_addr.h"
44 #endif
45
46 #include "exec/cputlb.h"
47 #include "exec/page-protection.h"
48 #include "tb-internal.h"
49 #include "exec/translator.h"
50 #include "exec/tb-flush.h"
51 #include "qemu/bitmap.h"
52 #include "qemu/qemu-print.h"
53 #include "qemu/main-loop.h"
54 #include "qemu/cacheinfo.h"
55 #include "qemu/timer.h"
56 #include "exec/log.h"
57 #include "system/cpu-timers.h"
58 #include "system/tcg.h"
59 #include "qapi/error.h"
60 #include "accel/tcg/cpu-ops.h"
61 #include "tb-jmp-cache.h"
62 #include "tb-hash.h"
63 #include "tb-context.h"
64 #include "tb-internal.h"
65 #include "internal-common.h"
66 #include "internal-target.h"
67 #include "tcg/perf.h"
68 #include "tcg/insn-start-words.h"
69
70 TBContext tb_ctx;
71
72 /*
73 * Encode VAL as a signed leb128 sequence at P.
74 * Return P incremented past the encoded value.
75 */
encode_sleb128(uint8_t * p,int64_t val)76 static uint8_t *encode_sleb128(uint8_t *p, int64_t val)
77 {
78 int more, byte;
79
80 do {
81 byte = val & 0x7f;
82 val >>= 7;
83 more = !((val == 0 && (byte & 0x40) == 0)
84 || (val == -1 && (byte & 0x40) != 0));
85 if (more) {
86 byte |= 0x80;
87 }
88 *p++ = byte;
89 } while (more);
90
91 return p;
92 }
93
94 /*
95 * Decode a signed leb128 sequence at *PP; increment *PP past the
96 * decoded value. Return the decoded value.
97 */
decode_sleb128(const uint8_t ** pp)98 static int64_t decode_sleb128(const uint8_t **pp)
99 {
100 const uint8_t *p = *pp;
101 int64_t val = 0;
102 int byte, shift = 0;
103
104 do {
105 byte = *p++;
106 val |= (int64_t)(byte & 0x7f) << shift;
107 shift += 7;
108 } while (byte & 0x80);
109 if (shift < 64 && (byte & 0x40)) {
110 val |= -(int64_t)1 << shift;
111 }
112
113 *pp = p;
114 return val;
115 }
116
117 /* Encode the data collected about the instructions while compiling TB.
118 Place the data at BLOCK, and return the number of bytes consumed.
119
120 The logical table consists of TARGET_INSN_START_WORDS target_ulong's,
121 which come from the target's insn_start data, followed by a uintptr_t
122 which comes from the host pc of the end of the code implementing the insn.
123
124 Each line of the table is encoded as sleb128 deltas from the previous
125 line. The seed for the first line is { tb->pc, 0..., tb->tc.ptr }.
126 That is, the first column is seeded with the guest pc, the last column
127 with the host pc, and the middle columns with zeros. */
128
encode_search(TranslationBlock * tb,uint8_t * block)129 static int encode_search(TranslationBlock *tb, uint8_t *block)
130 {
131 uint8_t *highwater = tcg_ctx->code_gen_highwater;
132 uint64_t *insn_data = tcg_ctx->gen_insn_data;
133 uint16_t *insn_end_off = tcg_ctx->gen_insn_end_off;
134 uint8_t *p = block;
135 int i, j, n;
136
137 for (i = 0, n = tb->icount; i < n; ++i) {
138 uint64_t prev, curr;
139
140 for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
141 if (i == 0) {
142 prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0);
143 } else {
144 prev = insn_data[(i - 1) * TARGET_INSN_START_WORDS + j];
145 }
146 curr = insn_data[i * TARGET_INSN_START_WORDS + j];
147 p = encode_sleb128(p, curr - prev);
148 }
149 prev = (i == 0 ? 0 : insn_end_off[i - 1]);
150 curr = insn_end_off[i];
151 p = encode_sleb128(p, curr - prev);
152
153 /* Test for (pending) buffer overflow. The assumption is that any
154 one row beginning below the high water mark cannot overrun
155 the buffer completely. Thus we can test for overflow after
156 encoding a row without having to check during encoding. */
157 if (unlikely(p > highwater)) {
158 return -1;
159 }
160 }
161
162 return p - block;
163 }
164
cpu_unwind_data_from_tb(TranslationBlock * tb,uintptr_t host_pc,uint64_t * data)165 static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
166 uint64_t *data)
167 {
168 uintptr_t iter_pc = (uintptr_t)tb->tc.ptr;
169 const uint8_t *p = tb->tc.ptr + tb->tc.size;
170 int i, j, num_insns = tb->icount;
171
172 host_pc -= GETPC_ADJ;
173
174 if (host_pc < iter_pc) {
175 return -1;
176 }
177
178 memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
179 if (!(tb_cflags(tb) & CF_PCREL)) {
180 data[0] = tb->pc;
181 }
182
183 /*
184 * Reconstruct the stored insn data while looking for the point
185 * at which the end of the insn exceeds host_pc.
186 */
187 for (i = 0; i < num_insns; ++i) {
188 for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
189 data[j] += decode_sleb128(&p);
190 }
191 iter_pc += decode_sleb128(&p);
192 if (iter_pc > host_pc) {
193 return num_insns - i;
194 }
195 }
196 return -1;
197 }
198
199 /*
200 * The cpu state corresponding to 'host_pc' is restored in
201 * preparation for exiting the TB.
202 */
cpu_restore_state_from_tb(CPUState * cpu,TranslationBlock * tb,uintptr_t host_pc)203 void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
204 uintptr_t host_pc)
205 {
206 uint64_t data[TARGET_INSN_START_WORDS];
207 int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data);
208
209 if (insns_left < 0) {
210 return;
211 }
212
213 if (tb_cflags(tb) & CF_USE_ICOUNT) {
214 assert(icount_enabled());
215 /*
216 * Reset the cycle counter to the start of the block and
217 * shift if to the number of actually executed instructions.
218 */
219 cpu->neg.icount_decr.u16.low += insns_left;
220 }
221
222 cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data);
223 }
224
cpu_restore_state(CPUState * cpu,uintptr_t host_pc)225 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
226 {
227 /*
228 * The host_pc has to be in the rx region of the code buffer.
229 * If it is not we will not be able to resolve it here.
230 * The two cases where host_pc will not be correct are:
231 *
232 * - fault during translation (instruction fetch)
233 * - fault from helper (not using GETPC() macro)
234 *
235 * Either way we need return early as we can't resolve it here.
236 */
237 if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
238 TranslationBlock *tb = tcg_tb_lookup(host_pc);
239 if (tb) {
240 cpu_restore_state_from_tb(cpu, tb, host_pc);
241 return true;
242 }
243 }
244 return false;
245 }
246
cpu_unwind_state_data(CPUState * cpu,uintptr_t host_pc,uint64_t * data)247 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data)
248 {
249 if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
250 TranslationBlock *tb = tcg_tb_lookup(host_pc);
251 if (tb) {
252 return cpu_unwind_data_from_tb(tb, host_pc, data) >= 0;
253 }
254 }
255 return false;
256 }
257
page_init(void)258 void page_init(void)
259 {
260 page_table_config_init();
261 }
262
263 /*
264 * Isolate the portion of code gen which can setjmp/longjmp.
265 * Return the size of the generated code, or negative on error.
266 */
setjmp_gen_code(CPUArchState * env,TranslationBlock * tb,vaddr pc,void * host_pc,int * max_insns,int64_t * ti)267 static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb,
268 vaddr pc, void *host_pc,
269 int *max_insns, int64_t *ti)
270 {
271 int ret = sigsetjmp(tcg_ctx->jmp_trans, 0);
272 if (unlikely(ret != 0)) {
273 return ret;
274 }
275
276 tcg_func_start(tcg_ctx);
277
278 CPUState *cs = env_cpu(env);
279 tcg_ctx->cpu = cs;
280 cs->cc->tcg_ops->translate_code(cs, tb, max_insns, pc, host_pc);
281
282 assert(tb->size != 0);
283 tcg_ctx->cpu = NULL;
284 *max_insns = tb->icount;
285
286 return tcg_gen_code(tcg_ctx, tb, pc);
287 }
288
289 /* Called with mmap_lock held for user mode emulation. */
tb_gen_code(CPUState * cpu,vaddr pc,uint64_t cs_base,uint32_t flags,int cflags)290 TranslationBlock *tb_gen_code(CPUState *cpu,
291 vaddr pc, uint64_t cs_base,
292 uint32_t flags, int cflags)
293 {
294 CPUArchState *env = cpu_env(cpu);
295 TranslationBlock *tb, *existing_tb;
296 tb_page_addr_t phys_pc, phys_p2;
297 tcg_insn_unit *gen_code_buf;
298 int gen_code_size, search_size, max_insns;
299 int64_t ti;
300 void *host_pc;
301
302 assert_memory_lock();
303 qemu_thread_jit_write();
304
305 phys_pc = get_page_addr_code_hostp(env, pc, &host_pc);
306
307 if (phys_pc == -1) {
308 /* Generate a one-shot TB with 1 insn in it */
309 cflags = (cflags & ~CF_COUNT_MASK) | 1;
310 }
311
312 max_insns = cflags & CF_COUNT_MASK;
313 if (max_insns == 0) {
314 max_insns = TCG_MAX_INSNS;
315 }
316 QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 != TCG_MAX_INSNS);
317
318 buffer_overflow:
319 assert_no_pages_locked();
320 tb = tcg_tb_alloc(tcg_ctx);
321 if (unlikely(!tb)) {
322 /* flush must be done */
323 tb_flush(cpu);
324 mmap_unlock();
325 /* Make the execution loop process the flush as soon as possible. */
326 cpu->exception_index = EXCP_INTERRUPT;
327 cpu_loop_exit(cpu);
328 }
329
330 gen_code_buf = tcg_ctx->code_gen_ptr;
331 tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf);
332 if (!(cflags & CF_PCREL)) {
333 tb->pc = pc;
334 }
335 tb->cs_base = cs_base;
336 tb->flags = flags;
337 tb->cflags = cflags;
338 tb_set_page_addr0(tb, phys_pc);
339 tb_set_page_addr1(tb, -1);
340 if (phys_pc != -1) {
341 tb_lock_page0(phys_pc);
342 }
343
344 tcg_ctx->gen_tb = tb;
345 tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
346 #ifdef CONFIG_SOFTMMU
347 tcg_ctx->page_bits = TARGET_PAGE_BITS;
348 tcg_ctx->page_mask = TARGET_PAGE_MASK;
349 tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
350 #endif
351 tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
352 #ifdef TCG_GUEST_DEFAULT_MO
353 tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO;
354 #else
355 tcg_ctx->guest_mo = TCG_MO_ALL;
356 #endif
357
358 restart_translate:
359 trace_translate_block(tb, pc, tb->tc.ptr);
360
361 gen_code_size = setjmp_gen_code(env, tb, pc, host_pc, &max_insns, &ti);
362 if (unlikely(gen_code_size < 0)) {
363 switch (gen_code_size) {
364 case -1:
365 /*
366 * Overflow of code_gen_buffer, or the current slice of it.
367 *
368 * TODO: We don't need to re-do tcg_ops->translate_code, nor
369 * should we re-do the tcg optimization currently hidden
370 * inside tcg_gen_code. All that should be required is to
371 * flush the TBs, allocate a new TB, re-initialize it per
372 * above, and re-do the actual code generation.
373 */
374 qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT,
375 "Restarting code generation for "
376 "code_gen_buffer overflow\n");
377 tb_unlock_pages(tb);
378 tcg_ctx->gen_tb = NULL;
379 goto buffer_overflow;
380
381 case -2:
382 /*
383 * The code generated for the TranslationBlock is too large.
384 * The maximum size allowed by the unwind info is 64k.
385 * There may be stricter constraints from relocations
386 * in the tcg backend.
387 *
388 * Try again with half as many insns as we attempted this time.
389 * If a single insn overflows, there's a bug somewhere...
390 */
391 assert(max_insns > 1);
392 max_insns /= 2;
393 qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT,
394 "Restarting code generation with "
395 "smaller translation block (max %d insns)\n",
396 max_insns);
397
398 /*
399 * The half-sized TB may not cross pages.
400 * TODO: Fix all targets that cross pages except with
401 * the first insn, at which point this can't be reached.
402 */
403 phys_p2 = tb_page_addr1(tb);
404 if (unlikely(phys_p2 != -1)) {
405 tb_unlock_page1(phys_pc, phys_p2);
406 tb_set_page_addr1(tb, -1);
407 }
408 goto restart_translate;
409
410 case -3:
411 /*
412 * We had a page lock ordering problem. In order to avoid
413 * deadlock we had to drop the lock on page0, which means
414 * that everything we translated so far is compromised.
415 * Restart with locks held on both pages.
416 */
417 qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT,
418 "Restarting code generation with re-locked pages");
419 goto restart_translate;
420
421 default:
422 g_assert_not_reached();
423 }
424 }
425 tcg_ctx->gen_tb = NULL;
426
427 search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size);
428 if (unlikely(search_size < 0)) {
429 tb_unlock_pages(tb);
430 goto buffer_overflow;
431 }
432 tb->tc.size = gen_code_size;
433
434 /*
435 * For CF_PCREL, attribute all executions of the generated code
436 * to its first mapping.
437 */
438 perf_report_code(pc, tb, tcg_splitwx_to_rx(gen_code_buf));
439
440 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) &&
441 qemu_log_in_addr_range(pc)) {
442 FILE *logfile = qemu_log_trylock();
443 if (logfile) {
444 int code_size, data_size;
445 const tcg_target_ulong *rx_data_gen_ptr;
446 size_t chunk_start;
447 int insn = 0;
448
449 if (tcg_ctx->data_gen_ptr) {
450 rx_data_gen_ptr = tcg_splitwx_to_rx(tcg_ctx->data_gen_ptr);
451 code_size = (const void *)rx_data_gen_ptr - tb->tc.ptr;
452 data_size = gen_code_size - code_size;
453 } else {
454 rx_data_gen_ptr = 0;
455 code_size = gen_code_size;
456 data_size = 0;
457 }
458
459 /* Dump header and the first instruction */
460 fprintf(logfile, "OUT: [size=%d]\n", gen_code_size);
461 fprintf(logfile,
462 " -- guest addr 0x%016" PRIx64 " + tb prologue\n",
463 tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
464 chunk_start = tcg_ctx->gen_insn_end_off[insn];
465 disas(logfile, tb->tc.ptr, chunk_start);
466
467 /*
468 * Dump each instruction chunk, wrapping up empty chunks into
469 * the next instruction. The whole array is offset so the
470 * first entry is the beginning of the 2nd instruction.
471 */
472 while (insn < tb->icount) {
473 size_t chunk_end = tcg_ctx->gen_insn_end_off[insn];
474 if (chunk_end > chunk_start) {
475 fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n",
476 tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
477 disas(logfile, tb->tc.ptr + chunk_start,
478 chunk_end - chunk_start);
479 chunk_start = chunk_end;
480 }
481 insn++;
482 }
483
484 if (chunk_start < code_size) {
485 fprintf(logfile, " -- tb slow paths + alignment\n");
486 disas(logfile, tb->tc.ptr + chunk_start,
487 code_size - chunk_start);
488 }
489
490 /* Finally dump any data we may have after the block */
491 if (data_size) {
492 int i;
493 fprintf(logfile, " data: [size=%d]\n", data_size);
494 for (i = 0; i < data_size / sizeof(tcg_target_ulong); i++) {
495 if (sizeof(tcg_target_ulong) == 8) {
496 fprintf(logfile,
497 "0x%08" PRIxPTR ": .quad 0x%016" TCG_PRIlx "\n",
498 (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]);
499 } else if (sizeof(tcg_target_ulong) == 4) {
500 fprintf(logfile,
501 "0x%08" PRIxPTR ": .long 0x%08" TCG_PRIlx "\n",
502 (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]);
503 } else {
504 qemu_build_not_reached();
505 }
506 }
507 }
508 fprintf(logfile, "\n");
509 qemu_log_unlock(logfile);
510 }
511 }
512
513 qatomic_set(&tcg_ctx->code_gen_ptr, (void *)
514 ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size,
515 CODE_GEN_ALIGN));
516
517 /* init jump list */
518 qemu_spin_init(&tb->jmp_lock);
519 tb->jmp_list_head = (uintptr_t)NULL;
520 tb->jmp_list_next[0] = (uintptr_t)NULL;
521 tb->jmp_list_next[1] = (uintptr_t)NULL;
522 tb->jmp_dest[0] = (uintptr_t)NULL;
523 tb->jmp_dest[1] = (uintptr_t)NULL;
524
525 /* init original jump addresses which have been set during tcg_gen_code() */
526 if (tb->jmp_reset_offset[0] != TB_JMP_OFFSET_INVALID) {
527 tb_reset_jump(tb, 0);
528 }
529 if (tb->jmp_reset_offset[1] != TB_JMP_OFFSET_INVALID) {
530 tb_reset_jump(tb, 1);
531 }
532
533 /*
534 * Insert TB into the corresponding region tree before publishing it
535 * through QHT. Otherwise rewinding happened in the TB might fail to
536 * lookup itself using host PC.
537 */
538 tcg_tb_insert(tb);
539
540 /*
541 * If the TB is not associated with a physical RAM page then it must be
542 * a temporary one-insn TB.
543 *
544 * Such TBs must be added to region trees in order to make sure that
545 * restore_state_to_opc() - which on some architectures is not limited to
546 * rewinding, but also affects exception handling! - is called when such a
547 * TB causes an exception.
548 *
549 * At the same time, temporary one-insn TBs must be executed at most once,
550 * because subsequent reads from, e.g., I/O memory may return different
551 * values. So return early before attempting to link to other TBs or add
552 * to the QHT.
553 */
554 if (tb_page_addr0(tb) == -1) {
555 assert_no_pages_locked();
556 return tb;
557 }
558
559 /*
560 * No explicit memory barrier is required -- tb_link_page() makes the
561 * TB visible in a consistent state.
562 */
563 existing_tb = tb_link_page(tb);
564 assert_no_pages_locked();
565
566 /* if the TB already exists, discard what we just translated */
567 if (unlikely(existing_tb != tb)) {
568 uintptr_t orig_aligned = (uintptr_t)gen_code_buf;
569
570 orig_aligned -= ROUND_UP(sizeof(*tb), qemu_icache_linesize);
571 qatomic_set(&tcg_ctx->code_gen_ptr, (void *)orig_aligned);
572 tcg_tb_remove(tb);
573 return existing_tb;
574 }
575 return tb;
576 }
577
578 /* user-mode: call with mmap_lock held */
tb_check_watchpoint(CPUState * cpu,uintptr_t retaddr)579 void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr)
580 {
581 TranslationBlock *tb;
582
583 assert_memory_lock();
584
585 tb = tcg_tb_lookup(retaddr);
586 if (tb) {
587 /* We can use retranslation to find the PC. */
588 cpu_restore_state_from_tb(cpu, tb, retaddr);
589 tb_phys_invalidate(tb, -1);
590 } else {
591 /* The exception probably happened in a helper. The CPU state should
592 have been saved before calling it. Fetch the PC from there. */
593 CPUArchState *env = cpu_env(cpu);
594 vaddr pc;
595 uint64_t cs_base;
596 tb_page_addr_t addr;
597 uint32_t flags;
598
599 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
600 addr = get_page_addr_code(env, pc);
601 if (addr != -1) {
602 tb_invalidate_phys_range(addr, addr);
603 }
604 }
605 }
606
607 #ifndef CONFIG_USER_ONLY
608 /*
609 * In deterministic execution mode, instructions doing device I/Os
610 * must be at the end of the TB.
611 *
612 * Called by softmmu_template.h, with iothread mutex not held.
613 */
cpu_io_recompile(CPUState * cpu,uintptr_t retaddr)614 void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
615 {
616 TranslationBlock *tb;
617 CPUClass *cc;
618 uint32_t n;
619
620 tb = tcg_tb_lookup(retaddr);
621 if (!tb) {
622 cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p",
623 (void *)retaddr);
624 }
625 cpu_restore_state_from_tb(cpu, tb, retaddr);
626
627 /*
628 * Some guests must re-execute the branch when re-executing a delay
629 * slot instruction. When this is the case, adjust icount and N
630 * to account for the re-execution of the branch.
631 */
632 n = 1;
633 cc = cpu->cc;
634 if (cc->tcg_ops->io_recompile_replay_branch &&
635 cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) {
636 cpu->neg.icount_decr.u16.low++;
637 n = 2;
638 }
639
640 /*
641 * Exit the loop and potentially generate a new TB executing the
642 * just the I/O insns. We also limit instrumentation to memory
643 * operations only (which execute after completion) so we don't
644 * double instrument the instruction. Also don't let an IRQ sneak
645 * in before we execute it.
646 */
647 cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_NOIRQ | n;
648
649 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
650 vaddr pc = cpu->cc->get_pc(cpu);
651 if (qemu_log_in_addr_range(pc)) {
652 qemu_log("cpu_io_recompile: rewound execution of TB to %016"
653 VADDR_PRIx "\n", pc);
654 }
655 }
656
657 cpu_loop_exit_noexc(cpu);
658 }
659
660 #endif /* CONFIG_USER_ONLY */
661
662 /*
663 * Called by generic code at e.g. cpu reset after cpu creation,
664 * therefore we must be prepared to allocate the jump cache.
665 */
tcg_flush_jmp_cache(CPUState * cpu)666 void tcg_flush_jmp_cache(CPUState *cpu)
667 {
668 CPUJumpCache *jc = cpu->tb_jmp_cache;
669
670 /* During early initialization, the cache may not yet be allocated. */
671 if (unlikely(jc == NULL)) {
672 return;
673 }
674
675 for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) {
676 qatomic_set(&jc->array[i].tb, NULL);
677 }
678 }
679