1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI K3 R5F (MCU) Remote Processor driver
4 *
5 * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/mailbox_client.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/of_platform.h>
19 #include <linux/omap-mailbox.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/remoteproc.h>
23 #include <linux/reset.h>
24 #include <linux/slab.h>
25
26 #include "omap_remoteproc.h"
27 #include "remoteproc_internal.h"
28 #include "ti_sci_proc.h"
29
30 /* This address can either be for ATCM or BTCM with the other at address 0x0 */
31 #define K3_R5_TCM_DEV_ADDR 0x41010000
32
33 /* R5 TI-SCI Processor Configuration Flags */
34 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
35 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
36 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
37 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
38 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
39 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
40 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
41 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
42 /* Available from J7200 SoCs onwards */
43 #define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000
44 /* Applicable to only AM64x SoCs */
45 #define PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE 0x00008000
46
47 /* R5 TI-SCI Processor Control Flags */
48 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
49
50 /* R5 TI-SCI Processor Status Flags */
51 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
52 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
53 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
54 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
55 /* Applicable to only AM64x SoCs */
56 #define PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY 0x00000200
57
58 /**
59 * struct k3_r5_mem - internal memory structure
60 * @cpu_addr: MPU virtual address of the memory region
61 * @bus_addr: Bus address used to access the memory region
62 * @dev_addr: Device address from remoteproc view
63 * @size: Size of the memory region
64 */
65 struct k3_r5_mem {
66 void __iomem *cpu_addr;
67 phys_addr_t bus_addr;
68 u32 dev_addr;
69 size_t size;
70 };
71
72 /*
73 * All cluster mode values are not applicable on all SoCs. The following
74 * are the modes supported on various SoCs:
75 * Split mode : AM65x, J721E, J7200 and AM64x SoCs
76 * LockStep mode : AM65x, J721E and J7200 SoCs
77 * Single-CPU mode : AM64x SoCs only
78 * Single-Core mode : AM62x, AM62A SoCs
79 */
80 enum cluster_mode {
81 CLUSTER_MODE_SPLIT = 0,
82 CLUSTER_MODE_LOCKSTEP,
83 CLUSTER_MODE_SINGLECPU,
84 CLUSTER_MODE_SINGLECORE
85 };
86
87 /**
88 * struct k3_r5_soc_data - match data to handle SoC variations
89 * @tcm_is_double: flag to denote the larger unified TCMs in certain modes
90 * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
91 * @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode
92 * @is_single_core: flag to denote if SoC/IP has only single core R5
93 */
94 struct k3_r5_soc_data {
95 bool tcm_is_double;
96 bool tcm_ecc_autoinit;
97 bool single_cpu_mode;
98 bool is_single_core;
99 };
100
101 /**
102 * struct k3_r5_cluster - K3 R5F Cluster structure
103 * @dev: cached device pointer
104 * @mode: Mode to configure the Cluster - Split or LockStep
105 * @cores: list of R5 cores within the cluster
106 * @core_transition: wait queue to sync core state changes
107 * @soc_data: SoC-specific feature data for a R5FSS
108 */
109 struct k3_r5_cluster {
110 struct device *dev;
111 enum cluster_mode mode;
112 struct list_head cores;
113 wait_queue_head_t core_transition;
114 const struct k3_r5_soc_data *soc_data;
115 };
116
117 /**
118 * struct k3_r5_core - K3 R5 core structure
119 * @elem: linked list item
120 * @dev: cached device pointer
121 * @rproc: rproc handle representing this core
122 * @mem: internal memory regions data
123 * @sram: on-chip SRAM memory regions data
124 * @num_mems: number of internal memory regions
125 * @num_sram: number of on-chip SRAM memory regions
126 * @reset: reset control handle
127 * @tsp: TI-SCI processor control handle
128 * @ti_sci: TI-SCI handle
129 * @ti_sci_id: TI-SCI device identifier
130 * @atcm_enable: flag to control ATCM enablement
131 * @btcm_enable: flag to control BTCM enablement
132 * @loczrama: flag to dictate which TCM is at device address 0x0
133 * @released_from_reset: flag to signal when core is out of reset
134 */
135 struct k3_r5_core {
136 struct list_head elem;
137 struct device *dev;
138 struct rproc *rproc;
139 struct k3_r5_mem *mem;
140 struct k3_r5_mem *sram;
141 int num_mems;
142 int num_sram;
143 struct reset_control *reset;
144 struct ti_sci_proc *tsp;
145 const struct ti_sci_handle *ti_sci;
146 u32 ti_sci_id;
147 u32 atcm_enable;
148 u32 btcm_enable;
149 u32 loczrama;
150 bool released_from_reset;
151 };
152
153 /**
154 * struct k3_r5_rproc - K3 remote processor state
155 * @dev: cached device pointer
156 * @cluster: cached pointer to parent cluster structure
157 * @mbox: mailbox channel handle
158 * @client: mailbox client to request the mailbox channel
159 * @rproc: rproc handle
160 * @core: cached pointer to r5 core structure being used
161 * @rmem: reserved memory regions data
162 * @num_rmems: number of reserved memory regions
163 */
164 struct k3_r5_rproc {
165 struct device *dev;
166 struct k3_r5_cluster *cluster;
167 struct mbox_chan *mbox;
168 struct mbox_client client;
169 struct rproc *rproc;
170 struct k3_r5_core *core;
171 struct k3_r5_mem *rmem;
172 int num_rmems;
173 };
174
175 /**
176 * k3_r5_rproc_mbox_callback() - inbound mailbox message handler
177 * @client: mailbox client pointer used for requesting the mailbox channel
178 * @data: mailbox payload
179 *
180 * This handler is invoked by the OMAP mailbox driver whenever a mailbox
181 * message is received. Usually, the mailbox payload simply contains
182 * the index of the virtqueue that is kicked by the remote processor,
183 * and we let remoteproc core handle it.
184 *
185 * In addition to virtqueue indices, we also have some out-of-band values
186 * that indicate different events. Those values are deliberately very
187 * large so they don't coincide with virtqueue indices.
188 */
k3_r5_rproc_mbox_callback(struct mbox_client * client,void * data)189 static void k3_r5_rproc_mbox_callback(struct mbox_client *client, void *data)
190 {
191 struct k3_r5_rproc *kproc = container_of(client, struct k3_r5_rproc,
192 client);
193 struct device *dev = kproc->rproc->dev.parent;
194 const char *name = kproc->rproc->name;
195 u32 msg = omap_mbox_message(data);
196
197 dev_dbg(dev, "mbox msg: 0x%x\n", msg);
198
199 switch (msg) {
200 case RP_MBOX_CRASH:
201 /*
202 * remoteproc detected an exception, but error recovery is not
203 * supported. So, just log this for now
204 */
205 dev_err(dev, "K3 R5F rproc %s crashed\n", name);
206 break;
207 case RP_MBOX_ECHO_REPLY:
208 dev_info(dev, "received echo reply from %s\n", name);
209 break;
210 default:
211 /* silently handle all other valid messages */
212 if (msg >= RP_MBOX_READY && msg < RP_MBOX_END_MSG)
213 return;
214 if (msg > kproc->rproc->max_notifyid) {
215 dev_dbg(dev, "dropping unknown message 0x%x", msg);
216 return;
217 }
218 /* msg contains the index of the triggered vring */
219 if (rproc_vq_interrupt(kproc->rproc, msg) == IRQ_NONE)
220 dev_dbg(dev, "no message was found in vqid %d\n", msg);
221 }
222 }
223
224 /* kick a virtqueue */
k3_r5_rproc_kick(struct rproc * rproc,int vqid)225 static void k3_r5_rproc_kick(struct rproc *rproc, int vqid)
226 {
227 struct k3_r5_rproc *kproc = rproc->priv;
228 struct device *dev = rproc->dev.parent;
229 mbox_msg_t msg = (mbox_msg_t)vqid;
230 int ret;
231
232 /* send the index of the triggered virtqueue in the mailbox payload */
233 ret = mbox_send_message(kproc->mbox, (void *)msg);
234 if (ret < 0)
235 dev_err(dev, "failed to send mailbox message, status = %d\n",
236 ret);
237 }
238
k3_r5_split_reset(struct k3_r5_core * core)239 static int k3_r5_split_reset(struct k3_r5_core *core)
240 {
241 int ret;
242
243 ret = reset_control_assert(core->reset);
244 if (ret) {
245 dev_err(core->dev, "local-reset assert failed, ret = %d\n",
246 ret);
247 return ret;
248 }
249
250 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
251 core->ti_sci_id);
252 if (ret) {
253 dev_err(core->dev, "module-reset assert failed, ret = %d\n",
254 ret);
255 if (reset_control_deassert(core->reset))
256 dev_warn(core->dev, "local-reset deassert back failed\n");
257 }
258
259 return ret;
260 }
261
k3_r5_split_release(struct k3_r5_core * core)262 static int k3_r5_split_release(struct k3_r5_core *core)
263 {
264 int ret;
265
266 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
267 core->ti_sci_id);
268 if (ret) {
269 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
270 ret);
271 return ret;
272 }
273
274 ret = reset_control_deassert(core->reset);
275 if (ret) {
276 dev_err(core->dev, "local-reset deassert failed, ret = %d\n",
277 ret);
278 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
279 core->ti_sci_id))
280 dev_warn(core->dev, "module-reset assert back failed\n");
281 }
282
283 return ret;
284 }
285
k3_r5_lockstep_reset(struct k3_r5_cluster * cluster)286 static int k3_r5_lockstep_reset(struct k3_r5_cluster *cluster)
287 {
288 struct k3_r5_core *core;
289 int ret;
290
291 /* assert local reset on all applicable cores */
292 list_for_each_entry(core, &cluster->cores, elem) {
293 ret = reset_control_assert(core->reset);
294 if (ret) {
295 dev_err(core->dev, "local-reset assert failed, ret = %d\n",
296 ret);
297 core = list_prev_entry(core, elem);
298 goto unroll_local_reset;
299 }
300 }
301
302 /* disable PSC modules on all applicable cores */
303 list_for_each_entry(core, &cluster->cores, elem) {
304 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
305 core->ti_sci_id);
306 if (ret) {
307 dev_err(core->dev, "module-reset assert failed, ret = %d\n",
308 ret);
309 goto unroll_module_reset;
310 }
311 }
312
313 return 0;
314
315 unroll_module_reset:
316 list_for_each_entry_continue_reverse(core, &cluster->cores, elem) {
317 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
318 core->ti_sci_id))
319 dev_warn(core->dev, "module-reset assert back failed\n");
320 }
321 core = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
322 unroll_local_reset:
323 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
324 if (reset_control_deassert(core->reset))
325 dev_warn(core->dev, "local-reset deassert back failed\n");
326 }
327
328 return ret;
329 }
330
k3_r5_lockstep_release(struct k3_r5_cluster * cluster)331 static int k3_r5_lockstep_release(struct k3_r5_cluster *cluster)
332 {
333 struct k3_r5_core *core;
334 int ret;
335
336 /* enable PSC modules on all applicable cores */
337 list_for_each_entry_reverse(core, &cluster->cores, elem) {
338 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
339 core->ti_sci_id);
340 if (ret) {
341 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
342 ret);
343 core = list_next_entry(core, elem);
344 goto unroll_module_reset;
345 }
346 }
347
348 /* deassert local reset on all applicable cores */
349 list_for_each_entry_reverse(core, &cluster->cores, elem) {
350 ret = reset_control_deassert(core->reset);
351 if (ret) {
352 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
353 ret);
354 goto unroll_local_reset;
355 }
356 }
357
358 return 0;
359
360 unroll_local_reset:
361 list_for_each_entry_continue(core, &cluster->cores, elem) {
362 if (reset_control_assert(core->reset))
363 dev_warn(core->dev, "local-reset assert back failed\n");
364 }
365 core = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
366 unroll_module_reset:
367 list_for_each_entry_from(core, &cluster->cores, elem) {
368 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
369 core->ti_sci_id))
370 dev_warn(core->dev, "module-reset assert back failed\n");
371 }
372
373 return ret;
374 }
375
k3_r5_core_halt(struct k3_r5_core * core)376 static inline int k3_r5_core_halt(struct k3_r5_core *core)
377 {
378 return ti_sci_proc_set_control(core->tsp,
379 PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
380 }
381
k3_r5_core_run(struct k3_r5_core * core)382 static inline int k3_r5_core_run(struct k3_r5_core *core)
383 {
384 return ti_sci_proc_set_control(core->tsp,
385 0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT);
386 }
387
k3_r5_rproc_request_mbox(struct rproc * rproc)388 static int k3_r5_rproc_request_mbox(struct rproc *rproc)
389 {
390 struct k3_r5_rproc *kproc = rproc->priv;
391 struct mbox_client *client = &kproc->client;
392 struct device *dev = kproc->dev;
393 int ret;
394
395 client->dev = dev;
396 client->tx_done = NULL;
397 client->rx_callback = k3_r5_rproc_mbox_callback;
398 client->tx_block = false;
399 client->knows_txdone = false;
400
401 kproc->mbox = mbox_request_channel(client, 0);
402 if (IS_ERR(kproc->mbox))
403 return dev_err_probe(dev, PTR_ERR(kproc->mbox),
404 "mbox_request_channel failed\n");
405
406 /*
407 * Ping the remote processor, this is only for sanity-sake for now;
408 * there is no functional effect whatsoever.
409 *
410 * Note that the reply will _not_ arrive immediately: this message
411 * will wait in the mailbox fifo until the remote processor is booted.
412 */
413 ret = mbox_send_message(kproc->mbox, (void *)RP_MBOX_ECHO_REQUEST);
414 if (ret < 0) {
415 dev_err(dev, "mbox_send_message failed: %d\n", ret);
416 mbox_free_channel(kproc->mbox);
417 return ret;
418 }
419
420 return 0;
421 }
422
423 /*
424 * The R5F cores have controls for both a reset and a halt/run. The code
425 * execution from DDR requires the initial boot-strapping code to be run
426 * from the internal TCMs. This function is used to release the resets on
427 * applicable cores to allow loading into the TCMs. The .prepare() ops is
428 * invoked by remoteproc core before any firmware loading, and is followed
429 * by the .start() ops after loading to actually let the R5 cores run.
430 *
431 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to
432 * execute code, but combines the TCMs from both cores. The resets for both
433 * cores need to be released to make this possible, as the TCMs are in general
434 * private to each core. Only Core0 needs to be unhalted for running the
435 * cluster in this mode. The function uses the same reset logic as LockStep
436 * mode for this (though the behavior is agnostic of the reset release order).
437 * This callback is invoked only in remoteproc mode.
438 */
k3_r5_rproc_prepare(struct rproc * rproc)439 static int k3_r5_rproc_prepare(struct rproc *rproc)
440 {
441 struct k3_r5_rproc *kproc = rproc->priv;
442 struct k3_r5_cluster *cluster = kproc->cluster;
443 struct k3_r5_core *core = kproc->core;
444 struct device *dev = kproc->dev;
445 u32 ctrl = 0, cfg = 0, stat = 0;
446 u64 boot_vec = 0;
447 bool mem_init_dis;
448 int ret;
449
450 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl, &stat);
451 if (ret < 0)
452 return ret;
453 mem_init_dis = !!(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
454
455 /* Re-use LockStep-mode reset logic for Single-CPU mode */
456 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
457 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
458 k3_r5_lockstep_release(cluster) : k3_r5_split_release(core);
459 if (ret) {
460 dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n",
461 ret);
462 return ret;
463 }
464
465 /*
466 * Newer IP revisions like on J7200 SoCs support h/w auto-initialization
467 * of TCMs, so there is no need to perform the s/w memzero. This bit is
468 * configurable through System Firmware, the default value does perform
469 * auto-init, but account for it in case it is disabled
470 */
471 if (cluster->soc_data->tcm_ecc_autoinit && !mem_init_dis) {
472 dev_dbg(dev, "leveraging h/w init for TCM memories\n");
473 return 0;
474 }
475
476 /*
477 * Zero out both TCMs unconditionally (access from v8 Arm core is not
478 * affected by ATCM & BTCM enable configuration values) so that ECC
479 * can be effective on all TCM addresses.
480 */
481 dev_dbg(dev, "zeroing out ATCM memory\n");
482 memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
483
484 dev_dbg(dev, "zeroing out BTCM memory\n");
485 memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
486
487 return 0;
488 }
489
490 /*
491 * This function implements the .unprepare() ops and performs the complimentary
492 * operations to that of the .prepare() ops. The function is used to assert the
493 * resets on all applicable cores for the rproc device (depending on LockStep
494 * or Split mode). This completes the second portion of powering down the R5F
495 * cores. The cores themselves are only halted in the .stop() ops, and the
496 * .unprepare() ops is invoked by the remoteproc core after the remoteproc is
497 * stopped.
498 *
499 * The Single-CPU mode on applicable SoCs (eg: AM64x) combines the TCMs from
500 * both cores. The access is made possible only with releasing the resets for
501 * both cores, but with only Core0 unhalted. This function re-uses the same
502 * reset assert logic as LockStep mode for this mode (though the behavior is
503 * agnostic of the reset assert order). This callback is invoked only in
504 * remoteproc mode.
505 */
k3_r5_rproc_unprepare(struct rproc * rproc)506 static int k3_r5_rproc_unprepare(struct rproc *rproc)
507 {
508 struct k3_r5_rproc *kproc = rproc->priv;
509 struct k3_r5_cluster *cluster = kproc->cluster;
510 struct k3_r5_core *core = kproc->core;
511 struct device *dev = kproc->dev;
512 int ret;
513
514 /* Re-use LockStep-mode reset logic for Single-CPU mode */
515 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
516 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
517 k3_r5_lockstep_reset(cluster) : k3_r5_split_reset(core);
518 if (ret)
519 dev_err(dev, "unable to disable cores, ret = %d\n", ret);
520
521 return ret;
522 }
523
524 /*
525 * The R5F start sequence includes two different operations
526 * 1. Configure the boot vector for R5F core(s)
527 * 2. Unhalt/Run the R5F core(s)
528 *
529 * The sequence is different between LockStep and Split modes. The LockStep
530 * mode requires the boot vector to be configured only for Core0, and then
531 * unhalt both the cores to start the execution - Core1 needs to be unhalted
532 * first followed by Core0. The Split-mode requires that Core0 to be maintained
533 * always in a higher power state that Core1 (implying Core1 needs to be started
534 * always only after Core0 is started).
535 *
536 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
537 * code, so only Core0 needs to be unhalted. The function uses the same logic
538 * flow as Split-mode for this. This callback is invoked only in remoteproc
539 * mode.
540 */
k3_r5_rproc_start(struct rproc * rproc)541 static int k3_r5_rproc_start(struct rproc *rproc)
542 {
543 struct k3_r5_rproc *kproc = rproc->priv;
544 struct k3_r5_cluster *cluster = kproc->cluster;
545 struct device *dev = kproc->dev;
546 struct k3_r5_core *core0, *core;
547 u32 boot_addr;
548 int ret;
549
550 boot_addr = rproc->bootaddr;
551 /* TODO: add boot_addr sanity checking */
552 dev_dbg(dev, "booting R5F core using boot addr = 0x%x\n", boot_addr);
553
554 /* boot vector need not be programmed for Core1 in LockStep mode */
555 core = kproc->core;
556 ret = ti_sci_proc_set_config(core->tsp, boot_addr, 0, 0);
557 if (ret)
558 return ret;
559
560 /* unhalt/run all applicable cores */
561 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
562 list_for_each_entry_reverse(core, &cluster->cores, elem) {
563 ret = k3_r5_core_run(core);
564 if (ret)
565 goto unroll_core_run;
566 }
567 } else {
568 /* do not allow core 1 to start before core 0 */
569 core0 = list_first_entry(&cluster->cores, struct k3_r5_core,
570 elem);
571 if (core != core0 && core0->rproc->state == RPROC_OFFLINE) {
572 dev_err(dev, "%s: can not start core 1 before core 0\n",
573 __func__);
574 return -EPERM;
575 }
576
577 ret = k3_r5_core_run(core);
578 if (ret)
579 return ret;
580
581 core->released_from_reset = true;
582 wake_up_interruptible(&cluster->core_transition);
583 }
584
585 return 0;
586
587 unroll_core_run:
588 list_for_each_entry_continue(core, &cluster->cores, elem) {
589 if (k3_r5_core_halt(core))
590 dev_warn(core->dev, "core halt back failed\n");
591 }
592 return ret;
593 }
594
595 /*
596 * The R5F stop function includes the following operations
597 * 1. Halt R5F core(s)
598 *
599 * The sequence is different between LockStep and Split modes, and the order
600 * of cores the operations are performed are also in general reverse to that
601 * of the start function. The LockStep mode requires each operation to be
602 * performed first on Core0 followed by Core1. The Split-mode requires that
603 * Core0 to be maintained always in a higher power state that Core1 (implying
604 * Core1 needs to be stopped first before Core0).
605 *
606 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
607 * code, so only Core0 needs to be halted. The function uses the same logic
608 * flow as Split-mode for this.
609 *
610 * Note that the R5F halt operation in general is not effective when the R5F
611 * core is running, but is needed to make sure the core won't run after
612 * deasserting the reset the subsequent time. The asserting of reset can
613 * be done here, but is preferred to be done in the .unprepare() ops - this
614 * maintains the symmetric behavior between the .start(), .stop(), .prepare()
615 * and .unprepare() ops, and also balances them well between sysfs 'state'
616 * flow and device bind/unbind or module removal. This callback is invoked
617 * only in remoteproc mode.
618 */
k3_r5_rproc_stop(struct rproc * rproc)619 static int k3_r5_rproc_stop(struct rproc *rproc)
620 {
621 struct k3_r5_rproc *kproc = rproc->priv;
622 struct k3_r5_cluster *cluster = kproc->cluster;
623 struct device *dev = kproc->dev;
624 struct k3_r5_core *core1, *core = kproc->core;
625 int ret;
626
627 /* halt all applicable cores */
628 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
629 list_for_each_entry(core, &cluster->cores, elem) {
630 ret = k3_r5_core_halt(core);
631 if (ret) {
632 core = list_prev_entry(core, elem);
633 goto unroll_core_halt;
634 }
635 }
636 } else {
637 /* do not allow core 0 to stop before core 1 */
638 core1 = list_last_entry(&cluster->cores, struct k3_r5_core,
639 elem);
640 if (core != core1 && core1->rproc->state != RPROC_OFFLINE) {
641 dev_err(dev, "%s: can not stop core 0 before core 1\n",
642 __func__);
643 ret = -EPERM;
644 goto out;
645 }
646
647 ret = k3_r5_core_halt(core);
648 if (ret)
649 goto out;
650 }
651
652 return 0;
653
654 unroll_core_halt:
655 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
656 if (k3_r5_core_run(core))
657 dev_warn(core->dev, "core run back failed\n");
658 }
659 out:
660 return ret;
661 }
662
663 /*
664 * Attach to a running R5F remote processor (IPC-only mode)
665 *
666 * The R5F attach callback is a NOP. The remote processor is already booted, and
667 * all required resources have been acquired during probe routine, so there is
668 * no need to issue any TI-SCI commands to boot the R5F cores in IPC-only mode.
669 * This callback is invoked only in IPC-only mode and exists because
670 * rproc_validate() checks for its existence.
671 */
k3_r5_rproc_attach(struct rproc * rproc)672 static int k3_r5_rproc_attach(struct rproc *rproc) { return 0; }
673
674 /*
675 * Detach from a running R5F remote processor (IPC-only mode)
676 *
677 * The R5F detach callback is a NOP. The R5F cores are not stopped and will be
678 * left in booted state in IPC-only mode. This callback is invoked only in
679 * IPC-only mode and exists for sanity sake.
680 */
k3_r5_rproc_detach(struct rproc * rproc)681 static int k3_r5_rproc_detach(struct rproc *rproc) { return 0; }
682
683 /*
684 * This function implements the .get_loaded_rsc_table() callback and is used
685 * to provide the resource table for the booted R5F in IPC-only mode. The K3 R5F
686 * firmwares follow a design-by-contract approach and are expected to have the
687 * resource table at the base of the DDR region reserved for firmware usage.
688 * This provides flexibility for the remote processor to be booted by different
689 * bootloaders that may or may not have the ability to publish the resource table
690 * address and size through a DT property. This callback is invoked only in
691 * IPC-only mode.
692 */
k3_r5_get_loaded_rsc_table(struct rproc * rproc,size_t * rsc_table_sz)693 static struct resource_table *k3_r5_get_loaded_rsc_table(struct rproc *rproc,
694 size_t *rsc_table_sz)
695 {
696 struct k3_r5_rproc *kproc = rproc->priv;
697 struct device *dev = kproc->dev;
698
699 if (!kproc->rmem[0].cpu_addr) {
700 dev_err(dev, "memory-region #1 does not exist, loaded rsc table can't be found");
701 return ERR_PTR(-ENOMEM);
702 }
703
704 /*
705 * NOTE: The resource table size is currently hard-coded to a maximum
706 * of 256 bytes. The most common resource table usage for K3 firmwares
707 * is to only have the vdev resource entry and an optional trace entry.
708 * The exact size could be computed based on resource table address, but
709 * the hard-coded value suffices to support the IPC-only mode.
710 */
711 *rsc_table_sz = 256;
712 return (struct resource_table *)kproc->rmem[0].cpu_addr;
713 }
714
715 /*
716 * Internal Memory translation helper
717 *
718 * Custom function implementing the rproc .da_to_va ops to provide address
719 * translation (device address to kernel virtual address) for internal RAMs
720 * present in a DSP or IPU device). The translated addresses can be used
721 * either by the remoteproc core for loading, or by any rpmsg bus drivers.
722 */
k3_r5_rproc_da_to_va(struct rproc * rproc,u64 da,size_t len,bool * is_iomem)723 static void *k3_r5_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
724 {
725 struct k3_r5_rproc *kproc = rproc->priv;
726 struct k3_r5_core *core = kproc->core;
727 void __iomem *va = NULL;
728 phys_addr_t bus_addr;
729 u32 dev_addr, offset;
730 size_t size;
731 int i;
732
733 if (len == 0)
734 return NULL;
735
736 /* handle both R5 and SoC views of ATCM and BTCM */
737 for (i = 0; i < core->num_mems; i++) {
738 bus_addr = core->mem[i].bus_addr;
739 dev_addr = core->mem[i].dev_addr;
740 size = core->mem[i].size;
741
742 /* handle R5-view addresses of TCMs */
743 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
744 offset = da - dev_addr;
745 va = core->mem[i].cpu_addr + offset;
746 return (__force void *)va;
747 }
748
749 /* handle SoC-view addresses of TCMs */
750 if (da >= bus_addr && ((da + len) <= (bus_addr + size))) {
751 offset = da - bus_addr;
752 va = core->mem[i].cpu_addr + offset;
753 return (__force void *)va;
754 }
755 }
756
757 /* handle any SRAM regions using SoC-view addresses */
758 for (i = 0; i < core->num_sram; i++) {
759 dev_addr = core->sram[i].dev_addr;
760 size = core->sram[i].size;
761
762 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
763 offset = da - dev_addr;
764 va = core->sram[i].cpu_addr + offset;
765 return (__force void *)va;
766 }
767 }
768
769 /* handle static DDR reserved memory regions */
770 for (i = 0; i < kproc->num_rmems; i++) {
771 dev_addr = kproc->rmem[i].dev_addr;
772 size = kproc->rmem[i].size;
773
774 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
775 offset = da - dev_addr;
776 va = kproc->rmem[i].cpu_addr + offset;
777 return (__force void *)va;
778 }
779 }
780
781 return NULL;
782 }
783
784 static const struct rproc_ops k3_r5_rproc_ops = {
785 .prepare = k3_r5_rproc_prepare,
786 .unprepare = k3_r5_rproc_unprepare,
787 .start = k3_r5_rproc_start,
788 .stop = k3_r5_rproc_stop,
789 .kick = k3_r5_rproc_kick,
790 .da_to_va = k3_r5_rproc_da_to_va,
791 };
792
793 /*
794 * Internal R5F Core configuration
795 *
796 * Each R5FSS has a cluster-level setting for configuring the processor
797 * subsystem either in a safety/fault-tolerant LockStep mode or a performance
798 * oriented Split mode on most SoCs. A fewer SoCs support a non-safety mode
799 * as an alternate for LockStep mode that exercises only a single R5F core
800 * called Single-CPU mode. Each R5F core has a number of settings to either
801 * enable/disable each of the TCMs, control which TCM appears at the R5F core's
802 * address 0x0. These settings need to be configured before the resets for the
803 * corresponding core are released. These settings are all protected and managed
804 * by the System Processor.
805 *
806 * This function is used to pre-configure these settings for each R5F core, and
807 * the configuration is all done through various ti_sci_proc functions that
808 * communicate with the System Processor. The function also ensures that both
809 * the cores are halted before the .prepare() step.
810 *
811 * The function is called from k3_r5_cluster_rproc_init() and is invoked either
812 * once (in LockStep mode or Single-CPU modes) or twice (in Split mode). Support
813 * for LockStep-mode is dictated by an eFUSE register bit, and the config
814 * settings retrieved from DT are adjusted accordingly as per the permitted
815 * cluster mode. Another eFUSE register bit dictates if the R5F cluster only
816 * supports a Single-CPU mode. All cluster level settings like Cluster mode and
817 * TEINIT (exception handling state dictating ARM or Thumb mode) can only be set
818 * and retrieved using Core0.
819 *
820 * The function behavior is different based on the cluster mode. The R5F cores
821 * are configured independently as per their individual settings in Split mode.
822 * They are identically configured in LockStep mode using the primary Core0
823 * settings. However, some individual settings cannot be set in LockStep mode.
824 * This is overcome by switching to Split-mode initially and then programming
825 * both the cores with the same settings, before reconfiguing again for
826 * LockStep mode.
827 */
k3_r5_rproc_configure(struct k3_r5_rproc * kproc)828 static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc)
829 {
830 struct k3_r5_cluster *cluster = kproc->cluster;
831 struct device *dev = kproc->dev;
832 struct k3_r5_core *core0, *core, *temp;
833 u32 ctrl = 0, cfg = 0, stat = 0;
834 u32 set_cfg = 0, clr_cfg = 0;
835 u64 boot_vec = 0;
836 bool lockstep_en;
837 bool single_cpu;
838 int ret;
839
840 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
841 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
842 cluster->mode == CLUSTER_MODE_SINGLECPU ||
843 cluster->mode == CLUSTER_MODE_SINGLECORE) {
844 core = core0;
845 } else {
846 core = kproc->core;
847 }
848
849 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,
850 &stat);
851 if (ret < 0)
852 return ret;
853
854 dev_dbg(dev, "boot_vector = 0x%llx, cfg = 0x%x ctrl = 0x%x stat = 0x%x\n",
855 boot_vec, cfg, ctrl, stat);
856
857 single_cpu = !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY);
858 lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED);
859
860 /* Override to single CPU mode if set in status flag */
861 if (single_cpu && cluster->mode == CLUSTER_MODE_SPLIT) {
862 dev_err(cluster->dev, "split-mode not permitted, force configuring for single-cpu mode\n");
863 cluster->mode = CLUSTER_MODE_SINGLECPU;
864 }
865
866 /* Override to split mode if lockstep enable bit is not set in status flag */
867 if (!lockstep_en && cluster->mode == CLUSTER_MODE_LOCKSTEP) {
868 dev_err(cluster->dev, "lockstep mode not permitted, force configuring for split-mode\n");
869 cluster->mode = CLUSTER_MODE_SPLIT;
870 }
871
872 /* always enable ARM mode and set boot vector to 0 */
873 boot_vec = 0x0;
874 if (core == core0) {
875 clr_cfg = PROC_BOOT_CFG_FLAG_R5_TEINIT;
876 /*
877 * Single-CPU configuration bit can only be configured
878 * on Core0 and system firmware will NACK any requests
879 * with the bit configured, so program it only on
880 * permitted cores
881 */
882 if (cluster->mode == CLUSTER_MODE_SINGLECPU ||
883 cluster->mode == CLUSTER_MODE_SINGLECORE) {
884 set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE;
885 } else {
886 /*
887 * LockStep configuration bit is Read-only on Split-mode
888 * _only_ devices and system firmware will NACK any
889 * requests with the bit configured, so program it only
890 * on permitted devices
891 */
892 if (lockstep_en)
893 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
894 }
895 }
896
897 if (core->atcm_enable)
898 set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
899 else
900 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
901
902 if (core->btcm_enable)
903 set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
904 else
905 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
906
907 if (core->loczrama)
908 set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
909 else
910 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
911
912 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
913 /*
914 * work around system firmware limitations to make sure both
915 * cores are programmed symmetrically in LockStep. LockStep
916 * and TEINIT config is only allowed with Core0.
917 */
918 list_for_each_entry(temp, &cluster->cores, elem) {
919 ret = k3_r5_core_halt(temp);
920 if (ret)
921 goto out;
922
923 if (temp != core) {
924 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
925 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_TEINIT;
926 }
927 ret = ti_sci_proc_set_config(temp->tsp, boot_vec,
928 set_cfg, clr_cfg);
929 if (ret)
930 goto out;
931 }
932
933 set_cfg = PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
934 clr_cfg = 0;
935 ret = ti_sci_proc_set_config(core->tsp, boot_vec,
936 set_cfg, clr_cfg);
937 } else {
938 ret = k3_r5_core_halt(core);
939 if (ret)
940 goto out;
941
942 ret = ti_sci_proc_set_config(core->tsp, boot_vec,
943 set_cfg, clr_cfg);
944 }
945
946 out:
947 return ret;
948 }
949
k3_r5_reserved_mem_init(struct k3_r5_rproc * kproc)950 static int k3_r5_reserved_mem_init(struct k3_r5_rproc *kproc)
951 {
952 struct device *dev = kproc->dev;
953 struct device_node *np = dev_of_node(dev);
954 struct device_node *rmem_np;
955 struct reserved_mem *rmem;
956 int num_rmems;
957 int ret, i;
958
959 num_rmems = of_property_count_elems_of_size(np, "memory-region",
960 sizeof(phandle));
961 if (num_rmems <= 0) {
962 dev_err(dev, "device does not have reserved memory regions, ret = %d\n",
963 num_rmems);
964 return -EINVAL;
965 }
966 if (num_rmems < 2) {
967 dev_err(dev, "device needs at least two memory regions to be defined, num = %d\n",
968 num_rmems);
969 return -EINVAL;
970 }
971
972 /* use reserved memory region 0 for vring DMA allocations */
973 ret = of_reserved_mem_device_init_by_idx(dev, np, 0);
974 if (ret) {
975 dev_err(dev, "device cannot initialize DMA pool, ret = %d\n",
976 ret);
977 return ret;
978 }
979
980 num_rmems--;
981 kproc->rmem = kcalloc(num_rmems, sizeof(*kproc->rmem), GFP_KERNEL);
982 if (!kproc->rmem) {
983 ret = -ENOMEM;
984 goto release_rmem;
985 }
986
987 /* use remaining reserved memory regions for static carveouts */
988 for (i = 0; i < num_rmems; i++) {
989 rmem_np = of_parse_phandle(np, "memory-region", i + 1);
990 if (!rmem_np) {
991 ret = -EINVAL;
992 goto unmap_rmem;
993 }
994
995 rmem = of_reserved_mem_lookup(rmem_np);
996 if (!rmem) {
997 of_node_put(rmem_np);
998 ret = -EINVAL;
999 goto unmap_rmem;
1000 }
1001 of_node_put(rmem_np);
1002
1003 kproc->rmem[i].bus_addr = rmem->base;
1004 /*
1005 * R5Fs do not have an MMU, but have a Region Address Translator
1006 * (RAT) module that provides a fixed entry translation between
1007 * the 32-bit processor addresses to 64-bit bus addresses. The
1008 * RAT is programmable only by the R5F cores. Support for RAT
1009 * is currently not supported, so 64-bit address regions are not
1010 * supported. The absence of MMUs implies that the R5F device
1011 * addresses/supported memory regions are restricted to 32-bit
1012 * bus addresses, and are identical
1013 */
1014 kproc->rmem[i].dev_addr = (u32)rmem->base;
1015 kproc->rmem[i].size = rmem->size;
1016 kproc->rmem[i].cpu_addr = ioremap_wc(rmem->base, rmem->size);
1017 if (!kproc->rmem[i].cpu_addr) {
1018 dev_err(dev, "failed to map reserved memory#%d at %pa of size %pa\n",
1019 i + 1, &rmem->base, &rmem->size);
1020 ret = -ENOMEM;
1021 goto unmap_rmem;
1022 }
1023
1024 dev_dbg(dev, "reserved memory%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1025 i + 1, &kproc->rmem[i].bus_addr,
1026 kproc->rmem[i].size, kproc->rmem[i].cpu_addr,
1027 kproc->rmem[i].dev_addr);
1028 }
1029 kproc->num_rmems = num_rmems;
1030
1031 return 0;
1032
1033 unmap_rmem:
1034 for (i--; i >= 0; i--)
1035 iounmap(kproc->rmem[i].cpu_addr);
1036 kfree(kproc->rmem);
1037 release_rmem:
1038 of_reserved_mem_device_release(dev);
1039 return ret;
1040 }
1041
k3_r5_reserved_mem_exit(struct k3_r5_rproc * kproc)1042 static void k3_r5_reserved_mem_exit(struct k3_r5_rproc *kproc)
1043 {
1044 int i;
1045
1046 for (i = 0; i < kproc->num_rmems; i++)
1047 iounmap(kproc->rmem[i].cpu_addr);
1048 kfree(kproc->rmem);
1049
1050 of_reserved_mem_device_release(kproc->dev);
1051 }
1052
1053 /*
1054 * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
1055 * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
1056 * cores are usable in Split-mode, but only the Core0 TCMs can be used in
1057 * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
1058 * leveraging the Core1 TCMs as well in certain modes where they would have
1059 * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs, Single-CPU mode on
1060 * AM64x SoCs). This is done by making a Core1 TCM visible immediately after the
1061 * corresponding Core0 TCM. The SoC memory map uses the larger 64 KB sizes for
1062 * the Core0 TCMs, and the dts representation reflects this increased size on
1063 * supported SoCs. The Core0 TCM sizes therefore have to be adjusted to only
1064 * half the original size in Split mode.
1065 */
k3_r5_adjust_tcm_sizes(struct k3_r5_rproc * kproc)1066 static void k3_r5_adjust_tcm_sizes(struct k3_r5_rproc *kproc)
1067 {
1068 struct k3_r5_cluster *cluster = kproc->cluster;
1069 struct k3_r5_core *core = kproc->core;
1070 struct device *cdev = core->dev;
1071 struct k3_r5_core *core0;
1072
1073 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1074 cluster->mode == CLUSTER_MODE_SINGLECPU ||
1075 cluster->mode == CLUSTER_MODE_SINGLECORE ||
1076 !cluster->soc_data->tcm_is_double)
1077 return;
1078
1079 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
1080 if (core == core0) {
1081 WARN_ON(core->mem[0].size != SZ_64K);
1082 WARN_ON(core->mem[1].size != SZ_64K);
1083
1084 core->mem[0].size /= 2;
1085 core->mem[1].size /= 2;
1086
1087 dev_dbg(cdev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
1088 core->mem[0].size, core->mem[1].size);
1089 }
1090 }
1091
1092 /*
1093 * This function checks and configures a R5F core for IPC-only or remoteproc
1094 * mode. The driver is configured to be in IPC-only mode for a R5F core when
1095 * the core has been loaded and started by a bootloader. The IPC-only mode is
1096 * detected by querying the System Firmware for reset, power on and halt status
1097 * and ensuring that the core is running. Any incomplete steps at bootloader
1098 * are validated and errored out.
1099 *
1100 * In IPC-only mode, the driver state flags for ATCM, BTCM and LOCZRAMA settings
1101 * and cluster mode parsed originally from kernel DT are updated to reflect the
1102 * actual values configured by bootloader. The driver internal device memory
1103 * addresses for TCMs are also updated.
1104 */
k3_r5_rproc_configure_mode(struct k3_r5_rproc * kproc)1105 static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc)
1106 {
1107 struct k3_r5_cluster *cluster = kproc->cluster;
1108 struct k3_r5_core *core = kproc->core;
1109 struct device *cdev = core->dev;
1110 bool r_state = false, c_state = false, lockstep_en = false, single_cpu = false;
1111 u32 ctrl = 0, cfg = 0, stat = 0, halted = 0;
1112 u64 boot_vec = 0;
1113 u32 atcm_enable, btcm_enable, loczrama;
1114 struct k3_r5_core *core0;
1115 enum cluster_mode mode = cluster->mode;
1116 int ret;
1117
1118 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
1119
1120 ret = core->ti_sci->ops.dev_ops.is_on(core->ti_sci, core->ti_sci_id,
1121 &r_state, &c_state);
1122 if (ret) {
1123 dev_err(cdev, "failed to get initial state, mode cannot be determined, ret = %d\n",
1124 ret);
1125 return ret;
1126 }
1127 if (r_state != c_state) {
1128 dev_warn(cdev, "R5F core may have been powered on by a different host, programmed state (%d) != actual state (%d)\n",
1129 r_state, c_state);
1130 }
1131
1132 ret = reset_control_status(core->reset);
1133 if (ret < 0) {
1134 dev_err(cdev, "failed to get initial local reset status, ret = %d\n",
1135 ret);
1136 return ret;
1137 }
1138
1139 /*
1140 * Skip the waiting mechanism for sequential power-on of cores if the
1141 * core has already been booted by another entity.
1142 */
1143 core->released_from_reset = c_state;
1144
1145 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,
1146 &stat);
1147 if (ret < 0) {
1148 dev_err(cdev, "failed to get initial processor status, ret = %d\n",
1149 ret);
1150 return ret;
1151 }
1152 atcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_ATCM_EN ? 1 : 0;
1153 btcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_BTCM_EN ? 1 : 0;
1154 loczrama = cfg & PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE ? 1 : 0;
1155 single_cpu = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? 1 : 0;
1156 lockstep_en = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? 1 : 0;
1157
1158 if (single_cpu && mode != CLUSTER_MODE_SINGLECORE)
1159 mode = CLUSTER_MODE_SINGLECPU;
1160 if (lockstep_en)
1161 mode = CLUSTER_MODE_LOCKSTEP;
1162
1163 halted = ctrl & PROC_BOOT_CTRL_FLAG_R5_CORE_HALT;
1164
1165 /*
1166 * IPC-only mode detection requires both local and module resets to
1167 * be deasserted and R5F core to be unhalted. Local reset status is
1168 * irrelevant if module reset is asserted (POR value has local reset
1169 * deasserted), and is deemed as remoteproc mode
1170 */
1171 if (c_state && !ret && !halted) {
1172 dev_info(cdev, "configured R5F for IPC-only mode\n");
1173 kproc->rproc->state = RPROC_DETACHED;
1174 ret = 1;
1175 /* override rproc ops with only required IPC-only mode ops */
1176 kproc->rproc->ops->prepare = NULL;
1177 kproc->rproc->ops->unprepare = NULL;
1178 kproc->rproc->ops->start = NULL;
1179 kproc->rproc->ops->stop = NULL;
1180 kproc->rproc->ops->attach = k3_r5_rproc_attach;
1181 kproc->rproc->ops->detach = k3_r5_rproc_detach;
1182 kproc->rproc->ops->get_loaded_rsc_table =
1183 k3_r5_get_loaded_rsc_table;
1184 } else if (!c_state) {
1185 dev_info(cdev, "configured R5F for remoteproc mode\n");
1186 ret = 0;
1187 } else {
1188 dev_err(cdev, "mismatched mode: local_reset = %s, module_reset = %s, core_state = %s\n",
1189 !ret ? "deasserted" : "asserted",
1190 c_state ? "deasserted" : "asserted",
1191 halted ? "halted" : "unhalted");
1192 ret = -EINVAL;
1193 }
1194
1195 /* fixup TCMs, cluster & core flags to actual values in IPC-only mode */
1196 if (ret > 0) {
1197 if (core == core0)
1198 cluster->mode = mode;
1199 core->atcm_enable = atcm_enable;
1200 core->btcm_enable = btcm_enable;
1201 core->loczrama = loczrama;
1202 core->mem[0].dev_addr = loczrama ? 0 : K3_R5_TCM_DEV_ADDR;
1203 core->mem[1].dev_addr = loczrama ? K3_R5_TCM_DEV_ADDR : 0;
1204 }
1205
1206 return ret;
1207 }
1208
k3_r5_cluster_rproc_init(struct platform_device * pdev)1209 static int k3_r5_cluster_rproc_init(struct platform_device *pdev)
1210 {
1211 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1212 struct device *dev = &pdev->dev;
1213 struct k3_r5_rproc *kproc;
1214 struct k3_r5_core *core, *core1;
1215 struct device *cdev;
1216 const char *fw_name;
1217 struct rproc *rproc;
1218 int ret, ret1;
1219
1220 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1221 list_for_each_entry(core, &cluster->cores, elem) {
1222 cdev = core->dev;
1223 ret = rproc_of_parse_firmware(cdev, 0, &fw_name);
1224 if (ret) {
1225 dev_err(dev, "failed to parse firmware-name property, ret = %d\n",
1226 ret);
1227 goto out;
1228 }
1229
1230 rproc = rproc_alloc(cdev, dev_name(cdev), &k3_r5_rproc_ops,
1231 fw_name, sizeof(*kproc));
1232 if (!rproc) {
1233 ret = -ENOMEM;
1234 goto out;
1235 }
1236
1237 /* K3 R5s have a Region Address Translator (RAT) but no MMU */
1238 rproc->has_iommu = false;
1239 /* error recovery is not supported at present */
1240 rproc->recovery_disabled = true;
1241
1242 kproc = rproc->priv;
1243 kproc->cluster = cluster;
1244 kproc->core = core;
1245 kproc->dev = cdev;
1246 kproc->rproc = rproc;
1247 core->rproc = rproc;
1248
1249 ret = k3_r5_rproc_request_mbox(rproc);
1250 if (ret)
1251 return ret;
1252
1253 ret = k3_r5_rproc_configure_mode(kproc);
1254 if (ret < 0)
1255 goto err_config;
1256 if (ret)
1257 goto init_rmem;
1258
1259 ret = k3_r5_rproc_configure(kproc);
1260 if (ret) {
1261 dev_err(dev, "initial configure failed, ret = %d\n",
1262 ret);
1263 goto err_config;
1264 }
1265
1266 init_rmem:
1267 k3_r5_adjust_tcm_sizes(kproc);
1268
1269 ret = k3_r5_reserved_mem_init(kproc);
1270 if (ret) {
1271 dev_err(dev, "reserved memory init failed, ret = %d\n",
1272 ret);
1273 goto err_config;
1274 }
1275
1276 ret = rproc_add(rproc);
1277 if (ret) {
1278 dev_err(dev, "rproc_add failed, ret = %d\n", ret);
1279 goto err_add;
1280 }
1281
1282 /* create only one rproc in lockstep, single-cpu or
1283 * single core mode
1284 */
1285 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1286 cluster->mode == CLUSTER_MODE_SINGLECPU ||
1287 cluster->mode == CLUSTER_MODE_SINGLECORE)
1288 break;
1289
1290 /*
1291 * R5 cores require to be powered on sequentially, core0
1292 * should be in higher power state than core1 in a cluster
1293 * So, wait for current core to power up before proceeding
1294 * to next core and put timeout of 2sec for each core.
1295 *
1296 * This waiting mechanism is necessary because
1297 * rproc_auto_boot_callback() for core1 can be called before
1298 * core0 due to thread execution order.
1299 */
1300 ret = wait_event_interruptible_timeout(cluster->core_transition,
1301 core->released_from_reset,
1302 msecs_to_jiffies(2000));
1303 if (ret <= 0) {
1304 dev_err(dev,
1305 "Timed out waiting for %s core to power up!\n",
1306 rproc->name);
1307 goto err_powerup;
1308 }
1309 }
1310
1311 return 0;
1312
1313 err_split:
1314 if (rproc->state == RPROC_ATTACHED) {
1315 ret1 = rproc_detach(rproc);
1316 if (ret1) {
1317 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n",
1318 ret1);
1319 return ret1;
1320 }
1321 }
1322
1323 err_powerup:
1324 rproc_del(rproc);
1325 err_add:
1326 k3_r5_reserved_mem_exit(kproc);
1327 err_config:
1328 rproc_free(rproc);
1329 core->rproc = NULL;
1330 out:
1331 /* undo core0 upon any failures on core1 in split-mode */
1332 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1) {
1333 core = list_prev_entry(core, elem);
1334 rproc = core->rproc;
1335 kproc = rproc->priv;
1336 goto err_split;
1337 }
1338 return ret;
1339 }
1340
k3_r5_cluster_rproc_exit(void * data)1341 static void k3_r5_cluster_rproc_exit(void *data)
1342 {
1343 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1344 struct k3_r5_rproc *kproc;
1345 struct k3_r5_core *core;
1346 struct rproc *rproc;
1347 int ret;
1348
1349 /*
1350 * lockstep mode and single-cpu modes have only one rproc associated
1351 * with first core, whereas split-mode has two rprocs associated with
1352 * each core, and requires that core1 be powered down first
1353 */
1354 core = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1355 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
1356 list_first_entry(&cluster->cores, struct k3_r5_core, elem) :
1357 list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1358
1359 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
1360 rproc = core->rproc;
1361 kproc = rproc->priv;
1362
1363 if (rproc->state == RPROC_ATTACHED) {
1364 ret = rproc_detach(rproc);
1365 if (ret) {
1366 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n", ret);
1367 return;
1368 }
1369 }
1370
1371 mbox_free_channel(kproc->mbox);
1372
1373 rproc_del(rproc);
1374
1375 k3_r5_reserved_mem_exit(kproc);
1376
1377 rproc_free(rproc);
1378 core->rproc = NULL;
1379 }
1380 }
1381
k3_r5_core_of_get_internal_memories(struct platform_device * pdev,struct k3_r5_core * core)1382 static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,
1383 struct k3_r5_core *core)
1384 {
1385 static const char * const mem_names[] = {"atcm", "btcm"};
1386 struct device *dev = &pdev->dev;
1387 struct resource *res;
1388 int num_mems;
1389 int i;
1390
1391 num_mems = ARRAY_SIZE(mem_names);
1392 core->mem = devm_kcalloc(dev, num_mems, sizeof(*core->mem), GFP_KERNEL);
1393 if (!core->mem)
1394 return -ENOMEM;
1395
1396 for (i = 0; i < num_mems; i++) {
1397 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1398 mem_names[i]);
1399 if (!res) {
1400 dev_err(dev, "found no memory resource for %s\n",
1401 mem_names[i]);
1402 return -EINVAL;
1403 }
1404 if (!devm_request_mem_region(dev, res->start,
1405 resource_size(res),
1406 dev_name(dev))) {
1407 dev_err(dev, "could not request %s region for resource\n",
1408 mem_names[i]);
1409 return -EBUSY;
1410 }
1411
1412 /*
1413 * TCMs are designed in general to support RAM-like backing
1414 * memories. So, map these as Normal Non-Cached memories. This
1415 * also avoids/fixes any potential alignment faults due to
1416 * unaligned data accesses when using memcpy() or memset()
1417 * functions (normally seen with device type memory).
1418 */
1419 core->mem[i].cpu_addr = devm_ioremap_wc(dev, res->start,
1420 resource_size(res));
1421 if (!core->mem[i].cpu_addr) {
1422 dev_err(dev, "failed to map %s memory\n", mem_names[i]);
1423 return -ENOMEM;
1424 }
1425 core->mem[i].bus_addr = res->start;
1426
1427 /*
1428 * TODO:
1429 * The R5F cores can place ATCM & BTCM anywhere in its address
1430 * based on the corresponding Region Registers in the System
1431 * Control coprocessor. For now, place ATCM and BTCM at
1432 * addresses 0 and 0x41010000 (same as the bus address on AM65x
1433 * SoCs) based on loczrama setting
1434 */
1435 if (!strcmp(mem_names[i], "atcm")) {
1436 core->mem[i].dev_addr = core->loczrama ?
1437 0 : K3_R5_TCM_DEV_ADDR;
1438 } else {
1439 core->mem[i].dev_addr = core->loczrama ?
1440 K3_R5_TCM_DEV_ADDR : 0;
1441 }
1442 core->mem[i].size = resource_size(res);
1443
1444 dev_dbg(dev, "memory %5s: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1445 mem_names[i], &core->mem[i].bus_addr,
1446 core->mem[i].size, core->mem[i].cpu_addr,
1447 core->mem[i].dev_addr);
1448 }
1449 core->num_mems = num_mems;
1450
1451 return 0;
1452 }
1453
k3_r5_core_of_get_sram_memories(struct platform_device * pdev,struct k3_r5_core * core)1454 static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev,
1455 struct k3_r5_core *core)
1456 {
1457 struct device_node *np = pdev->dev.of_node;
1458 struct device *dev = &pdev->dev;
1459 struct device_node *sram_np;
1460 struct resource res;
1461 int num_sram;
1462 int i, ret;
1463
1464 num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));
1465 if (num_sram <= 0) {
1466 dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n",
1467 num_sram);
1468 return 0;
1469 }
1470
1471 core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL);
1472 if (!core->sram)
1473 return -ENOMEM;
1474
1475 for (i = 0; i < num_sram; i++) {
1476 sram_np = of_parse_phandle(np, "sram", i);
1477 if (!sram_np)
1478 return -EINVAL;
1479
1480 if (!of_device_is_available(sram_np)) {
1481 of_node_put(sram_np);
1482 return -EINVAL;
1483 }
1484
1485 ret = of_address_to_resource(sram_np, 0, &res);
1486 of_node_put(sram_np);
1487 if (ret)
1488 return -EINVAL;
1489
1490 core->sram[i].bus_addr = res.start;
1491 core->sram[i].dev_addr = res.start;
1492 core->sram[i].size = resource_size(&res);
1493 core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start,
1494 resource_size(&res));
1495 if (!core->sram[i].cpu_addr) {
1496 dev_err(dev, "failed to parse and map sram%d memory at %pad\n",
1497 i, &res.start);
1498 return -ENOMEM;
1499 }
1500
1501 dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1502 i, &core->sram[i].bus_addr,
1503 core->sram[i].size, core->sram[i].cpu_addr,
1504 core->sram[i].dev_addr);
1505 }
1506 core->num_sram = num_sram;
1507
1508 return 0;
1509 }
1510
1511 static
k3_r5_core_of_get_tsp(struct device * dev,const struct ti_sci_handle * sci)1512 struct ti_sci_proc *k3_r5_core_of_get_tsp(struct device *dev,
1513 const struct ti_sci_handle *sci)
1514 {
1515 struct ti_sci_proc *tsp;
1516 u32 temp[2];
1517 int ret;
1518
1519 ret = of_property_read_u32_array(dev_of_node(dev), "ti,sci-proc-ids",
1520 temp, 2);
1521 if (ret < 0)
1522 return ERR_PTR(ret);
1523
1524 tsp = devm_kzalloc(dev, sizeof(*tsp), GFP_KERNEL);
1525 if (!tsp)
1526 return ERR_PTR(-ENOMEM);
1527
1528 tsp->dev = dev;
1529 tsp->sci = sci;
1530 tsp->ops = &sci->ops.proc_ops;
1531 tsp->proc_id = temp[0];
1532 tsp->host_id = temp[1];
1533
1534 return tsp;
1535 }
1536
k3_r5_core_of_init(struct platform_device * pdev)1537 static int k3_r5_core_of_init(struct platform_device *pdev)
1538 {
1539 struct device *dev = &pdev->dev;
1540 struct device_node *np = dev_of_node(dev);
1541 struct k3_r5_core *core;
1542 int ret;
1543
1544 if (!devres_open_group(dev, k3_r5_core_of_init, GFP_KERNEL))
1545 return -ENOMEM;
1546
1547 core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
1548 if (!core) {
1549 ret = -ENOMEM;
1550 goto err;
1551 }
1552
1553 core->dev = dev;
1554 /*
1555 * Use SoC Power-on-Reset values as default if no DT properties are
1556 * used to dictate the TCM configurations
1557 */
1558 core->atcm_enable = 0;
1559 core->btcm_enable = 1;
1560 core->loczrama = 1;
1561
1562 ret = of_property_read_u32(np, "ti,atcm-enable", &core->atcm_enable);
1563 if (ret < 0 && ret != -EINVAL) {
1564 dev_err(dev, "invalid format for ti,atcm-enable, ret = %d\n",
1565 ret);
1566 goto err;
1567 }
1568
1569 ret = of_property_read_u32(np, "ti,btcm-enable", &core->btcm_enable);
1570 if (ret < 0 && ret != -EINVAL) {
1571 dev_err(dev, "invalid format for ti,btcm-enable, ret = %d\n",
1572 ret);
1573 goto err;
1574 }
1575
1576 ret = of_property_read_u32(np, "ti,loczrama", &core->loczrama);
1577 if (ret < 0 && ret != -EINVAL) {
1578 dev_err(dev, "invalid format for ti,loczrama, ret = %d\n", ret);
1579 goto err;
1580 }
1581
1582 core->ti_sci = devm_ti_sci_get_by_phandle(dev, "ti,sci");
1583 if (IS_ERR(core->ti_sci)) {
1584 ret = PTR_ERR(core->ti_sci);
1585 if (ret != -EPROBE_DEFER) {
1586 dev_err(dev, "failed to get ti-sci handle, ret = %d\n",
1587 ret);
1588 }
1589 core->ti_sci = NULL;
1590 goto err;
1591 }
1592
1593 ret = of_property_read_u32(np, "ti,sci-dev-id", &core->ti_sci_id);
1594 if (ret) {
1595 dev_err(dev, "missing 'ti,sci-dev-id' property\n");
1596 goto err;
1597 }
1598
1599 core->reset = devm_reset_control_get_exclusive(dev, NULL);
1600 if (IS_ERR_OR_NULL(core->reset)) {
1601 ret = PTR_ERR_OR_ZERO(core->reset);
1602 if (!ret)
1603 ret = -ENODEV;
1604 if (ret != -EPROBE_DEFER) {
1605 dev_err(dev, "failed to get reset handle, ret = %d\n",
1606 ret);
1607 }
1608 goto err;
1609 }
1610
1611 core->tsp = k3_r5_core_of_get_tsp(dev, core->ti_sci);
1612 if (IS_ERR(core->tsp)) {
1613 ret = PTR_ERR(core->tsp);
1614 dev_err(dev, "failed to construct ti-sci proc control, ret = %d\n",
1615 ret);
1616 goto err;
1617 }
1618
1619 ret = k3_r5_core_of_get_internal_memories(pdev, core);
1620 if (ret) {
1621 dev_err(dev, "failed to get internal memories, ret = %d\n",
1622 ret);
1623 goto err;
1624 }
1625
1626 ret = k3_r5_core_of_get_sram_memories(pdev, core);
1627 if (ret) {
1628 dev_err(dev, "failed to get sram memories, ret = %d\n", ret);
1629 goto err;
1630 }
1631
1632 ret = ti_sci_proc_request(core->tsp);
1633 if (ret < 0) {
1634 dev_err(dev, "ti_sci_proc_request failed, ret = %d\n", ret);
1635 goto err;
1636 }
1637
1638 platform_set_drvdata(pdev, core);
1639 devres_close_group(dev, k3_r5_core_of_init);
1640
1641 return 0;
1642
1643 err:
1644 devres_release_group(dev, k3_r5_core_of_init);
1645 return ret;
1646 }
1647
1648 /*
1649 * free the resources explicitly since driver model is not being used
1650 * for the child R5F devices
1651 */
k3_r5_core_of_exit(struct platform_device * pdev)1652 static void k3_r5_core_of_exit(struct platform_device *pdev)
1653 {
1654 struct k3_r5_core *core = platform_get_drvdata(pdev);
1655 struct device *dev = &pdev->dev;
1656 int ret;
1657
1658 ret = ti_sci_proc_release(core->tsp);
1659 if (ret)
1660 dev_err(dev, "failed to release proc, ret = %d\n", ret);
1661
1662 platform_set_drvdata(pdev, NULL);
1663 devres_release_group(dev, k3_r5_core_of_init);
1664 }
1665
k3_r5_cluster_of_exit(void * data)1666 static void k3_r5_cluster_of_exit(void *data)
1667 {
1668 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1669 struct platform_device *cpdev;
1670 struct k3_r5_core *core, *temp;
1671
1672 list_for_each_entry_safe_reverse(core, temp, &cluster->cores, elem) {
1673 list_del(&core->elem);
1674 cpdev = to_platform_device(core->dev);
1675 k3_r5_core_of_exit(cpdev);
1676 }
1677 }
1678
k3_r5_cluster_of_init(struct platform_device * pdev)1679 static int k3_r5_cluster_of_init(struct platform_device *pdev)
1680 {
1681 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1682 struct device *dev = &pdev->dev;
1683 struct device_node *np = dev_of_node(dev);
1684 struct platform_device *cpdev;
1685 struct device_node *child;
1686 struct k3_r5_core *core;
1687 int ret;
1688
1689 for_each_available_child_of_node(np, child) {
1690 cpdev = of_find_device_by_node(child);
1691 if (!cpdev) {
1692 ret = -ENODEV;
1693 dev_err(dev, "could not get R5 core platform device\n");
1694 of_node_put(child);
1695 goto fail;
1696 }
1697
1698 ret = k3_r5_core_of_init(cpdev);
1699 if (ret) {
1700 dev_err(dev, "k3_r5_core_of_init failed, ret = %d\n",
1701 ret);
1702 put_device(&cpdev->dev);
1703 of_node_put(child);
1704 goto fail;
1705 }
1706
1707 core = platform_get_drvdata(cpdev);
1708 put_device(&cpdev->dev);
1709 list_add_tail(&core->elem, &cluster->cores);
1710 }
1711
1712 return 0;
1713
1714 fail:
1715 k3_r5_cluster_of_exit(pdev);
1716 return ret;
1717 }
1718
k3_r5_probe(struct platform_device * pdev)1719 static int k3_r5_probe(struct platform_device *pdev)
1720 {
1721 struct device *dev = &pdev->dev;
1722 struct device_node *np = dev_of_node(dev);
1723 struct k3_r5_cluster *cluster;
1724 const struct k3_r5_soc_data *data;
1725 int ret;
1726 int num_cores;
1727
1728 data = of_device_get_match_data(&pdev->dev);
1729 if (!data) {
1730 dev_err(dev, "SoC-specific data is not defined\n");
1731 return -ENODEV;
1732 }
1733
1734 cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);
1735 if (!cluster)
1736 return -ENOMEM;
1737
1738 cluster->dev = dev;
1739 cluster->soc_data = data;
1740 INIT_LIST_HEAD(&cluster->cores);
1741 init_waitqueue_head(&cluster->core_transition);
1742
1743 ret = of_property_read_u32(np, "ti,cluster-mode", &cluster->mode);
1744 if (ret < 0 && ret != -EINVAL) {
1745 dev_err(dev, "invalid format for ti,cluster-mode, ret = %d\n",
1746 ret);
1747 return ret;
1748 }
1749
1750 if (ret == -EINVAL) {
1751 /*
1752 * default to most common efuse configurations - Split-mode on AM64x
1753 * and LockStep-mode on all others
1754 * default to most common efuse configurations -
1755 * Split-mode on AM64x
1756 * Single core on AM62x
1757 * LockStep-mode on all others
1758 */
1759 if (!data->is_single_core)
1760 cluster->mode = data->single_cpu_mode ?
1761 CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP;
1762 else
1763 cluster->mode = CLUSTER_MODE_SINGLECORE;
1764 }
1765
1766 if ((cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) ||
1767 (cluster->mode == CLUSTER_MODE_SINGLECORE && !data->is_single_core)) {
1768 dev_err(dev, "Cluster mode = %d is not supported on this SoC\n", cluster->mode);
1769 return -EINVAL;
1770 }
1771
1772 num_cores = of_get_available_child_count(np);
1773 if (num_cores != 2 && !data->is_single_core) {
1774 dev_err(dev, "MCU cluster requires both R5F cores to be enabled but num_cores is set to = %d\n",
1775 num_cores);
1776 return -ENODEV;
1777 }
1778
1779 if (num_cores != 1 && data->is_single_core) {
1780 dev_err(dev, "SoC supports only single core R5 but num_cores is set to %d\n",
1781 num_cores);
1782 return -ENODEV;
1783 }
1784
1785 platform_set_drvdata(pdev, cluster);
1786
1787 ret = devm_of_platform_populate(dev);
1788 if (ret) {
1789 dev_err(dev, "devm_of_platform_populate failed, ret = %d\n",
1790 ret);
1791 return ret;
1792 }
1793
1794 ret = k3_r5_cluster_of_init(pdev);
1795 if (ret) {
1796 dev_err(dev, "k3_r5_cluster_of_init failed, ret = %d\n", ret);
1797 return ret;
1798 }
1799
1800 ret = devm_add_action_or_reset(dev, k3_r5_cluster_of_exit, pdev);
1801 if (ret)
1802 return ret;
1803
1804 ret = k3_r5_cluster_rproc_init(pdev);
1805 if (ret) {
1806 dev_err(dev, "k3_r5_cluster_rproc_init failed, ret = %d\n",
1807 ret);
1808 return ret;
1809 }
1810
1811 ret = devm_add_action_or_reset(dev, k3_r5_cluster_rproc_exit, pdev);
1812 if (ret)
1813 return ret;
1814
1815 return 0;
1816 }
1817
1818 static const struct k3_r5_soc_data am65_j721e_soc_data = {
1819 .tcm_is_double = false,
1820 .tcm_ecc_autoinit = false,
1821 .single_cpu_mode = false,
1822 .is_single_core = false,
1823 };
1824
1825 static const struct k3_r5_soc_data j7200_j721s2_soc_data = {
1826 .tcm_is_double = true,
1827 .tcm_ecc_autoinit = true,
1828 .single_cpu_mode = false,
1829 .is_single_core = false,
1830 };
1831
1832 static const struct k3_r5_soc_data am64_soc_data = {
1833 .tcm_is_double = true,
1834 .tcm_ecc_autoinit = true,
1835 .single_cpu_mode = true,
1836 .is_single_core = false,
1837 };
1838
1839 static const struct k3_r5_soc_data am62_soc_data = {
1840 .tcm_is_double = false,
1841 .tcm_ecc_autoinit = true,
1842 .single_cpu_mode = false,
1843 .is_single_core = true,
1844 };
1845
1846 static const struct of_device_id k3_r5_of_match[] = {
1847 { .compatible = "ti,am654-r5fss", .data = &am65_j721e_soc_data, },
1848 { .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, },
1849 { .compatible = "ti,j7200-r5fss", .data = &j7200_j721s2_soc_data, },
1850 { .compatible = "ti,am64-r5fss", .data = &am64_soc_data, },
1851 { .compatible = "ti,am62-r5fss", .data = &am62_soc_data, },
1852 { .compatible = "ti,j721s2-r5fss", .data = &j7200_j721s2_soc_data, },
1853 { /* sentinel */ },
1854 };
1855 MODULE_DEVICE_TABLE(of, k3_r5_of_match);
1856
1857 static struct platform_driver k3_r5_rproc_driver = {
1858 .probe = k3_r5_probe,
1859 .driver = {
1860 .name = "k3_r5_rproc",
1861 .of_match_table = k3_r5_of_match,
1862 },
1863 };
1864
1865 module_platform_driver(k3_r5_rproc_driver);
1866
1867 MODULE_LICENSE("GPL v2");
1868 MODULE_DESCRIPTION("TI K3 R5F remote processor driver");
1869 MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
1870