xref: /openbmc/linux/drivers/mmc/host/sdhci-msm.c (revision 360823a09426347ea8f232b0b0b5156d0aed0302)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4  *
5  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6  */
7 
8 #include <linux/module.h>
9 #include <linux/delay.h>
10 #include <linux/mmc/mmc.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/pm_opp.h>
13 #include <linux/slab.h>
14 #include <linux/iopoll.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/interconnect.h>
17 #include <linux/of.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/reset.h>
20 
21 #include <soc/qcom/ice.h>
22 
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
25 #include "cqhci.h"
26 
27 #define CORE_MCI_VERSION		0x50
28 #define CORE_VERSION_MAJOR_SHIFT	28
29 #define CORE_VERSION_MAJOR_MASK		(0xf << CORE_VERSION_MAJOR_SHIFT)
30 #define CORE_VERSION_MINOR_MASK		0xff
31 
32 #define CORE_MCI_GENERICS		0x70
33 #define SWITCHABLE_SIGNALING_VOLTAGE	BIT(29)
34 
35 #define HC_MODE_EN		0x1
36 #define CORE_POWER		0x0
37 #define CORE_SW_RST		BIT(7)
38 #define FF_CLK_SW_RST_DIS	BIT(13)
39 
40 #define CORE_PWRCTL_BUS_OFF	BIT(0)
41 #define CORE_PWRCTL_BUS_ON	BIT(1)
42 #define CORE_PWRCTL_IO_LOW	BIT(2)
43 #define CORE_PWRCTL_IO_HIGH	BIT(3)
44 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
45 #define CORE_PWRCTL_BUS_FAIL    BIT(1)
46 #define CORE_PWRCTL_IO_SUCCESS	BIT(2)
47 #define CORE_PWRCTL_IO_FAIL     BIT(3)
48 #define REQ_BUS_OFF		BIT(0)
49 #define REQ_BUS_ON		BIT(1)
50 #define REQ_IO_LOW		BIT(2)
51 #define REQ_IO_HIGH		BIT(3)
52 #define INT_MASK		0xf
53 #define MAX_PHASES		16
54 #define CORE_DLL_LOCK		BIT(7)
55 #define CORE_DDR_DLL_LOCK	BIT(11)
56 #define CORE_DLL_EN		BIT(16)
57 #define CORE_CDR_EN		BIT(17)
58 #define CORE_CK_OUT_EN		BIT(18)
59 #define CORE_CDR_EXT_EN		BIT(19)
60 #define CORE_DLL_PDN		BIT(29)
61 #define CORE_DLL_RST		BIT(30)
62 #define CORE_CMD_DAT_TRACK_SEL	BIT(0)
63 
64 #define CORE_DDR_CAL_EN		BIT(0)
65 #define CORE_FLL_CYCLE_CNT	BIT(18)
66 #define CORE_DLL_CLOCK_DISABLE	BIT(21)
67 
68 #define DLL_USR_CTL_POR_VAL	0x10800
69 #define ENABLE_DLL_LOCK_STATUS	BIT(26)
70 #define FINE_TUNE_MODE_EN	BIT(27)
71 #define BIAS_OK_SIGNAL		BIT(29)
72 
73 #define DLL_CONFIG_3_LOW_FREQ_VAL	0x08
74 #define DLL_CONFIG_3_HIGH_FREQ_VAL	0x10
75 
76 #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
77 #define CORE_CLK_PWRSAVE	BIT(1)
78 #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
79 #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
80 #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
81 #define CORE_IO_PAD_PWR_SWITCH_EN	BIT(15)
82 #define CORE_IO_PAD_PWR_SWITCH	BIT(16)
83 #define CORE_HC_SELECT_IN_EN	BIT(18)
84 #define CORE_HC_SELECT_IN_HS400	(6 << 19)
85 #define CORE_HC_SELECT_IN_MASK	(7 << 19)
86 
87 #define CORE_3_0V_SUPPORT	BIT(25)
88 #define CORE_1_8V_SUPPORT	BIT(26)
89 #define CORE_VOLT_SUPPORT	(CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
90 
91 #define CORE_CSR_CDC_CTLR_CFG0		0x130
92 #define CORE_SW_TRIG_FULL_CALIB		BIT(16)
93 #define CORE_HW_AUTOCAL_ENA		BIT(17)
94 
95 #define CORE_CSR_CDC_CTLR_CFG1		0x134
96 #define CORE_CSR_CDC_CAL_TIMER_CFG0	0x138
97 #define CORE_TIMER_ENA			BIT(16)
98 
99 #define CORE_CSR_CDC_CAL_TIMER_CFG1	0x13C
100 #define CORE_CSR_CDC_REFCOUNT_CFG	0x140
101 #define CORE_CSR_CDC_COARSE_CAL_CFG	0x144
102 #define CORE_CDC_OFFSET_CFG		0x14C
103 #define CORE_CSR_CDC_DELAY_CFG		0x150
104 #define CORE_CDC_SLAVE_DDA_CFG		0x160
105 #define CORE_CSR_CDC_STATUS0		0x164
106 #define CORE_CALIBRATION_DONE		BIT(0)
107 
108 #define CORE_CDC_ERROR_CODE_MASK	0x7000000
109 
110 #define CORE_CSR_CDC_GEN_CFG		0x178
111 #define CORE_CDC_SWITCH_BYPASS_OFF	BIT(0)
112 #define CORE_CDC_SWITCH_RC_EN		BIT(1)
113 
114 #define CORE_CDC_T4_DLY_SEL		BIT(0)
115 #define CORE_CMDIN_RCLK_EN		BIT(1)
116 #define CORE_START_CDC_TRAFFIC		BIT(6)
117 
118 #define CORE_PWRSAVE_DLL	BIT(3)
119 
120 #define DDR_CONFIG_POR_VAL	0x80040873
121 
122 
123 #define INVALID_TUNING_PHASE	-1
124 #define SDHCI_MSM_MIN_CLOCK	400000
125 #define CORE_FREQ_100MHZ	(100 * 1000 * 1000)
126 
127 #define CDR_SELEXT_SHIFT	20
128 #define CDR_SELEXT_MASK		(0xf << CDR_SELEXT_SHIFT)
129 #define CMUX_SHIFT_PHASE_SHIFT	24
130 #define CMUX_SHIFT_PHASE_MASK	(7 << CMUX_SHIFT_PHASE_SHIFT)
131 
132 #define MSM_MMC_AUTOSUSPEND_DELAY_MS	50
133 
134 /* Timeout value to avoid infinite waiting for pwr_irq */
135 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
136 
137 /* Max load for eMMC Vdd supply */
138 #define MMC_VMMC_MAX_LOAD_UA	570000
139 
140 /* Max load for eMMC Vdd-io supply */
141 #define MMC_VQMMC_MAX_LOAD_UA	325000
142 
143 /* Max load for SD Vdd supply */
144 #define SD_VMMC_MAX_LOAD_UA	800000
145 
146 /* Max load for SD Vdd-io supply */
147 #define SD_VQMMC_MAX_LOAD_UA	22000
148 
149 #define msm_host_readl(msm_host, host, offset) \
150 	msm_host->var_ops->msm_readl_relaxed(host, offset)
151 
152 #define msm_host_writel(msm_host, val, host, offset) \
153 	msm_host->var_ops->msm_writel_relaxed(val, host, offset)
154 
155 /* CQHCI vendor specific registers */
156 #define CQHCI_VENDOR_CFG1	0xA00
157 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN	(0x3 << 13)
158 
159 struct sdhci_msm_offset {
160 	u32 core_hc_mode;
161 	u32 core_mci_data_cnt;
162 	u32 core_mci_status;
163 	u32 core_mci_fifo_cnt;
164 	u32 core_mci_version;
165 	u32 core_generics;
166 	u32 core_testbus_config;
167 	u32 core_testbus_sel2_bit;
168 	u32 core_testbus_ena;
169 	u32 core_testbus_sel2;
170 	u32 core_pwrctl_status;
171 	u32 core_pwrctl_mask;
172 	u32 core_pwrctl_clear;
173 	u32 core_pwrctl_ctl;
174 	u32 core_sdcc_debug_reg;
175 	u32 core_dll_config;
176 	u32 core_dll_status;
177 	u32 core_vendor_spec;
178 	u32 core_vendor_spec_adma_err_addr0;
179 	u32 core_vendor_spec_adma_err_addr1;
180 	u32 core_vendor_spec_func2;
181 	u32 core_vendor_spec_capabilities0;
182 	u32 core_ddr_200_cfg;
183 	u32 core_vendor_spec3;
184 	u32 core_dll_config_2;
185 	u32 core_dll_config_3;
186 	u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
187 	u32 core_ddr_config;
188 	u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
189 };
190 
191 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
192 	.core_mci_data_cnt = 0x35c,
193 	.core_mci_status = 0x324,
194 	.core_mci_fifo_cnt = 0x308,
195 	.core_mci_version = 0x318,
196 	.core_generics = 0x320,
197 	.core_testbus_config = 0x32c,
198 	.core_testbus_sel2_bit = 3,
199 	.core_testbus_ena = (1 << 31),
200 	.core_testbus_sel2 = (1 << 3),
201 	.core_pwrctl_status = 0x240,
202 	.core_pwrctl_mask = 0x244,
203 	.core_pwrctl_clear = 0x248,
204 	.core_pwrctl_ctl = 0x24c,
205 	.core_sdcc_debug_reg = 0x358,
206 	.core_dll_config = 0x200,
207 	.core_dll_status = 0x208,
208 	.core_vendor_spec = 0x20c,
209 	.core_vendor_spec_adma_err_addr0 = 0x214,
210 	.core_vendor_spec_adma_err_addr1 = 0x218,
211 	.core_vendor_spec_func2 = 0x210,
212 	.core_vendor_spec_capabilities0 = 0x21c,
213 	.core_ddr_200_cfg = 0x224,
214 	.core_vendor_spec3 = 0x250,
215 	.core_dll_config_2 = 0x254,
216 	.core_dll_config_3 = 0x258,
217 	.core_ddr_config = 0x25c,
218 	.core_dll_usr_ctl = 0x388,
219 };
220 
221 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
222 	.core_hc_mode = 0x78,
223 	.core_mci_data_cnt = 0x30,
224 	.core_mci_status = 0x34,
225 	.core_mci_fifo_cnt = 0x44,
226 	.core_mci_version = 0x050,
227 	.core_generics = 0x70,
228 	.core_testbus_config = 0x0cc,
229 	.core_testbus_sel2_bit = 4,
230 	.core_testbus_ena = (1 << 3),
231 	.core_testbus_sel2 = (1 << 4),
232 	.core_pwrctl_status = 0xdc,
233 	.core_pwrctl_mask = 0xe0,
234 	.core_pwrctl_clear = 0xe4,
235 	.core_pwrctl_ctl = 0xe8,
236 	.core_sdcc_debug_reg = 0x124,
237 	.core_dll_config = 0x100,
238 	.core_dll_status = 0x108,
239 	.core_vendor_spec = 0x10c,
240 	.core_vendor_spec_adma_err_addr0 = 0x114,
241 	.core_vendor_spec_adma_err_addr1 = 0x118,
242 	.core_vendor_spec_func2 = 0x110,
243 	.core_vendor_spec_capabilities0 = 0x11c,
244 	.core_ddr_200_cfg = 0x184,
245 	.core_vendor_spec3 = 0x1b0,
246 	.core_dll_config_2 = 0x1b4,
247 	.core_ddr_config_old = 0x1b8,
248 	.core_ddr_config = 0x1bc,
249 };
250 
251 struct sdhci_msm_variant_ops {
252 	u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
253 	void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
254 			u32 offset);
255 };
256 
257 /*
258  * From V5, register spaces have changed. Wrap this info in a structure
259  * and choose the data_structure based on version info mentioned in DT.
260  */
261 struct sdhci_msm_variant_info {
262 	bool mci_removed;
263 	bool restore_dll_config;
264 	const struct sdhci_msm_variant_ops *var_ops;
265 	const struct sdhci_msm_offset *offset;
266 };
267 
268 struct sdhci_msm_host {
269 	struct platform_device *pdev;
270 	void __iomem *core_mem;	/* MSM SDCC mapped address */
271 	int pwr_irq;		/* power irq */
272 	struct clk *bus_clk;	/* SDHC bus voter clock */
273 	struct clk *xo_clk;	/* TCXO clk needed for FLL feature of cm_dll*/
274 	/* core, iface, cal and sleep clocks */
275 	struct clk_bulk_data bulk_clks[4];
276 #ifdef CONFIG_MMC_CRYPTO
277 	struct qcom_ice *ice;
278 #endif
279 	unsigned long clk_rate;
280 	struct mmc_host *mmc;
281 	bool use_14lpp_dll_reset;
282 	bool tuning_done;
283 	bool calibration_done;
284 	u8 saved_tuning_phase;
285 	bool use_cdclp533;
286 	u32 curr_pwr_state;
287 	u32 curr_io_level;
288 	wait_queue_head_t pwr_irq_wait;
289 	bool pwr_irq_flag;
290 	u32 caps_0;
291 	bool mci_removed;
292 	bool restore_dll_config;
293 	const struct sdhci_msm_variant_ops *var_ops;
294 	const struct sdhci_msm_offset *offset;
295 	bool use_cdr;
296 	u32 transfer_mode;
297 	bool updated_ddr_cfg;
298 	bool uses_tassadar_dll;
299 	u32 dll_config;
300 	u32 ddr_config;
301 	bool vqmmc_enabled;
302 };
303 
sdhci_priv_msm_offset(struct sdhci_host * host)304 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
305 {
306 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
307 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
308 
309 	return msm_host->offset;
310 }
311 
312 /*
313  * APIs to read/write to vendor specific registers which were there in the
314  * core_mem region before MCI was removed.
315  */
sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host * host,u32 offset)316 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
317 		u32 offset)
318 {
319 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
320 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
321 
322 	return readl_relaxed(msm_host->core_mem + offset);
323 }
324 
sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host * host,u32 offset)325 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
326 		u32 offset)
327 {
328 	return readl_relaxed(host->ioaddr + offset);
329 }
330 
sdhci_msm_mci_variant_writel_relaxed(u32 val,struct sdhci_host * host,u32 offset)331 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
332 		struct sdhci_host *host, u32 offset)
333 {
334 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
335 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
336 
337 	writel_relaxed(val, msm_host->core_mem + offset);
338 }
339 
sdhci_msm_v5_variant_writel_relaxed(u32 val,struct sdhci_host * host,u32 offset)340 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
341 		struct sdhci_host *host, u32 offset)
342 {
343 	writel_relaxed(val, host->ioaddr + offset);
344 }
345 
msm_get_clock_mult_for_bus_mode(struct sdhci_host * host)346 static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host)
347 {
348 	struct mmc_ios ios = host->mmc->ios;
349 	/*
350 	 * The SDHC requires internal clock frequency to be double the
351 	 * actual clock that will be set for DDR mode. The controller
352 	 * uses the faster clock(100/400MHz) for some of its parts and
353 	 * send the actual required clock (50/200MHz) to the card.
354 	 */
355 	if (ios.timing == MMC_TIMING_UHS_DDR50 ||
356 	    ios.timing == MMC_TIMING_MMC_DDR52 ||
357 	    ios.timing == MMC_TIMING_MMC_HS400 ||
358 	    host->flags & SDHCI_HS400_TUNING)
359 		return 2;
360 	return 1;
361 }
362 
msm_set_clock_rate_for_bus_mode(struct sdhci_host * host,unsigned int clock)363 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
364 					    unsigned int clock)
365 {
366 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
367 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
368 	struct mmc_ios curr_ios = host->mmc->ios;
369 	struct clk *core_clk = msm_host->bulk_clks[0].clk;
370 	unsigned long achieved_rate;
371 	unsigned int desired_rate;
372 	unsigned int mult;
373 	int rc;
374 
375 	mult = msm_get_clock_mult_for_bus_mode(host);
376 	desired_rate = clock * mult;
377 	rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate);
378 	if (rc) {
379 		pr_err("%s: Failed to set clock at rate %u at timing %d\n",
380 		       mmc_hostname(host->mmc), desired_rate, curr_ios.timing);
381 		return;
382 	}
383 
384 	/*
385 	 * Qualcomm clock drivers by default round clock _up_ if they can't
386 	 * make the requested rate.  This is not good for SD.  Yell if we
387 	 * encounter it.
388 	 */
389 	achieved_rate = clk_get_rate(core_clk);
390 	if (achieved_rate > desired_rate)
391 		pr_warn("%s: Card appears overclocked; req %u Hz, actual %lu Hz\n",
392 			mmc_hostname(host->mmc), desired_rate, achieved_rate);
393 	host->mmc->actual_clock = achieved_rate / mult;
394 
395 	/* Stash the rate we requested to use in sdhci_msm_runtime_resume() */
396 	msm_host->clk_rate = desired_rate;
397 
398 	pr_debug("%s: Setting clock at rate %lu at timing %d\n",
399 		 mmc_hostname(host->mmc), achieved_rate, curr_ios.timing);
400 }
401 
402 /* Platform specific tuning */
msm_dll_poll_ck_out_en(struct sdhci_host * host,u8 poll)403 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
404 {
405 	u32 wait_cnt = 50;
406 	u8 ck_out_en;
407 	struct mmc_host *mmc = host->mmc;
408 	const struct sdhci_msm_offset *msm_offset =
409 					sdhci_priv_msm_offset(host);
410 
411 	/* Poll for CK_OUT_EN bit.  max. poll time = 50us */
412 	ck_out_en = !!(readl_relaxed(host->ioaddr +
413 			msm_offset->core_dll_config) & CORE_CK_OUT_EN);
414 
415 	while (ck_out_en != poll) {
416 		if (--wait_cnt == 0) {
417 			dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
418 			       mmc_hostname(mmc), poll);
419 			return -ETIMEDOUT;
420 		}
421 		udelay(1);
422 
423 		ck_out_en = !!(readl_relaxed(host->ioaddr +
424 			msm_offset->core_dll_config) & CORE_CK_OUT_EN);
425 	}
426 
427 	return 0;
428 }
429 
msm_config_cm_dll_phase(struct sdhci_host * host,u8 phase)430 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
431 {
432 	int rc;
433 	static const u8 grey_coded_phase_table[] = {
434 		0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
435 		0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
436 	};
437 	unsigned long flags;
438 	u32 config;
439 	struct mmc_host *mmc = host->mmc;
440 	const struct sdhci_msm_offset *msm_offset =
441 					sdhci_priv_msm_offset(host);
442 
443 	if (phase > 0xf)
444 		return -EINVAL;
445 
446 	spin_lock_irqsave(&host->lock, flags);
447 
448 	config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
449 	config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
450 	config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
451 	writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
452 
453 	/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
454 	rc = msm_dll_poll_ck_out_en(host, 0);
455 	if (rc)
456 		goto err_out;
457 
458 	/*
459 	 * Write the selected DLL clock output phase (0 ... 15)
460 	 * to CDR_SELEXT bit field of DLL_CONFIG register.
461 	 */
462 	config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
463 	config &= ~CDR_SELEXT_MASK;
464 	config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
465 	writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
466 
467 	config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
468 	config |= CORE_CK_OUT_EN;
469 	writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
470 
471 	/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
472 	rc = msm_dll_poll_ck_out_en(host, 1);
473 	if (rc)
474 		goto err_out;
475 
476 	config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
477 	config |= CORE_CDR_EN;
478 	config &= ~CORE_CDR_EXT_EN;
479 	writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
480 	goto out;
481 
482 err_out:
483 	dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
484 	       mmc_hostname(mmc), phase);
485 out:
486 	spin_unlock_irqrestore(&host->lock, flags);
487 	return rc;
488 }
489 
490 /*
491  * Find out the greatest range of consecuitive selected
492  * DLL clock output phases that can be used as sampling
493  * setting for SD3.0 UHS-I card read operation (in SDR104
494  * timing mode) or for eMMC4.5 card read operation (in
495  * HS400/HS200 timing mode).
496  * Select the 3/4 of the range and configure the DLL with the
497  * selected DLL clock output phase.
498  */
499 
msm_find_most_appropriate_phase(struct sdhci_host * host,u8 * phase_table,u8 total_phases)500 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
501 					   u8 *phase_table, u8 total_phases)
502 {
503 	int ret;
504 	u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
505 	u8 phases_per_row[MAX_PHASES] = { 0 };
506 	int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
507 	int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
508 	bool phase_0_found = false, phase_15_found = false;
509 	struct mmc_host *mmc = host->mmc;
510 
511 	if (!total_phases || (total_phases > MAX_PHASES)) {
512 		dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
513 		       mmc_hostname(mmc), total_phases);
514 		return -EINVAL;
515 	}
516 
517 	for (cnt = 0; cnt < total_phases; cnt++) {
518 		ranges[row_index][col_index] = phase_table[cnt];
519 		phases_per_row[row_index] += 1;
520 		col_index++;
521 
522 		if ((cnt + 1) == total_phases) {
523 			continue;
524 		/* check if next phase in phase_table is consecutive or not */
525 		} else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
526 			row_index++;
527 			col_index = 0;
528 		}
529 	}
530 
531 	if (row_index >= MAX_PHASES)
532 		return -EINVAL;
533 
534 	/* Check if phase-0 is present in first valid window? */
535 	if (!ranges[0][0]) {
536 		phase_0_found = true;
537 		phase_0_raw_index = 0;
538 		/* Check if cycle exist between 2 valid windows */
539 		for (cnt = 1; cnt <= row_index; cnt++) {
540 			if (phases_per_row[cnt]) {
541 				for (i = 0; i < phases_per_row[cnt]; i++) {
542 					if (ranges[cnt][i] == 15) {
543 						phase_15_found = true;
544 						phase_15_raw_index = cnt;
545 						break;
546 					}
547 				}
548 			}
549 		}
550 	}
551 
552 	/* If 2 valid windows form cycle then merge them as single window */
553 	if (phase_0_found && phase_15_found) {
554 		/* number of phases in raw where phase 0 is present */
555 		u8 phases_0 = phases_per_row[phase_0_raw_index];
556 		/* number of phases in raw where phase 15 is present */
557 		u8 phases_15 = phases_per_row[phase_15_raw_index];
558 
559 		if (phases_0 + phases_15 >= MAX_PHASES)
560 			/*
561 			 * If there are more than 1 phase windows then total
562 			 * number of phases in both the windows should not be
563 			 * more than or equal to MAX_PHASES.
564 			 */
565 			return -EINVAL;
566 
567 		/* Merge 2 cyclic windows */
568 		i = phases_15;
569 		for (cnt = 0; cnt < phases_0; cnt++) {
570 			ranges[phase_15_raw_index][i] =
571 			    ranges[phase_0_raw_index][cnt];
572 			if (++i >= MAX_PHASES)
573 				break;
574 		}
575 
576 		phases_per_row[phase_0_raw_index] = 0;
577 		phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
578 	}
579 
580 	for (cnt = 0; cnt <= row_index; cnt++) {
581 		if (phases_per_row[cnt] > curr_max) {
582 			curr_max = phases_per_row[cnt];
583 			selected_row_index = cnt;
584 		}
585 	}
586 
587 	i = (curr_max * 3) / 4;
588 	if (i)
589 		i--;
590 
591 	ret = ranges[selected_row_index][i];
592 
593 	if (ret >= MAX_PHASES) {
594 		ret = -EINVAL;
595 		dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
596 		       mmc_hostname(mmc), ret);
597 	}
598 
599 	return ret;
600 }
601 
msm_cm_dll_set_freq(struct sdhci_host * host)602 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
603 {
604 	u32 mclk_freq = 0, config;
605 	const struct sdhci_msm_offset *msm_offset =
606 					sdhci_priv_msm_offset(host);
607 
608 	/* Program the MCLK value to MCLK_FREQ bit field */
609 	if (host->clock <= 112000000)
610 		mclk_freq = 0;
611 	else if (host->clock <= 125000000)
612 		mclk_freq = 1;
613 	else if (host->clock <= 137000000)
614 		mclk_freq = 2;
615 	else if (host->clock <= 150000000)
616 		mclk_freq = 3;
617 	else if (host->clock <= 162000000)
618 		mclk_freq = 4;
619 	else if (host->clock <= 175000000)
620 		mclk_freq = 5;
621 	else if (host->clock <= 187000000)
622 		mclk_freq = 6;
623 	else if (host->clock <= 200000000)
624 		mclk_freq = 7;
625 
626 	config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
627 	config &= ~CMUX_SHIFT_PHASE_MASK;
628 	config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
629 	writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
630 }
631 
632 /* Initialize the DLL (Programmable Delay Line) */
msm_init_cm_dll(struct sdhci_host * host)633 static int msm_init_cm_dll(struct sdhci_host *host)
634 {
635 	struct mmc_host *mmc = host->mmc;
636 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
637 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
638 	int wait_cnt = 50;
639 	unsigned long flags, xo_clk = 0;
640 	u32 config;
641 	const struct sdhci_msm_offset *msm_offset =
642 					msm_host->offset;
643 
644 	if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
645 		xo_clk = clk_get_rate(msm_host->xo_clk);
646 
647 	spin_lock_irqsave(&host->lock, flags);
648 
649 	/*
650 	 * Make sure that clock is always enabled when DLL
651 	 * tuning is in progress. Keeping PWRSAVE ON may
652 	 * turn off the clock.
653 	 */
654 	config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
655 	config &= ~CORE_CLK_PWRSAVE;
656 	writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
657 
658 	if (msm_host->dll_config)
659 		writel_relaxed(msm_host->dll_config,
660 				host->ioaddr + msm_offset->core_dll_config);
661 
662 	if (msm_host->use_14lpp_dll_reset) {
663 		config = readl_relaxed(host->ioaddr +
664 				msm_offset->core_dll_config);
665 		config &= ~CORE_CK_OUT_EN;
666 		writel_relaxed(config, host->ioaddr +
667 				msm_offset->core_dll_config);
668 
669 		config = readl_relaxed(host->ioaddr +
670 				msm_offset->core_dll_config_2);
671 		config |= CORE_DLL_CLOCK_DISABLE;
672 		writel_relaxed(config, host->ioaddr +
673 				msm_offset->core_dll_config_2);
674 	}
675 
676 	config = readl_relaxed(host->ioaddr +
677 			msm_offset->core_dll_config);
678 	config |= CORE_DLL_RST;
679 	writel_relaxed(config, host->ioaddr +
680 			msm_offset->core_dll_config);
681 
682 	config = readl_relaxed(host->ioaddr +
683 			msm_offset->core_dll_config);
684 	config |= CORE_DLL_PDN;
685 	writel_relaxed(config, host->ioaddr +
686 			msm_offset->core_dll_config);
687 
688 	if (!msm_host->dll_config)
689 		msm_cm_dll_set_freq(host);
690 
691 	if (msm_host->use_14lpp_dll_reset &&
692 	    !IS_ERR_OR_NULL(msm_host->xo_clk)) {
693 		u32 mclk_freq = 0;
694 
695 		config = readl_relaxed(host->ioaddr +
696 				msm_offset->core_dll_config_2);
697 		config &= CORE_FLL_CYCLE_CNT;
698 		if (config)
699 			mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
700 					xo_clk);
701 		else
702 			mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
703 					xo_clk);
704 
705 		config = readl_relaxed(host->ioaddr +
706 				msm_offset->core_dll_config_2);
707 		config &= ~(0xFF << 10);
708 		config |= mclk_freq << 10;
709 
710 		writel_relaxed(config, host->ioaddr +
711 				msm_offset->core_dll_config_2);
712 		/* wait for 5us before enabling DLL clock */
713 		udelay(5);
714 	}
715 
716 	config = readl_relaxed(host->ioaddr +
717 			msm_offset->core_dll_config);
718 	config &= ~CORE_DLL_RST;
719 	writel_relaxed(config, host->ioaddr +
720 			msm_offset->core_dll_config);
721 
722 	config = readl_relaxed(host->ioaddr +
723 			msm_offset->core_dll_config);
724 	config &= ~CORE_DLL_PDN;
725 	writel_relaxed(config, host->ioaddr +
726 			msm_offset->core_dll_config);
727 
728 	if (msm_host->use_14lpp_dll_reset) {
729 		if (!msm_host->dll_config)
730 			msm_cm_dll_set_freq(host);
731 		config = readl_relaxed(host->ioaddr +
732 				msm_offset->core_dll_config_2);
733 		config &= ~CORE_DLL_CLOCK_DISABLE;
734 		writel_relaxed(config, host->ioaddr +
735 				msm_offset->core_dll_config_2);
736 	}
737 
738 	/*
739 	 * Configure DLL user control register to enable DLL status.
740 	 * This setting is applicable to SDCC v5.1 onwards only.
741 	 */
742 	if (msm_host->uses_tassadar_dll) {
743 		config = DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
744 			ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;
745 		writel_relaxed(config, host->ioaddr +
746 				msm_offset->core_dll_usr_ctl);
747 
748 		config = readl_relaxed(host->ioaddr +
749 				msm_offset->core_dll_config_3);
750 		config &= ~0xFF;
751 		if (msm_host->clk_rate < 150000000)
752 			config |= DLL_CONFIG_3_LOW_FREQ_VAL;
753 		else
754 			config |= DLL_CONFIG_3_HIGH_FREQ_VAL;
755 		writel_relaxed(config, host->ioaddr +
756 			msm_offset->core_dll_config_3);
757 	}
758 
759 	config = readl_relaxed(host->ioaddr +
760 			msm_offset->core_dll_config);
761 	config |= CORE_DLL_EN;
762 	writel_relaxed(config, host->ioaddr +
763 			msm_offset->core_dll_config);
764 
765 	config = readl_relaxed(host->ioaddr +
766 			msm_offset->core_dll_config);
767 	config |= CORE_CK_OUT_EN;
768 	writel_relaxed(config, host->ioaddr +
769 			msm_offset->core_dll_config);
770 
771 	/* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
772 	while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
773 		 CORE_DLL_LOCK)) {
774 		/* max. wait for 50us sec for LOCK bit to be set */
775 		if (--wait_cnt == 0) {
776 			dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
777 			       mmc_hostname(mmc));
778 			spin_unlock_irqrestore(&host->lock, flags);
779 			return -ETIMEDOUT;
780 		}
781 		udelay(1);
782 	}
783 
784 	spin_unlock_irqrestore(&host->lock, flags);
785 	return 0;
786 }
787 
msm_hc_select_default(struct sdhci_host * host)788 static void msm_hc_select_default(struct sdhci_host *host)
789 {
790 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
791 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
792 	u32 config;
793 	const struct sdhci_msm_offset *msm_offset =
794 					msm_host->offset;
795 
796 	if (!msm_host->use_cdclp533) {
797 		config = readl_relaxed(host->ioaddr +
798 				msm_offset->core_vendor_spec3);
799 		config &= ~CORE_PWRSAVE_DLL;
800 		writel_relaxed(config, host->ioaddr +
801 				msm_offset->core_vendor_spec3);
802 	}
803 
804 	config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
805 	config &= ~CORE_HC_MCLK_SEL_MASK;
806 	config |= CORE_HC_MCLK_SEL_DFLT;
807 	writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
808 
809 	/*
810 	 * Disable HC_SELECT_IN to be able to use the UHS mode select
811 	 * configuration from Host Control2 register for all other
812 	 * modes.
813 	 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
814 	 * in VENDOR_SPEC_FUNC
815 	 */
816 	config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
817 	config &= ~CORE_HC_SELECT_IN_EN;
818 	config &= ~CORE_HC_SELECT_IN_MASK;
819 	writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
820 
821 	/*
822 	 * Make sure above writes impacting free running MCLK are completed
823 	 * before changing the clk_rate at GCC.
824 	 */
825 	wmb();
826 }
827 
msm_hc_select_hs400(struct sdhci_host * host)828 static void msm_hc_select_hs400(struct sdhci_host *host)
829 {
830 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
831 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
832 	struct mmc_ios ios = host->mmc->ios;
833 	u32 config, dll_lock;
834 	int rc;
835 	const struct sdhci_msm_offset *msm_offset =
836 					msm_host->offset;
837 
838 	/* Select the divided clock (free running MCLK/2) */
839 	config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
840 	config &= ~CORE_HC_MCLK_SEL_MASK;
841 	config |= CORE_HC_MCLK_SEL_HS400;
842 
843 	writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
844 	/*
845 	 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
846 	 * register
847 	 */
848 	if ((msm_host->tuning_done || ios.enhanced_strobe) &&
849 	    !msm_host->calibration_done) {
850 		config = readl_relaxed(host->ioaddr +
851 				msm_offset->core_vendor_spec);
852 		config |= CORE_HC_SELECT_IN_HS400;
853 		config |= CORE_HC_SELECT_IN_EN;
854 		writel_relaxed(config, host->ioaddr +
855 				msm_offset->core_vendor_spec);
856 	}
857 	if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
858 		/*
859 		 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
860 		 * core_dll_status to be set. This should get set
861 		 * within 15 us at 200 MHz.
862 		 */
863 		rc = readl_relaxed_poll_timeout(host->ioaddr +
864 						msm_offset->core_dll_status,
865 						dll_lock,
866 						(dll_lock &
867 						(CORE_DLL_LOCK |
868 						CORE_DDR_DLL_LOCK)), 10,
869 						1000);
870 		if (rc == -ETIMEDOUT)
871 			pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
872 			       mmc_hostname(host->mmc), dll_lock);
873 	}
874 	/*
875 	 * Make sure above writes impacting free running MCLK are completed
876 	 * before changing the clk_rate at GCC.
877 	 */
878 	wmb();
879 }
880 
881 /*
882  * sdhci_msm_hc_select_mode :- In general all timing modes are
883  * controlled via UHS mode select in Host Control2 register.
884  * eMMC specific HS200/HS400 doesn't have their respective modes
885  * defined here, hence we use these values.
886  *
887  * HS200 - SDR104 (Since they both are equivalent in functionality)
888  * HS400 - This involves multiple configurations
889  *		Initially SDR104 - when tuning is required as HS200
890  *		Then when switching to DDR @ 400MHz (HS400) we use
891  *		the vendor specific HC_SELECT_IN to control the mode.
892  *
893  * In addition to controlling the modes we also need to select the
894  * correct input clock for DLL depending on the mode.
895  *
896  * HS400 - divided clock (free running MCLK/2)
897  * All other modes - default (free running MCLK)
898  */
sdhci_msm_hc_select_mode(struct sdhci_host * host)899 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
900 {
901 	struct mmc_ios ios = host->mmc->ios;
902 
903 	if (ios.timing == MMC_TIMING_MMC_HS400 ||
904 	    host->flags & SDHCI_HS400_TUNING)
905 		msm_hc_select_hs400(host);
906 	else
907 		msm_hc_select_default(host);
908 }
909 
sdhci_msm_cdclp533_calibration(struct sdhci_host * host)910 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
911 {
912 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
913 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
914 	u32 config, calib_done;
915 	int ret;
916 	const struct sdhci_msm_offset *msm_offset =
917 					msm_host->offset;
918 
919 	pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
920 
921 	/*
922 	 * Retuning in HS400 (DDR mode) will fail, just reset the
923 	 * tuning block and restore the saved tuning phase.
924 	 */
925 	ret = msm_init_cm_dll(host);
926 	if (ret)
927 		goto out;
928 
929 	/* Set the selected phase in delay line hw block */
930 	ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
931 	if (ret)
932 		goto out;
933 
934 	config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
935 	config |= CORE_CMD_DAT_TRACK_SEL;
936 	writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
937 
938 	config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
939 	config &= ~CORE_CDC_T4_DLY_SEL;
940 	writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
941 
942 	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
943 	config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
944 	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
945 
946 	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
947 	config |= CORE_CDC_SWITCH_RC_EN;
948 	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
949 
950 	config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
951 	config &= ~CORE_START_CDC_TRAFFIC;
952 	writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
953 
954 	/* Perform CDC Register Initialization Sequence */
955 
956 	writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
957 	writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
958 	writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
959 	writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
960 	writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
961 	writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
962 	writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
963 	writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
964 	writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
965 
966 	/* CDC HW Calibration */
967 
968 	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
969 	config |= CORE_SW_TRIG_FULL_CALIB;
970 	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
971 
972 	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
973 	config &= ~CORE_SW_TRIG_FULL_CALIB;
974 	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
975 
976 	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
977 	config |= CORE_HW_AUTOCAL_ENA;
978 	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
979 
980 	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
981 	config |= CORE_TIMER_ENA;
982 	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
983 
984 	ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
985 					 calib_done,
986 					 (calib_done & CORE_CALIBRATION_DONE),
987 					 1, 50);
988 
989 	if (ret == -ETIMEDOUT) {
990 		pr_err("%s: %s: CDC calibration was not completed\n",
991 		       mmc_hostname(host->mmc), __func__);
992 		goto out;
993 	}
994 
995 	ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
996 			& CORE_CDC_ERROR_CODE_MASK;
997 	if (ret) {
998 		pr_err("%s: %s: CDC error code %d\n",
999 		       mmc_hostname(host->mmc), __func__, ret);
1000 		ret = -EINVAL;
1001 		goto out;
1002 	}
1003 
1004 	config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
1005 	config |= CORE_START_CDC_TRAFFIC;
1006 	writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
1007 out:
1008 	pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1009 		 __func__, ret);
1010 	return ret;
1011 }
1012 
sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host * host)1013 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
1014 {
1015 	struct mmc_host *mmc = host->mmc;
1016 	u32 dll_status, config, ddr_cfg_offset;
1017 	int ret;
1018 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1019 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1020 	const struct sdhci_msm_offset *msm_offset =
1021 					sdhci_priv_msm_offset(host);
1022 
1023 	pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1024 
1025 	/*
1026 	 * Currently the core_ddr_config register defaults to desired
1027 	 * configuration on reset. Currently reprogramming the power on
1028 	 * reset (POR) value in case it might have been modified by
1029 	 * bootloaders. In the future, if this changes, then the desired
1030 	 * values will need to be programmed appropriately.
1031 	 */
1032 	if (msm_host->updated_ddr_cfg)
1033 		ddr_cfg_offset = msm_offset->core_ddr_config;
1034 	else
1035 		ddr_cfg_offset = msm_offset->core_ddr_config_old;
1036 	writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
1037 
1038 	if (mmc->ios.enhanced_strobe) {
1039 		config = readl_relaxed(host->ioaddr +
1040 				msm_offset->core_ddr_200_cfg);
1041 		config |= CORE_CMDIN_RCLK_EN;
1042 		writel_relaxed(config, host->ioaddr +
1043 				msm_offset->core_ddr_200_cfg);
1044 	}
1045 
1046 	config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
1047 	config |= CORE_DDR_CAL_EN;
1048 	writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
1049 
1050 	ret = readl_relaxed_poll_timeout(host->ioaddr +
1051 					msm_offset->core_dll_status,
1052 					dll_status,
1053 					(dll_status & CORE_DDR_DLL_LOCK),
1054 					10, 1000);
1055 
1056 	if (ret == -ETIMEDOUT) {
1057 		pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
1058 		       mmc_hostname(host->mmc), __func__);
1059 		goto out;
1060 	}
1061 
1062 	/*
1063 	 * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
1064 	 * When MCLK is gated OFF, it is not gated for less than 0.5us
1065 	 * and MCLK must be switched on for at-least 1us before DATA
1066 	 * starts coming. Controllers with 14lpp and later tech DLL cannot
1067 	 * guarantee above requirement. So PWRSAVE_DLL should not be
1068 	 * turned on for host controllers using this DLL.
1069 	 */
1070 	if (!msm_host->use_14lpp_dll_reset) {
1071 		config = readl_relaxed(host->ioaddr +
1072 				msm_offset->core_vendor_spec3);
1073 		config |= CORE_PWRSAVE_DLL;
1074 		writel_relaxed(config, host->ioaddr +
1075 				msm_offset->core_vendor_spec3);
1076 	}
1077 
1078 	/*
1079 	 * Drain writebuffer to ensure above DLL calibration
1080 	 * and PWRSAVE DLL is enabled.
1081 	 */
1082 	wmb();
1083 out:
1084 	pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1085 		 __func__, ret);
1086 	return ret;
1087 }
1088 
sdhci_msm_hs400_dll_calibration(struct sdhci_host * host)1089 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
1090 {
1091 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1092 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1093 	struct mmc_host *mmc = host->mmc;
1094 	int ret;
1095 	u32 config;
1096 	const struct sdhci_msm_offset *msm_offset =
1097 					msm_host->offset;
1098 
1099 	pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1100 
1101 	/*
1102 	 * Retuning in HS400 (DDR mode) will fail, just reset the
1103 	 * tuning block and restore the saved tuning phase.
1104 	 */
1105 	ret = msm_init_cm_dll(host);
1106 	if (ret)
1107 		goto out;
1108 
1109 	if (!mmc->ios.enhanced_strobe) {
1110 		/* Set the selected phase in delay line hw block */
1111 		ret = msm_config_cm_dll_phase(host,
1112 					      msm_host->saved_tuning_phase);
1113 		if (ret)
1114 			goto out;
1115 		config = readl_relaxed(host->ioaddr +
1116 				msm_offset->core_dll_config);
1117 		config |= CORE_CMD_DAT_TRACK_SEL;
1118 		writel_relaxed(config, host->ioaddr +
1119 				msm_offset->core_dll_config);
1120 	}
1121 
1122 	if (msm_host->use_cdclp533)
1123 		ret = sdhci_msm_cdclp533_calibration(host);
1124 	else
1125 		ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1126 out:
1127 	pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1128 		 __func__, ret);
1129 	return ret;
1130 }
1131 
sdhci_msm_is_tuning_needed(struct sdhci_host * host)1132 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1133 {
1134 	struct mmc_ios *ios = &host->mmc->ios;
1135 
1136 	/*
1137 	 * Tuning is required for SDR104, HS200 and HS400 cards and
1138 	 * if clock frequency is greater than 100MHz in these modes.
1139 	 */
1140 	if (host->clock <= CORE_FREQ_100MHZ ||
1141 	    !(ios->timing == MMC_TIMING_MMC_HS400 ||
1142 	    ios->timing == MMC_TIMING_MMC_HS200 ||
1143 	    ios->timing == MMC_TIMING_UHS_SDR104) ||
1144 	    ios->enhanced_strobe)
1145 		return false;
1146 
1147 	return true;
1148 }
1149 
sdhci_msm_restore_sdr_dll_config(struct sdhci_host * host)1150 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1151 {
1152 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1153 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1154 	int ret;
1155 
1156 	/*
1157 	 * SDR DLL comes into picture only for timing modes which needs
1158 	 * tuning.
1159 	 */
1160 	if (!sdhci_msm_is_tuning_needed(host))
1161 		return 0;
1162 
1163 	/* Reset the tuning block */
1164 	ret = msm_init_cm_dll(host);
1165 	if (ret)
1166 		return ret;
1167 
1168 	/* Restore the tuning block */
1169 	ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1170 
1171 	return ret;
1172 }
1173 
sdhci_msm_set_cdr(struct sdhci_host * host,bool enable)1174 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1175 {
1176 	const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1177 	u32 config, oldconfig = readl_relaxed(host->ioaddr +
1178 					      msm_offset->core_dll_config);
1179 
1180 	config = oldconfig;
1181 	if (enable) {
1182 		config |= CORE_CDR_EN;
1183 		config &= ~CORE_CDR_EXT_EN;
1184 	} else {
1185 		config &= ~CORE_CDR_EN;
1186 		config |= CORE_CDR_EXT_EN;
1187 	}
1188 
1189 	if (config != oldconfig) {
1190 		writel_relaxed(config, host->ioaddr +
1191 			       msm_offset->core_dll_config);
1192 	}
1193 }
1194 
sdhci_msm_execute_tuning(struct mmc_host * mmc,u32 opcode)1195 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1196 {
1197 	struct sdhci_host *host = mmc_priv(mmc);
1198 	int tuning_seq_cnt = 10;
1199 	u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1200 	int rc;
1201 	struct mmc_ios ios = host->mmc->ios;
1202 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1203 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1204 
1205 	if (!sdhci_msm_is_tuning_needed(host)) {
1206 		msm_host->use_cdr = false;
1207 		sdhci_msm_set_cdr(host, false);
1208 		return 0;
1209 	}
1210 
1211 	/* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1212 	msm_host->use_cdr = true;
1213 
1214 	/*
1215 	 * Clear tuning_done flag before tuning to ensure proper
1216 	 * HS400 settings.
1217 	 */
1218 	msm_host->tuning_done = 0;
1219 
1220 	/*
1221 	 * For HS400 tuning in HS200 timing requires:
1222 	 * - select MCLK/2 in VENDOR_SPEC
1223 	 * - program MCLK to 400MHz (or nearest supported) in GCC
1224 	 */
1225 	if (host->flags & SDHCI_HS400_TUNING) {
1226 		sdhci_msm_hc_select_mode(host);
1227 		msm_set_clock_rate_for_bus_mode(host, ios.clock);
1228 		host->flags &= ~SDHCI_HS400_TUNING;
1229 	}
1230 
1231 retry:
1232 	/* First of all reset the tuning block */
1233 	rc = msm_init_cm_dll(host);
1234 	if (rc)
1235 		return rc;
1236 
1237 	phase = 0;
1238 	do {
1239 		/* Set the phase in delay line hw block */
1240 		rc = msm_config_cm_dll_phase(host, phase);
1241 		if (rc)
1242 			return rc;
1243 
1244 		rc = mmc_send_tuning(mmc, opcode, NULL);
1245 		if (!rc) {
1246 			/* Tuning is successful at this tuning point */
1247 			tuned_phases[tuned_phase_cnt++] = phase;
1248 			dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1249 				 mmc_hostname(mmc), phase);
1250 		}
1251 	} while (++phase < ARRAY_SIZE(tuned_phases));
1252 
1253 	if (tuned_phase_cnt) {
1254 		if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {
1255 			/*
1256 			 * All phases valid is _almost_ as bad as no phases
1257 			 * valid.  Probably all phases are not really reliable
1258 			 * but we didn't detect where the unreliable place is.
1259 			 * That means we'll essentially be guessing and hoping
1260 			 * we get a good phase.  Better to try a few times.
1261 			 */
1262 			dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n",
1263 				mmc_hostname(mmc));
1264 			if (--tuning_seq_cnt) {
1265 				tuned_phase_cnt = 0;
1266 				goto retry;
1267 			}
1268 		}
1269 
1270 		rc = msm_find_most_appropriate_phase(host, tuned_phases,
1271 						     tuned_phase_cnt);
1272 		if (rc < 0)
1273 			return rc;
1274 		else
1275 			phase = rc;
1276 
1277 		/*
1278 		 * Finally set the selected phase in delay
1279 		 * line hw block.
1280 		 */
1281 		rc = msm_config_cm_dll_phase(host, phase);
1282 		if (rc)
1283 			return rc;
1284 		msm_host->saved_tuning_phase = phase;
1285 		dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1286 			 mmc_hostname(mmc), phase);
1287 	} else {
1288 		if (--tuning_seq_cnt)
1289 			goto retry;
1290 		/* Tuning failed */
1291 		dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1292 		       mmc_hostname(mmc));
1293 		rc = -EIO;
1294 	}
1295 
1296 	if (!rc)
1297 		msm_host->tuning_done = true;
1298 	return rc;
1299 }
1300 
1301 /*
1302  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1303  * This needs to be done for both tuning and enhanced_strobe mode.
1304  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1305  * fixed feedback clock is used.
1306  */
sdhci_msm_hs400(struct sdhci_host * host,struct mmc_ios * ios)1307 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1308 {
1309 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1310 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1311 	int ret;
1312 
1313 	if (host->clock > CORE_FREQ_100MHZ &&
1314 	    (msm_host->tuning_done || ios->enhanced_strobe) &&
1315 	    !msm_host->calibration_done) {
1316 		ret = sdhci_msm_hs400_dll_calibration(host);
1317 		if (!ret)
1318 			msm_host->calibration_done = true;
1319 		else
1320 			pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1321 			       mmc_hostname(host->mmc), ret);
1322 	}
1323 }
1324 
sdhci_msm_set_uhs_signaling(struct sdhci_host * host,unsigned int uhs)1325 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1326 					unsigned int uhs)
1327 {
1328 	struct mmc_host *mmc = host->mmc;
1329 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1330 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1331 	u16 ctrl_2;
1332 	u32 config;
1333 	const struct sdhci_msm_offset *msm_offset =
1334 					msm_host->offset;
1335 
1336 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1337 	/* Select Bus Speed Mode for host */
1338 	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1339 	switch (uhs) {
1340 	case MMC_TIMING_UHS_SDR12:
1341 		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1342 		break;
1343 	case MMC_TIMING_UHS_SDR25:
1344 		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1345 		break;
1346 	case MMC_TIMING_UHS_SDR50:
1347 		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1348 		break;
1349 	case MMC_TIMING_MMC_HS400:
1350 	case MMC_TIMING_MMC_HS200:
1351 	case MMC_TIMING_UHS_SDR104:
1352 		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1353 		break;
1354 	case MMC_TIMING_UHS_DDR50:
1355 	case MMC_TIMING_MMC_DDR52:
1356 		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1357 		break;
1358 	}
1359 
1360 	/*
1361 	 * When clock frequency is less than 100MHz, the feedback clock must be
1362 	 * provided and DLL must not be used so that tuning can be skipped. To
1363 	 * provide feedback clock, the mode selection can be any value less
1364 	 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1365 	 */
1366 	if (host->clock <= CORE_FREQ_100MHZ) {
1367 		if (uhs == MMC_TIMING_MMC_HS400 ||
1368 		    uhs == MMC_TIMING_MMC_HS200 ||
1369 		    uhs == MMC_TIMING_UHS_SDR104)
1370 			ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1371 		/*
1372 		 * DLL is not required for clock <= 100MHz
1373 		 * Thus, make sure DLL it is disabled when not required
1374 		 */
1375 		config = readl_relaxed(host->ioaddr +
1376 				msm_offset->core_dll_config);
1377 		config |= CORE_DLL_RST;
1378 		writel_relaxed(config, host->ioaddr +
1379 				msm_offset->core_dll_config);
1380 
1381 		config = readl_relaxed(host->ioaddr +
1382 				msm_offset->core_dll_config);
1383 		config |= CORE_DLL_PDN;
1384 		writel_relaxed(config, host->ioaddr +
1385 				msm_offset->core_dll_config);
1386 
1387 		/*
1388 		 * The DLL needs to be restored and CDCLP533 recalibrated
1389 		 * when the clock frequency is set back to 400MHz.
1390 		 */
1391 		msm_host->calibration_done = false;
1392 	}
1393 
1394 	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1395 		mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1396 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1397 
1398 	if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1399 		sdhci_msm_hs400(host, &mmc->ios);
1400 }
1401 
sdhci_msm_set_pincfg(struct sdhci_msm_host * msm_host,bool level)1402 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
1403 {
1404 	struct platform_device *pdev = msm_host->pdev;
1405 	int ret;
1406 
1407 	if (level)
1408 		ret = pinctrl_pm_select_default_state(&pdev->dev);
1409 	else
1410 		ret = pinctrl_pm_select_sleep_state(&pdev->dev);
1411 
1412 	return ret;
1413 }
1414 
msm_config_vmmc_regulator(struct mmc_host * mmc,bool hpm)1415 static void msm_config_vmmc_regulator(struct mmc_host *mmc, bool hpm)
1416 {
1417 	int load;
1418 
1419 	if (!hpm)
1420 		load = 0;
1421 	else if (!mmc->card)
1422 		load = max(MMC_VMMC_MAX_LOAD_UA, SD_VMMC_MAX_LOAD_UA);
1423 	else if (mmc_card_mmc(mmc->card))
1424 		load = MMC_VMMC_MAX_LOAD_UA;
1425 	else if (mmc_card_sd(mmc->card))
1426 		load = SD_VMMC_MAX_LOAD_UA;
1427 	else
1428 		return;
1429 
1430 	regulator_set_load(mmc->supply.vmmc, load);
1431 }
1432 
msm_config_vqmmc_regulator(struct mmc_host * mmc,bool hpm)1433 static void msm_config_vqmmc_regulator(struct mmc_host *mmc, bool hpm)
1434 {
1435 	int load;
1436 
1437 	if (!hpm)
1438 		load = 0;
1439 	else if (!mmc->card)
1440 		load = max(MMC_VQMMC_MAX_LOAD_UA, SD_VQMMC_MAX_LOAD_UA);
1441 	else if (mmc_card_sd(mmc->card))
1442 		load = SD_VQMMC_MAX_LOAD_UA;
1443 	else
1444 		return;
1445 
1446 	regulator_set_load(mmc->supply.vqmmc, load);
1447 }
1448 
sdhci_msm_set_vmmc(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool hpm)1449 static int sdhci_msm_set_vmmc(struct sdhci_msm_host *msm_host,
1450 			      struct mmc_host *mmc, bool hpm)
1451 {
1452 	if (IS_ERR(mmc->supply.vmmc))
1453 		return 0;
1454 
1455 	msm_config_vmmc_regulator(mmc, hpm);
1456 
1457 	return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);
1458 }
1459 
msm_toggle_vqmmc(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool level)1460 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
1461 			      struct mmc_host *mmc, bool level)
1462 {
1463 	int ret;
1464 	struct mmc_ios ios;
1465 
1466 	if (msm_host->vqmmc_enabled == level)
1467 		return 0;
1468 
1469 	msm_config_vqmmc_regulator(mmc, level);
1470 
1471 	if (level) {
1472 		/* Set the IO voltage regulator to default voltage level */
1473 		if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
1474 			ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330;
1475 		else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
1476 			ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180;
1477 
1478 		if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1479 			ret = mmc_regulator_set_vqmmc(mmc, &ios);
1480 			if (ret < 0) {
1481 				dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n",
1482 					mmc_hostname(mmc), ret);
1483 				goto out;
1484 			}
1485 		}
1486 		ret = regulator_enable(mmc->supply.vqmmc);
1487 	} else {
1488 		ret = regulator_disable(mmc->supply.vqmmc);
1489 	}
1490 
1491 	if (ret)
1492 		dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n",
1493 			mmc_hostname(mmc), level ? "en":"dis", ret);
1494 	else
1495 		msm_host->vqmmc_enabled = level;
1496 out:
1497 	return ret;
1498 }
1499 
msm_config_vqmmc_mode(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool hpm)1500 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
1501 			      struct mmc_host *mmc, bool hpm)
1502 {
1503 	int load, ret;
1504 
1505 	load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;
1506 	ret = regulator_set_load(mmc->supply.vqmmc, load);
1507 	if (ret)
1508 		dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n",
1509 			mmc_hostname(mmc), ret);
1510 	return ret;
1511 }
1512 
sdhci_msm_set_vqmmc(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool level)1513 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
1514 			      struct mmc_host *mmc, bool level)
1515 {
1516 	int ret;
1517 	bool always_on;
1518 
1519 	if (IS_ERR(mmc->supply.vqmmc) ||
1520 			(mmc->ios.power_mode == MMC_POWER_UNDEFINED))
1521 		return 0;
1522 	/*
1523 	 * For eMMC don't turn off Vqmmc, Instead just configure it in LPM
1524 	 * and HPM modes by setting the corresponding load.
1525 	 *
1526 	 * Till eMMC is initialized (i.e. always_on == 0), just turn on/off
1527 	 * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off
1528 	 * gets invoked. Once eMMC is initialized (i.e. always_on == 1),
1529 	 * Vqmmc should remain ON, So just set the load instead of turning it
1530 	 * off/on.
1531 	 */
1532 	always_on = !mmc_card_is_removable(mmc) &&
1533 			mmc->card && mmc_card_mmc(mmc->card);
1534 
1535 	if (always_on)
1536 		ret = msm_config_vqmmc_mode(msm_host, mmc, level);
1537 	else
1538 		ret = msm_toggle_vqmmc(msm_host, mmc, level);
1539 
1540 	return ret;
1541 }
1542 
sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host * msm_host)1543 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1544 {
1545 	init_waitqueue_head(&msm_host->pwr_irq_wait);
1546 }
1547 
sdhci_msm_complete_pwr_irq_wait(struct sdhci_msm_host * msm_host)1548 static inline void sdhci_msm_complete_pwr_irq_wait(
1549 		struct sdhci_msm_host *msm_host)
1550 {
1551 	wake_up(&msm_host->pwr_irq_wait);
1552 }
1553 
1554 /*
1555  * sdhci_msm_check_power_status API should be called when registers writes
1556  * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1557  * To what state the register writes will change the IO lines should be passed
1558  * as the argument req_type. This API will check whether the IO line's state
1559  * is already the expected state and will wait for power irq only if
1560  * power irq is expected to be triggered based on the current IO line state
1561  * and expected IO line state.
1562  */
sdhci_msm_check_power_status(struct sdhci_host * host,u32 req_type)1563 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1564 {
1565 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1566 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1567 	bool done = false;
1568 	u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1569 	const struct sdhci_msm_offset *msm_offset =
1570 					msm_host->offset;
1571 
1572 	pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1573 			mmc_hostname(host->mmc), __func__, req_type,
1574 			msm_host->curr_pwr_state, msm_host->curr_io_level);
1575 
1576 	/*
1577 	 * The power interrupt will not be generated for signal voltage
1578 	 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1579 	 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1580 	 * it as always set.
1581 	 */
1582 	if (!msm_host->mci_removed)
1583 		val = msm_host_readl(msm_host, host,
1584 				msm_offset->core_generics);
1585 	if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1586 	    !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1587 		return;
1588 	}
1589 
1590 	/*
1591 	 * The IRQ for request type IO High/LOW will be generated when -
1592 	 * there is a state change in 1.8V enable bit (bit 3) of
1593 	 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1594 	 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1595 	 * to set it to 3.3V before card detection happens, the
1596 	 * IRQ doesn't get triggered as there is no state change in this bit.
1597 	 * The driver already handles this case by changing the IO voltage
1598 	 * level to high as part of controller power up sequence. Hence, check
1599 	 * for host->pwr to handle a case where IO voltage high request is
1600 	 * issued even before controller power up.
1601 	 */
1602 	if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1603 		pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1604 				mmc_hostname(host->mmc), req_type);
1605 		return;
1606 	}
1607 	if ((req_type & msm_host->curr_pwr_state) ||
1608 			(req_type & msm_host->curr_io_level))
1609 		done = true;
1610 	/*
1611 	 * This is needed here to handle cases where register writes will
1612 	 * not change the current bus state or io level of the controller.
1613 	 * In this case, no power irq will be triggerred and we should
1614 	 * not wait.
1615 	 */
1616 	if (!done) {
1617 		if (!wait_event_timeout(msm_host->pwr_irq_wait,
1618 				msm_host->pwr_irq_flag,
1619 				msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1620 			dev_warn(&msm_host->pdev->dev,
1621 				 "%s: pwr_irq for req: (%d) timed out\n",
1622 				 mmc_hostname(host->mmc), req_type);
1623 	}
1624 	pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1625 			__func__, req_type);
1626 }
1627 
sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host * host)1628 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1629 {
1630 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1631 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1632 	const struct sdhci_msm_offset *msm_offset =
1633 					msm_host->offset;
1634 
1635 	pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1636 		mmc_hostname(host->mmc),
1637 		msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1638 		msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1639 		msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1640 }
1641 
sdhci_msm_handle_pwr_irq(struct sdhci_host * host,int irq)1642 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1643 {
1644 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1645 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1646 	struct mmc_host *mmc = host->mmc;
1647 	u32 irq_status, irq_ack = 0;
1648 	int retry = 10, ret;
1649 	u32 pwr_state = 0, io_level = 0;
1650 	u32 config;
1651 	const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1652 
1653 	irq_status = msm_host_readl(msm_host, host,
1654 			msm_offset->core_pwrctl_status);
1655 	irq_status &= INT_MASK;
1656 
1657 	msm_host_writel(msm_host, irq_status, host,
1658 			msm_offset->core_pwrctl_clear);
1659 
1660 	/*
1661 	 * There is a rare HW scenario where the first clear pulse could be
1662 	 * lost when actual reset and clear/read of status register is
1663 	 * happening at a time. Hence, retry for at least 10 times to make
1664 	 * sure status register is cleared. Otherwise, this will result in
1665 	 * a spurious power IRQ resulting in system instability.
1666 	 */
1667 	while (irq_status & msm_host_readl(msm_host, host,
1668 				msm_offset->core_pwrctl_status)) {
1669 		if (retry == 0) {
1670 			pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1671 					mmc_hostname(host->mmc), irq_status);
1672 			sdhci_msm_dump_pwr_ctrl_regs(host);
1673 			WARN_ON(1);
1674 			break;
1675 		}
1676 		msm_host_writel(msm_host, irq_status, host,
1677 			msm_offset->core_pwrctl_clear);
1678 		retry--;
1679 		udelay(10);
1680 	}
1681 
1682 	/* Handle BUS ON/OFF*/
1683 	if (irq_status & CORE_PWRCTL_BUS_ON) {
1684 		pwr_state = REQ_BUS_ON;
1685 		io_level = REQ_IO_HIGH;
1686 	}
1687 	if (irq_status & CORE_PWRCTL_BUS_OFF) {
1688 		pwr_state = REQ_BUS_OFF;
1689 		io_level = REQ_IO_LOW;
1690 	}
1691 
1692 	if (pwr_state) {
1693 		ret = sdhci_msm_set_vmmc(msm_host, mmc,
1694 					 pwr_state & REQ_BUS_ON);
1695 		if (!ret)
1696 			ret = sdhci_msm_set_vqmmc(msm_host, mmc,
1697 					pwr_state & REQ_BUS_ON);
1698 		if (!ret)
1699 			ret = sdhci_msm_set_pincfg(msm_host,
1700 					pwr_state & REQ_BUS_ON);
1701 		if (!ret)
1702 			irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1703 		else
1704 			irq_ack |= CORE_PWRCTL_BUS_FAIL;
1705 	}
1706 
1707 	/* Handle IO LOW/HIGH */
1708 	if (irq_status & CORE_PWRCTL_IO_LOW)
1709 		io_level = REQ_IO_LOW;
1710 
1711 	if (irq_status & CORE_PWRCTL_IO_HIGH)
1712 		io_level = REQ_IO_HIGH;
1713 
1714 	if (io_level)
1715 		irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1716 
1717 	if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) {
1718 		ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
1719 		if (ret < 0) {
1720 			dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",
1721 					mmc_hostname(mmc), ret,
1722 					mmc->ios.signal_voltage, mmc->ios.vdd,
1723 					irq_status);
1724 			irq_ack |= CORE_PWRCTL_IO_FAIL;
1725 		}
1726 	}
1727 
1728 	/*
1729 	 * The driver has to acknowledge the interrupt, switch voltages and
1730 	 * report back if it succeded or not to this register. The voltage
1731 	 * switches are handled by the sdhci core, so just report success.
1732 	 */
1733 	msm_host_writel(msm_host, irq_ack, host,
1734 			msm_offset->core_pwrctl_ctl);
1735 
1736 	/*
1737 	 * If we don't have info regarding the voltage levels supported by
1738 	 * regulators, don't change the IO PAD PWR SWITCH.
1739 	 */
1740 	if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1741 		u32 new_config;
1742 		/*
1743 		 * We should unset IO PAD PWR switch only if the register write
1744 		 * can set IO lines high and the regulator also switches to 3 V.
1745 		 * Else, we should keep the IO PAD PWR switch set.
1746 		 * This is applicable to certain targets where eMMC vccq supply
1747 		 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1748 		 * IO PAD PWR switch must be kept set to reflect actual
1749 		 * regulator voltage. This way, during initialization of
1750 		 * controllers with only 1.8V, we will set the IO PAD bit
1751 		 * without waiting for a REQ_IO_LOW.
1752 		 */
1753 		config = readl_relaxed(host->ioaddr +
1754 				msm_offset->core_vendor_spec);
1755 		new_config = config;
1756 
1757 		if ((io_level & REQ_IO_HIGH) &&
1758 				(msm_host->caps_0 & CORE_3_0V_SUPPORT))
1759 			new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1760 		else if ((io_level & REQ_IO_LOW) ||
1761 				(msm_host->caps_0 & CORE_1_8V_SUPPORT))
1762 			new_config |= CORE_IO_PAD_PWR_SWITCH;
1763 
1764 		if (config ^ new_config)
1765 			writel_relaxed(new_config, host->ioaddr +
1766 					msm_offset->core_vendor_spec);
1767 	}
1768 
1769 	if (pwr_state)
1770 		msm_host->curr_pwr_state = pwr_state;
1771 	if (io_level)
1772 		msm_host->curr_io_level = io_level;
1773 
1774 	dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1775 		mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1776 		irq_ack);
1777 }
1778 
sdhci_msm_pwr_irq(int irq,void * data)1779 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1780 {
1781 	struct sdhci_host *host = (struct sdhci_host *)data;
1782 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1783 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1784 
1785 	sdhci_msm_handle_pwr_irq(host, irq);
1786 	msm_host->pwr_irq_flag = 1;
1787 	sdhci_msm_complete_pwr_irq_wait(msm_host);
1788 
1789 
1790 	return IRQ_HANDLED;
1791 }
1792 
sdhci_msm_get_max_clock(struct sdhci_host * host)1793 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1794 {
1795 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1796 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1797 	struct clk *core_clk = msm_host->bulk_clks[0].clk;
1798 
1799 	return clk_round_rate(core_clk, ULONG_MAX);
1800 }
1801 
sdhci_msm_get_min_clock(struct sdhci_host * host)1802 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1803 {
1804 	return SDHCI_MSM_MIN_CLOCK;
1805 }
1806 
1807 /*
1808  * __sdhci_msm_set_clock - sdhci_msm clock control.
1809  *
1810  * Description:
1811  * MSM controller does not use internal divider and
1812  * instead directly control the GCC clock as per
1813  * HW recommendation.
1814  **/
__sdhci_msm_set_clock(struct sdhci_host * host,unsigned int clock)1815 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1816 {
1817 	u16 clk;
1818 
1819 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1820 
1821 	if (clock == 0)
1822 		return;
1823 
1824 	/*
1825 	 * MSM controller do not use clock divider.
1826 	 * Thus read SDHCI_CLOCK_CONTROL and only enable
1827 	 * clock with no divider value programmed.
1828 	 */
1829 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1830 	sdhci_enable_clk(host, clk);
1831 }
1832 
1833 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
sdhci_msm_set_clock(struct sdhci_host * host,unsigned int clock)1834 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1835 {
1836 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1837 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1838 
1839 	if (!clock) {
1840 		host->mmc->actual_clock = msm_host->clk_rate = 0;
1841 		goto out;
1842 	}
1843 
1844 	sdhci_msm_hc_select_mode(host);
1845 
1846 	msm_set_clock_rate_for_bus_mode(host, clock);
1847 out:
1848 	__sdhci_msm_set_clock(host, clock);
1849 }
1850 
1851 /*****************************************************************************\
1852  *                                                                           *
1853  * Inline Crypto Engine (ICE) support                                        *
1854  *                                                                           *
1855 \*****************************************************************************/
1856 
1857 #ifdef CONFIG_MMC_CRYPTO
1858 
sdhci_msm_ice_init(struct sdhci_msm_host * msm_host,struct cqhci_host * cq_host)1859 static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1860 			      struct cqhci_host *cq_host)
1861 {
1862 	struct mmc_host *mmc = msm_host->mmc;
1863 	struct device *dev = mmc_dev(mmc);
1864 	struct qcom_ice *ice;
1865 
1866 	if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
1867 		return 0;
1868 
1869 	ice = of_qcom_ice_get(dev);
1870 	if (ice == ERR_PTR(-EOPNOTSUPP)) {
1871 		dev_warn(dev, "Disabling inline encryption support\n");
1872 		ice = NULL;
1873 	}
1874 
1875 	if (IS_ERR_OR_NULL(ice))
1876 		return PTR_ERR_OR_ZERO(ice);
1877 
1878 	msm_host->ice = ice;
1879 	mmc->caps2 |= MMC_CAP2_CRYPTO;
1880 
1881 	return 0;
1882 }
1883 
sdhci_msm_ice_enable(struct sdhci_msm_host * msm_host)1884 static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
1885 {
1886 	if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1887 		qcom_ice_enable(msm_host->ice);
1888 }
1889 
sdhci_msm_ice_resume(struct sdhci_msm_host * msm_host)1890 static __maybe_unused int sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
1891 {
1892 	if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1893 		return qcom_ice_resume(msm_host->ice);
1894 
1895 	return 0;
1896 }
1897 
sdhci_msm_ice_suspend(struct sdhci_msm_host * msm_host)1898 static __maybe_unused int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
1899 {
1900 	if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1901 		return qcom_ice_suspend(msm_host->ice);
1902 
1903 	return 0;
1904 }
1905 
1906 /*
1907  * Program a key into a QC ICE keyslot, or evict a keyslot.  QC ICE requires
1908  * vendor-specific SCM calls for this; it doesn't support the standard way.
1909  */
sdhci_msm_program_key(struct cqhci_host * cq_host,const union cqhci_crypto_cfg_entry * cfg,int slot)1910 static int sdhci_msm_program_key(struct cqhci_host *cq_host,
1911 				 const union cqhci_crypto_cfg_entry *cfg,
1912 				 int slot)
1913 {
1914 	struct sdhci_host *host = mmc_priv(cq_host->mmc);
1915 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1916 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1917 	union cqhci_crypto_cap_entry cap;
1918 
1919 	if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE))
1920 		return qcom_ice_evict_key(msm_host->ice, slot);
1921 
1922 	/* Only AES-256-XTS has been tested so far. */
1923 	cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
1924 	if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
1925 		cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256)
1926 		return -EINVAL;
1927 
1928 	return qcom_ice_program_key(msm_host->ice,
1929 				    QCOM_ICE_CRYPTO_ALG_AES_XTS,
1930 				    QCOM_ICE_CRYPTO_KEY_SIZE_256,
1931 				    cfg->crypto_key,
1932 				    cfg->data_unit_size, slot);
1933 }
1934 
1935 #else /* CONFIG_MMC_CRYPTO */
1936 
sdhci_msm_ice_init(struct sdhci_msm_host * msm_host,struct cqhci_host * cq_host)1937 static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1938 				     struct cqhci_host *cq_host)
1939 {
1940 	return 0;
1941 }
1942 
sdhci_msm_ice_enable(struct sdhci_msm_host * msm_host)1943 static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
1944 {
1945 }
1946 
1947 static inline __maybe_unused int
sdhci_msm_ice_resume(struct sdhci_msm_host * msm_host)1948 sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
1949 {
1950 	return 0;
1951 }
1952 
1953 static inline __maybe_unused int
sdhci_msm_ice_suspend(struct sdhci_msm_host * msm_host)1954 sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
1955 {
1956 	return 0;
1957 }
1958 #endif /* !CONFIG_MMC_CRYPTO */
1959 
1960 /*****************************************************************************\
1961  *                                                                           *
1962  * MSM Command Queue Engine (CQE)                                            *
1963  *                                                                           *
1964 \*****************************************************************************/
1965 
sdhci_msm_cqe_irq(struct sdhci_host * host,u32 intmask)1966 static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
1967 {
1968 	int cmd_error = 0;
1969 	int data_error = 0;
1970 
1971 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1972 		return intmask;
1973 
1974 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1975 	return 0;
1976 }
1977 
sdhci_msm_cqe_enable(struct mmc_host * mmc)1978 static void sdhci_msm_cqe_enable(struct mmc_host *mmc)
1979 {
1980 	struct sdhci_host *host = mmc_priv(mmc);
1981 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1982 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1983 
1984 	sdhci_cqe_enable(mmc);
1985 	sdhci_msm_ice_enable(msm_host);
1986 }
1987 
sdhci_msm_cqe_disable(struct mmc_host * mmc,bool recovery)1988 static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
1989 {
1990 	struct sdhci_host *host = mmc_priv(mmc);
1991 	unsigned long flags;
1992 	u32 ctrl;
1993 
1994 	/*
1995 	 * When CQE is halted, the legacy SDHCI path operates only
1996 	 * on 16-byte descriptors in 64bit mode.
1997 	 */
1998 	if (host->flags & SDHCI_USE_64_BIT_DMA)
1999 		host->desc_sz = 16;
2000 
2001 	spin_lock_irqsave(&host->lock, flags);
2002 
2003 	/*
2004 	 * During CQE command transfers, command complete bit gets latched.
2005 	 * So s/w should clear command complete interrupt status when CQE is
2006 	 * either halted or disabled. Otherwise unexpected SDCHI legacy
2007 	 * interrupt gets triggered when CQE is halted/disabled.
2008 	 */
2009 	ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
2010 	ctrl |= SDHCI_INT_RESPONSE;
2011 	sdhci_writel(host,  ctrl, SDHCI_INT_ENABLE);
2012 	sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
2013 
2014 	spin_unlock_irqrestore(&host->lock, flags);
2015 
2016 	sdhci_cqe_disable(mmc, recovery);
2017 }
2018 
sdhci_msm_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)2019 static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
2020 {
2021 	u32 count, start = 15;
2022 
2023 	__sdhci_set_timeout(host, cmd);
2024 	count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL);
2025 	/*
2026 	 * Update software timeout value if its value is less than hardware data
2027 	 * timeout value. Qcom SoC hardware data timeout value was calculated
2028 	 * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
2029 	 */
2030 	if (cmd && cmd->data && host->clock > 400000 &&
2031 	    host->clock <= 50000000 &&
2032 	    ((1 << (count + start)) > (10 * host->clock)))
2033 		host->data_timeout = 22LL * NSEC_PER_SEC;
2034 }
2035 
2036 static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
2037 	.enable		= sdhci_msm_cqe_enable,
2038 	.disable	= sdhci_msm_cqe_disable,
2039 #ifdef CONFIG_MMC_CRYPTO
2040 	.program_key	= sdhci_msm_program_key,
2041 #endif
2042 };
2043 
sdhci_msm_cqe_add_host(struct sdhci_host * host,struct platform_device * pdev)2044 static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
2045 				struct platform_device *pdev)
2046 {
2047 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2048 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2049 	struct cqhci_host *cq_host;
2050 	bool dma64;
2051 	u32 cqcfg;
2052 	int ret;
2053 
2054 	/*
2055 	 * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
2056 	 * So ensure ADMA table is allocated for 16byte descriptors.
2057 	 */
2058 	if (host->caps & SDHCI_CAN_64BIT)
2059 		host->alloc_desc_sz = 16;
2060 
2061 	ret = sdhci_setup_host(host);
2062 	if (ret)
2063 		return ret;
2064 
2065 	cq_host = cqhci_pltfm_init(pdev);
2066 	if (IS_ERR(cq_host)) {
2067 		ret = PTR_ERR(cq_host);
2068 		dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
2069 		goto cleanup;
2070 	}
2071 
2072 	msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2073 	cq_host->ops = &sdhci_msm_cqhci_ops;
2074 
2075 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
2076 
2077 	ret = sdhci_msm_ice_init(msm_host, cq_host);
2078 	if (ret)
2079 		goto cleanup;
2080 
2081 	ret = cqhci_init(cq_host, host->mmc, dma64);
2082 	if (ret) {
2083 		dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
2084 				mmc_hostname(host->mmc), ret);
2085 		goto cleanup;
2086 	}
2087 
2088 	/* Disable cqe reset due to cqe enable signal */
2089 	cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
2090 	cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
2091 	cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
2092 
2093 	/*
2094 	 * SDHC expects 12byte ADMA descriptors till CQE is enabled.
2095 	 * So limit desc_sz to 12 so that the data commands that are sent
2096 	 * during card initialization (before CQE gets enabled) would
2097 	 * get executed without any issues.
2098 	 */
2099 	if (host->flags & SDHCI_USE_64_BIT_DMA)
2100 		host->desc_sz = 12;
2101 
2102 	ret = __sdhci_add_host(host);
2103 	if (ret)
2104 		goto cleanup;
2105 
2106 	dev_info(&pdev->dev, "%s: CQE init: success\n",
2107 			mmc_hostname(host->mmc));
2108 	return ret;
2109 
2110 cleanup:
2111 	sdhci_cleanup_host(host);
2112 	return ret;
2113 }
2114 
2115 /*
2116  * Platform specific register write functions. This is so that, if any
2117  * register write needs to be followed up by platform specific actions,
2118  * they can be added here. These functions can go to sleep when writes
2119  * to certain registers are done.
2120  * These functions are relying on sdhci_set_ios not using spinlock.
2121  */
__sdhci_msm_check_write(struct sdhci_host * host,u16 val,int reg)2122 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
2123 {
2124 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2125 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2126 	u32 req_type = 0;
2127 
2128 	switch (reg) {
2129 	case SDHCI_HOST_CONTROL2:
2130 		req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
2131 			REQ_IO_HIGH;
2132 		break;
2133 	case SDHCI_SOFTWARE_RESET:
2134 		if (host->pwr && (val & SDHCI_RESET_ALL))
2135 			req_type = REQ_BUS_OFF;
2136 		break;
2137 	case SDHCI_POWER_CONTROL:
2138 		req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
2139 		break;
2140 	case SDHCI_TRANSFER_MODE:
2141 		msm_host->transfer_mode = val;
2142 		break;
2143 	case SDHCI_COMMAND:
2144 		if (!msm_host->use_cdr)
2145 			break;
2146 		if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
2147 		    !mmc_op_tuning(SDHCI_GET_CMD(val)))
2148 			sdhci_msm_set_cdr(host, true);
2149 		else
2150 			sdhci_msm_set_cdr(host, false);
2151 		break;
2152 	}
2153 
2154 	if (req_type) {
2155 		msm_host->pwr_irq_flag = 0;
2156 		/*
2157 		 * Since this register write may trigger a power irq, ensure
2158 		 * all previous register writes are complete by this point.
2159 		 */
2160 		mb();
2161 	}
2162 	return req_type;
2163 }
2164 
2165 /* This function may sleep*/
sdhci_msm_writew(struct sdhci_host * host,u16 val,int reg)2166 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
2167 {
2168 	u32 req_type = 0;
2169 
2170 	req_type = __sdhci_msm_check_write(host, val, reg);
2171 	writew_relaxed(val, host->ioaddr + reg);
2172 
2173 	if (req_type)
2174 		sdhci_msm_check_power_status(host, req_type);
2175 }
2176 
2177 /* This function may sleep*/
sdhci_msm_writeb(struct sdhci_host * host,u8 val,int reg)2178 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
2179 {
2180 	u32 req_type = 0;
2181 
2182 	req_type = __sdhci_msm_check_write(host, val, reg);
2183 
2184 	writeb_relaxed(val, host->ioaddr + reg);
2185 
2186 	if (req_type)
2187 		sdhci_msm_check_power_status(host, req_type);
2188 }
2189 
sdhci_msm_set_regulator_caps(struct sdhci_msm_host * msm_host)2190 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
2191 {
2192 	struct mmc_host *mmc = msm_host->mmc;
2193 	struct regulator *supply = mmc->supply.vqmmc;
2194 	u32 caps = 0, config;
2195 	struct sdhci_host *host = mmc_priv(mmc);
2196 	const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2197 
2198 	if (!IS_ERR(mmc->supply.vqmmc)) {
2199 		if (regulator_is_supported_voltage(supply, 1700000, 1950000))
2200 			caps |= CORE_1_8V_SUPPORT;
2201 		if (regulator_is_supported_voltage(supply, 2700000, 3600000))
2202 			caps |= CORE_3_0V_SUPPORT;
2203 
2204 		if (!caps)
2205 			pr_warn("%s: 1.8/3V not supported for vqmmc\n",
2206 					mmc_hostname(mmc));
2207 	}
2208 
2209 	if (caps) {
2210 		/*
2211 		 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
2212 		 * bit can be used as required later on.
2213 		 */
2214 		u32 io_level = msm_host->curr_io_level;
2215 
2216 		config = readl_relaxed(host->ioaddr +
2217 				msm_offset->core_vendor_spec);
2218 		config |= CORE_IO_PAD_PWR_SWITCH_EN;
2219 
2220 		if ((io_level & REQ_IO_HIGH) && (caps &	CORE_3_0V_SUPPORT))
2221 			config &= ~CORE_IO_PAD_PWR_SWITCH;
2222 		else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
2223 			config |= CORE_IO_PAD_PWR_SWITCH;
2224 
2225 		writel_relaxed(config,
2226 				host->ioaddr + msm_offset->core_vendor_spec);
2227 	}
2228 	msm_host->caps_0 |= caps;
2229 	pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
2230 }
2231 
sdhci_msm_register_vreg(struct sdhci_msm_host * msm_host)2232 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
2233 {
2234 	int ret;
2235 
2236 	ret = mmc_regulator_get_supply(msm_host->mmc);
2237 	if (ret)
2238 		return ret;
2239 
2240 	sdhci_msm_set_regulator_caps(msm_host);
2241 
2242 	return 0;
2243 }
2244 
sdhci_msm_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)2245 static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc,
2246 				      struct mmc_ios *ios)
2247 {
2248 	struct sdhci_host *host = mmc_priv(mmc);
2249 	u16 ctrl, status;
2250 
2251 	/*
2252 	 * Signal Voltage Switching is only applicable for Host Controllers
2253 	 * v3.00 and above.
2254 	 */
2255 	if (host->version < SDHCI_SPEC_300)
2256 		return 0;
2257 
2258 	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2259 
2260 	switch (ios->signal_voltage) {
2261 	case MMC_SIGNAL_VOLTAGE_330:
2262 		if (!(host->flags & SDHCI_SIGNALING_330))
2263 			return -EINVAL;
2264 
2265 		/* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2266 		ctrl &= ~SDHCI_CTRL_VDD_180;
2267 		break;
2268 	case MMC_SIGNAL_VOLTAGE_180:
2269 		if (!(host->flags & SDHCI_SIGNALING_180))
2270 			return -EINVAL;
2271 
2272 		/* Enable 1.8V Signal Enable in the Host Control2 register */
2273 		ctrl |= SDHCI_CTRL_VDD_180;
2274 		break;
2275 
2276 	default:
2277 		return -EINVAL;
2278 	}
2279 
2280 	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2281 
2282 	/* Wait for 5ms */
2283 	usleep_range(5000, 5500);
2284 
2285 	/* regulator output should be stable within 5 ms */
2286 	status = ctrl & SDHCI_CTRL_VDD_180;
2287 	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2288 	if ((ctrl & SDHCI_CTRL_VDD_180) == status)
2289 		return 0;
2290 
2291 	dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n",
2292 		mmc_hostname(mmc));
2293 
2294 	return -EAGAIN;
2295 }
2296 
2297 #define DRIVER_NAME "sdhci_msm"
2298 #define SDHCI_MSM_DUMP(f, x...) \
2299 	pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2300 
sdhci_msm_dump_vendor_regs(struct sdhci_host * host)2301 static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
2302 {
2303 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2304 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2305 	const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2306 
2307 	SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
2308 
2309 	SDHCI_MSM_DUMP(
2310 			"DLL sts: 0x%08x | DLL cfg:  0x%08x | DLL cfg2: 0x%08x\n",
2311 		readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
2312 		readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
2313 		readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
2314 	SDHCI_MSM_DUMP(
2315 			"DLL cfg3: 0x%08x | DLL usr ctl:  0x%08x | DDR cfg: 0x%08x\n",
2316 		readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
2317 		readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
2318 		readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
2319 	SDHCI_MSM_DUMP(
2320 			"Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
2321 		readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
2322 		readl_relaxed(host->ioaddr +
2323 			msm_offset->core_vendor_spec_func2),
2324 		readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
2325 }
2326 
2327 static const struct sdhci_msm_variant_ops mci_var_ops = {
2328 	.msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
2329 	.msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
2330 };
2331 
2332 static const struct sdhci_msm_variant_ops v5_var_ops = {
2333 	.msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
2334 	.msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
2335 };
2336 
2337 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
2338 	.var_ops = &mci_var_ops,
2339 	.offset = &sdhci_msm_mci_offset,
2340 };
2341 
2342 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
2343 	.mci_removed = true,
2344 	.var_ops = &v5_var_ops,
2345 	.offset = &sdhci_msm_v5_offset,
2346 };
2347 
2348 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
2349 	.mci_removed = true,
2350 	.restore_dll_config = true,
2351 	.var_ops = &v5_var_ops,
2352 	.offset = &sdhci_msm_v5_offset,
2353 };
2354 
2355 static const struct of_device_id sdhci_msm_dt_match[] = {
2356 	/*
2357 	 * Do not add new variants to the driver which are compatible with
2358 	 * generic ones, unless they need customization.
2359 	 */
2360 	{.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2361 	{.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2362 	{.compatible = "qcom,sdm670-sdhci", .data = &sdm845_sdhci_var},
2363 	{.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2364 	{.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2365 	{},
2366 };
2367 
2368 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
2369 
2370 static const struct sdhci_ops sdhci_msm_ops = {
2371 	.reset = sdhci_and_cqhci_reset,
2372 	.set_clock = sdhci_msm_set_clock,
2373 	.get_min_clock = sdhci_msm_get_min_clock,
2374 	.get_max_clock = sdhci_msm_get_max_clock,
2375 	.set_bus_width = sdhci_set_bus_width,
2376 	.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
2377 	.write_w = sdhci_msm_writew,
2378 	.write_b = sdhci_msm_writeb,
2379 	.irq	= sdhci_msm_cqe_irq,
2380 	.dump_vendor_regs = sdhci_msm_dump_vendor_regs,
2381 	.set_power = sdhci_set_power_noreg,
2382 	.set_timeout = sdhci_msm_set_timeout,
2383 };
2384 
2385 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
2386 	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
2387 		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
2388 		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
2389 		  SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
2390 
2391 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
2392 	.ops = &sdhci_msm_ops,
2393 };
2394 
sdhci_msm_get_of_property(struct platform_device * pdev,struct sdhci_host * host)2395 static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
2396 		struct sdhci_host *host)
2397 {
2398 	struct device_node *node = pdev->dev.of_node;
2399 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2400 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2401 
2402 	if (of_property_read_u32(node, "qcom,ddr-config",
2403 				&msm_host->ddr_config))
2404 		msm_host->ddr_config = DDR_CONFIG_POR_VAL;
2405 
2406 	of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2407 
2408 	if (of_device_is_compatible(node, "qcom,msm8916-sdhci"))
2409 		host->quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA;
2410 }
2411 
sdhci_msm_gcc_reset(struct device * dev,struct sdhci_host * host)2412 static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)
2413 {
2414 	struct reset_control *reset;
2415 	int ret = 0;
2416 
2417 	reset = reset_control_get_optional_exclusive(dev, NULL);
2418 	if (IS_ERR(reset))
2419 		return dev_err_probe(dev, PTR_ERR(reset),
2420 				"unable to acquire core_reset\n");
2421 
2422 	if (!reset)
2423 		return ret;
2424 
2425 	ret = reset_control_assert(reset);
2426 	if (ret) {
2427 		reset_control_put(reset);
2428 		return dev_err_probe(dev, ret, "core_reset assert failed\n");
2429 	}
2430 
2431 	/*
2432 	 * The hardware requirement for delay between assert/deassert
2433 	 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
2434 	 * ~125us (4/32768). To be on the safe side add 200us delay.
2435 	 */
2436 	usleep_range(200, 210);
2437 
2438 	ret = reset_control_deassert(reset);
2439 	if (ret) {
2440 		reset_control_put(reset);
2441 		return dev_err_probe(dev, ret, "core_reset deassert failed\n");
2442 	}
2443 
2444 	usleep_range(200, 210);
2445 	reset_control_put(reset);
2446 
2447 	return ret;
2448 }
2449 
sdhci_msm_probe(struct platform_device * pdev)2450 static int sdhci_msm_probe(struct platform_device *pdev)
2451 {
2452 	struct sdhci_host *host;
2453 	struct sdhci_pltfm_host *pltfm_host;
2454 	struct sdhci_msm_host *msm_host;
2455 	struct clk *clk;
2456 	int ret;
2457 	u16 host_version, core_minor;
2458 	u32 core_version, config;
2459 	u8 core_major;
2460 	const struct sdhci_msm_offset *msm_offset;
2461 	const struct sdhci_msm_variant_info *var_info;
2462 	struct device_node *node = pdev->dev.of_node;
2463 
2464 	host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
2465 	if (IS_ERR(host))
2466 		return PTR_ERR(host);
2467 
2468 	host->sdma_boundary = 0;
2469 	pltfm_host = sdhci_priv(host);
2470 	msm_host = sdhci_pltfm_priv(pltfm_host);
2471 	msm_host->mmc = host->mmc;
2472 	msm_host->pdev = pdev;
2473 
2474 	ret = mmc_of_parse(host->mmc);
2475 	if (ret)
2476 		goto pltfm_free;
2477 
2478 	/*
2479 	 * Based on the compatible string, load the required msm host info from
2480 	 * the data associated with the version info.
2481 	 */
2482 	var_info = of_device_get_match_data(&pdev->dev);
2483 
2484 	msm_host->mci_removed = var_info->mci_removed;
2485 	msm_host->restore_dll_config = var_info->restore_dll_config;
2486 	msm_host->var_ops = var_info->var_ops;
2487 	msm_host->offset = var_info->offset;
2488 
2489 	msm_offset = msm_host->offset;
2490 
2491 	sdhci_get_of_property(pdev);
2492 	sdhci_msm_get_of_property(pdev, host);
2493 
2494 	msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2495 
2496 	ret = sdhci_msm_gcc_reset(&pdev->dev, host);
2497 	if (ret)
2498 		goto pltfm_free;
2499 
2500 	/* Setup SDCC bus voter clock. */
2501 	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
2502 	if (!IS_ERR(msm_host->bus_clk)) {
2503 		/* Vote for max. clk rate for max. performance */
2504 		ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
2505 		if (ret)
2506 			goto pltfm_free;
2507 		ret = clk_prepare_enable(msm_host->bus_clk);
2508 		if (ret)
2509 			goto pltfm_free;
2510 	}
2511 
2512 	/* Setup main peripheral bus clock */
2513 	clk = devm_clk_get(&pdev->dev, "iface");
2514 	if (IS_ERR(clk)) {
2515 		ret = PTR_ERR(clk);
2516 		dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
2517 		goto bus_clk_disable;
2518 	}
2519 	msm_host->bulk_clks[1].clk = clk;
2520 
2521 	/* Setup SDC MMC clock */
2522 	clk = devm_clk_get(&pdev->dev, "core");
2523 	if (IS_ERR(clk)) {
2524 		ret = PTR_ERR(clk);
2525 		dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
2526 		goto bus_clk_disable;
2527 	}
2528 	msm_host->bulk_clks[0].clk = clk;
2529 
2530 	 /* Check for optional interconnect paths */
2531 	ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL);
2532 	if (ret)
2533 		goto bus_clk_disable;
2534 
2535 	ret = devm_pm_opp_set_clkname(&pdev->dev, "core");
2536 	if (ret)
2537 		goto bus_clk_disable;
2538 
2539 	/* OPP table is optional */
2540 	ret = devm_pm_opp_of_add_table(&pdev->dev);
2541 	if (ret && ret != -ENODEV) {
2542 		dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
2543 		goto bus_clk_disable;
2544 	}
2545 
2546 	/* Vote for maximum clock rate for maximum performance */
2547 	ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX);
2548 	if (ret)
2549 		dev_warn(&pdev->dev, "core clock boost failed\n");
2550 
2551 	clk = devm_clk_get(&pdev->dev, "cal");
2552 	if (IS_ERR(clk))
2553 		clk = NULL;
2554 	msm_host->bulk_clks[2].clk = clk;
2555 
2556 	clk = devm_clk_get(&pdev->dev, "sleep");
2557 	if (IS_ERR(clk))
2558 		clk = NULL;
2559 	msm_host->bulk_clks[3].clk = clk;
2560 
2561 	ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2562 				      msm_host->bulk_clks);
2563 	if (ret)
2564 		goto bus_clk_disable;
2565 
2566 	/*
2567 	 * xo clock is needed for FLL feature of cm_dll.
2568 	 * In case if xo clock is not mentioned in DT, warn and proceed.
2569 	 */
2570 	msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
2571 	if (IS_ERR(msm_host->xo_clk)) {
2572 		ret = PTR_ERR(msm_host->xo_clk);
2573 		dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
2574 	}
2575 
2576 	if (!msm_host->mci_removed) {
2577 		msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
2578 		if (IS_ERR(msm_host->core_mem)) {
2579 			ret = PTR_ERR(msm_host->core_mem);
2580 			goto clk_disable;
2581 		}
2582 	}
2583 
2584 	/* Reset the vendor spec register to power on reset state */
2585 	writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
2586 			host->ioaddr + msm_offset->core_vendor_spec);
2587 
2588 	if (!msm_host->mci_removed) {
2589 		/* Set HC_MODE_EN bit in HC_MODE register */
2590 		msm_host_writel(msm_host, HC_MODE_EN, host,
2591 				msm_offset->core_hc_mode);
2592 		config = msm_host_readl(msm_host, host,
2593 				msm_offset->core_hc_mode);
2594 		config |= FF_CLK_SW_RST_DIS;
2595 		msm_host_writel(msm_host, config, host,
2596 				msm_offset->core_hc_mode);
2597 	}
2598 
2599 	host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
2600 	dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
2601 		host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
2602 			       SDHCI_VENDOR_VER_SHIFT));
2603 
2604 	core_version = msm_host_readl(msm_host, host,
2605 			msm_offset->core_mci_version);
2606 	core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
2607 		      CORE_VERSION_MAJOR_SHIFT;
2608 	core_minor = core_version & CORE_VERSION_MINOR_MASK;
2609 	dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
2610 		core_version, core_major, core_minor);
2611 
2612 	if (core_major == 1 && core_minor >= 0x42)
2613 		msm_host->use_14lpp_dll_reset = true;
2614 
2615 	/*
2616 	 * SDCC 5 controller with major version 1, minor version 0x34 and later
2617 	 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
2618 	 */
2619 	if (core_major == 1 && core_minor < 0x34)
2620 		msm_host->use_cdclp533 = true;
2621 
2622 	/*
2623 	 * Support for some capabilities is not advertised by newer
2624 	 * controller versions and must be explicitly enabled.
2625 	 */
2626 	if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
2627 		config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
2628 		config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
2629 		writel_relaxed(config, host->ioaddr +
2630 				msm_offset->core_vendor_spec_capabilities0);
2631 	}
2632 
2633 	if (core_major == 1 && core_minor >= 0x49)
2634 		msm_host->updated_ddr_cfg = true;
2635 
2636 	if (core_major == 1 && core_minor >= 0x71)
2637 		msm_host->uses_tassadar_dll = true;
2638 
2639 	ret = sdhci_msm_register_vreg(msm_host);
2640 	if (ret)
2641 		goto clk_disable;
2642 
2643 	/*
2644 	 * Power on reset state may trigger power irq if previous status of
2645 	 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
2646 	 * interrupt in GIC, any pending power irq interrupt should be
2647 	 * acknowledged. Otherwise power irq interrupt handler would be
2648 	 * fired prematurely.
2649 	 */
2650 	sdhci_msm_handle_pwr_irq(host, 0);
2651 
2652 	/*
2653 	 * Ensure that above writes are propogated before interrupt enablement
2654 	 * in GIC.
2655 	 */
2656 	mb();
2657 
2658 	/* Setup IRQ for handling power/voltage tasks with PMIC */
2659 	msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2660 	if (msm_host->pwr_irq < 0) {
2661 		ret = msm_host->pwr_irq;
2662 		goto clk_disable;
2663 	}
2664 
2665 	sdhci_msm_init_pwr_irq_wait(msm_host);
2666 	/* Enable pwr irq interrupts */
2667 	msm_host_writel(msm_host, INT_MASK, host,
2668 		msm_offset->core_pwrctl_mask);
2669 
2670 	ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2671 					sdhci_msm_pwr_irq, IRQF_ONESHOT,
2672 					dev_name(&pdev->dev), host);
2673 	if (ret) {
2674 		dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
2675 		goto clk_disable;
2676 	}
2677 
2678 	msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
2679 
2680 	/* Set the timeout value to max possible */
2681 	host->max_timeout_count = 0xF;
2682 
2683 	pm_runtime_get_noresume(&pdev->dev);
2684 	pm_runtime_set_active(&pdev->dev);
2685 	pm_runtime_enable(&pdev->dev);
2686 	pm_runtime_set_autosuspend_delay(&pdev->dev,
2687 					 MSM_MMC_AUTOSUSPEND_DELAY_MS);
2688 	pm_runtime_use_autosuspend(&pdev->dev);
2689 
2690 	host->mmc_host_ops.start_signal_voltage_switch =
2691 		sdhci_msm_start_signal_voltage_switch;
2692 	host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
2693 	if (of_property_read_bool(node, "supports-cqe"))
2694 		ret = sdhci_msm_cqe_add_host(host, pdev);
2695 	else
2696 		ret = sdhci_add_host(host);
2697 	if (ret)
2698 		goto pm_runtime_disable;
2699 
2700 	pm_runtime_mark_last_busy(&pdev->dev);
2701 	pm_runtime_put_autosuspend(&pdev->dev);
2702 
2703 	return 0;
2704 
2705 pm_runtime_disable:
2706 	pm_runtime_disable(&pdev->dev);
2707 	pm_runtime_set_suspended(&pdev->dev);
2708 	pm_runtime_put_noidle(&pdev->dev);
2709 clk_disable:
2710 	clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2711 				   msm_host->bulk_clks);
2712 bus_clk_disable:
2713 	if (!IS_ERR(msm_host->bus_clk))
2714 		clk_disable_unprepare(msm_host->bus_clk);
2715 pltfm_free:
2716 	sdhci_pltfm_free(pdev);
2717 	return ret;
2718 }
2719 
sdhci_msm_remove(struct platform_device * pdev)2720 static void sdhci_msm_remove(struct platform_device *pdev)
2721 {
2722 	struct sdhci_host *host = platform_get_drvdata(pdev);
2723 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2724 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2725 	int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
2726 		    0xffffffff);
2727 
2728 	sdhci_remove_host(host, dead);
2729 
2730 	pm_runtime_get_sync(&pdev->dev);
2731 	pm_runtime_disable(&pdev->dev);
2732 	pm_runtime_put_noidle(&pdev->dev);
2733 
2734 	clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2735 				   msm_host->bulk_clks);
2736 	if (!IS_ERR(msm_host->bus_clk))
2737 		clk_disable_unprepare(msm_host->bus_clk);
2738 	sdhci_pltfm_free(pdev);
2739 }
2740 
sdhci_msm_runtime_suspend(struct device * dev)2741 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
2742 {
2743 	struct sdhci_host *host = dev_get_drvdata(dev);
2744 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2745 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2746 	unsigned long flags;
2747 
2748 	spin_lock_irqsave(&host->lock, flags);
2749 	host->runtime_suspended = true;
2750 	spin_unlock_irqrestore(&host->lock, flags);
2751 
2752 	/* Drop the performance vote */
2753 	dev_pm_opp_set_rate(dev, 0);
2754 	clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2755 				   msm_host->bulk_clks);
2756 
2757 	return sdhci_msm_ice_suspend(msm_host);
2758 }
2759 
sdhci_msm_runtime_resume(struct device * dev)2760 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2761 {
2762 	struct sdhci_host *host = dev_get_drvdata(dev);
2763 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2764 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2765 	unsigned long flags;
2766 	int ret;
2767 
2768 	ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2769 				       msm_host->bulk_clks);
2770 	if (ret)
2771 		return ret;
2772 	/*
2773 	 * Whenever core-clock is gated dynamically, it's needed to
2774 	 * restore the SDR DLL settings when the clock is ungated.
2775 	 */
2776 	if (msm_host->restore_dll_config && msm_host->clk_rate) {
2777 		ret = sdhci_msm_restore_sdr_dll_config(host);
2778 		if (ret)
2779 			return ret;
2780 	}
2781 
2782 	dev_pm_opp_set_rate(dev, msm_host->clk_rate);
2783 
2784 	ret = sdhci_msm_ice_resume(msm_host);
2785 	if (ret)
2786 		return ret;
2787 
2788 	spin_lock_irqsave(&host->lock, flags);
2789 	host->runtime_suspended = false;
2790 	spin_unlock_irqrestore(&host->lock, flags);
2791 
2792 	return ret;
2793 }
2794 
2795 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2796 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2797 				pm_runtime_force_resume)
2798 	SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2799 			   sdhci_msm_runtime_resume,
2800 			   NULL)
2801 };
2802 
2803 static struct platform_driver sdhci_msm_driver = {
2804 	.probe = sdhci_msm_probe,
2805 	.remove_new = sdhci_msm_remove,
2806 	.driver = {
2807 		   .name = "sdhci_msm",
2808 		   .of_match_table = sdhci_msm_dt_match,
2809 		   .pm = &sdhci_msm_pm_ops,
2810 		   .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2811 	},
2812 };
2813 
2814 module_platform_driver(sdhci_msm_driver);
2815 
2816 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2817 MODULE_LICENSE("GPL v2");
2818