1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef RVU_H
9 #define RVU_H
10
11 #include <linux/pci.h>
12 #include <net/devlink.h>
13
14 #include "rvu_struct.h"
15 #include "rvu_devlink.h"
16 #include "common.h"
17 #include "mbox.h"
18 #include "npc.h"
19 #include "rvu_reg.h"
20 #include "ptp.h"
21
22 /* PCI device IDs */
23 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
24 #define PCI_DEVID_OCTEONTX2_LBK 0xA061
25
26 /* Subsystem Device ID */
27 #define PCI_SUBSYS_DEVID_98XX 0xB100
28 #define PCI_SUBSYS_DEVID_96XX 0xB200
29 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900
30 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00
31 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00
32 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00
33 #define PCI_SUBSYS_DEVID_CN20KA 0xC220
34 #define PCI_SUBSYS_DEVID_CNF20KA 0xC320
35
36 /* PCI BAR nos */
37 #define PCI_AF_REG_BAR_NUM 0
38 #define PCI_PF_REG_BAR_NUM 2
39 #define PCI_MBOX_BAR_NUM 4
40
41 #define NAME_SIZE 32
42 #define MAX_NIX_BLKS 2
43 #define MAX_CPT_BLKS 2
44
45 /* PF_FUNC */
46 #define RVU_PFVF_PF_SHIFT 10
47 #define RVU_PFVF_PF_MASK 0x3F
48 #define RVU_PFVF_FUNC_SHIFT 0
49 #define RVU_PFVF_FUNC_MASK 0x3FF
50
51 #ifdef CONFIG_DEBUG_FS
52 struct dump_ctx {
53 int lf;
54 int id;
55 bool all;
56 };
57
58 struct cpt_ctx {
59 int blkaddr;
60 struct rvu *rvu;
61 };
62
63 struct rvu_debugfs {
64 struct dentry *root;
65 struct dentry *cgx_root;
66 struct dentry *cgx;
67 struct dentry *lmac;
68 struct dentry *npa;
69 struct dentry *nix;
70 struct dentry *npc;
71 struct dentry *cpt;
72 struct dentry *mcs_root;
73 struct dentry *mcs;
74 struct dentry *mcs_rx;
75 struct dentry *mcs_tx;
76 struct dump_ctx npa_aura_ctx;
77 struct dump_ctx npa_pool_ctx;
78 struct dump_ctx nix_cq_ctx;
79 struct dump_ctx nix_rq_ctx;
80 struct dump_ctx nix_sq_ctx;
81 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
82 int npa_qsize_id;
83 int nix_qsize_id;
84 };
85 #endif
86
87 struct rvu_work {
88 struct work_struct work;
89 struct rvu *rvu;
90 int num_msgs;
91 int up_num_msgs;
92 };
93
94 struct rsrc_bmap {
95 unsigned long *bmap; /* Pointer to resource bitmap */
96 u16 max; /* Max resource id or count */
97 };
98
99 struct rvu_block {
100 struct rsrc_bmap lf;
101 struct admin_queue *aq; /* NIX/NPA AQ */
102 u16 *fn_map; /* LF to pcifunc mapping */
103 bool multislot;
104 bool implemented;
105 u8 addr; /* RVU_BLOCK_ADDR_E */
106 u8 type; /* RVU_BLOCK_TYPE_E */
107 u8 lfshift;
108 u64 lookup_reg;
109 u64 pf_lfcnt_reg;
110 u64 vf_lfcnt_reg;
111 u64 lfcfg_reg;
112 u64 msixcfg_reg;
113 u64 lfreset_reg;
114 unsigned char name[NAME_SIZE];
115 struct rvu *rvu;
116 u64 cpt_flt_eng_map[3];
117 u64 cpt_rcvrd_eng_map[3];
118 };
119
120 struct nix_mcast {
121 struct qmem *mce_ctx;
122 struct qmem *mcast_buf;
123 int replay_pkind;
124 int next_free_mce;
125 struct mutex mce_lock; /* Serialize MCE updates */
126 };
127
128 struct nix_mce_list {
129 struct hlist_head head;
130 int count;
131 int max;
132 };
133
134 /* layer metadata to uniquely identify a packet header field */
135 struct npc_layer_mdata {
136 u8 lid;
137 u8 ltype;
138 u8 hdr;
139 u8 key;
140 u8 len;
141 };
142
143 /* Structure to represent a field present in the
144 * generated key. A key field may present anywhere and can
145 * be of any size in the generated key. Once this structure
146 * is populated for fields of interest then field's presence
147 * and location (if present) can be known.
148 */
149 struct npc_key_field {
150 /* Masks where all set bits indicate position
151 * of a field in the key
152 */
153 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
154 /* Number of words in the key a field spans. If a field is
155 * of 16 bytes and key offset is 4 then the field will use
156 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
157 * nr_kws will be 3(KW0, KW1 and KW2).
158 */
159 int nr_kws;
160 /* used by packet header fields */
161 struct npc_layer_mdata layer_mdata;
162 };
163
164 struct npc_mcam {
165 struct rsrc_bmap counters;
166 struct mutex lock; /* MCAM entries and counters update lock */
167 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
168 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
169 u16 bmap_entries; /* Number of unreserved MCAM entries */
170 u16 bmap_fcnt; /* MCAM entries free count */
171 u16 *entry2pfvf_map;
172 u16 *entry2cntr_map;
173 u16 *cntr2pfvf_map;
174 u16 *cntr_refcnt;
175 u16 *entry2target_pffunc;
176 u8 keysize; /* MCAM keysize 112/224/448 bits */
177 u8 banks; /* Number of MCAM banks */
178 u8 banks_per_entry;/* Number of keywords in key */
179 u16 banksize; /* Number of MCAM entries in each bank */
180 u16 total_entries; /* Total number of MCAM entries */
181 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
182 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
183 u16 lprio_count;
184 u16 lprio_start;
185 u16 hprio_count;
186 u16 hprio_end;
187 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
188 /* fields present in the generated key */
189 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX];
190 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX];
191 u64 tx_features;
192 u64 rx_features;
193 struct list_head mcam_rules;
194 };
195
196 /* Structure for per RVU func info ie PF/VF */
197 struct rvu_pfvf {
198 bool npalf; /* Only one NPALF per RVU_FUNC */
199 bool nixlf; /* Only one NIXLF per RVU_FUNC */
200 u16 sso;
201 u16 ssow;
202 u16 cptlfs;
203 u16 timlfs;
204 u16 cpt1_lfs;
205 u8 cgx_lmac;
206
207 /* Block LF's MSIX vector info */
208 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
209 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
210 u16 *msix_lfmap; /* Vector to block LF mapping */
211
212 /* NPA contexts */
213 struct qmem *aura_ctx;
214 struct qmem *pool_ctx;
215 struct qmem *npa_qints_ctx;
216 unsigned long *aura_bmap;
217 unsigned long *pool_bmap;
218
219 /* NIX contexts */
220 struct qmem *rq_ctx;
221 struct qmem *sq_ctx;
222 struct qmem *cq_ctx;
223 struct qmem *rss_ctx;
224 struct qmem *cq_ints_ctx;
225 struct qmem *nix_qints_ctx;
226 unsigned long *sq_bmap;
227 unsigned long *rq_bmap;
228 unsigned long *cq_bmap;
229
230 u16 rx_chan_base;
231 u16 tx_chan_base;
232 u8 rx_chan_cnt; /* total number of RX channels */
233 u8 tx_chan_cnt; /* total number of TX channels */
234 u16 maxlen;
235 u16 minlen;
236
237 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */
238 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
239 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */
240
241 /* Broadcast/Multicast/Promisc pkt replication info */
242 u16 bcast_mce_idx;
243 u16 mcast_mce_idx;
244 u16 promisc_mce_idx;
245 struct nix_mce_list bcast_mce_list;
246 struct nix_mce_list mcast_mce_list;
247 struct nix_mce_list promisc_mce_list;
248 bool use_mce_list;
249
250 struct rvu_npc_mcam_rule *def_ucast_rule;
251
252 bool cgx_in_use; /* this PF/VF using CGX? */
253 int cgx_users; /* number of cgx users - used only by PFs */
254
255 int intf_mode;
256 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
257 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
258 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
259 u8 lbkid; /* NIX0/1 lbk link ID */
260 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
261 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
262 unsigned long flags;
263 struct sdp_node_info *sdp_info;
264 };
265
266 enum rvu_pfvf_flags {
267 NIXLF_INITIALIZED = 0,
268 PF_SET_VF_MAC,
269 PF_SET_VF_CFG,
270 PF_SET_VF_TRUSTED,
271 };
272
273 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
274
275 struct nix_txsch {
276 struct rsrc_bmap schq;
277 u8 lvl;
278 #define NIX_TXSCHQ_FREE BIT_ULL(1)
279 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
280 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
281 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
282 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
283 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
284 u32 *pfvf_map;
285 };
286
287 struct nix_mark_format {
288 u8 total;
289 u8 in_use;
290 u32 *cfg;
291 };
292
293 /* smq(flush) to tl1 cir/pir info */
294 struct nix_smq_tree_ctx {
295 u16 schq;
296 u64 cir_off;
297 u64 cir_val;
298 u64 pir_off;
299 u64 pir_val;
300 };
301
302 /* smq flush context */
303 struct nix_smq_flush_ctx {
304 int smq;
305 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT];
306 };
307
308 struct npc_pkind {
309 struct rsrc_bmap rsrc;
310 u32 *pfchan_map;
311 };
312
313 struct nix_flowkey {
314 #define NIX_FLOW_KEY_ALG_MAX 32
315 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
316 int in_use;
317 };
318
319 struct nix_lso {
320 u8 total;
321 u8 in_use;
322 };
323
324 struct nix_txvlan {
325 #define NIX_TX_VTAG_DEF_MAX 0x400
326 struct rsrc_bmap rsrc;
327 u16 *entry2pfvf_map;
328 struct mutex rsrc_lock; /* Serialize resource alloc/free */
329 };
330
331 struct nix_ipolicer {
332 struct rsrc_bmap band_prof;
333 u16 *pfvf_map;
334 u16 *match_id;
335 u16 *ref_count;
336 };
337
338 struct nix_hw {
339 int blkaddr;
340 struct rvu *rvu;
341 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
342 struct nix_mcast mcast;
343 struct nix_flowkey flowkey;
344 struct nix_mark_format mark_format;
345 struct nix_lso lso;
346 struct nix_txvlan txvlan;
347 struct nix_ipolicer *ipolicer;
348 u64 *tx_credits;
349 u8 cc_mcs_cnt;
350 };
351
352 /* RVU block's capabilities or functionality,
353 * which vary by silicon version/skew.
354 */
355 struct hw_cap {
356 /* Transmit side supported functionality */
357 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
358 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
359 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
360 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
361 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
362 bool nix_shaping; /* Is shaping and coloring supported */
363 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
364 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
365 bool nix_rx_multicast; /* Rx packet replication support */
366 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
367 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
368 bool programmable_chans; /* Channels programmable ? */
369 bool ipolicer;
370 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */
371 bool npc_hash_extract; /* Hash extract enabled ? */
372 bool npc_exact_match_enabled; /* Exact match supported ? */
373 };
374
375 struct rvu_hwinfo {
376 u8 total_pfs; /* MAX RVU PFs HW supports */
377 u16 total_vfs; /* Max RVU VFs HW supports */
378 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
379 u8 cgx;
380 u8 lmac_per_cgx;
381 u16 cgx_chan_base; /* CGX base channel number */
382 u16 lbk_chan_base; /* LBK base channel number */
383 u16 sdp_chan_base; /* SDP base channel number */
384 u16 cpt_chan_base; /* CPT base channel number */
385 u8 cgx_links;
386 u8 lbk_links;
387 u8 sdp_links;
388 u8 cpt_links; /* Number of CPT links */
389 u8 npc_kpus; /* No of parser units */
390 u8 npc_pkinds; /* No of port kinds */
391 u8 npc_intfs; /* No of interfaces */
392 u8 npc_kpu_entries; /* No of KPU entries */
393 u16 npc_counters; /* No of match stats counters */
394 u32 lbk_bufsize; /* FIFO size supported by LBK */
395 bool npc_ext_set; /* Extended register set */
396 u64 npc_stat_ena; /* Match stats enable bit */
397
398 struct hw_cap cap;
399 struct rvu_block block[BLK_COUNT]; /* Block info */
400 struct nix_hw *nix;
401 struct rvu *rvu;
402 struct npc_pkind pkind;
403 struct npc_mcam mcam;
404 struct npc_exact_table *table;
405 };
406
407 struct mbox_wq_info {
408 struct otx2_mbox mbox;
409 struct rvu_work *mbox_wrk;
410
411 struct otx2_mbox mbox_up;
412 struct rvu_work *mbox_wrk_up;
413
414 struct workqueue_struct *mbox_wq;
415 };
416
417 struct rvu_fwdata {
418 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
419 #define RVU_FWDATA_VERSION 0x0001
420 u32 header_magic;
421 u32 version; /* version id */
422
423 /* MAC address */
424 #define PF_MACNUM_MAX 32
425 #define VF_MACNUM_MAX 256
426 u64 pf_macs[PF_MACNUM_MAX];
427 u64 vf_macs[VF_MACNUM_MAX];
428 u64 sclk;
429 u64 rclk;
430 u64 mcam_addr;
431 u64 mcam_sz;
432 u64 msixtr_base;
433 u32 ptp_ext_clk_rate;
434 u32 ptp_ext_tstamp;
435 #define FWDATA_RESERVED_MEM 1022
436 u64 reserved[FWDATA_RESERVED_MEM];
437 #define CGX_MAX 9
438 #define CGX_LMACS_MAX 4
439 #define CGX_LMACS_USX 8
440 union {
441 struct cgx_lmac_fwdata_s
442 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
443 struct cgx_lmac_fwdata_s
444 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX];
445 };
446 /* Do not add new fields below this line */
447 };
448
449 struct ptp;
450
451 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
452 * source where it came from.
453 */
454 struct npc_kpu_profile_adapter {
455 const char *name;
456 u64 version;
457 const struct npc_lt_def_cfg *lt_def;
458 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
459 const struct npc_kpu_profile *kpu; /* array[kpus] */
460 struct npc_mcam_kex *mkex;
461 struct npc_mcam_kex_hash *mkex_hash;
462 bool custom;
463 size_t pkinds;
464 size_t kpus;
465 };
466
467 #define RVU_SWITCH_LBK_CHAN 63
468
469 struct rvu_switch {
470 struct mutex switch_lock; /* Serialize flow installation */
471 u32 used_entries;
472 u16 *entry2pcifunc;
473 u16 mode;
474 u16 start_entry;
475 };
476
477 struct rvu {
478 void __iomem *afreg_base;
479 void __iomem *pfreg_base;
480 struct pci_dev *pdev;
481 struct device *dev;
482 struct rvu_hwinfo *hw;
483 struct rvu_pfvf *pf;
484 struct rvu_pfvf *hwvf;
485 struct mutex rsrc_lock; /* Serialize resource alloc/free */
486 struct mutex alias_lock; /* Serialize bar2 alias access */
487 int vfs; /* Number of VFs attached to RVU */
488 int nix_blkaddr[MAX_NIX_BLKS];
489
490 /* Mbox */
491 struct mbox_wq_info afpf_wq_info;
492 struct mbox_wq_info afvf_wq_info;
493
494 /* PF FLR */
495 struct rvu_work *flr_wrk;
496 struct workqueue_struct *flr_wq;
497 struct mutex flr_lock; /* Serialize FLRs */
498
499 /* MSI-X */
500 u16 num_vec;
501 char *irq_name;
502 bool *irq_allocated;
503 dma_addr_t msix_base_iova;
504 u64 msixtr_base_phy; /* Register reset value */
505
506 /* CGX */
507 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
508 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */
509 u8 cgx_mapped_pfs;
510 u8 cgx_cnt_max; /* CGX port count max */
511 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
512 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for
513 * every cgx lmac port
514 */
515 unsigned long pf_notify_bmap; /* Flags for PF notification */
516 void **cgx_idmap; /* cgx id to cgx data map table */
517 struct work_struct cgx_evh_work;
518 struct workqueue_struct *cgx_evh_wq;
519 spinlock_t cgx_evq_lock; /* cgx event queue lock */
520 struct list_head cgx_evq_head; /* cgx event queue head */
521 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
522
523 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
524 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
525
526 /* Firmware data */
527 struct rvu_fwdata *fwdata;
528 void *kpu_fwdata;
529 size_t kpu_fwdata_sz;
530 void __iomem *kpu_prfl_addr;
531
532 /* NPC KPU data */
533 struct npc_kpu_profile_adapter kpu;
534
535 struct ptp *ptp;
536
537 int mcs_blk_cnt;
538 int cpt_pf_num;
539
540 #ifdef CONFIG_DEBUG_FS
541 struct rvu_debugfs rvu_dbg;
542 #endif
543 struct rvu_devlink *rvu_dl;
544
545 /* RVU switch implementation over NPC with DMAC rules */
546 struct rvu_switch rswitch;
547
548 struct work_struct mcs_intr_work;
549 struct workqueue_struct *mcs_intr_wq;
550 struct list_head mcs_intrq_head;
551 /* mcs interrupt queue lock */
552 spinlock_t mcs_intrq_lock;
553 /* CPT interrupt lock */
554 spinlock_t cpt_intr_lock;
555
556 struct mutex mbox_lock; /* Serialize mbox up and down msgs */
557 };
558
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)559 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
560 {
561 writeq(val, rvu->afreg_base + ((block << 28) | offset));
562 }
563
rvu_read64(struct rvu * rvu,u64 block,u64 offset)564 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
565 {
566 return readq(rvu->afreg_base + ((block << 28) | offset));
567 }
568
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)569 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
570 {
571 writeq(val, rvu->pfreg_base + offset);
572 }
573
rvupf_read64(struct rvu * rvu,u64 offset)574 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
575 {
576 return readq(rvu->pfreg_base + offset);
577 }
578
rvu_bar2_sel_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)579 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
580 {
581 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of
582 * write operation.
583 */
584 rvu_write64(rvu, block, offset, val);
585 rvu_read64(rvu, block, offset);
586 /* Barrier to ensure read completes before accessing LF registers */
587 mb();
588 }
589
590 /* Silicon revisions */
is_rvu_pre_96xx_C0(struct rvu * rvu)591 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
592 {
593 struct pci_dev *pdev = rvu->pdev;
594 /* 96XX A0/B0, 95XX A0/A1/B0 chips */
595 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
596 (pdev->revision == 0x10) || (pdev->revision == 0x11) ||
597 (pdev->revision == 0x14));
598 }
599
is_rvu_96xx_A0(struct rvu * rvu)600 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
601 {
602 struct pci_dev *pdev = rvu->pdev;
603
604 return (pdev->revision == 0x00);
605 }
606
is_rvu_96xx_B0(struct rvu * rvu)607 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
608 {
609 struct pci_dev *pdev = rvu->pdev;
610
611 return (pdev->revision == 0x00) || (pdev->revision == 0x01);
612 }
613
is_rvu_95xx_A0(struct rvu * rvu)614 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
615 {
616 struct pci_dev *pdev = rvu->pdev;
617
618 return (pdev->revision == 0x10) || (pdev->revision == 0x11);
619 }
620
621 /* REVID for PCIe devices.
622 * Bits 0..1: minor pass, bit 3..2: major pass
623 * bits 7..4: midr id
624 */
625 #define PCI_REVISION_ID_96XX 0x00
626 #define PCI_REVISION_ID_95XX 0x10
627 #define PCI_REVISION_ID_95XXN 0x20
628 #define PCI_REVISION_ID_98XX 0x30
629 #define PCI_REVISION_ID_95XXMM 0x40
630 #define PCI_REVISION_ID_95XXO 0xE0
631
is_rvu_otx2(struct rvu * rvu)632 static inline bool is_rvu_otx2(struct rvu *rvu)
633 {
634 struct pci_dev *pdev = rvu->pdev;
635
636 u8 midr = pdev->revision & 0xF0;
637
638 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
639 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
640 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
641 }
642
is_cnf10ka_a0(struct rvu * rvu)643 static inline bool is_cnf10ka_a0(struct rvu *rvu)
644 {
645 struct pci_dev *pdev = rvu->pdev;
646
647 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A &&
648 (pdev->revision & 0x0F) == 0x0)
649 return true;
650 return false;
651 }
652
is_rvu_npc_hash_extract_en(struct rvu * rvu)653 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
654 {
655 u64 npc_const3;
656
657 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
658 if (!(npc_const3 & BIT_ULL(62)))
659 return false;
660
661 return true;
662 }
663
rvu_nix_chan_cgx(struct rvu * rvu,u8 cgxid,u8 lmacid,u8 chan)664 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
665 u8 lmacid, u8 chan)
666 {
667 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
668 u16 cgx_chans = nix_const & 0xFFULL;
669 struct rvu_hwinfo *hw = rvu->hw;
670
671 if (!hw->cap.programmable_chans)
672 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
673
674 return rvu->hw->cgx_chan_base +
675 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
676 }
677
rvu_nix_chan_lbk(struct rvu * rvu,u8 lbkid,u8 chan)678 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
679 u8 chan)
680 {
681 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
682 u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
683 struct rvu_hwinfo *hw = rvu->hw;
684
685 if (!hw->cap.programmable_chans)
686 return NIX_CHAN_LBK_CHX(lbkid, chan);
687
688 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
689 }
690
rvu_nix_chan_sdp(struct rvu * rvu,u8 chan)691 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
692 {
693 struct rvu_hwinfo *hw = rvu->hw;
694
695 if (!hw->cap.programmable_chans)
696 return NIX_CHAN_SDP_CHX(chan);
697
698 return hw->sdp_chan_base + chan;
699 }
700
rvu_nix_chan_cpt(struct rvu * rvu,u8 chan)701 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
702 {
703 return rvu->hw->cpt_chan_base + chan;
704 }
705
is_rvu_supports_nix1(struct rvu * rvu)706 static inline bool is_rvu_supports_nix1(struct rvu *rvu)
707 {
708 struct pci_dev *pdev = rvu->pdev;
709
710 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)
711 return true;
712
713 return false;
714 }
715
716 /* Function Prototypes
717 * RVU
718 */
is_afvf(u16 pcifunc)719 static inline bool is_afvf(u16 pcifunc)
720 {
721 return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
722 }
723
is_vf(u16 pcifunc)724 static inline bool is_vf(u16 pcifunc)
725 {
726 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
727 }
728
729 /* check if PF_FUNC is AF */
is_pffunc_af(u16 pcifunc)730 static inline bool is_pffunc_af(u16 pcifunc)
731 {
732 return !pcifunc;
733 }
734
is_rvu_fwdata_valid(struct rvu * rvu)735 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
736 {
737 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
738 (rvu->fwdata->version == RVU_FWDATA_VERSION);
739 }
740
741 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
742 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
743 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
744 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
745 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
746 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
747 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
748 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
749 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
750 int rvu_get_pf(u16 pcifunc);
751 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
752 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
753 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
754 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
755 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
756 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
757 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
758 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
759 int rvu_get_num_lbk_chans(void);
760 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
761 u16 global_slot, u16 *slot_in_block);
762
763 /* RVU HW reg validation */
764 enum regmap_block {
765 TXSCHQ_HWREGMAP = 0,
766 MAX_HWREGMAP,
767 };
768
769 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
770
771 /* NPA/NIX AQ APIs */
772 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
773 int qsize, int inst_size, int res_size);
774 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
775
776 /* SDP APIs */
777 int rvu_sdp_init(struct rvu *rvu);
778 bool is_sdp_pfvf(u16 pcifunc);
779 bool is_sdp_pf(u16 pcifunc);
780 bool is_sdp_vf(u16 pcifunc);
781
782 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)783 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
784 {
785 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
786 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
787 }
788
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)789 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
790 {
791 *cgx_id = (map >> 4) & 0xF;
792 *lmac_id = (map & 0xF);
793 }
794
is_cgx_vf(struct rvu * rvu,u16 pcifunc)795 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
796 {
797 return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
798 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)));
799 }
800
801 #define M(_name, _id, fn_name, req, rsp) \
802 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
803 MBOX_MESSAGES
804 #undef M
805
806 int rvu_cgx_init(struct rvu *rvu);
807 int rvu_cgx_exit(struct rvu *rvu);
808 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
809 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
810 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
811 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
812 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
813 int rxtxflag, u64 *stat);
814 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
815
816 /* NPA APIs */
817 int rvu_npa_init(struct rvu *rvu);
818 void rvu_npa_freemem(struct rvu *rvu);
819 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
820 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
821 struct npa_aq_enq_rsp *rsp);
822
823 /* NIX APIs */
824 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
825 int rvu_nix_init(struct rvu *rvu);
826 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
827 int blkaddr, u32 cfg);
828 void rvu_nix_freemem(struct rvu *rvu);
829 int rvu_get_nixlf_count(struct rvu *rvu);
830 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
831 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
832 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
833 struct nix_mce_list *mce_list,
834 int mce_idx, int mcam_index, bool add);
835 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
836 struct nix_mce_list **mce_list, int *mce_idx);
837 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
838 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
839 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
840 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
841 struct nix_hw **nix_hw, int *blkaddr);
842 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
843 u16 rq_idx, u16 match_id);
844 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
845 struct nix_cn10k_aq_enq_req *aq_req,
846 struct nix_cn10k_aq_enq_rsp *aq_rsp,
847 u16 pcifunc, u8 ctype, u32 qidx);
848 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
849 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type);
850 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
851 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
852 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc,
853 struct nix_txsch *txsch, bool enable);
854
855 /* NPC APIs */
856 void rvu_npc_freemem(struct rvu *rvu);
857 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
858 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
859 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
860 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
861 int nixlf, u64 chan, u8 *mac_addr);
862 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
863 int nixlf, u64 chan, u8 chan_cnt);
864 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
865 bool enable);
866 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
867 int nixlf, u64 chan);
868 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
869 bool enable);
870 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
871 u64 chan);
872 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
873 bool enable);
874
875 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
876 int nixlf, int type, bool enable);
877 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
878 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
879 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
880 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
881 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
882 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
883 int group, int alg_idx, int mcam_index);
884
885 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
886 int blkaddr, int *alloc_cnt,
887 int *enable_cnt);
888 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
889 int blkaddr, int *alloc_cnt,
890 int *enable_cnt);
891 bool is_npc_intf_tx(u8 intf);
892 bool is_npc_intf_rx(u8 intf);
893 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
894 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
895 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
896 const char *npc_get_field_name(u8 hdr);
897 int npc_get_bank(struct npc_mcam *mcam, int index);
898 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
899 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
900 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
901 int blkaddr, int index, bool enable);
902 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
903 int blkaddr, u16 src, struct mcam_entry *entry,
904 u8 *intf, u8 *ena);
905 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
906 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
907 u32 rvu_cgx_get_fifolen(struct rvu *rvu);
908 void *rvu_first_cgx_pdata(struct rvu *rvu);
909 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
910 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
911 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable);
912 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
913 u16 pfc_en);
914 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
915 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc);
916 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
917 void cgx_start_linkup(struct rvu *rvu);
918 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
919 int type);
920 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
921 int index);
922 int rvu_npc_init(struct rvu *rvu);
923 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
924 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
925 u64 bcast_mcast_val, u64 bcast_mcast_mask);
926 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
927 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf);
928
929 /* CPT APIs */
930 int rvu_cpt_register_interrupts(struct rvu *rvu);
931 void rvu_cpt_unregister_interrupts(struct rvu *rvu);
932 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
933 int slot);
934 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
935 int rvu_cpt_init(struct rvu *rvu);
936
937 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
938 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
939
940 /* CN10K RVU */
941 int rvu_set_channels_base(struct rvu *rvu);
942 void rvu_program_channels(struct rvu *rvu);
943
944 /* CN10K NIX */
945 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
946
947 /* CN10K RVU - LMT*/
948 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
949
950 #ifdef CONFIG_DEBUG_FS
951 void rvu_dbg_init(struct rvu *rvu);
952 void rvu_dbg_exit(struct rvu *rvu);
953 #else
rvu_dbg_init(struct rvu * rvu)954 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)955 static inline void rvu_dbg_exit(struct rvu *rvu) {}
956 #endif
957
958 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
959
960 /* RVU Switch */
961 void rvu_switch_enable(struct rvu *rvu);
962 void rvu_switch_disable(struct rvu *rvu);
963 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
964
965 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
966 u64 pkind, u8 var_len_off, u8 var_len_off_mask,
967 u8 shift_dir);
968 int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
969
970 /* CN10K MCS */
971 int rvu_mcs_init(struct rvu *rvu);
972 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc);
973 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena);
974 void rvu_mcs_exit(struct rvu *rvu);
975
976 #endif /* RVU_H */
977