1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MFD core driver for Intel Broxton Whiskey Cove PMIC
4 *
5 * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/bits.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/core.h>
15 #include <linux/mfd/intel_soc_pmic.h>
16 #include <linux/mfd/intel_soc_pmic_bxtwc.h>
17 #include <linux/module.h>
18
19 #include <asm/intel_scu_ipc.h>
20
21 /* PMIC device registers */
22 #define REG_ADDR_MASK GENMASK(15, 8)
23 #define REG_ADDR_SHIFT 8
24 #define REG_OFFSET_MASK GENMASK(7, 0)
25
26 /* Interrupt Status Registers */
27 #define BXTWC_IRQLVL1 0x4E02
28
29 #define BXTWC_PWRBTNIRQ 0x4E03
30 #define BXTWC_THRM0IRQ 0x4E04
31 #define BXTWC_THRM1IRQ 0x4E05
32 #define BXTWC_THRM2IRQ 0x4E06
33 #define BXTWC_BCUIRQ 0x4E07
34 #define BXTWC_ADCIRQ 0x4E08
35 #define BXTWC_CHGR0IRQ 0x4E09
36 #define BXTWC_CHGR1IRQ 0x4E0A
37 #define BXTWC_GPIOIRQ0 0x4E0B
38 #define BXTWC_GPIOIRQ1 0x4E0C
39 #define BXTWC_CRITIRQ 0x4E0D
40 #define BXTWC_TMUIRQ 0x4FB6
41
42 /* Interrupt MASK Registers */
43 #define BXTWC_MIRQLVL1 0x4E0E
44 #define BXTWC_MIRQLVL1_MCHGR BIT(5)
45
46 #define BXTWC_MPWRBTNIRQ 0x4E0F
47 #define BXTWC_MTHRM0IRQ 0x4E12
48 #define BXTWC_MTHRM1IRQ 0x4E13
49 #define BXTWC_MTHRM2IRQ 0x4E14
50 #define BXTWC_MBCUIRQ 0x4E15
51 #define BXTWC_MADCIRQ 0x4E16
52 #define BXTWC_MCHGR0IRQ 0x4E17
53 #define BXTWC_MCHGR1IRQ 0x4E18
54 #define BXTWC_MGPIO0IRQ 0x4E19
55 #define BXTWC_MGPIO1IRQ 0x4E1A
56 #define BXTWC_MCRITIRQ 0x4E1B
57 #define BXTWC_MTMUIRQ 0x4FB7
58
59 /* Whiskey Cove PMIC share same ACPI ID between different platforms */
60 #define BROXTON_PMIC_WC_HRV 4
61
62 #define PMC_PMIC_ACCESS 0xFF
63 #define PMC_PMIC_READ 0x0
64 #define PMC_PMIC_WRITE 0x1
65
66 enum bxtwc_irqs {
67 BXTWC_PWRBTN_LVL1_IRQ = 0,
68 BXTWC_TMU_LVL1_IRQ,
69 BXTWC_THRM_LVL1_IRQ,
70 BXTWC_BCU_LVL1_IRQ,
71 BXTWC_ADC_LVL1_IRQ,
72 BXTWC_CHGR_LVL1_IRQ,
73 BXTWC_GPIO_LVL1_IRQ,
74 BXTWC_CRIT_LVL1_IRQ,
75 };
76
77 enum bxtwc_irqs_pwrbtn {
78 BXTWC_PWRBTN_IRQ = 0,
79 BXTWC_UIBTN_IRQ,
80 };
81
82 enum bxtwc_irqs_bcu {
83 BXTWC_BCU_IRQ = 0,
84 };
85
86 enum bxtwc_irqs_adc {
87 BXTWC_ADC_IRQ = 0,
88 };
89
90 enum bxtwc_irqs_chgr {
91 BXTWC_USBC_IRQ = 0,
92 BXTWC_CHGR0_IRQ,
93 BXTWC_CHGR1_IRQ,
94 };
95
96 enum bxtwc_irqs_tmu {
97 BXTWC_TMU_IRQ = 0,
98 };
99
100 enum bxtwc_irqs_crit {
101 BXTWC_CRIT_IRQ = 0,
102 };
103
104 static const struct regmap_irq bxtwc_regmap_irqs[] = {
105 REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
106 REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
107 REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
108 REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
109 REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
110 REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
111 REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
112 REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
113 };
114
115 static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
116 REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, BIT(0)),
117 };
118
119 static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
120 REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)),
121 };
122
123 static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
124 REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)),
125 };
126
127 static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
128 REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
129 REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)),
130 REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)),
131 };
132
133 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
134 REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)),
135 };
136
137 static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
138 REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)),
139 };
140
141 static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
142 .name = "bxtwc_irq_chip",
143 .status_base = BXTWC_IRQLVL1,
144 .mask_base = BXTWC_MIRQLVL1,
145 .irqs = bxtwc_regmap_irqs,
146 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
147 .num_regs = 1,
148 };
149
150 static struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
151 .name = "bxtwc_irq_chip_pwrbtn",
152 .status_base = BXTWC_PWRBTNIRQ,
153 .mask_base = BXTWC_MPWRBTNIRQ,
154 .irqs = bxtwc_regmap_irqs_pwrbtn,
155 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn),
156 .num_regs = 1,
157 };
158
159 static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
160 .name = "bxtwc_irq_chip_tmu",
161 .status_base = BXTWC_TMUIRQ,
162 .mask_base = BXTWC_MTMUIRQ,
163 .irqs = bxtwc_regmap_irqs_tmu,
164 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
165 .num_regs = 1,
166 };
167
168 static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
169 .name = "bxtwc_irq_chip_bcu",
170 .status_base = BXTWC_BCUIRQ,
171 .mask_base = BXTWC_MBCUIRQ,
172 .irqs = bxtwc_regmap_irqs_bcu,
173 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
174 .num_regs = 1,
175 };
176
177 static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
178 .name = "bxtwc_irq_chip_adc",
179 .status_base = BXTWC_ADCIRQ,
180 .mask_base = BXTWC_MADCIRQ,
181 .irqs = bxtwc_regmap_irqs_adc,
182 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
183 .num_regs = 1,
184 };
185
186 static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
187 .name = "bxtwc_irq_chip_chgr",
188 .status_base = BXTWC_CHGR0IRQ,
189 .mask_base = BXTWC_MCHGR0IRQ,
190 .irqs = bxtwc_regmap_irqs_chgr,
191 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
192 .num_regs = 2,
193 };
194
195 static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
196 .name = "bxtwc_irq_chip_crit",
197 .status_base = BXTWC_CRITIRQ,
198 .mask_base = BXTWC_MCRITIRQ,
199 .irqs = bxtwc_regmap_irqs_crit,
200 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
201 .num_regs = 1,
202 };
203
204 static const struct resource gpio_resources[] = {
205 DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
206 };
207
208 static const struct resource adc_resources[] = {
209 DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
210 };
211
212 static const struct resource usbc_resources[] = {
213 DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
214 };
215
216 static const struct resource charger_resources[] = {
217 DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
218 DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
219 };
220
221 static const struct resource thermal_resources[] = {
222 DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
223 };
224
225 static const struct resource bcu_resources[] = {
226 DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
227 };
228
229 static const struct resource tmu_resources[] = {
230 DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
231 };
232
233 static struct mfd_cell bxt_wc_dev[] = {
234 {
235 .name = "bxt_wcove_thermal",
236 .num_resources = ARRAY_SIZE(thermal_resources),
237 .resources = thermal_resources,
238 },
239 {
240 .name = "bxt_wcove_gpio",
241 .num_resources = ARRAY_SIZE(gpio_resources),
242 .resources = gpio_resources,
243 },
244 {
245 .name = "bxt_wcove_region",
246 },
247 };
248
249 static const struct mfd_cell bxt_wc_tmu_dev[] = {
250 {
251 .name = "bxt_wcove_tmu",
252 .num_resources = ARRAY_SIZE(tmu_resources),
253 .resources = tmu_resources,
254 },
255 };
256
257 static const struct mfd_cell bxt_wc_bcu_dev[] = {
258 {
259 .name = "bxt_wcove_bcu",
260 .num_resources = ARRAY_SIZE(bcu_resources),
261 .resources = bcu_resources,
262 },
263 };
264
265 static const struct mfd_cell bxt_wc_adc_dev[] = {
266 {
267 .name = "bxt_wcove_gpadc",
268 .num_resources = ARRAY_SIZE(adc_resources),
269 .resources = adc_resources,
270 },
271 };
272
273 static struct mfd_cell bxt_wc_chgr_dev[] = {
274 {
275 .name = "bxt_wcove_usbc",
276 .num_resources = ARRAY_SIZE(usbc_resources),
277 .resources = usbc_resources,
278 },
279 {
280 .name = "bxt_wcove_ext_charger",
281 .num_resources = ARRAY_SIZE(charger_resources),
282 .resources = charger_resources,
283 },
284 };
285
regmap_ipc_byte_reg_read(void * context,unsigned int reg,unsigned int * val)286 static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
287 unsigned int *val)
288 {
289 int ret;
290 int i2c_addr;
291 u8 ipc_in[2];
292 u8 ipc_out[4];
293 struct intel_soc_pmic *pmic = context;
294
295 if (!pmic)
296 return -EINVAL;
297
298 if (reg & REG_ADDR_MASK)
299 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
300 else
301 i2c_addr = BXTWC_DEVICE1_ADDR;
302
303 reg &= REG_OFFSET_MASK;
304
305 ipc_in[0] = reg;
306 ipc_in[1] = i2c_addr;
307 ret = intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,
308 PMC_PMIC_READ, ipc_in, sizeof(ipc_in),
309 ipc_out, sizeof(ipc_out));
310 if (ret)
311 return ret;
312
313 *val = ipc_out[0];
314
315 return 0;
316 }
317
regmap_ipc_byte_reg_write(void * context,unsigned int reg,unsigned int val)318 static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
319 unsigned int val)
320 {
321 int i2c_addr;
322 u8 ipc_in[3];
323 struct intel_soc_pmic *pmic = context;
324
325 if (!pmic)
326 return -EINVAL;
327
328 if (reg & REG_ADDR_MASK)
329 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
330 else
331 i2c_addr = BXTWC_DEVICE1_ADDR;
332
333 reg &= REG_OFFSET_MASK;
334
335 ipc_in[0] = reg;
336 ipc_in[1] = i2c_addr;
337 ipc_in[2] = val;
338 return intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,
339 PMC_PMIC_WRITE, ipc_in, sizeof(ipc_in),
340 NULL, 0);
341 }
342
343 /* sysfs interfaces to r/w PMIC registers, required by initial script */
344 static unsigned long bxtwc_reg_addr;
addr_show(struct device * dev,struct device_attribute * attr,char * buf)345 static ssize_t addr_show(struct device *dev,
346 struct device_attribute *attr, char *buf)
347 {
348 return sysfs_emit(buf, "0x%lx\n", bxtwc_reg_addr);
349 }
350
addr_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)351 static ssize_t addr_store(struct device *dev,
352 struct device_attribute *attr, const char *buf, size_t count)
353 {
354 int ret;
355
356 ret = kstrtoul(buf, 0, &bxtwc_reg_addr);
357 if (ret)
358 return ret;
359
360 return count;
361 }
362
val_show(struct device * dev,struct device_attribute * attr,char * buf)363 static ssize_t val_show(struct device *dev,
364 struct device_attribute *attr, char *buf)
365 {
366 int ret;
367 unsigned int val;
368 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
369
370 ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
371 if (ret) {
372 dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
373 return ret;
374 }
375
376 return sysfs_emit(buf, "0x%02x\n", val);
377 }
378
val_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)379 static ssize_t val_store(struct device *dev,
380 struct device_attribute *attr, const char *buf, size_t count)
381 {
382 int ret;
383 unsigned int val;
384 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
385
386 ret = kstrtouint(buf, 0, &val);
387 if (ret)
388 return ret;
389
390 ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
391 if (ret) {
392 dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
393 val, bxtwc_reg_addr);
394 return ret;
395 }
396 return count;
397 }
398
399 static DEVICE_ATTR_ADMIN_RW(addr);
400 static DEVICE_ATTR_ADMIN_RW(val);
401 static struct attribute *bxtwc_attrs[] = {
402 &dev_attr_addr.attr,
403 &dev_attr_val.attr,
404 NULL
405 };
406
407 static const struct attribute_group bxtwc_group = {
408 .attrs = bxtwc_attrs,
409 };
410
411 static const struct attribute_group *bxtwc_groups[] = {
412 &bxtwc_group,
413 NULL
414 };
415
416 static const struct regmap_config bxtwc_regmap_config = {
417 .reg_bits = 16,
418 .val_bits = 8,
419 .reg_write = regmap_ipc_byte_reg_write,
420 .reg_read = regmap_ipc_byte_reg_read,
421 };
422
bxtwc_add_chained_irq_chip(struct intel_soc_pmic * pmic,struct regmap_irq_chip_data * pdata,int pirq,int irq_flags,const struct regmap_irq_chip * chip,struct regmap_irq_chip_data ** data)423 static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
424 struct regmap_irq_chip_data *pdata,
425 int pirq, int irq_flags,
426 const struct regmap_irq_chip *chip,
427 struct regmap_irq_chip_data **data)
428 {
429 int irq;
430
431 irq = regmap_irq_get_virq(pdata, pirq);
432 if (irq < 0)
433 return dev_err_probe(pmic->dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
434 pirq, chip->name);
435
436 return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
437 0, chip, data);
438 }
439
bxtwc_add_chained_devices(struct intel_soc_pmic * pmic,const struct mfd_cell * cells,int n_devs,struct regmap_irq_chip_data * pdata,int pirq,int irq_flags,const struct regmap_irq_chip * chip,struct regmap_irq_chip_data ** data)440 static int bxtwc_add_chained_devices(struct intel_soc_pmic *pmic,
441 const struct mfd_cell *cells, int n_devs,
442 struct regmap_irq_chip_data *pdata,
443 int pirq, int irq_flags,
444 const struct regmap_irq_chip *chip,
445 struct regmap_irq_chip_data **data)
446 {
447 struct device *dev = pmic->dev;
448 struct irq_domain *domain;
449 int ret;
450
451 ret = bxtwc_add_chained_irq_chip(pmic, pdata, pirq, irq_flags, chip, data);
452 if (ret)
453 return dev_err_probe(dev, ret, "Failed to add %s IRQ chip\n", chip->name);
454
455 domain = regmap_irq_get_domain(*data);
456
457 return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, cells, n_devs, NULL, 0, domain);
458 }
459
bxtwc_probe(struct platform_device * pdev)460 static int bxtwc_probe(struct platform_device *pdev)
461 {
462 struct device *dev = &pdev->dev;
463 int ret;
464 acpi_status status;
465 unsigned long long hrv;
466 struct intel_soc_pmic *pmic;
467
468 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
469 if (ACPI_FAILURE(status))
470 return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");
471 if (hrv != BROXTON_PMIC_WC_HRV)
472 return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);
473
474 pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
475 if (!pmic)
476 return -ENOMEM;
477
478 ret = platform_get_irq(pdev, 0);
479 if (ret < 0)
480 return ret;
481 pmic->irq = ret;
482
483 platform_set_drvdata(pdev, pmic);
484 pmic->dev = dev;
485
486 pmic->scu = devm_intel_scu_ipc_dev_get(dev);
487 if (!pmic->scu)
488 return -EPROBE_DEFER;
489
490 pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bxtwc_regmap_config);
491 if (IS_ERR(pmic->regmap))
492 return dev_err_probe(dev, PTR_ERR(pmic->regmap), "Failed to initialise regmap\n");
493
494 ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
495 IRQF_ONESHOT | IRQF_SHARED,
496 0, &bxtwc_regmap_irq_chip,
497 &pmic->irq_chip_data);
498 if (ret)
499 return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");
500
501 ret = bxtwc_add_chained_devices(pmic, bxt_wc_tmu_dev, ARRAY_SIZE(bxt_wc_tmu_dev),
502 pmic->irq_chip_data,
503 BXTWC_TMU_LVL1_IRQ,
504 IRQF_ONESHOT,
505 &bxtwc_regmap_irq_chip_tmu,
506 &pmic->irq_chip_data_tmu);
507 if (ret)
508 return ret;
509
510 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
511 BXTWC_PWRBTN_LVL1_IRQ,
512 IRQF_ONESHOT,
513 &bxtwc_regmap_irq_chip_pwrbtn,
514 &pmic->irq_chip_data_pwrbtn);
515 if (ret)
516 return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n");
517
518 ret = bxtwc_add_chained_devices(pmic, bxt_wc_bcu_dev, ARRAY_SIZE(bxt_wc_bcu_dev),
519 pmic->irq_chip_data,
520 BXTWC_BCU_LVL1_IRQ,
521 IRQF_ONESHOT,
522 &bxtwc_regmap_irq_chip_bcu,
523 &pmic->irq_chip_data_bcu);
524 if (ret)
525 return ret;
526
527 ret = bxtwc_add_chained_devices(pmic, bxt_wc_adc_dev, ARRAY_SIZE(bxt_wc_adc_dev),
528 pmic->irq_chip_data,
529 BXTWC_ADC_LVL1_IRQ,
530 IRQF_ONESHOT,
531 &bxtwc_regmap_irq_chip_adc,
532 &pmic->irq_chip_data_adc);
533 if (ret)
534 return ret;
535
536 ret = bxtwc_add_chained_devices(pmic, bxt_wc_chgr_dev, ARRAY_SIZE(bxt_wc_chgr_dev),
537 pmic->irq_chip_data,
538 BXTWC_CHGR_LVL1_IRQ,
539 IRQF_ONESHOT,
540 &bxtwc_regmap_irq_chip_chgr,
541 &pmic->irq_chip_data_chgr);
542 if (ret)
543 return ret;
544
545 /* Add chained IRQ handler for CRIT IRQs */
546 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
547 BXTWC_CRIT_LVL1_IRQ,
548 IRQF_ONESHOT,
549 &bxtwc_regmap_irq_chip_crit,
550 &pmic->irq_chip_data_crit);
551 if (ret)
552 return dev_err_probe(dev, ret, "Failed to add CRIT IRQ chip\n");
553
554 ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),
555 NULL, 0, NULL);
556 if (ret)
557 return dev_err_probe(dev, ret, "Failed to add devices\n");
558
559 /*
560 * There is a known H/W bug. Upon reset, BIT 5 of register
561 * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
562 * later it's set to 1(masked) automatically by hardware. So we
563 * place the software workaround here to unmask it again in order
564 * to re-enable the charger interrupt.
565 */
566 regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, BXTWC_MIRQLVL1_MCHGR, 0);
567
568 return 0;
569 }
570
bxtwc_shutdown(struct platform_device * pdev)571 static void bxtwc_shutdown(struct platform_device *pdev)
572 {
573 struct intel_soc_pmic *pmic = platform_get_drvdata(pdev);
574
575 disable_irq(pmic->irq);
576 }
577
bxtwc_suspend(struct device * dev)578 static int bxtwc_suspend(struct device *dev)
579 {
580 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
581
582 disable_irq(pmic->irq);
583
584 return 0;
585 }
586
bxtwc_resume(struct device * dev)587 static int bxtwc_resume(struct device *dev)
588 {
589 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
590
591 enable_irq(pmic->irq);
592 return 0;
593 }
594
595 static DEFINE_SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
596
597 static const struct acpi_device_id bxtwc_acpi_ids[] = {
598 { "INT34D3", },
599 { }
600 };
601 MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
602
603 static struct platform_driver bxtwc_driver = {
604 .probe = bxtwc_probe,
605 .shutdown = bxtwc_shutdown,
606 .driver = {
607 .name = "BXTWC PMIC",
608 .pm = pm_sleep_ptr(&bxtwc_pm_ops),
609 .acpi_match_table = bxtwc_acpi_ids,
610 .dev_groups = bxtwc_groups,
611 },
612 };
613
614 module_platform_driver(bxtwc_driver);
615
616 MODULE_LICENSE("GPL v2");
617 MODULE_AUTHOR("Qipeng Zha <qipeng.zha@intel.com>");
618