1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/ctype.h>
12 #include <linux/stringify.h>
13 #include <linux/ethtool.h>
14 #include <linux/ethtool_netlink.h>
15 #include <linux/linkmode.h>
16 #include <linux/interrupt.h>
17 #include <linux/pci.h>
18 #include <linux/etherdevice.h>
19 #include <linux/crc32.h>
20 #include <linux/firmware.h>
21 #include <linux/utsname.h>
22 #include <linux/time.h>
23 #include <linux/ptp_clock_kernel.h>
24 #include <linux/net_tstamp.h>
25 #include <linux/timecounter.h>
26 #include <net/netlink.h>
27 #include "bnxt_hsi.h"
28 #include "bnxt.h"
29 #include "bnxt_hwrm.h"
30 #include "bnxt_ulp.h"
31 #include "bnxt_xdp.h"
32 #include "bnxt_ptp.h"
33 #include "bnxt_ethtool.h"
34 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
35 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
36 #include "bnxt_coredump.h"
37
38 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \
39 do { \
40 if (extack) \
41 NL_SET_ERR_MSG_MOD(extack, msg); \
42 netdev_err(dev, "%s\n", msg); \
43 } while (0)
44
bnxt_get_msglevel(struct net_device * dev)45 static u32 bnxt_get_msglevel(struct net_device *dev)
46 {
47 struct bnxt *bp = netdev_priv(dev);
48
49 return bp->msg_enable;
50 }
51
bnxt_set_msglevel(struct net_device * dev,u32 value)52 static void bnxt_set_msglevel(struct net_device *dev, u32 value)
53 {
54 struct bnxt *bp = netdev_priv(dev);
55
56 bp->msg_enable = value;
57 }
58
bnxt_get_coalesce(struct net_device * dev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)59 static int bnxt_get_coalesce(struct net_device *dev,
60 struct ethtool_coalesce *coal,
61 struct kernel_ethtool_coalesce *kernel_coal,
62 struct netlink_ext_ack *extack)
63 {
64 struct bnxt *bp = netdev_priv(dev);
65 struct bnxt_coal *hw_coal;
66 u16 mult;
67
68 memset(coal, 0, sizeof(*coal));
69
70 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
71
72 hw_coal = &bp->rx_coal;
73 mult = hw_coal->bufs_per_record;
74 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
75 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
76 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
77 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
78 if (hw_coal->flags &
79 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
80 kernel_coal->use_cqe_mode_rx = true;
81
82 hw_coal = &bp->tx_coal;
83 mult = hw_coal->bufs_per_record;
84 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
85 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
86 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
87 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
88 if (hw_coal->flags &
89 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
90 kernel_coal->use_cqe_mode_tx = true;
91
92 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
93
94 return 0;
95 }
96
bnxt_set_coalesce(struct net_device * dev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)97 static int bnxt_set_coalesce(struct net_device *dev,
98 struct ethtool_coalesce *coal,
99 struct kernel_ethtool_coalesce *kernel_coal,
100 struct netlink_ext_ack *extack)
101 {
102 struct bnxt *bp = netdev_priv(dev);
103 bool update_stats = false;
104 struct bnxt_coal *hw_coal;
105 int rc = 0;
106 u16 mult;
107
108 if (coal->use_adaptive_rx_coalesce) {
109 bp->flags |= BNXT_FLAG_DIM;
110 } else {
111 if (bp->flags & BNXT_FLAG_DIM) {
112 bp->flags &= ~(BNXT_FLAG_DIM);
113 goto reset_coalesce;
114 }
115 }
116
117 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
118 !(bp->coal_cap.cmpl_params &
119 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET))
120 return -EOPNOTSUPP;
121
122 hw_coal = &bp->rx_coal;
123 mult = hw_coal->bufs_per_record;
124 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
125 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
126 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
127 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
128 hw_coal->flags &=
129 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
130 if (kernel_coal->use_cqe_mode_rx)
131 hw_coal->flags |=
132 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
133
134 hw_coal = &bp->tx_coal;
135 mult = hw_coal->bufs_per_record;
136 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
137 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
138 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
139 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
140 hw_coal->flags &=
141 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
142 if (kernel_coal->use_cqe_mode_tx)
143 hw_coal->flags |=
144 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
145
146 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
147 u32 stats_ticks = coal->stats_block_coalesce_usecs;
148
149 /* Allow 0, which means disable. */
150 if (stats_ticks)
151 stats_ticks = clamp_t(u32, stats_ticks,
152 BNXT_MIN_STATS_COAL_TICKS,
153 BNXT_MAX_STATS_COAL_TICKS);
154 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
155 bp->stats_coal_ticks = stats_ticks;
156 if (bp->stats_coal_ticks)
157 bp->current_interval =
158 bp->stats_coal_ticks * HZ / 1000000;
159 else
160 bp->current_interval = BNXT_TIMER_INTERVAL;
161 update_stats = true;
162 }
163
164 reset_coalesce:
165 if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
166 if (update_stats) {
167 bnxt_close_nic(bp, true, false);
168 rc = bnxt_open_nic(bp, true, false);
169 } else {
170 rc = bnxt_hwrm_set_coal(bp);
171 }
172 }
173
174 return rc;
175 }
176
177 static const char * const bnxt_ring_rx_stats_str[] = {
178 "rx_ucast_packets",
179 "rx_mcast_packets",
180 "rx_bcast_packets",
181 "rx_discards",
182 "rx_errors",
183 "rx_ucast_bytes",
184 "rx_mcast_bytes",
185 "rx_bcast_bytes",
186 };
187
188 static const char * const bnxt_ring_tx_stats_str[] = {
189 "tx_ucast_packets",
190 "tx_mcast_packets",
191 "tx_bcast_packets",
192 "tx_errors",
193 "tx_discards",
194 "tx_ucast_bytes",
195 "tx_mcast_bytes",
196 "tx_bcast_bytes",
197 };
198
199 static const char * const bnxt_ring_tpa_stats_str[] = {
200 "tpa_packets",
201 "tpa_bytes",
202 "tpa_events",
203 "tpa_aborts",
204 };
205
206 static const char * const bnxt_ring_tpa2_stats_str[] = {
207 "rx_tpa_eligible_pkt",
208 "rx_tpa_eligible_bytes",
209 "rx_tpa_pkt",
210 "rx_tpa_bytes",
211 "rx_tpa_errors",
212 "rx_tpa_events",
213 };
214
215 static const char * const bnxt_rx_sw_stats_str[] = {
216 "rx_l4_csum_errors",
217 "rx_resets",
218 "rx_buf_errors",
219 };
220
221 static const char * const bnxt_cmn_sw_stats_str[] = {
222 "missed_irqs",
223 };
224
225 #define BNXT_RX_STATS_ENTRY(counter) \
226 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
227
228 #define BNXT_TX_STATS_ENTRY(counter) \
229 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
230
231 #define BNXT_RX_STATS_EXT_ENTRY(counter) \
232 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
233
234 #define BNXT_TX_STATS_EXT_ENTRY(counter) \
235 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
236
237 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
238 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
240
241 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
242 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
244
245 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \
246 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
247 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
248 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
249 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
250 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
251 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
252 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
253 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
254
255 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \
256 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
257 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
258 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
259 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
260 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
261 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
262 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
263 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
264
265 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
266 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
267 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
268
269 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
270 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
271 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
272
273 #define BNXT_RX_STATS_EXT_COS_ENTRIES \
274 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
275 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
276 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
277 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
278 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
279 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
280 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
281 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
282
283 #define BNXT_TX_STATS_EXT_COS_ENTRIES \
284 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
285 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
286 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
287 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
288 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
289 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
290 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
291 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
292
293 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
294 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
296
297 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
298 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
306
307 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
308 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
309 __stringify(counter##_pri##n) }
310
311 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
312 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
313 __stringify(counter##_pri##n) }
314
315 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \
316 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
317 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
318 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
319 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
320 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
321 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
322 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
323 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
324
325 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \
326 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
327 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
328 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
329 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
330 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
331 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
332 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
333 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
334
335 enum {
336 RX_TOTAL_DISCARDS,
337 TX_TOTAL_DISCARDS,
338 RX_NETPOLL_DISCARDS,
339 };
340
341 static const char *const bnxt_ring_err_stats_arr[] = {
342 "rx_total_l4_csum_errors",
343 "rx_total_resets",
344 "rx_total_buf_errors",
345 "rx_total_oom_discards",
346 "rx_total_netpoll_discards",
347 "rx_total_ring_discards",
348 "tx_total_resets",
349 "tx_total_ring_discards",
350 "total_missed_irqs",
351 };
352
353 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str)
354 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str)
355 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str)
356 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str)
357
358 static const struct {
359 long offset;
360 char string[ETH_GSTRING_LEN];
361 } bnxt_port_stats_arr[] = {
362 BNXT_RX_STATS_ENTRY(rx_64b_frames),
363 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
364 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
365 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
366 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
367 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
368 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
369 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
370 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
371 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
372 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
373 BNXT_RX_STATS_ENTRY(rx_total_frames),
374 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
375 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
376 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
377 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
378 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
379 BNXT_RX_STATS_ENTRY(rx_pause_frames),
380 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
381 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
382 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
383 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
384 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
385 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
386 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
387 BNXT_RX_STATS_ENTRY(rx_good_frames),
388 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
396 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
397 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
399 BNXT_RX_STATS_ENTRY(rx_bytes),
400 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
401 BNXT_RX_STATS_ENTRY(rx_runt_frames),
402 BNXT_RX_STATS_ENTRY(rx_stat_discard),
403 BNXT_RX_STATS_ENTRY(rx_stat_err),
404
405 BNXT_TX_STATS_ENTRY(tx_64b_frames),
406 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
407 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
408 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
409 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
410 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
411 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
412 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
413 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
414 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
415 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
416 BNXT_TX_STATS_ENTRY(tx_good_frames),
417 BNXT_TX_STATS_ENTRY(tx_total_frames),
418 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
419 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
420 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
421 BNXT_TX_STATS_ENTRY(tx_pause_frames),
422 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
423 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
424 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
425 BNXT_TX_STATS_ENTRY(tx_err),
426 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
427 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
435 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
437 BNXT_TX_STATS_ENTRY(tx_total_collisions),
438 BNXT_TX_STATS_ENTRY(tx_bytes),
439 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
440 BNXT_TX_STATS_ENTRY(tx_stat_discard),
441 BNXT_TX_STATS_ENTRY(tx_stat_error),
442 };
443
444 static const struct {
445 long offset;
446 char string[ETH_GSTRING_LEN];
447 } bnxt_port_stats_ext_arr[] = {
448 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
449 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
450 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
451 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
452 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
453 BNXT_RX_STATS_EXT_COS_ENTRIES,
454 BNXT_RX_STATS_EXT_PFC_ENTRIES,
455 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
456 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
457 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
458 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
459 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
460 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks),
461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks),
462 };
463
464 static const struct {
465 long offset;
466 char string[ETH_GSTRING_LEN];
467 } bnxt_tx_port_stats_ext_arr[] = {
468 BNXT_TX_STATS_EXT_COS_ENTRIES,
469 BNXT_TX_STATS_EXT_PFC_ENTRIES,
470 };
471
472 static const struct {
473 long base_off;
474 char string[ETH_GSTRING_LEN];
475 } bnxt_rx_bytes_pri_arr[] = {
476 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
477 };
478
479 static const struct {
480 long base_off;
481 char string[ETH_GSTRING_LEN];
482 } bnxt_rx_pkts_pri_arr[] = {
483 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
484 };
485
486 static const struct {
487 long base_off;
488 char string[ETH_GSTRING_LEN];
489 } bnxt_tx_bytes_pri_arr[] = {
490 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
491 };
492
493 static const struct {
494 long base_off;
495 char string[ETH_GSTRING_LEN];
496 } bnxt_tx_pkts_pri_arr[] = {
497 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
498 };
499
500 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr)
501 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
502 #define BNXT_NUM_STATS_PRI \
503 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
504 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
505 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
506 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
507
bnxt_get_num_tpa_ring_stats(struct bnxt * bp)508 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
509 {
510 if (BNXT_SUPPORTS_TPA(bp)) {
511 if (bp->max_tpa_v2) {
512 if (BNXT_CHIP_P5_THOR(bp))
513 return BNXT_NUM_TPA_RING_STATS_P5;
514 return BNXT_NUM_TPA_RING_STATS_P5_SR2;
515 }
516 return BNXT_NUM_TPA_RING_STATS;
517 }
518 return 0;
519 }
520
bnxt_get_num_ring_stats(struct bnxt * bp)521 static int bnxt_get_num_ring_stats(struct bnxt *bp)
522 {
523 int rx, tx, cmn;
524
525 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
526 bnxt_get_num_tpa_ring_stats(bp);
527 tx = NUM_RING_TX_HW_STATS;
528 cmn = NUM_RING_CMN_SW_STATS;
529 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings +
530 cmn * bp->cp_nr_rings;
531 }
532
bnxt_get_num_stats(struct bnxt * bp)533 static int bnxt_get_num_stats(struct bnxt *bp)
534 {
535 int num_stats = bnxt_get_num_ring_stats(bp);
536
537 num_stats += BNXT_NUM_RING_ERR_STATS;
538
539 if (bp->flags & BNXT_FLAG_PORT_STATS)
540 num_stats += BNXT_NUM_PORT_STATS;
541
542 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
543 num_stats += bp->fw_rx_stats_ext_size +
544 bp->fw_tx_stats_ext_size;
545 if (bp->pri2cos_valid)
546 num_stats += BNXT_NUM_STATS_PRI;
547 }
548
549 return num_stats;
550 }
551
bnxt_get_sset_count(struct net_device * dev,int sset)552 static int bnxt_get_sset_count(struct net_device *dev, int sset)
553 {
554 struct bnxt *bp = netdev_priv(dev);
555
556 switch (sset) {
557 case ETH_SS_STATS:
558 return bnxt_get_num_stats(bp);
559 case ETH_SS_TEST:
560 if (!bp->num_tests)
561 return -EOPNOTSUPP;
562 return bp->num_tests;
563 default:
564 return -EOPNOTSUPP;
565 }
566 }
567
is_rx_ring(struct bnxt * bp,int ring_num)568 static bool is_rx_ring(struct bnxt *bp, int ring_num)
569 {
570 return ring_num < bp->rx_nr_rings;
571 }
572
is_tx_ring(struct bnxt * bp,int ring_num)573 static bool is_tx_ring(struct bnxt *bp, int ring_num)
574 {
575 int tx_base = 0;
576
577 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
578 tx_base = bp->rx_nr_rings;
579
580 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
581 return true;
582 return false;
583 }
584
bnxt_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * buf)585 static void bnxt_get_ethtool_stats(struct net_device *dev,
586 struct ethtool_stats *stats, u64 *buf)
587 {
588 struct bnxt_total_ring_err_stats ring_err_stats = {0};
589 struct bnxt *bp = netdev_priv(dev);
590 u64 *curr, *prev;
591 u32 tpa_stats;
592 u32 i, j = 0;
593
594 if (!bp->bnapi) {
595 j += bnxt_get_num_ring_stats(bp);
596 goto skip_ring_stats;
597 }
598
599 tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
600 for (i = 0; i < bp->cp_nr_rings; i++) {
601 struct bnxt_napi *bnapi = bp->bnapi[i];
602 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
603 u64 *sw_stats = cpr->stats.sw_stats;
604 u64 *sw;
605 int k;
606
607 if (is_rx_ring(bp, i)) {
608 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
609 buf[j] = sw_stats[k];
610 }
611 if (is_tx_ring(bp, i)) {
612 k = NUM_RING_RX_HW_STATS;
613 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
614 j++, k++)
615 buf[j] = sw_stats[k];
616 }
617 if (!tpa_stats || !is_rx_ring(bp, i))
618 goto skip_tpa_ring_stats;
619
620 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
621 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
622 tpa_stats; j++, k++)
623 buf[j] = sw_stats[k];
624
625 skip_tpa_ring_stats:
626 sw = (u64 *)&cpr->sw_stats.rx;
627 if (is_rx_ring(bp, i)) {
628 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
629 buf[j] = sw[k];
630 }
631
632 sw = (u64 *)&cpr->sw_stats.cmn;
633 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
634 buf[j] = sw[k];
635 }
636
637 bnxt_get_ring_err_stats(bp, &ring_err_stats);
638
639 skip_ring_stats:
640 curr = &ring_err_stats.rx_total_l4_csum_errors;
641 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors;
642 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++)
643 buf[j] = *curr + *prev;
644
645 if (bp->flags & BNXT_FLAG_PORT_STATS) {
646 u64 *port_stats = bp->port_stats.sw_stats;
647
648 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
649 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
650 }
651 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
652 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
653 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
654
655 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) {
656 buf[j] = *(rx_port_stats_ext +
657 bnxt_port_stats_ext_arr[i].offset);
658 }
659 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) {
660 buf[j] = *(tx_port_stats_ext +
661 bnxt_tx_port_stats_ext_arr[i].offset);
662 }
663 if (bp->pri2cos_valid) {
664 for (i = 0; i < 8; i++, j++) {
665 long n = bnxt_rx_bytes_pri_arr[i].base_off +
666 bp->pri2cos_idx[i];
667
668 buf[j] = *(rx_port_stats_ext + n);
669 }
670 for (i = 0; i < 8; i++, j++) {
671 long n = bnxt_rx_pkts_pri_arr[i].base_off +
672 bp->pri2cos_idx[i];
673
674 buf[j] = *(rx_port_stats_ext + n);
675 }
676 for (i = 0; i < 8; i++, j++) {
677 long n = bnxt_tx_bytes_pri_arr[i].base_off +
678 bp->pri2cos_idx[i];
679
680 buf[j] = *(tx_port_stats_ext + n);
681 }
682 for (i = 0; i < 8; i++, j++) {
683 long n = bnxt_tx_pkts_pri_arr[i].base_off +
684 bp->pri2cos_idx[i];
685
686 buf[j] = *(tx_port_stats_ext + n);
687 }
688 }
689 }
690 }
691
bnxt_get_strings(struct net_device * dev,u32 stringset,u8 * buf)692 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
693 {
694 struct bnxt *bp = netdev_priv(dev);
695 static const char * const *str;
696 u32 i, j, num_str;
697
698 switch (stringset) {
699 case ETH_SS_STATS:
700 for (i = 0; i < bp->cp_nr_rings; i++) {
701 if (is_rx_ring(bp, i)) {
702 num_str = NUM_RING_RX_HW_STATS;
703 for (j = 0; j < num_str; j++) {
704 sprintf(buf, "[%d]: %s", i,
705 bnxt_ring_rx_stats_str[j]);
706 buf += ETH_GSTRING_LEN;
707 }
708 }
709 if (is_tx_ring(bp, i)) {
710 num_str = NUM_RING_TX_HW_STATS;
711 for (j = 0; j < num_str; j++) {
712 sprintf(buf, "[%d]: %s", i,
713 bnxt_ring_tx_stats_str[j]);
714 buf += ETH_GSTRING_LEN;
715 }
716 }
717 num_str = bnxt_get_num_tpa_ring_stats(bp);
718 if (!num_str || !is_rx_ring(bp, i))
719 goto skip_tpa_stats;
720
721 if (bp->max_tpa_v2)
722 str = bnxt_ring_tpa2_stats_str;
723 else
724 str = bnxt_ring_tpa_stats_str;
725
726 for (j = 0; j < num_str; j++) {
727 sprintf(buf, "[%d]: %s", i, str[j]);
728 buf += ETH_GSTRING_LEN;
729 }
730 skip_tpa_stats:
731 if (is_rx_ring(bp, i)) {
732 num_str = NUM_RING_RX_SW_STATS;
733 for (j = 0; j < num_str; j++) {
734 sprintf(buf, "[%d]: %s", i,
735 bnxt_rx_sw_stats_str[j]);
736 buf += ETH_GSTRING_LEN;
737 }
738 }
739 num_str = NUM_RING_CMN_SW_STATS;
740 for (j = 0; j < num_str; j++) {
741 sprintf(buf, "[%d]: %s", i,
742 bnxt_cmn_sw_stats_str[j]);
743 buf += ETH_GSTRING_LEN;
744 }
745 }
746 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) {
747 strscpy(buf, bnxt_ring_err_stats_arr[i], ETH_GSTRING_LEN);
748 buf += ETH_GSTRING_LEN;
749 }
750
751 if (bp->flags & BNXT_FLAG_PORT_STATS) {
752 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
753 strcpy(buf, bnxt_port_stats_arr[i].string);
754 buf += ETH_GSTRING_LEN;
755 }
756 }
757 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
758 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) {
759 strcpy(buf, bnxt_port_stats_ext_arr[i].string);
760 buf += ETH_GSTRING_LEN;
761 }
762 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) {
763 strcpy(buf,
764 bnxt_tx_port_stats_ext_arr[i].string);
765 buf += ETH_GSTRING_LEN;
766 }
767 if (bp->pri2cos_valid) {
768 for (i = 0; i < 8; i++) {
769 strcpy(buf,
770 bnxt_rx_bytes_pri_arr[i].string);
771 buf += ETH_GSTRING_LEN;
772 }
773 for (i = 0; i < 8; i++) {
774 strcpy(buf,
775 bnxt_rx_pkts_pri_arr[i].string);
776 buf += ETH_GSTRING_LEN;
777 }
778 for (i = 0; i < 8; i++) {
779 strcpy(buf,
780 bnxt_tx_bytes_pri_arr[i].string);
781 buf += ETH_GSTRING_LEN;
782 }
783 for (i = 0; i < 8; i++) {
784 strcpy(buf,
785 bnxt_tx_pkts_pri_arr[i].string);
786 buf += ETH_GSTRING_LEN;
787 }
788 }
789 }
790 break;
791 case ETH_SS_TEST:
792 if (bp->num_tests)
793 memcpy(buf, bp->test_info->string,
794 bp->num_tests * ETH_GSTRING_LEN);
795 break;
796 default:
797 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
798 stringset);
799 break;
800 }
801 }
802
bnxt_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)803 static void bnxt_get_ringparam(struct net_device *dev,
804 struct ethtool_ringparam *ering,
805 struct kernel_ethtool_ringparam *kernel_ering,
806 struct netlink_ext_ack *extack)
807 {
808 struct bnxt *bp = netdev_priv(dev);
809
810 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
811 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
812 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
813 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED;
814 } else {
815 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
816 ering->rx_jumbo_max_pending = 0;
817 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED;
818 }
819 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
820
821 ering->rx_pending = bp->rx_ring_size;
822 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
823 ering->tx_pending = bp->tx_ring_size;
824 }
825
bnxt_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)826 static int bnxt_set_ringparam(struct net_device *dev,
827 struct ethtool_ringparam *ering,
828 struct kernel_ethtool_ringparam *kernel_ering,
829 struct netlink_ext_ack *extack)
830 {
831 struct bnxt *bp = netdev_priv(dev);
832
833 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
834 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
835 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
836 return -EINVAL;
837
838 if (netif_running(dev))
839 bnxt_close_nic(bp, false, false);
840
841 bp->rx_ring_size = ering->rx_pending;
842 bp->tx_ring_size = ering->tx_pending;
843 bnxt_set_ring_params(bp);
844
845 if (netif_running(dev))
846 return bnxt_open_nic(bp, false, false);
847
848 return 0;
849 }
850
bnxt_get_channels(struct net_device * dev,struct ethtool_channels * channel)851 static void bnxt_get_channels(struct net_device *dev,
852 struct ethtool_channels *channel)
853 {
854 struct bnxt *bp = netdev_priv(dev);
855 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
856 int max_rx_rings, max_tx_rings, tcs;
857 int max_tx_sch_inputs, tx_grps;
858
859 /* Get the most up-to-date max_tx_sch_inputs. */
860 if (netif_running(dev) && BNXT_NEW_RM(bp))
861 bnxt_hwrm_func_resc_qcaps(bp, false);
862 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
863
864 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
865 if (max_tx_sch_inputs)
866 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
867
868 tcs = netdev_get_num_tc(dev);
869 tx_grps = max(tcs, 1);
870 if (bp->tx_nr_rings_xdp)
871 tx_grps++;
872 max_tx_rings /= tx_grps;
873 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
874
875 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
876 max_rx_rings = 0;
877 max_tx_rings = 0;
878 }
879 if (max_tx_sch_inputs)
880 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
881
882 if (tcs > 1)
883 max_tx_rings /= tcs;
884
885 channel->max_rx = max_rx_rings;
886 channel->max_tx = max_tx_rings;
887 channel->max_other = 0;
888 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
889 channel->combined_count = bp->rx_nr_rings;
890 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
891 channel->combined_count--;
892 } else {
893 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
894 channel->rx_count = bp->rx_nr_rings;
895 channel->tx_count = bp->tx_nr_rings_per_tc;
896 }
897 }
898 }
899
bnxt_set_channels(struct net_device * dev,struct ethtool_channels * channel)900 static int bnxt_set_channels(struct net_device *dev,
901 struct ethtool_channels *channel)
902 {
903 struct bnxt *bp = netdev_priv(dev);
904 int req_tx_rings, req_rx_rings, tcs;
905 bool sh = false;
906 int tx_xdp = 0;
907 int rc = 0;
908
909 if (channel->other_count)
910 return -EINVAL;
911
912 if (!channel->combined_count &&
913 (!channel->rx_count || !channel->tx_count))
914 return -EINVAL;
915
916 if (channel->combined_count &&
917 (channel->rx_count || channel->tx_count))
918 return -EINVAL;
919
920 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
921 channel->tx_count))
922 return -EINVAL;
923
924 if (channel->combined_count)
925 sh = true;
926
927 tcs = netdev_get_num_tc(dev);
928
929 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
930 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
931 if (bp->tx_nr_rings_xdp) {
932 if (!sh) {
933 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
934 return -EINVAL;
935 }
936 tx_xdp = req_rx_rings;
937 }
938 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
939 if (rc) {
940 netdev_warn(dev, "Unable to allocate the requested rings\n");
941 return rc;
942 }
943
944 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
945 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
946 netif_is_rxfh_configured(dev)) {
947 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n");
948 return -EINVAL;
949 }
950
951 if (netif_running(dev)) {
952 if (BNXT_PF(bp)) {
953 /* TODO CHIMP_FW: Send message to all VF's
954 * before PF unload
955 */
956 }
957 bnxt_close_nic(bp, true, false);
958 }
959
960 if (sh) {
961 bp->flags |= BNXT_FLAG_SHARED_RINGS;
962 bp->rx_nr_rings = channel->combined_count;
963 bp->tx_nr_rings_per_tc = channel->combined_count;
964 } else {
965 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
966 bp->rx_nr_rings = channel->rx_count;
967 bp->tx_nr_rings_per_tc = channel->tx_count;
968 }
969 bp->tx_nr_rings_xdp = tx_xdp;
970 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
971 if (tcs > 1)
972 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
973
974 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
975 bp->tx_nr_rings + bp->rx_nr_rings;
976
977 /* After changing number of rx channels, update NTUPLE feature. */
978 netdev_update_features(dev);
979 if (netif_running(dev)) {
980 rc = bnxt_open_nic(bp, true, false);
981 if ((!rc) && BNXT_PF(bp)) {
982 /* TODO CHIMP_FW: Send message to all VF's
983 * to renable
984 */
985 }
986 } else {
987 rc = bnxt_reserve_rings(bp, true);
988 }
989
990 return rc;
991 }
992
993 #ifdef CONFIG_RFS_ACCEL
bnxt_grxclsrlall(struct bnxt * bp,struct ethtool_rxnfc * cmd,u32 * rule_locs)994 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
995 u32 *rule_locs)
996 {
997 int i, j = 0;
998
999 cmd->data = bp->ntp_fltr_count;
1000 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
1001 struct hlist_head *head;
1002 struct bnxt_ntuple_filter *fltr;
1003
1004 head = &bp->ntp_fltr_hash_tbl[i];
1005 rcu_read_lock();
1006 hlist_for_each_entry_rcu(fltr, head, hash) {
1007 if (j == cmd->rule_cnt)
1008 break;
1009 rule_locs[j++] = fltr->sw_id;
1010 }
1011 rcu_read_unlock();
1012 if (j == cmd->rule_cnt)
1013 break;
1014 }
1015 cmd->rule_cnt = j;
1016 return 0;
1017 }
1018
bnxt_grxclsrule(struct bnxt * bp,struct ethtool_rxnfc * cmd)1019 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1020 {
1021 struct ethtool_rx_flow_spec *fs =
1022 (struct ethtool_rx_flow_spec *)&cmd->fs;
1023 struct bnxt_ntuple_filter *fltr;
1024 struct flow_keys *fkeys;
1025 int i, rc = -EINVAL;
1026
1027 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
1028 return rc;
1029
1030 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
1031 struct hlist_head *head;
1032
1033 head = &bp->ntp_fltr_hash_tbl[i];
1034 rcu_read_lock();
1035 hlist_for_each_entry_rcu(fltr, head, hash) {
1036 if (fltr->sw_id == fs->location)
1037 goto fltr_found;
1038 }
1039 rcu_read_unlock();
1040 }
1041 return rc;
1042
1043 fltr_found:
1044 fkeys = &fltr->fkeys;
1045 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
1046 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1047 fs->flow_type = TCP_V4_FLOW;
1048 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1049 fs->flow_type = UDP_V4_FLOW;
1050 else
1051 goto fltr_err;
1052
1053 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1054 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
1055
1056 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1057 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
1058
1059 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1060 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
1061
1062 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1063 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
1064 } else {
1065 int i;
1066
1067 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1068 fs->flow_type = TCP_V6_FLOW;
1069 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1070 fs->flow_type = UDP_V6_FLOW;
1071 else
1072 goto fltr_err;
1073
1074 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1075 fkeys->addrs.v6addrs.src;
1076 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1077 fkeys->addrs.v6addrs.dst;
1078 for (i = 0; i < 4; i++) {
1079 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0);
1080 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0);
1081 }
1082 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1083 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);
1084
1085 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1086 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);
1087 }
1088
1089 fs->ring_cookie = fltr->rxq;
1090 rc = 0;
1091
1092 fltr_err:
1093 rcu_read_unlock();
1094
1095 return rc;
1096 }
1097 #endif
1098
get_ethtool_ipv4_rss(struct bnxt * bp)1099 static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1100 {
1101 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1102 return RXH_IP_SRC | RXH_IP_DST;
1103 return 0;
1104 }
1105
get_ethtool_ipv6_rss(struct bnxt * bp)1106 static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1107 {
1108 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1109 return RXH_IP_SRC | RXH_IP_DST;
1110 return 0;
1111 }
1112
bnxt_grxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1113 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1114 {
1115 cmd->data = 0;
1116 switch (cmd->flow_type) {
1117 case TCP_V4_FLOW:
1118 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1119 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1120 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1121 cmd->data |= get_ethtool_ipv4_rss(bp);
1122 break;
1123 case UDP_V4_FLOW:
1124 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1125 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1126 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1127 fallthrough;
1128 case SCTP_V4_FLOW:
1129 case AH_ESP_V4_FLOW:
1130 case AH_V4_FLOW:
1131 case ESP_V4_FLOW:
1132 case IPV4_FLOW:
1133 cmd->data |= get_ethtool_ipv4_rss(bp);
1134 break;
1135
1136 case TCP_V6_FLOW:
1137 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1138 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1139 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1140 cmd->data |= get_ethtool_ipv6_rss(bp);
1141 break;
1142 case UDP_V6_FLOW:
1143 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1144 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1145 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1146 fallthrough;
1147 case SCTP_V6_FLOW:
1148 case AH_ESP_V6_FLOW:
1149 case AH_V6_FLOW:
1150 case ESP_V6_FLOW:
1151 case IPV6_FLOW:
1152 cmd->data |= get_ethtool_ipv6_rss(bp);
1153 break;
1154 }
1155 return 0;
1156 }
1157
1158 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1159 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1160
bnxt_srxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1161 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1162 {
1163 u32 rss_hash_cfg = bp->rss_hash_cfg;
1164 int tuple, rc = 0;
1165
1166 if (cmd->data == RXH_4TUPLE)
1167 tuple = 4;
1168 else if (cmd->data == RXH_2TUPLE)
1169 tuple = 2;
1170 else if (!cmd->data)
1171 tuple = 0;
1172 else
1173 return -EINVAL;
1174
1175 if (cmd->flow_type == TCP_V4_FLOW) {
1176 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1177 if (tuple == 4)
1178 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1179 } else if (cmd->flow_type == UDP_V4_FLOW) {
1180 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1181 return -EINVAL;
1182 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1183 if (tuple == 4)
1184 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1185 } else if (cmd->flow_type == TCP_V6_FLOW) {
1186 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1187 if (tuple == 4)
1188 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1189 } else if (cmd->flow_type == UDP_V6_FLOW) {
1190 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1191 return -EINVAL;
1192 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1193 if (tuple == 4)
1194 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1195 } else if (tuple == 4) {
1196 return -EINVAL;
1197 }
1198
1199 switch (cmd->flow_type) {
1200 case TCP_V4_FLOW:
1201 case UDP_V4_FLOW:
1202 case SCTP_V4_FLOW:
1203 case AH_ESP_V4_FLOW:
1204 case AH_V4_FLOW:
1205 case ESP_V4_FLOW:
1206 case IPV4_FLOW:
1207 if (tuple == 2)
1208 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1209 else if (!tuple)
1210 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1211 break;
1212
1213 case TCP_V6_FLOW:
1214 case UDP_V6_FLOW:
1215 case SCTP_V6_FLOW:
1216 case AH_ESP_V6_FLOW:
1217 case AH_V6_FLOW:
1218 case ESP_V6_FLOW:
1219 case IPV6_FLOW:
1220 if (tuple == 2)
1221 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1222 else if (!tuple)
1223 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1224 break;
1225 }
1226
1227 if (bp->rss_hash_cfg == rss_hash_cfg)
1228 return 0;
1229
1230 if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
1231 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg;
1232 bp->rss_hash_cfg = rss_hash_cfg;
1233 if (netif_running(bp->dev)) {
1234 bnxt_close_nic(bp, false, false);
1235 rc = bnxt_open_nic(bp, false, false);
1236 }
1237 return rc;
1238 }
1239
bnxt_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1240 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1241 u32 *rule_locs)
1242 {
1243 struct bnxt *bp = netdev_priv(dev);
1244 int rc = 0;
1245
1246 switch (cmd->cmd) {
1247 #ifdef CONFIG_RFS_ACCEL
1248 case ETHTOOL_GRXRINGS:
1249 cmd->data = bp->rx_nr_rings;
1250 break;
1251
1252 case ETHTOOL_GRXCLSRLCNT:
1253 cmd->rule_cnt = bp->ntp_fltr_count;
1254 cmd->data = BNXT_NTP_FLTR_MAX_FLTR;
1255 break;
1256
1257 case ETHTOOL_GRXCLSRLALL:
1258 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1259 break;
1260
1261 case ETHTOOL_GRXCLSRULE:
1262 rc = bnxt_grxclsrule(bp, cmd);
1263 break;
1264 #endif
1265
1266 case ETHTOOL_GRXFH:
1267 rc = bnxt_grxfh(bp, cmd);
1268 break;
1269
1270 default:
1271 rc = -EOPNOTSUPP;
1272 break;
1273 }
1274
1275 return rc;
1276 }
1277
bnxt_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)1278 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1279 {
1280 struct bnxt *bp = netdev_priv(dev);
1281 int rc;
1282
1283 switch (cmd->cmd) {
1284 case ETHTOOL_SRXFH:
1285 rc = bnxt_srxfh(bp, cmd);
1286 break;
1287
1288 default:
1289 rc = -EOPNOTSUPP;
1290 break;
1291 }
1292 return rc;
1293 }
1294
bnxt_get_rxfh_indir_size(struct net_device * dev)1295 u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1296 {
1297 struct bnxt *bp = netdev_priv(dev);
1298
1299 if (bp->flags & BNXT_FLAG_CHIP_P5)
1300 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5);
1301 return HW_HASH_INDEX_SIZE;
1302 }
1303
bnxt_get_rxfh_key_size(struct net_device * dev)1304 static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1305 {
1306 return HW_HASH_KEY_SIZE;
1307 }
1308
bnxt_get_rxfh(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc)1309 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1310 u8 *hfunc)
1311 {
1312 struct bnxt *bp = netdev_priv(dev);
1313 struct bnxt_vnic_info *vnic;
1314 u32 i, tbl_size;
1315
1316 if (hfunc)
1317 *hfunc = ETH_RSS_HASH_TOP;
1318
1319 if (!bp->vnic_info)
1320 return 0;
1321
1322 vnic = &bp->vnic_info[0];
1323 if (indir && bp->rss_indir_tbl) {
1324 tbl_size = bnxt_get_rxfh_indir_size(dev);
1325 for (i = 0; i < tbl_size; i++)
1326 indir[i] = bp->rss_indir_tbl[i];
1327 }
1328
1329 if (key && vnic->rss_hash_key)
1330 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1331
1332 return 0;
1333 }
1334
bnxt_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)1335 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir,
1336 const u8 *key, const u8 hfunc)
1337 {
1338 struct bnxt *bp = netdev_priv(dev);
1339 int rc = 0;
1340
1341 if (hfunc && hfunc != ETH_RSS_HASH_TOP)
1342 return -EOPNOTSUPP;
1343
1344 if (key)
1345 return -EOPNOTSUPP;
1346
1347 if (indir) {
1348 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev);
1349
1350 for (i = 0; i < tbl_size; i++)
1351 bp->rss_indir_tbl[i] = indir[i];
1352 pad = bp->rss_indir_tbl_entries - tbl_size;
1353 if (pad)
1354 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
1355 }
1356
1357 if (netif_running(bp->dev)) {
1358 bnxt_close_nic(bp, false, false);
1359 rc = bnxt_open_nic(bp, false, false);
1360 }
1361 return rc;
1362 }
1363
bnxt_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1364 static void bnxt_get_drvinfo(struct net_device *dev,
1365 struct ethtool_drvinfo *info)
1366 {
1367 struct bnxt *bp = netdev_priv(dev);
1368
1369 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1370 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
1371 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1372 info->n_stats = bnxt_get_num_stats(bp);
1373 info->testinfo_len = bp->num_tests;
1374 /* TODO CHIMP_FW: eeprom dump details */
1375 info->eedump_len = 0;
1376 /* TODO CHIMP FW: reg dump details */
1377 info->regdump_len = 0;
1378 }
1379
bnxt_get_regs_len(struct net_device * dev)1380 static int bnxt_get_regs_len(struct net_device *dev)
1381 {
1382 struct bnxt *bp = netdev_priv(dev);
1383 int reg_len;
1384
1385 if (!BNXT_PF(bp))
1386 return -EOPNOTSUPP;
1387
1388 reg_len = BNXT_PXP_REG_LEN;
1389
1390 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)
1391 reg_len += sizeof(struct pcie_ctx_hw_stats);
1392
1393 return reg_len;
1394 }
1395
1396 #define BNXT_PCIE_32B_ENTRY(start, end) \
1397 { offsetof(struct pcie_ctx_hw_stats, start), \
1398 offsetof(struct pcie_ctx_hw_stats, end) }
1399
1400 static const struct {
1401 u16 start;
1402 u16 end;
1403 } bnxt_pcie_32b_entries[] = {
1404 BNXT_PCIE_32B_ENTRY(pcie_ltssm_histogram[0], pcie_ltssm_histogram[3]),
1405 };
1406
bnxt_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * _p)1407 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1408 void *_p)
1409 {
1410 struct pcie_ctx_hw_stats *hw_pcie_stats;
1411 struct hwrm_pcie_qstats_input *req;
1412 struct bnxt *bp = netdev_priv(dev);
1413 dma_addr_t hw_pcie_stats_addr;
1414 int rc;
1415
1416 regs->version = 0;
1417 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
1418
1419 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
1420 return;
1421
1422 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
1423 return;
1424
1425 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
1426 &hw_pcie_stats_addr);
1427 if (!hw_pcie_stats) {
1428 hwrm_req_drop(bp, req);
1429 return;
1430 }
1431
1432 regs->version = 1;
1433 hwrm_req_hold(bp, req); /* hold on to slice */
1434 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
1435 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
1436 rc = hwrm_req_send(bp, req);
1437 if (!rc) {
1438 u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN);
1439 u8 *src = (u8 *)hw_pcie_stats;
1440 int i, j;
1441
1442 for (i = 0, j = 0; i < sizeof(*hw_pcie_stats); ) {
1443 if (i >= bnxt_pcie_32b_entries[j].start &&
1444 i <= bnxt_pcie_32b_entries[j].end) {
1445 u32 *dst32 = (u32 *)(dst + i);
1446
1447 *dst32 = le32_to_cpu(*(__le32 *)(src + i));
1448 i += 4;
1449 if (i > bnxt_pcie_32b_entries[j].end &&
1450 j < ARRAY_SIZE(bnxt_pcie_32b_entries) - 1)
1451 j++;
1452 } else {
1453 u64 *dst64 = (u64 *)(dst + i);
1454
1455 *dst64 = le64_to_cpu(*(__le64 *)(src + i));
1456 i += 8;
1457 }
1458 }
1459 }
1460 hwrm_req_drop(bp, req);
1461 }
1462
bnxt_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1463 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1464 {
1465 struct bnxt *bp = netdev_priv(dev);
1466
1467 wol->supported = 0;
1468 wol->wolopts = 0;
1469 memset(&wol->sopass, 0, sizeof(wol->sopass));
1470 if (bp->flags & BNXT_FLAG_WOL_CAP) {
1471 wol->supported = WAKE_MAGIC;
1472 if (bp->wol)
1473 wol->wolopts = WAKE_MAGIC;
1474 }
1475 }
1476
bnxt_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1477 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1478 {
1479 struct bnxt *bp = netdev_priv(dev);
1480
1481 if (wol->wolopts & ~WAKE_MAGIC)
1482 return -EINVAL;
1483
1484 if (wol->wolopts & WAKE_MAGIC) {
1485 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
1486 return -EINVAL;
1487 if (!bp->wol) {
1488 if (bnxt_hwrm_alloc_wol_fltr(bp))
1489 return -EBUSY;
1490 bp->wol = 1;
1491 }
1492 } else {
1493 if (bp->wol) {
1494 if (bnxt_hwrm_free_wol_fltr(bp))
1495 return -EBUSY;
1496 bp->wol = 0;
1497 }
1498 }
1499 return 0;
1500 }
1501
_bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds,u8 fw_pause)1502 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
1503 {
1504 u32 speed_mask = 0;
1505
1506 /* TODO: support 25GB, 40GB, 50GB with different cable type */
1507 /* set the advertised speeds */
1508 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
1509 speed_mask |= ADVERTISED_100baseT_Full;
1510 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
1511 speed_mask |= ADVERTISED_1000baseT_Full;
1512 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
1513 speed_mask |= ADVERTISED_2500baseX_Full;
1514 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
1515 speed_mask |= ADVERTISED_10000baseT_Full;
1516 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
1517 speed_mask |= ADVERTISED_40000baseCR4_Full;
1518
1519 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
1520 speed_mask |= ADVERTISED_Pause;
1521 else if (fw_pause & BNXT_LINK_PAUSE_TX)
1522 speed_mask |= ADVERTISED_Asym_Pause;
1523 else if (fw_pause & BNXT_LINK_PAUSE_RX)
1524 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1525
1526 return speed_mask;
1527 }
1528
1529 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\
1530 { \
1531 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \
1532 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1533 100baseT_Full); \
1534 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \
1535 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1536 1000baseT_Full); \
1537 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \
1538 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1539 10000baseT_Full); \
1540 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \
1541 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1542 25000baseCR_Full); \
1543 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \
1544 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1545 40000baseCR4_Full);\
1546 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \
1547 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1548 50000baseCR2_Full);\
1549 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \
1550 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1551 100000baseCR4_Full);\
1552 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \
1553 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1554 Pause); \
1555 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \
1556 ethtool_link_ksettings_add_link_mode( \
1557 lk_ksettings, name, Asym_Pause);\
1558 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \
1559 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1560 Asym_Pause); \
1561 } \
1562 }
1563
1564 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \
1565 { \
1566 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1567 100baseT_Full) || \
1568 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1569 100baseT_Half)) \
1570 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \
1571 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1572 1000baseT_Full) || \
1573 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1574 1000baseT_Half)) \
1575 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \
1576 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1577 10000baseT_Full)) \
1578 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \
1579 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1580 25000baseCR_Full)) \
1581 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \
1582 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1583 40000baseCR4_Full)) \
1584 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \
1585 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1586 50000baseCR2_Full)) \
1587 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \
1588 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1589 100000baseCR4_Full)) \
1590 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \
1591 }
1592
1593 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1594 { \
1595 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \
1596 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1597 50000baseCR_Full); \
1598 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \
1599 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1600 100000baseCR2_Full);\
1601 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \
1602 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1603 200000baseCR4_Full);\
1604 }
1605
1606 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1607 { \
1608 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1609 50000baseCR_Full)) \
1610 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \
1611 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1612 100000baseCR2_Full)) \
1613 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \
1614 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1615 200000baseCR4_Full)) \
1616 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \
1617 }
1618
bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1619 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
1620 struct ethtool_link_ksettings *lk_ksettings)
1621 {
1622 u16 fec_cfg = link_info->fec_cfg;
1623
1624 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
1625 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1626 lk_ksettings->link_modes.advertising);
1627 return;
1628 }
1629 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1630 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1631 lk_ksettings->link_modes.advertising);
1632 if (fec_cfg & BNXT_FEC_ENC_RS)
1633 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1634 lk_ksettings->link_modes.advertising);
1635 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1636 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1637 lk_ksettings->link_modes.advertising);
1638 }
1639
bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1640 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info,
1641 struct ethtool_link_ksettings *lk_ksettings)
1642 {
1643 u16 fw_speeds = link_info->advertising;
1644 u8 fw_pause = 0;
1645
1646 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1647 fw_pause = link_info->auto_pause_setting;
1648
1649 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising);
1650 fw_speeds = link_info->advertising_pam4;
1651 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising);
1652 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
1653 }
1654
bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1655 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info,
1656 struct ethtool_link_ksettings *lk_ksettings)
1657 {
1658 u16 fw_speeds = link_info->lp_auto_link_speeds;
1659 u8 fw_pause = 0;
1660
1661 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1662 fw_pause = link_info->lp_pause;
1663
1664 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings,
1665 lp_advertising);
1666 fw_speeds = link_info->lp_auto_pam4_link_speeds;
1667 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising);
1668 }
1669
bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1670 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
1671 struct ethtool_link_ksettings *lk_ksettings)
1672 {
1673 u16 fec_cfg = link_info->fec_cfg;
1674
1675 if (fec_cfg & BNXT_FEC_NONE) {
1676 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1677 lk_ksettings->link_modes.supported);
1678 return;
1679 }
1680 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
1681 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1682 lk_ksettings->link_modes.supported);
1683 if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
1684 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1685 lk_ksettings->link_modes.supported);
1686 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
1687 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1688 lk_ksettings->link_modes.supported);
1689 }
1690
bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1691 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info,
1692 struct ethtool_link_ksettings *lk_ksettings)
1693 {
1694 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
1695 u16 fw_speeds = link_info->support_speeds;
1696
1697 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported);
1698 fw_speeds = link_info->support_pam4_speeds;
1699 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported);
1700
1701 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) {
1702 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1703 Pause);
1704 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1705 Asym_Pause);
1706 }
1707
1708 if (link_info->support_auto_speeds ||
1709 link_info->support_pam4_auto_speeds)
1710 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1711 Autoneg);
1712 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
1713 }
1714
bnxt_fw_to_ethtool_speed(u16 fw_link_speed)1715 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
1716 {
1717 switch (fw_link_speed) {
1718 case BNXT_LINK_SPEED_100MB:
1719 return SPEED_100;
1720 case BNXT_LINK_SPEED_1GB:
1721 return SPEED_1000;
1722 case BNXT_LINK_SPEED_2_5GB:
1723 return SPEED_2500;
1724 case BNXT_LINK_SPEED_10GB:
1725 return SPEED_10000;
1726 case BNXT_LINK_SPEED_20GB:
1727 return SPEED_20000;
1728 case BNXT_LINK_SPEED_25GB:
1729 return SPEED_25000;
1730 case BNXT_LINK_SPEED_40GB:
1731 return SPEED_40000;
1732 case BNXT_LINK_SPEED_50GB:
1733 return SPEED_50000;
1734 case BNXT_LINK_SPEED_100GB:
1735 return SPEED_100000;
1736 case BNXT_LINK_SPEED_200GB:
1737 return SPEED_200000;
1738 default:
1739 return SPEED_UNKNOWN;
1740 }
1741 }
1742
bnxt_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * lk_ksettings)1743 static int bnxt_get_link_ksettings(struct net_device *dev,
1744 struct ethtool_link_ksettings *lk_ksettings)
1745 {
1746 struct bnxt *bp = netdev_priv(dev);
1747 struct bnxt_link_info *link_info = &bp->link_info;
1748 struct ethtool_link_settings *base = &lk_ksettings->base;
1749 u32 ethtool_speed;
1750
1751 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
1752 mutex_lock(&bp->link_lock);
1753 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings);
1754
1755 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
1756 if (link_info->autoneg) {
1757 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings);
1758 ethtool_link_ksettings_add_link_mode(lk_ksettings,
1759 advertising, Autoneg);
1760 base->autoneg = AUTONEG_ENABLE;
1761 base->duplex = DUPLEX_UNKNOWN;
1762 if (link_info->phy_link_status == BNXT_LINK_LINK) {
1763 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings);
1764 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
1765 base->duplex = DUPLEX_FULL;
1766 else
1767 base->duplex = DUPLEX_HALF;
1768 }
1769 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
1770 } else {
1771 base->autoneg = AUTONEG_DISABLE;
1772 ethtool_speed =
1773 bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
1774 base->duplex = DUPLEX_HALF;
1775 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
1776 base->duplex = DUPLEX_FULL;
1777 }
1778 base->speed = ethtool_speed;
1779
1780 base->port = PORT_NONE;
1781 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1782 base->port = PORT_TP;
1783 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1784 TP);
1785 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1786 TP);
1787 } else {
1788 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1789 FIBRE);
1790 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1791 FIBRE);
1792
1793 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
1794 base->port = PORT_DA;
1795 else if (link_info->media_type ==
1796 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE)
1797 base->port = PORT_FIBRE;
1798 }
1799 base->phy_address = link_info->phy_addr;
1800 mutex_unlock(&bp->link_lock);
1801
1802 return 0;
1803 }
1804
bnxt_force_link_speed(struct net_device * dev,u32 ethtool_speed)1805 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed)
1806 {
1807 struct bnxt *bp = netdev_priv(dev);
1808 struct bnxt_link_info *link_info = &bp->link_info;
1809 u16 support_pam4_spds = link_info->support_pam4_speeds;
1810 u16 support_spds = link_info->support_speeds;
1811 u8 sig_mode = BNXT_SIG_MODE_NRZ;
1812 u16 fw_speed = 0;
1813
1814 switch (ethtool_speed) {
1815 case SPEED_100:
1816 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
1817 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
1818 break;
1819 case SPEED_1000:
1820 if (support_spds & BNXT_LINK_SPEED_MSK_1GB)
1821 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
1822 break;
1823 case SPEED_2500:
1824 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
1825 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
1826 break;
1827 case SPEED_10000:
1828 if (support_spds & BNXT_LINK_SPEED_MSK_10GB)
1829 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
1830 break;
1831 case SPEED_20000:
1832 if (support_spds & BNXT_LINK_SPEED_MSK_20GB)
1833 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
1834 break;
1835 case SPEED_25000:
1836 if (support_spds & BNXT_LINK_SPEED_MSK_25GB)
1837 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
1838 break;
1839 case SPEED_40000:
1840 if (support_spds & BNXT_LINK_SPEED_MSK_40GB)
1841 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
1842 break;
1843 case SPEED_50000:
1844 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) {
1845 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
1846 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
1847 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
1848 sig_mode = BNXT_SIG_MODE_PAM4;
1849 }
1850 break;
1851 case SPEED_100000:
1852 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) {
1853 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
1854 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
1855 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
1856 sig_mode = BNXT_SIG_MODE_PAM4;
1857 }
1858 break;
1859 case SPEED_200000:
1860 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
1861 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
1862 sig_mode = BNXT_SIG_MODE_PAM4;
1863 }
1864 break;
1865 }
1866
1867 if (!fw_speed) {
1868 netdev_err(dev, "unsupported speed!\n");
1869 return -EINVAL;
1870 }
1871
1872 if (link_info->req_link_speed == fw_speed &&
1873 link_info->req_signal_mode == sig_mode &&
1874 link_info->autoneg == 0)
1875 return -EALREADY;
1876
1877 link_info->req_link_speed = fw_speed;
1878 link_info->req_signal_mode = sig_mode;
1879 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
1880 link_info->autoneg = 0;
1881 link_info->advertising = 0;
1882 link_info->advertising_pam4 = 0;
1883
1884 return 0;
1885 }
1886
bnxt_get_fw_auto_link_speeds(u32 advertising)1887 u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
1888 {
1889 u16 fw_speed_mask = 0;
1890
1891 /* only support autoneg at speed 100, 1000, and 10000 */
1892 if (advertising & (ADVERTISED_100baseT_Full |
1893 ADVERTISED_100baseT_Half)) {
1894 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
1895 }
1896 if (advertising & (ADVERTISED_1000baseT_Full |
1897 ADVERTISED_1000baseT_Half)) {
1898 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
1899 }
1900 if (advertising & ADVERTISED_10000baseT_Full)
1901 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
1902
1903 if (advertising & ADVERTISED_40000baseCR4_Full)
1904 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
1905
1906 return fw_speed_mask;
1907 }
1908
bnxt_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * lk_ksettings)1909 static int bnxt_set_link_ksettings(struct net_device *dev,
1910 const struct ethtool_link_ksettings *lk_ksettings)
1911 {
1912 struct bnxt *bp = netdev_priv(dev);
1913 struct bnxt_link_info *link_info = &bp->link_info;
1914 const struct ethtool_link_settings *base = &lk_ksettings->base;
1915 bool set_pause = false;
1916 u32 speed;
1917 int rc = 0;
1918
1919 if (!BNXT_PHY_CFG_ABLE(bp))
1920 return -EOPNOTSUPP;
1921
1922 mutex_lock(&bp->link_lock);
1923 if (base->autoneg == AUTONEG_ENABLE) {
1924 link_info->advertising = 0;
1925 link_info->advertising_pam4 = 0;
1926 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings,
1927 advertising);
1928 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4,
1929 lk_ksettings, advertising);
1930 link_info->autoneg |= BNXT_AUTONEG_SPEED;
1931 if (!link_info->advertising && !link_info->advertising_pam4) {
1932 link_info->advertising = link_info->support_auto_speeds;
1933 link_info->advertising_pam4 =
1934 link_info->support_pam4_auto_speeds;
1935 }
1936 /* any change to autoneg will cause link change, therefore the
1937 * driver should put back the original pause setting in autoneg
1938 */
1939 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
1940 set_pause = true;
1941 } else {
1942 u8 phy_type = link_info->phy_type;
1943
1944 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
1945 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
1946 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1947 netdev_err(dev, "10GBase-T devices must autoneg\n");
1948 rc = -EINVAL;
1949 goto set_setting_exit;
1950 }
1951 if (base->duplex == DUPLEX_HALF) {
1952 netdev_err(dev, "HALF DUPLEX is not supported!\n");
1953 rc = -EINVAL;
1954 goto set_setting_exit;
1955 }
1956 speed = base->speed;
1957 rc = bnxt_force_link_speed(dev, speed);
1958 if (rc) {
1959 if (rc == -EALREADY)
1960 rc = 0;
1961 goto set_setting_exit;
1962 }
1963 }
1964
1965 if (netif_running(dev))
1966 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
1967
1968 set_setting_exit:
1969 mutex_unlock(&bp->link_lock);
1970 return rc;
1971 }
1972
bnxt_get_fecparam(struct net_device * dev,struct ethtool_fecparam * fec)1973 static int bnxt_get_fecparam(struct net_device *dev,
1974 struct ethtool_fecparam *fec)
1975 {
1976 struct bnxt *bp = netdev_priv(dev);
1977 struct bnxt_link_info *link_info;
1978 u8 active_fec;
1979 u16 fec_cfg;
1980
1981 link_info = &bp->link_info;
1982 fec_cfg = link_info->fec_cfg;
1983 active_fec = link_info->active_fec_sig_mode &
1984 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
1985 if (fec_cfg & BNXT_FEC_NONE) {
1986 fec->fec = ETHTOOL_FEC_NONE;
1987 fec->active_fec = ETHTOOL_FEC_NONE;
1988 return 0;
1989 }
1990 if (fec_cfg & BNXT_FEC_AUTONEG)
1991 fec->fec |= ETHTOOL_FEC_AUTO;
1992 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1993 fec->fec |= ETHTOOL_FEC_BASER;
1994 if (fec_cfg & BNXT_FEC_ENC_RS)
1995 fec->fec |= ETHTOOL_FEC_RS;
1996 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1997 fec->fec |= ETHTOOL_FEC_LLRS;
1998
1999 switch (active_fec) {
2000 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
2001 fec->active_fec |= ETHTOOL_FEC_BASER;
2002 break;
2003 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
2004 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
2005 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
2006 fec->active_fec |= ETHTOOL_FEC_RS;
2007 break;
2008 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
2009 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
2010 fec->active_fec |= ETHTOOL_FEC_LLRS;
2011 break;
2012 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
2013 fec->active_fec |= ETHTOOL_FEC_OFF;
2014 break;
2015 }
2016 return 0;
2017 }
2018
bnxt_get_fec_stats(struct net_device * dev,struct ethtool_fec_stats * fec_stats)2019 static void bnxt_get_fec_stats(struct net_device *dev,
2020 struct ethtool_fec_stats *fec_stats)
2021 {
2022 struct bnxt *bp = netdev_priv(dev);
2023 u64 *rx;
2024
2025 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
2026 return;
2027
2028 rx = bp->rx_port_stats_ext.sw_stats;
2029 fec_stats->corrected_bits.total =
2030 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits));
2031
2032 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY)
2033 return;
2034
2035 fec_stats->corrected_blocks.total =
2036 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks));
2037 fec_stats->uncorrectable_blocks.total =
2038 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks));
2039 }
2040
bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info * link_info,u32 fec)2041 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
2042 u32 fec)
2043 {
2044 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
2045
2046 if (fec & ETHTOOL_FEC_BASER)
2047 fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
2048 else if (fec & ETHTOOL_FEC_RS)
2049 fw_fec |= BNXT_FEC_RS_ON(link_info);
2050 else if (fec & ETHTOOL_FEC_LLRS)
2051 fw_fec |= BNXT_FEC_LLRS_ON;
2052 return fw_fec;
2053 }
2054
bnxt_set_fecparam(struct net_device * dev,struct ethtool_fecparam * fecparam)2055 static int bnxt_set_fecparam(struct net_device *dev,
2056 struct ethtool_fecparam *fecparam)
2057 {
2058 struct hwrm_port_phy_cfg_input *req;
2059 struct bnxt *bp = netdev_priv(dev);
2060 struct bnxt_link_info *link_info;
2061 u32 new_cfg, fec = fecparam->fec;
2062 u16 fec_cfg;
2063 int rc;
2064
2065 link_info = &bp->link_info;
2066 fec_cfg = link_info->fec_cfg;
2067 if (fec_cfg & BNXT_FEC_NONE)
2068 return -EOPNOTSUPP;
2069
2070 if (fec & ETHTOOL_FEC_OFF) {
2071 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
2072 BNXT_FEC_ALL_OFF(link_info);
2073 goto apply_fec;
2074 }
2075 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
2076 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
2077 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
2078 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
2079 return -EINVAL;
2080
2081 if (fec & ETHTOOL_FEC_AUTO) {
2082 if (!link_info->autoneg)
2083 return -EINVAL;
2084 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
2085 } else {
2086 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
2087 }
2088
2089 apply_fec:
2090 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
2091 if (rc)
2092 return rc;
2093 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
2094 rc = hwrm_req_send(bp, req);
2095 /* update current settings */
2096 if (!rc) {
2097 mutex_lock(&bp->link_lock);
2098 bnxt_update_link(bp, false);
2099 mutex_unlock(&bp->link_lock);
2100 }
2101 return rc;
2102 }
2103
bnxt_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)2104 static void bnxt_get_pauseparam(struct net_device *dev,
2105 struct ethtool_pauseparam *epause)
2106 {
2107 struct bnxt *bp = netdev_priv(dev);
2108 struct bnxt_link_info *link_info = &bp->link_info;
2109
2110 if (BNXT_VF(bp))
2111 return;
2112 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
2113 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
2114 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
2115 }
2116
bnxt_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * epstat)2117 static void bnxt_get_pause_stats(struct net_device *dev,
2118 struct ethtool_pause_stats *epstat)
2119 {
2120 struct bnxt *bp = netdev_priv(dev);
2121 u64 *rx, *tx;
2122
2123 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
2124 return;
2125
2126 rx = bp->port_stats.sw_stats;
2127 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
2128
2129 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
2130 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
2131 }
2132
bnxt_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)2133 static int bnxt_set_pauseparam(struct net_device *dev,
2134 struct ethtool_pauseparam *epause)
2135 {
2136 int rc = 0;
2137 struct bnxt *bp = netdev_priv(dev);
2138 struct bnxt_link_info *link_info = &bp->link_info;
2139
2140 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
2141 return -EOPNOTSUPP;
2142
2143 mutex_lock(&bp->link_lock);
2144 if (epause->autoneg) {
2145 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2146 rc = -EINVAL;
2147 goto pause_exit;
2148 }
2149
2150 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
2151 link_info->req_flow_ctrl = 0;
2152 } else {
2153 /* when transition from auto pause to force pause,
2154 * force a link change
2155 */
2156 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2157 link_info->force_link_chng = true;
2158 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
2159 link_info->req_flow_ctrl = 0;
2160 }
2161 if (epause->rx_pause)
2162 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
2163
2164 if (epause->tx_pause)
2165 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
2166
2167 if (netif_running(dev))
2168 rc = bnxt_hwrm_set_pause(bp);
2169
2170 pause_exit:
2171 mutex_unlock(&bp->link_lock);
2172 return rc;
2173 }
2174
bnxt_get_link(struct net_device * dev)2175 static u32 bnxt_get_link(struct net_device *dev)
2176 {
2177 struct bnxt *bp = netdev_priv(dev);
2178
2179 /* TODO: handle MF, VF, driver close case */
2180 return BNXT_LINK_IS_UP(bp);
2181 }
2182
bnxt_hwrm_nvm_get_dev_info(struct bnxt * bp,struct hwrm_nvm_get_dev_info_output * nvm_dev_info)2183 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
2184 struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
2185 {
2186 struct hwrm_nvm_get_dev_info_output *resp;
2187 struct hwrm_nvm_get_dev_info_input *req;
2188 int rc;
2189
2190 if (BNXT_VF(bp))
2191 return -EOPNOTSUPP;
2192
2193 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO);
2194 if (rc)
2195 return rc;
2196
2197 resp = hwrm_req_hold(bp, req);
2198 rc = hwrm_req_send(bp, req);
2199 if (!rc)
2200 memcpy(nvm_dev_info, resp, sizeof(*resp));
2201 hwrm_req_drop(bp, req);
2202 return rc;
2203 }
2204
bnxt_print_admin_err(struct bnxt * bp)2205 static void bnxt_print_admin_err(struct bnxt *bp)
2206 {
2207 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
2208 }
2209
2210 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2211 u16 ext, u16 *index, u32 *item_length,
2212 u32 *data_length);
2213
bnxt_flash_nvram(struct net_device * dev,u16 dir_type,u16 dir_ordinal,u16 dir_ext,u16 dir_attr,u32 dir_item_len,const u8 * data,size_t data_len)2214 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
2215 u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
2216 u32 dir_item_len, const u8 *data,
2217 size_t data_len)
2218 {
2219 struct bnxt *bp = netdev_priv(dev);
2220 struct hwrm_nvm_write_input *req;
2221 int rc;
2222
2223 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE);
2224 if (rc)
2225 return rc;
2226
2227 if (data_len && data) {
2228 dma_addr_t dma_handle;
2229 u8 *kmem;
2230
2231 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle);
2232 if (!kmem) {
2233 hwrm_req_drop(bp, req);
2234 return -ENOMEM;
2235 }
2236
2237 req->dir_data_length = cpu_to_le32(data_len);
2238
2239 memcpy(kmem, data, data_len);
2240 req->host_src_addr = cpu_to_le64(dma_handle);
2241 }
2242
2243 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
2244 req->dir_type = cpu_to_le16(dir_type);
2245 req->dir_ordinal = cpu_to_le16(dir_ordinal);
2246 req->dir_ext = cpu_to_le16(dir_ext);
2247 req->dir_attr = cpu_to_le16(dir_attr);
2248 req->dir_item_length = cpu_to_le32(dir_item_len);
2249 rc = hwrm_req_send(bp, req);
2250
2251 if (rc == -EACCES)
2252 bnxt_print_admin_err(bp);
2253 return rc;
2254 }
2255
bnxt_hwrm_firmware_reset(struct net_device * dev,u8 proc_type,u8 self_reset,u8 flags)2256 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
2257 u8 self_reset, u8 flags)
2258 {
2259 struct bnxt *bp = netdev_priv(dev);
2260 struct hwrm_fw_reset_input *req;
2261 int rc;
2262
2263 if (!bnxt_hwrm_reset_permitted(bp)) {
2264 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver");
2265 return -EPERM;
2266 }
2267
2268 rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
2269 if (rc)
2270 return rc;
2271
2272 req->embedded_proc_type = proc_type;
2273 req->selfrst_status = self_reset;
2274 req->flags = flags;
2275
2276 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
2277 rc = hwrm_req_send_silent(bp, req);
2278 } else {
2279 rc = hwrm_req_send(bp, req);
2280 if (rc == -EACCES)
2281 bnxt_print_admin_err(bp);
2282 }
2283 return rc;
2284 }
2285
bnxt_firmware_reset(struct net_device * dev,enum bnxt_nvm_directory_type dir_type)2286 static int bnxt_firmware_reset(struct net_device *dev,
2287 enum bnxt_nvm_directory_type dir_type)
2288 {
2289 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
2290 u8 proc_type, flags = 0;
2291
2292 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
2293 /* (e.g. when firmware isn't already running) */
2294 switch (dir_type) {
2295 case BNX_DIR_TYPE_CHIMP_PATCH:
2296 case BNX_DIR_TYPE_BOOTCODE:
2297 case BNX_DIR_TYPE_BOOTCODE_2:
2298 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
2299 /* Self-reset ChiMP upon next PCIe reset: */
2300 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2301 break;
2302 case BNX_DIR_TYPE_APE_FW:
2303 case BNX_DIR_TYPE_APE_PATCH:
2304 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
2305 /* Self-reset APE upon next PCIe reset: */
2306 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2307 break;
2308 case BNX_DIR_TYPE_KONG_FW:
2309 case BNX_DIR_TYPE_KONG_PATCH:
2310 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
2311 break;
2312 case BNX_DIR_TYPE_BONO_FW:
2313 case BNX_DIR_TYPE_BONO_PATCH:
2314 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
2315 break;
2316 default:
2317 return -EINVAL;
2318 }
2319
2320 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
2321 }
2322
bnxt_firmware_reset_chip(struct net_device * dev)2323 static int bnxt_firmware_reset_chip(struct net_device *dev)
2324 {
2325 struct bnxt *bp = netdev_priv(dev);
2326 u8 flags = 0;
2327
2328 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
2329 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
2330
2331 return bnxt_hwrm_firmware_reset(dev,
2332 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
2333 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
2334 flags);
2335 }
2336
bnxt_firmware_reset_ap(struct net_device * dev)2337 static int bnxt_firmware_reset_ap(struct net_device *dev)
2338 {
2339 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
2340 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
2341 0);
2342 }
2343
bnxt_flash_firmware(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)2344 static int bnxt_flash_firmware(struct net_device *dev,
2345 u16 dir_type,
2346 const u8 *fw_data,
2347 size_t fw_size)
2348 {
2349 int rc = 0;
2350 u16 code_type;
2351 u32 stored_crc;
2352 u32 calculated_crc;
2353 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
2354
2355 switch (dir_type) {
2356 case BNX_DIR_TYPE_BOOTCODE:
2357 case BNX_DIR_TYPE_BOOTCODE_2:
2358 code_type = CODE_BOOT;
2359 break;
2360 case BNX_DIR_TYPE_CHIMP_PATCH:
2361 code_type = CODE_CHIMP_PATCH;
2362 break;
2363 case BNX_DIR_TYPE_APE_FW:
2364 code_type = CODE_MCTP_PASSTHRU;
2365 break;
2366 case BNX_DIR_TYPE_APE_PATCH:
2367 code_type = CODE_APE_PATCH;
2368 break;
2369 case BNX_DIR_TYPE_KONG_FW:
2370 code_type = CODE_KONG_FW;
2371 break;
2372 case BNX_DIR_TYPE_KONG_PATCH:
2373 code_type = CODE_KONG_PATCH;
2374 break;
2375 case BNX_DIR_TYPE_BONO_FW:
2376 code_type = CODE_BONO_FW;
2377 break;
2378 case BNX_DIR_TYPE_BONO_PATCH:
2379 code_type = CODE_BONO_PATCH;
2380 break;
2381 default:
2382 netdev_err(dev, "Unsupported directory entry type: %u\n",
2383 dir_type);
2384 return -EINVAL;
2385 }
2386 if (fw_size < sizeof(struct bnxt_fw_header)) {
2387 netdev_err(dev, "Invalid firmware file size: %u\n",
2388 (unsigned int)fw_size);
2389 return -EINVAL;
2390 }
2391 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
2392 netdev_err(dev, "Invalid firmware signature: %08X\n",
2393 le32_to_cpu(header->signature));
2394 return -EINVAL;
2395 }
2396 if (header->code_type != code_type) {
2397 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
2398 code_type, header->code_type);
2399 return -EINVAL;
2400 }
2401 if (header->device != DEVICE_CUMULUS_FAMILY) {
2402 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
2403 DEVICE_CUMULUS_FAMILY, header->device);
2404 return -EINVAL;
2405 }
2406 /* Confirm the CRC32 checksum of the file: */
2407 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2408 sizeof(stored_crc)));
2409 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2410 if (calculated_crc != stored_crc) {
2411 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
2412 (unsigned long)stored_crc,
2413 (unsigned long)calculated_crc);
2414 return -EINVAL;
2415 }
2416 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2417 0, 0, 0, fw_data, fw_size);
2418 if (rc == 0) /* Firmware update successful */
2419 rc = bnxt_firmware_reset(dev, dir_type);
2420
2421 return rc;
2422 }
2423
bnxt_flash_microcode(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)2424 static int bnxt_flash_microcode(struct net_device *dev,
2425 u16 dir_type,
2426 const u8 *fw_data,
2427 size_t fw_size)
2428 {
2429 struct bnxt_ucode_trailer *trailer;
2430 u32 calculated_crc;
2431 u32 stored_crc;
2432 int rc = 0;
2433
2434 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
2435 netdev_err(dev, "Invalid microcode file size: %u\n",
2436 (unsigned int)fw_size);
2437 return -EINVAL;
2438 }
2439 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
2440 sizeof(*trailer)));
2441 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
2442 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
2443 le32_to_cpu(trailer->sig));
2444 return -EINVAL;
2445 }
2446 if (le16_to_cpu(trailer->dir_type) != dir_type) {
2447 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
2448 dir_type, le16_to_cpu(trailer->dir_type));
2449 return -EINVAL;
2450 }
2451 if (le16_to_cpu(trailer->trailer_length) <
2452 sizeof(struct bnxt_ucode_trailer)) {
2453 netdev_err(dev, "Invalid microcode trailer length: %d\n",
2454 le16_to_cpu(trailer->trailer_length));
2455 return -EINVAL;
2456 }
2457
2458 /* Confirm the CRC32 checksum of the file: */
2459 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2460 sizeof(stored_crc)));
2461 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2462 if (calculated_crc != stored_crc) {
2463 netdev_err(dev,
2464 "CRC32 (%08lX) does not match calculated: %08lX\n",
2465 (unsigned long)stored_crc,
2466 (unsigned long)calculated_crc);
2467 return -EINVAL;
2468 }
2469 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2470 0, 0, 0, fw_data, fw_size);
2471
2472 return rc;
2473 }
2474
bnxt_dir_type_is_ape_bin_format(u16 dir_type)2475 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
2476 {
2477 switch (dir_type) {
2478 case BNX_DIR_TYPE_CHIMP_PATCH:
2479 case BNX_DIR_TYPE_BOOTCODE:
2480 case BNX_DIR_TYPE_BOOTCODE_2:
2481 case BNX_DIR_TYPE_APE_FW:
2482 case BNX_DIR_TYPE_APE_PATCH:
2483 case BNX_DIR_TYPE_KONG_FW:
2484 case BNX_DIR_TYPE_KONG_PATCH:
2485 case BNX_DIR_TYPE_BONO_FW:
2486 case BNX_DIR_TYPE_BONO_PATCH:
2487 return true;
2488 }
2489
2490 return false;
2491 }
2492
bnxt_dir_type_is_other_exec_format(u16 dir_type)2493 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
2494 {
2495 switch (dir_type) {
2496 case BNX_DIR_TYPE_AVS:
2497 case BNX_DIR_TYPE_EXP_ROM_MBA:
2498 case BNX_DIR_TYPE_PCIE:
2499 case BNX_DIR_TYPE_TSCF_UCODE:
2500 case BNX_DIR_TYPE_EXT_PHY:
2501 case BNX_DIR_TYPE_CCM:
2502 case BNX_DIR_TYPE_ISCSI_BOOT:
2503 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2504 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2505 return true;
2506 }
2507
2508 return false;
2509 }
2510
bnxt_dir_type_is_executable(u16 dir_type)2511 static bool bnxt_dir_type_is_executable(u16 dir_type)
2512 {
2513 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2514 bnxt_dir_type_is_other_exec_format(dir_type);
2515 }
2516
bnxt_flash_firmware_from_file(struct net_device * dev,u16 dir_type,const char * filename)2517 static int bnxt_flash_firmware_from_file(struct net_device *dev,
2518 u16 dir_type,
2519 const char *filename)
2520 {
2521 const struct firmware *fw;
2522 int rc;
2523
2524 rc = request_firmware(&fw, filename, &dev->dev);
2525 if (rc != 0) {
2526 netdev_err(dev, "Error %d requesting firmware file: %s\n",
2527 rc, filename);
2528 return rc;
2529 }
2530 if (bnxt_dir_type_is_ape_bin_format(dir_type))
2531 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
2532 else if (bnxt_dir_type_is_other_exec_format(dir_type))
2533 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
2534 else
2535 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2536 0, 0, 0, fw->data, fw->size);
2537 release_firmware(fw);
2538 return rc;
2539 }
2540
2541 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM"
2542 #define MSG_INVALID_PKG "PKG install error : Invalid package"
2543 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error"
2544 #define MSG_INVALID_DEV "PKG install error : Invalid device"
2545 #define MSG_INTERNAL_ERR "PKG install error : Internal error"
2546 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram"
2547 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram"
2548 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error"
2549 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected"
2550 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure"
2551
nvm_update_err_to_stderr(struct net_device * dev,u8 result,struct netlink_ext_ack * extack)2552 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result,
2553 struct netlink_ext_ack *extack)
2554 {
2555 switch (result) {
2556 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER:
2557 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER:
2558 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR:
2559 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR:
2560 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND:
2561 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED:
2562 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR);
2563 return -EINVAL;
2564 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE:
2565 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER:
2566 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE:
2567 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM:
2568 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH:
2569 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST:
2570 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER:
2571 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM:
2572 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM:
2573 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH:
2574 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE:
2575 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM:
2576 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM:
2577 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG);
2578 return -ENOPKG;
2579 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR:
2580 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR);
2581 return -EPERM;
2582 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV:
2583 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID:
2584 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR:
2585 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID:
2586 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM:
2587 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV);
2588 return -EOPNOTSUPP;
2589 default:
2590 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR);
2591 return -EIO;
2592 }
2593 }
2594
2595 #define BNXT_PKG_DMA_SIZE 0x40000
2596 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE))
2597 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST))
2598
bnxt_resize_update_entry(struct net_device * dev,size_t fw_size,struct netlink_ext_ack * extack)2599 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size,
2600 struct netlink_ext_ack *extack)
2601 {
2602 u32 item_len;
2603 int rc;
2604
2605 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
2606 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL,
2607 &item_len, NULL);
2608 if (rc) {
2609 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
2610 return rc;
2611 }
2612
2613 if (fw_size > item_len) {
2614 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE,
2615 BNX_DIR_ORDINAL_FIRST, 0, 1,
2616 round_up(fw_size, 4096), NULL, 0);
2617 if (rc) {
2618 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR);
2619 return rc;
2620 }
2621 }
2622 return 0;
2623 }
2624
bnxt_flash_package_from_fw_obj(struct net_device * dev,const struct firmware * fw,u32 install_type,struct netlink_ext_ack * extack)2625 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw,
2626 u32 install_type, struct netlink_ext_ack *extack)
2627 {
2628 struct hwrm_nvm_install_update_input *install;
2629 struct hwrm_nvm_install_update_output *resp;
2630 struct hwrm_nvm_modify_input *modify;
2631 struct bnxt *bp = netdev_priv(dev);
2632 bool defrag_attempted = false;
2633 dma_addr_t dma_handle;
2634 u8 *kmem = NULL;
2635 u32 modify_len;
2636 u32 item_len;
2637 u8 cmd_err;
2638 u16 index;
2639 int rc;
2640
2641 /* resize before flashing larger image than available space */
2642 rc = bnxt_resize_update_entry(dev, fw->size, extack);
2643 if (rc)
2644 return rc;
2645
2646 bnxt_hwrm_fw_set_time(bp);
2647
2648 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY);
2649 if (rc)
2650 return rc;
2651
2652 /* Try allocating a large DMA buffer first. Older fw will
2653 * cause excessive NVRAM erases when using small blocks.
2654 */
2655 modify_len = roundup_pow_of_two(fw->size);
2656 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE);
2657 while (1) {
2658 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle);
2659 if (!kmem && modify_len > PAGE_SIZE)
2660 modify_len /= 2;
2661 else
2662 break;
2663 }
2664 if (!kmem) {
2665 hwrm_req_drop(bp, modify);
2666 return -ENOMEM;
2667 }
2668
2669 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE);
2670 if (rc) {
2671 hwrm_req_drop(bp, modify);
2672 return rc;
2673 }
2674
2675 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout);
2676 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout);
2677
2678 hwrm_req_hold(bp, modify);
2679 modify->host_src_addr = cpu_to_le64(dma_handle);
2680
2681 resp = hwrm_req_hold(bp, install);
2682 if ((install_type & 0xffff) == 0)
2683 install_type >>= 16;
2684 install->install_type = cpu_to_le32(install_type);
2685
2686 do {
2687 u32 copied = 0, len = modify_len;
2688
2689 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
2690 BNX_DIR_ORDINAL_FIRST,
2691 BNX_DIR_EXT_NONE,
2692 &index, &item_len, NULL);
2693 if (rc) {
2694 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
2695 break;
2696 }
2697 if (fw->size > item_len) {
2698 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR);
2699 rc = -EFBIG;
2700 break;
2701 }
2702
2703 modify->dir_idx = cpu_to_le16(index);
2704
2705 if (fw->size > modify_len)
2706 modify->flags = BNXT_NVM_MORE_FLAG;
2707 while (copied < fw->size) {
2708 u32 balance = fw->size - copied;
2709
2710 if (balance <= modify_len) {
2711 len = balance;
2712 if (copied)
2713 modify->flags |= BNXT_NVM_LAST_FLAG;
2714 }
2715 memcpy(kmem, fw->data + copied, len);
2716 modify->len = cpu_to_le32(len);
2717 modify->offset = cpu_to_le32(copied);
2718 rc = hwrm_req_send(bp, modify);
2719 if (rc)
2720 goto pkg_abort;
2721 copied += len;
2722 }
2723
2724 rc = hwrm_req_send_silent(bp, install);
2725 if (!rc)
2726 break;
2727
2728 if (defrag_attempted) {
2729 /* We have tried to defragment already in the previous
2730 * iteration. Return with the result for INSTALL_UPDATE
2731 */
2732 break;
2733 }
2734
2735 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
2736
2737 switch (cmd_err) {
2738 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK:
2739 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR);
2740 rc = -EALREADY;
2741 break;
2742 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR:
2743 install->flags =
2744 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
2745
2746 rc = hwrm_req_send_silent(bp, install);
2747 if (!rc)
2748 break;
2749
2750 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
2751
2752 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) {
2753 /* FW has cleared NVM area, driver will create
2754 * UPDATE directory and try the flash again
2755 */
2756 defrag_attempted = true;
2757 install->flags = 0;
2758 rc = bnxt_flash_nvram(bp->dev,
2759 BNX_DIR_TYPE_UPDATE,
2760 BNX_DIR_ORDINAL_FIRST,
2761 0, 0, item_len, NULL, 0);
2762 if (!rc)
2763 break;
2764 }
2765 fallthrough;
2766 default:
2767 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR);
2768 }
2769 } while (defrag_attempted && !rc);
2770
2771 pkg_abort:
2772 hwrm_req_drop(bp, modify);
2773 hwrm_req_drop(bp, install);
2774
2775 if (resp->result) {
2776 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
2777 (s8)resp->result, (int)resp->problem_item);
2778 rc = nvm_update_err_to_stderr(dev, resp->result, extack);
2779 }
2780 if (rc == -EACCES)
2781 bnxt_print_admin_err(bp);
2782 return rc;
2783 }
2784
bnxt_flash_package_from_file(struct net_device * dev,const char * filename,u32 install_type,struct netlink_ext_ack * extack)2785 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
2786 u32 install_type, struct netlink_ext_ack *extack)
2787 {
2788 const struct firmware *fw;
2789 int rc;
2790
2791 rc = request_firmware(&fw, filename, &dev->dev);
2792 if (rc != 0) {
2793 netdev_err(dev, "PKG error %d requesting file: %s\n",
2794 rc, filename);
2795 return rc;
2796 }
2797
2798 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack);
2799
2800 release_firmware(fw);
2801
2802 return rc;
2803 }
2804
bnxt_flash_device(struct net_device * dev,struct ethtool_flash * flash)2805 static int bnxt_flash_device(struct net_device *dev,
2806 struct ethtool_flash *flash)
2807 {
2808 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
2809 netdev_err(dev, "flashdev not supported from a virtual function\n");
2810 return -EINVAL;
2811 }
2812
2813 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
2814 flash->region > 0xffff)
2815 return bnxt_flash_package_from_file(dev, flash->data,
2816 flash->region, NULL);
2817
2818 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
2819 }
2820
nvm_get_dir_info(struct net_device * dev,u32 * entries,u32 * length)2821 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
2822 {
2823 struct hwrm_nvm_get_dir_info_output *output;
2824 struct hwrm_nvm_get_dir_info_input *req;
2825 struct bnxt *bp = netdev_priv(dev);
2826 int rc;
2827
2828 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO);
2829 if (rc)
2830 return rc;
2831
2832 output = hwrm_req_hold(bp, req);
2833 rc = hwrm_req_send(bp, req);
2834 if (!rc) {
2835 *entries = le32_to_cpu(output->entries);
2836 *length = le32_to_cpu(output->entry_length);
2837 }
2838 hwrm_req_drop(bp, req);
2839 return rc;
2840 }
2841
bnxt_get_eeprom_len(struct net_device * dev)2842 static int bnxt_get_eeprom_len(struct net_device *dev)
2843 {
2844 struct bnxt *bp = netdev_priv(dev);
2845
2846 if (BNXT_VF(bp))
2847 return 0;
2848
2849 /* The -1 return value allows the entire 32-bit range of offsets to be
2850 * passed via the ethtool command-line utility.
2851 */
2852 return -1;
2853 }
2854
bnxt_get_nvram_directory(struct net_device * dev,u32 len,u8 * data)2855 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
2856 {
2857 struct bnxt *bp = netdev_priv(dev);
2858 int rc;
2859 u32 dir_entries;
2860 u32 entry_length;
2861 u8 *buf;
2862 size_t buflen;
2863 dma_addr_t dma_handle;
2864 struct hwrm_nvm_get_dir_entries_input *req;
2865
2866 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
2867 if (rc != 0)
2868 return rc;
2869
2870 if (!dir_entries || !entry_length)
2871 return -EIO;
2872
2873 /* Insert 2 bytes of directory info (count and size of entries) */
2874 if (len < 2)
2875 return -EINVAL;
2876
2877 *data++ = dir_entries;
2878 *data++ = entry_length;
2879 len -= 2;
2880 memset(data, 0xff, len);
2881
2882 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES);
2883 if (rc)
2884 return rc;
2885
2886 buflen = mul_u32_u32(dir_entries, entry_length);
2887 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle);
2888 if (!buf) {
2889 hwrm_req_drop(bp, req);
2890 return -ENOMEM;
2891 }
2892 req->host_dest_addr = cpu_to_le64(dma_handle);
2893
2894 hwrm_req_hold(bp, req); /* hold the slice */
2895 rc = hwrm_req_send(bp, req);
2896 if (rc == 0)
2897 memcpy(data, buf, len > buflen ? buflen : len);
2898 hwrm_req_drop(bp, req);
2899 return rc;
2900 }
2901
bnxt_get_nvram_item(struct net_device * dev,u32 index,u32 offset,u32 length,u8 * data)2902 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
2903 u32 length, u8 *data)
2904 {
2905 struct bnxt *bp = netdev_priv(dev);
2906 int rc;
2907 u8 *buf;
2908 dma_addr_t dma_handle;
2909 struct hwrm_nvm_read_input *req;
2910
2911 if (!length)
2912 return -EINVAL;
2913
2914 rc = hwrm_req_init(bp, req, HWRM_NVM_READ);
2915 if (rc)
2916 return rc;
2917
2918 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle);
2919 if (!buf) {
2920 hwrm_req_drop(bp, req);
2921 return -ENOMEM;
2922 }
2923
2924 req->host_dest_addr = cpu_to_le64(dma_handle);
2925 req->dir_idx = cpu_to_le16(index);
2926 req->offset = cpu_to_le32(offset);
2927 req->len = cpu_to_le32(length);
2928
2929 hwrm_req_hold(bp, req); /* hold the slice */
2930 rc = hwrm_req_send(bp, req);
2931 if (rc == 0)
2932 memcpy(data, buf, length);
2933 hwrm_req_drop(bp, req);
2934 return rc;
2935 }
2936
bnxt_find_nvram_item(struct net_device * dev,u16 type,u16 ordinal,u16 ext,u16 * index,u32 * item_length,u32 * data_length)2937 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2938 u16 ext, u16 *index, u32 *item_length,
2939 u32 *data_length)
2940 {
2941 struct hwrm_nvm_find_dir_entry_output *output;
2942 struct hwrm_nvm_find_dir_entry_input *req;
2943 struct bnxt *bp = netdev_priv(dev);
2944 int rc;
2945
2946 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY);
2947 if (rc)
2948 return rc;
2949
2950 req->enables = 0;
2951 req->dir_idx = 0;
2952 req->dir_type = cpu_to_le16(type);
2953 req->dir_ordinal = cpu_to_le16(ordinal);
2954 req->dir_ext = cpu_to_le16(ext);
2955 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
2956 output = hwrm_req_hold(bp, req);
2957 rc = hwrm_req_send_silent(bp, req);
2958 if (rc == 0) {
2959 if (index)
2960 *index = le16_to_cpu(output->dir_idx);
2961 if (item_length)
2962 *item_length = le32_to_cpu(output->dir_item_length);
2963 if (data_length)
2964 *data_length = le32_to_cpu(output->dir_data_length);
2965 }
2966 hwrm_req_drop(bp, req);
2967 return rc;
2968 }
2969
bnxt_parse_pkglog(int desired_field,u8 * data,size_t datalen)2970 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
2971 {
2972 char *retval = NULL;
2973 char *p;
2974 char *value;
2975 int field = 0;
2976
2977 if (datalen < 1)
2978 return NULL;
2979 /* null-terminate the log data (removing last '\n'): */
2980 data[datalen - 1] = 0;
2981 for (p = data; *p != 0; p++) {
2982 field = 0;
2983 retval = NULL;
2984 while (*p != 0 && *p != '\n') {
2985 value = p;
2986 while (*p != 0 && *p != '\t' && *p != '\n')
2987 p++;
2988 if (field == desired_field)
2989 retval = value;
2990 if (*p != '\t')
2991 break;
2992 *p = 0;
2993 field++;
2994 p++;
2995 }
2996 if (*p == 0)
2997 break;
2998 *p = 0;
2999 }
3000 return retval;
3001 }
3002
bnxt_get_pkginfo(struct net_device * dev,char * ver,int size)3003 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size)
3004 {
3005 struct bnxt *bp = netdev_priv(dev);
3006 u16 index = 0;
3007 char *pkgver;
3008 u32 pkglen;
3009 u8 *pkgbuf;
3010 int rc;
3011
3012 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
3013 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
3014 &index, NULL, &pkglen);
3015 if (rc)
3016 return rc;
3017
3018 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
3019 if (!pkgbuf) {
3020 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
3021 pkglen);
3022 return -ENOMEM;
3023 }
3024
3025 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf);
3026 if (rc)
3027 goto err;
3028
3029 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
3030 pkglen);
3031 if (pkgver && *pkgver != 0 && isdigit(*pkgver))
3032 strscpy(ver, pkgver, size);
3033 else
3034 rc = -ENOENT;
3035
3036 err:
3037 kfree(pkgbuf);
3038
3039 return rc;
3040 }
3041
bnxt_get_pkgver(struct net_device * dev)3042 static void bnxt_get_pkgver(struct net_device *dev)
3043 {
3044 struct bnxt *bp = netdev_priv(dev);
3045 char buf[FW_VER_STR_LEN];
3046 int len;
3047
3048 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) {
3049 len = strlen(bp->fw_ver_str);
3050 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len,
3051 "/pkg %s", buf);
3052 }
3053 }
3054
bnxt_get_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)3055 static int bnxt_get_eeprom(struct net_device *dev,
3056 struct ethtool_eeprom *eeprom,
3057 u8 *data)
3058 {
3059 u32 index;
3060 u32 offset;
3061
3062 if (eeprom->offset == 0) /* special offset value to get directory */
3063 return bnxt_get_nvram_directory(dev, eeprom->len, data);
3064
3065 index = eeprom->offset >> 24;
3066 offset = eeprom->offset & 0xffffff;
3067
3068 if (index == 0) {
3069 netdev_err(dev, "unsupported index value: %d\n", index);
3070 return -EINVAL;
3071 }
3072
3073 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
3074 }
3075
bnxt_erase_nvram_directory(struct net_device * dev,u8 index)3076 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
3077 {
3078 struct hwrm_nvm_erase_dir_entry_input *req;
3079 struct bnxt *bp = netdev_priv(dev);
3080 int rc;
3081
3082 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY);
3083 if (rc)
3084 return rc;
3085
3086 req->dir_idx = cpu_to_le16(index);
3087 return hwrm_req_send(bp, req);
3088 }
3089
bnxt_set_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)3090 static int bnxt_set_eeprom(struct net_device *dev,
3091 struct ethtool_eeprom *eeprom,
3092 u8 *data)
3093 {
3094 struct bnxt *bp = netdev_priv(dev);
3095 u8 index, dir_op;
3096 u16 type, ext, ordinal, attr;
3097
3098 if (!BNXT_PF(bp)) {
3099 netdev_err(dev, "NVM write not supported from a virtual function\n");
3100 return -EINVAL;
3101 }
3102
3103 type = eeprom->magic >> 16;
3104
3105 if (type == 0xffff) { /* special value for directory operations */
3106 index = eeprom->magic & 0xff;
3107 dir_op = eeprom->magic >> 8;
3108 if (index == 0)
3109 return -EINVAL;
3110 switch (dir_op) {
3111 case 0x0e: /* erase */
3112 if (eeprom->offset != ~eeprom->magic)
3113 return -EINVAL;
3114 return bnxt_erase_nvram_directory(dev, index - 1);
3115 default:
3116 return -EINVAL;
3117 }
3118 }
3119
3120 /* Create or re-write an NVM item: */
3121 if (bnxt_dir_type_is_executable(type))
3122 return -EOPNOTSUPP;
3123 ext = eeprom->magic & 0xffff;
3124 ordinal = eeprom->offset >> 16;
3125 attr = eeprom->offset & 0xffff;
3126
3127 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data,
3128 eeprom->len);
3129 }
3130
bnxt_set_eee(struct net_device * dev,struct ethtool_eee * edata)3131 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata)
3132 {
3133 struct bnxt *bp = netdev_priv(dev);
3134 struct ethtool_eee *eee = &bp->eee;
3135 struct bnxt_link_info *link_info = &bp->link_info;
3136 u32 advertising;
3137 int rc = 0;
3138
3139 if (!BNXT_PHY_CFG_ABLE(bp))
3140 return -EOPNOTSUPP;
3141
3142 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
3143 return -EOPNOTSUPP;
3144
3145 mutex_lock(&bp->link_lock);
3146 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
3147 if (!edata->eee_enabled)
3148 goto eee_ok;
3149
3150 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
3151 netdev_warn(dev, "EEE requires autoneg\n");
3152 rc = -EINVAL;
3153 goto eee_exit;
3154 }
3155 if (edata->tx_lpi_enabled) {
3156 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
3157 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
3158 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
3159 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
3160 rc = -EINVAL;
3161 goto eee_exit;
3162 } else if (!bp->lpi_tmr_hi) {
3163 edata->tx_lpi_timer = eee->tx_lpi_timer;
3164 }
3165 }
3166 if (!edata->advertised) {
3167 edata->advertised = advertising & eee->supported;
3168 } else if (edata->advertised & ~advertising) {
3169 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
3170 edata->advertised, advertising);
3171 rc = -EINVAL;
3172 goto eee_exit;
3173 }
3174
3175 eee->advertised = edata->advertised;
3176 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
3177 eee->tx_lpi_timer = edata->tx_lpi_timer;
3178 eee_ok:
3179 eee->eee_enabled = edata->eee_enabled;
3180
3181 if (netif_running(dev))
3182 rc = bnxt_hwrm_set_link_setting(bp, false, true);
3183
3184 eee_exit:
3185 mutex_unlock(&bp->link_lock);
3186 return rc;
3187 }
3188
bnxt_get_eee(struct net_device * dev,struct ethtool_eee * edata)3189 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata)
3190 {
3191 struct bnxt *bp = netdev_priv(dev);
3192
3193 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
3194 return -EOPNOTSUPP;
3195
3196 *edata = bp->eee;
3197 if (!bp->eee.eee_enabled) {
3198 /* Preserve tx_lpi_timer so that the last value will be used
3199 * by default when it is re-enabled.
3200 */
3201 edata->advertised = 0;
3202 edata->tx_lpi_enabled = 0;
3203 }
3204
3205 if (!bp->eee.eee_active)
3206 edata->lp_advertised = 0;
3207
3208 return 0;
3209 }
3210
bnxt_read_sfp_module_eeprom_info(struct bnxt * bp,u16 i2c_addr,u16 page_number,u8 bank,u16 start_addr,u16 data_length,u8 * buf)3211 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
3212 u16 page_number, u8 bank,
3213 u16 start_addr, u16 data_length,
3214 u8 *buf)
3215 {
3216 struct hwrm_port_phy_i2c_read_output *output;
3217 struct hwrm_port_phy_i2c_read_input *req;
3218 int rc, byte_offset = 0;
3219
3220 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ);
3221 if (rc)
3222 return rc;
3223
3224 output = hwrm_req_hold(bp, req);
3225 req->i2c_slave_addr = i2c_addr;
3226 req->page_number = cpu_to_le16(page_number);
3227 req->port_id = cpu_to_le16(bp->pf.port_id);
3228 do {
3229 u16 xfer_size;
3230
3231 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
3232 data_length -= xfer_size;
3233 req->page_offset = cpu_to_le16(start_addr + byte_offset);
3234 req->data_length = xfer_size;
3235 req->enables =
3236 cpu_to_le32((start_addr + byte_offset ?
3237 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET :
3238 0) |
3239 (bank ?
3240 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER :
3241 0));
3242 rc = hwrm_req_send(bp, req);
3243 if (!rc)
3244 memcpy(buf + byte_offset, output->data, xfer_size);
3245 byte_offset += xfer_size;
3246 } while (!rc && data_length > 0);
3247 hwrm_req_drop(bp, req);
3248
3249 return rc;
3250 }
3251
bnxt_get_module_info(struct net_device * dev,struct ethtool_modinfo * modinfo)3252 static int bnxt_get_module_info(struct net_device *dev,
3253 struct ethtool_modinfo *modinfo)
3254 {
3255 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
3256 struct bnxt *bp = netdev_priv(dev);
3257 int rc;
3258
3259 /* No point in going further if phy status indicates
3260 * module is not inserted or if it is powered down or
3261 * if it is of type 10GBase-T
3262 */
3263 if (bp->link_info.module_status >
3264 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
3265 return -EOPNOTSUPP;
3266
3267 /* This feature is not supported in older firmware versions */
3268 if (bp->hwrm_spec_code < 0x10202)
3269 return -EOPNOTSUPP;
3270
3271 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0,
3272 SFF_DIAG_SUPPORT_OFFSET + 1,
3273 data);
3274 if (!rc) {
3275 u8 module_id = data[0];
3276 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
3277
3278 switch (module_id) {
3279 case SFF_MODULE_ID_SFP:
3280 modinfo->type = ETH_MODULE_SFF_8472;
3281 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3282 if (!diag_supported)
3283 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
3284 break;
3285 case SFF_MODULE_ID_QSFP:
3286 case SFF_MODULE_ID_QSFP_PLUS:
3287 modinfo->type = ETH_MODULE_SFF_8436;
3288 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
3289 break;
3290 case SFF_MODULE_ID_QSFP28:
3291 modinfo->type = ETH_MODULE_SFF_8636;
3292 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
3293 break;
3294 default:
3295 rc = -EOPNOTSUPP;
3296 break;
3297 }
3298 }
3299 return rc;
3300 }
3301
bnxt_get_module_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)3302 static int bnxt_get_module_eeprom(struct net_device *dev,
3303 struct ethtool_eeprom *eeprom,
3304 u8 *data)
3305 {
3306 struct bnxt *bp = netdev_priv(dev);
3307 u16 start = eeprom->offset, length = eeprom->len;
3308 int rc = 0;
3309
3310 memset(data, 0, eeprom->len);
3311
3312 /* Read A0 portion of the EEPROM */
3313 if (start < ETH_MODULE_SFF_8436_LEN) {
3314 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
3315 length = ETH_MODULE_SFF_8436_LEN - start;
3316 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3317 start, length, data);
3318 if (rc)
3319 return rc;
3320 start += length;
3321 data += length;
3322 length = eeprom->len - length;
3323 }
3324
3325 /* Read A2 portion of the EEPROM */
3326 if (length) {
3327 start -= ETH_MODULE_SFF_8436_LEN;
3328 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0,
3329 start, length, data);
3330 }
3331 return rc;
3332 }
3333
bnxt_get_module_status(struct bnxt * bp,struct netlink_ext_ack * extack)3334 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack)
3335 {
3336 if (bp->link_info.module_status <=
3337 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
3338 return 0;
3339
3340 switch (bp->link_info.module_status) {
3341 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
3342 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down");
3343 break;
3344 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED:
3345 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted");
3346 break;
3347 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT:
3348 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault");
3349 break;
3350 default:
3351 NL_SET_ERR_MSG_MOD(extack, "Unknown error");
3352 break;
3353 }
3354 return -EINVAL;
3355 }
3356
bnxt_get_module_eeprom_by_page(struct net_device * dev,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)3357 static int bnxt_get_module_eeprom_by_page(struct net_device *dev,
3358 const struct ethtool_module_eeprom *page_data,
3359 struct netlink_ext_ack *extack)
3360 {
3361 struct bnxt *bp = netdev_priv(dev);
3362 int rc;
3363
3364 rc = bnxt_get_module_status(bp, extack);
3365 if (rc)
3366 return rc;
3367
3368 if (bp->hwrm_spec_code < 0x10202) {
3369 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old");
3370 return -EINVAL;
3371 }
3372
3373 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) {
3374 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection");
3375 return -EINVAL;
3376 }
3377
3378 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1,
3379 page_data->page, page_data->bank,
3380 page_data->offset,
3381 page_data->length,
3382 page_data->data);
3383 if (rc) {
3384 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed");
3385 return rc;
3386 }
3387 return page_data->length;
3388 }
3389
bnxt_nway_reset(struct net_device * dev)3390 static int bnxt_nway_reset(struct net_device *dev)
3391 {
3392 int rc = 0;
3393
3394 struct bnxt *bp = netdev_priv(dev);
3395 struct bnxt_link_info *link_info = &bp->link_info;
3396
3397 if (!BNXT_PHY_CFG_ABLE(bp))
3398 return -EOPNOTSUPP;
3399
3400 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
3401 return -EINVAL;
3402
3403 if (netif_running(dev))
3404 rc = bnxt_hwrm_set_link_setting(bp, true, false);
3405
3406 return rc;
3407 }
3408
bnxt_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)3409 static int bnxt_set_phys_id(struct net_device *dev,
3410 enum ethtool_phys_id_state state)
3411 {
3412 struct hwrm_port_led_cfg_input *req;
3413 struct bnxt *bp = netdev_priv(dev);
3414 struct bnxt_pf_info *pf = &bp->pf;
3415 struct bnxt_led_cfg *led_cfg;
3416 u8 led_state;
3417 __le16 duration;
3418 int rc, i;
3419
3420 if (!bp->num_leds || BNXT_VF(bp))
3421 return -EOPNOTSUPP;
3422
3423 if (state == ETHTOOL_ID_ACTIVE) {
3424 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
3425 duration = cpu_to_le16(500);
3426 } else if (state == ETHTOOL_ID_INACTIVE) {
3427 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
3428 duration = cpu_to_le16(0);
3429 } else {
3430 return -EINVAL;
3431 }
3432 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG);
3433 if (rc)
3434 return rc;
3435
3436 req->port_id = cpu_to_le16(pf->port_id);
3437 req->num_leds = bp->num_leds;
3438 led_cfg = (struct bnxt_led_cfg *)&req->led0_id;
3439 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3440 req->enables |= BNXT_LED_DFLT_ENABLES(i);
3441 led_cfg->led_id = bp->leds[i].led_id;
3442 led_cfg->led_state = led_state;
3443 led_cfg->led_blink_on = duration;
3444 led_cfg->led_blink_off = duration;
3445 led_cfg->led_group_id = bp->leds[i].led_group_id;
3446 }
3447 return hwrm_req_send(bp, req);
3448 }
3449
bnxt_hwrm_selftest_irq(struct bnxt * bp,u16 cmpl_ring)3450 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
3451 {
3452 struct hwrm_selftest_irq_input *req;
3453 int rc;
3454
3455 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ);
3456 if (rc)
3457 return rc;
3458
3459 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3460 return hwrm_req_send(bp, req);
3461 }
3462
bnxt_test_irq(struct bnxt * bp)3463 static int bnxt_test_irq(struct bnxt *bp)
3464 {
3465 int i;
3466
3467 for (i = 0; i < bp->cp_nr_rings; i++) {
3468 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
3469 int rc;
3470
3471 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
3472 if (rc)
3473 return rc;
3474 }
3475 return 0;
3476 }
3477
bnxt_hwrm_mac_loopback(struct bnxt * bp,bool enable)3478 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
3479 {
3480 struct hwrm_port_mac_cfg_input *req;
3481 int rc;
3482
3483 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
3484 if (rc)
3485 return rc;
3486
3487 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
3488 if (enable)
3489 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
3490 else
3491 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
3492 return hwrm_req_send(bp, req);
3493 }
3494
bnxt_query_force_speeds(struct bnxt * bp,u16 * force_speeds)3495 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
3496 {
3497 struct hwrm_port_phy_qcaps_output *resp;
3498 struct hwrm_port_phy_qcaps_input *req;
3499 int rc;
3500
3501 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
3502 if (rc)
3503 return rc;
3504
3505 resp = hwrm_req_hold(bp, req);
3506 rc = hwrm_req_send(bp, req);
3507 if (!rc)
3508 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
3509
3510 hwrm_req_drop(bp, req);
3511 return rc;
3512 }
3513
bnxt_disable_an_for_lpbk(struct bnxt * bp,struct hwrm_port_phy_cfg_input * req)3514 static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
3515 struct hwrm_port_phy_cfg_input *req)
3516 {
3517 struct bnxt_link_info *link_info = &bp->link_info;
3518 u16 fw_advertising;
3519 u16 fw_speed;
3520 int rc;
3521
3522 if (!link_info->autoneg ||
3523 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK))
3524 return 0;
3525
3526 rc = bnxt_query_force_speeds(bp, &fw_advertising);
3527 if (rc)
3528 return rc;
3529
3530 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
3531 if (BNXT_LINK_IS_UP(bp))
3532 fw_speed = bp->link_info.link_speed;
3533 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
3534 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
3535 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
3536 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
3537 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
3538 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
3539 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
3540 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
3541
3542 req->force_link_speed = cpu_to_le16(fw_speed);
3543 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
3544 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3545 rc = hwrm_req_send(bp, req);
3546 req->flags = 0;
3547 req->force_link_speed = cpu_to_le16(0);
3548 return rc;
3549 }
3550
bnxt_hwrm_phy_loopback(struct bnxt * bp,bool enable,bool ext)3551 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
3552 {
3553 struct hwrm_port_phy_cfg_input *req;
3554 int rc;
3555
3556 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
3557 if (rc)
3558 return rc;
3559
3560 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */
3561 hwrm_req_hold(bp, req);
3562
3563 if (enable) {
3564 bnxt_disable_an_for_lpbk(bp, req);
3565 if (ext)
3566 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
3567 else
3568 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
3569 } else {
3570 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
3571 }
3572 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
3573 rc = hwrm_req_send(bp, req);
3574 hwrm_req_drop(bp, req);
3575 return rc;
3576 }
3577
bnxt_rx_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,u32 raw_cons,int pkt_size)3578 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3579 u32 raw_cons, int pkt_size)
3580 {
3581 struct bnxt_napi *bnapi = cpr->bnapi;
3582 struct bnxt_rx_ring_info *rxr;
3583 struct bnxt_sw_rx_bd *rx_buf;
3584 struct rx_cmp *rxcmp;
3585 u16 cp_cons, cons;
3586 u8 *data;
3587 u32 len;
3588 int i;
3589
3590 rxr = bnapi->rx_ring;
3591 cp_cons = RING_CMP(raw_cons);
3592 rxcmp = (struct rx_cmp *)
3593 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
3594 cons = rxcmp->rx_cmp_opaque;
3595 rx_buf = &rxr->rx_buf_ring[cons];
3596 data = rx_buf->data_ptr;
3597 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
3598 if (len != pkt_size)
3599 return -EIO;
3600 i = ETH_ALEN;
3601 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
3602 return -EIO;
3603 i += ETH_ALEN;
3604 for ( ; i < pkt_size; i++) {
3605 if (data[i] != (u8)(i & 0xff))
3606 return -EIO;
3607 }
3608 return 0;
3609 }
3610
bnxt_poll_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,int pkt_size)3611 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3612 int pkt_size)
3613 {
3614 struct tx_cmp *txcmp;
3615 int rc = -EIO;
3616 u32 raw_cons;
3617 u32 cons;
3618 int i;
3619
3620 raw_cons = cpr->cp_raw_cons;
3621 for (i = 0; i < 200; i++) {
3622 cons = RING_CMP(raw_cons);
3623 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
3624
3625 if (!TX_CMP_VALID(txcmp, raw_cons)) {
3626 udelay(5);
3627 continue;
3628 }
3629
3630 /* The valid test of the entry must be done first before
3631 * reading any further.
3632 */
3633 dma_rmb();
3634 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {
3635 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
3636 raw_cons = NEXT_RAW_CMP(raw_cons);
3637 raw_cons = NEXT_RAW_CMP(raw_cons);
3638 break;
3639 }
3640 raw_cons = NEXT_RAW_CMP(raw_cons);
3641 }
3642 cpr->cp_raw_cons = raw_cons;
3643 return rc;
3644 }
3645
bnxt_run_loopback(struct bnxt * bp)3646 static int bnxt_run_loopback(struct bnxt *bp)
3647 {
3648 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
3649 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
3650 struct bnxt_cp_ring_info *cpr;
3651 int pkt_size, i = 0;
3652 struct sk_buff *skb;
3653 dma_addr_t map;
3654 u8 *data;
3655 int rc;
3656
3657 cpr = &rxr->bnapi->cp_ring;
3658 if (bp->flags & BNXT_FLAG_CHIP_P5)
3659 cpr = cpr->cp_ring_arr[BNXT_RX_HDL];
3660 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
3661 skb = netdev_alloc_skb(bp->dev, pkt_size);
3662 if (!skb)
3663 return -ENOMEM;
3664 data = skb_put(skb, pkt_size);
3665 ether_addr_copy(&data[i], bp->dev->dev_addr);
3666 i += ETH_ALEN;
3667 ether_addr_copy(&data[i], bp->dev->dev_addr);
3668 i += ETH_ALEN;
3669 for ( ; i < pkt_size; i++)
3670 data[i] = (u8)(i & 0xff);
3671
3672 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
3673 DMA_TO_DEVICE);
3674 if (dma_mapping_error(&bp->pdev->dev, map)) {
3675 dev_kfree_skb(skb);
3676 return -EIO;
3677 }
3678 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL);
3679
3680 /* Sync BD data before updating doorbell */
3681 wmb();
3682
3683 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
3684 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
3685
3686 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
3687 dev_kfree_skb(skb);
3688 return rc;
3689 }
3690
bnxt_run_fw_tests(struct bnxt * bp,u8 test_mask,u8 * test_results)3691 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
3692 {
3693 struct hwrm_selftest_exec_output *resp;
3694 struct hwrm_selftest_exec_input *req;
3695 int rc;
3696
3697 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC);
3698 if (rc)
3699 return rc;
3700
3701 hwrm_req_timeout(bp, req, bp->test_info->timeout);
3702 req->flags = test_mask;
3703
3704 resp = hwrm_req_hold(bp, req);
3705 rc = hwrm_req_send(bp, req);
3706 *test_results = resp->test_success;
3707 hwrm_req_drop(bp, req);
3708 return rc;
3709 }
3710
3711 #define BNXT_DRV_TESTS 4
3712 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
3713 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
3714 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
3715 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
3716
bnxt_self_test(struct net_device * dev,struct ethtool_test * etest,u64 * buf)3717 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
3718 u64 *buf)
3719 {
3720 struct bnxt *bp = netdev_priv(dev);
3721 bool do_ext_lpbk = false;
3722 bool offline = false;
3723 u8 test_results = 0;
3724 u8 test_mask = 0;
3725 int rc = 0, i;
3726
3727 if (!bp->num_tests || !BNXT_PF(bp))
3728 return;
3729 memset(buf, 0, sizeof(u64) * bp->num_tests);
3730 if (!netif_running(dev)) {
3731 etest->flags |= ETH_TEST_FL_FAILED;
3732 return;
3733 }
3734
3735 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
3736 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK))
3737 do_ext_lpbk = true;
3738
3739 if (etest->flags & ETH_TEST_FL_OFFLINE) {
3740 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
3741 etest->flags |= ETH_TEST_FL_FAILED;
3742 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
3743 return;
3744 }
3745 offline = true;
3746 }
3747
3748 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3749 u8 bit_val = 1 << i;
3750
3751 if (!(bp->test_info->offline_mask & bit_val))
3752 test_mask |= bit_val;
3753 else if (offline)
3754 test_mask |= bit_val;
3755 }
3756 if (!offline) {
3757 bnxt_run_fw_tests(bp, test_mask, &test_results);
3758 } else {
3759 bnxt_ulp_stop(bp);
3760 bnxt_close_nic(bp, true, false);
3761 bnxt_run_fw_tests(bp, test_mask, &test_results);
3762
3763 buf[BNXT_MACLPBK_TEST_IDX] = 1;
3764 bnxt_hwrm_mac_loopback(bp, true);
3765 msleep(250);
3766 rc = bnxt_half_open_nic(bp);
3767 if (rc) {
3768 bnxt_hwrm_mac_loopback(bp, false);
3769 etest->flags |= ETH_TEST_FL_FAILED;
3770 bnxt_ulp_start(bp, rc);
3771 return;
3772 }
3773 if (bnxt_run_loopback(bp))
3774 etest->flags |= ETH_TEST_FL_FAILED;
3775 else
3776 buf[BNXT_MACLPBK_TEST_IDX] = 0;
3777
3778 bnxt_hwrm_mac_loopback(bp, false);
3779 bnxt_hwrm_phy_loopback(bp, true, false);
3780 msleep(1000);
3781 if (bnxt_run_loopback(bp)) {
3782 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
3783 etest->flags |= ETH_TEST_FL_FAILED;
3784 }
3785 if (do_ext_lpbk) {
3786 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3787 bnxt_hwrm_phy_loopback(bp, true, true);
3788 msleep(1000);
3789 if (bnxt_run_loopback(bp)) {
3790 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
3791 etest->flags |= ETH_TEST_FL_FAILED;
3792 }
3793 }
3794 bnxt_hwrm_phy_loopback(bp, false, false);
3795 bnxt_half_close_nic(bp);
3796 rc = bnxt_open_nic(bp, true, true);
3797 bnxt_ulp_start(bp, rc);
3798 }
3799 if (rc || bnxt_test_irq(bp)) {
3800 buf[BNXT_IRQ_TEST_IDX] = 1;
3801 etest->flags |= ETH_TEST_FL_FAILED;
3802 }
3803 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3804 u8 bit_val = 1 << i;
3805
3806 if ((test_mask & bit_val) && !(test_results & bit_val)) {
3807 buf[i] = 1;
3808 etest->flags |= ETH_TEST_FL_FAILED;
3809 }
3810 }
3811 }
3812
bnxt_reset(struct net_device * dev,u32 * flags)3813 static int bnxt_reset(struct net_device *dev, u32 *flags)
3814 {
3815 struct bnxt *bp = netdev_priv(dev);
3816 bool reload = false;
3817 u32 req = *flags;
3818
3819 if (!req)
3820 return -EINVAL;
3821
3822 if (!BNXT_PF(bp)) {
3823 netdev_err(dev, "Reset is not supported from a VF\n");
3824 return -EOPNOTSUPP;
3825 }
3826
3827 if (pci_vfs_assigned(bp->pdev) &&
3828 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
3829 netdev_err(dev,
3830 "Reset not allowed when VFs are assigned to VMs\n");
3831 return -EBUSY;
3832 }
3833
3834 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
3835 /* This feature is not supported in older firmware versions */
3836 if (bp->hwrm_spec_code >= 0x10803) {
3837 if (!bnxt_firmware_reset_chip(dev)) {
3838 netdev_info(dev, "Firmware reset request successful.\n");
3839 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
3840 reload = true;
3841 *flags &= ~BNXT_FW_RESET_CHIP;
3842 }
3843 } else if (req == BNXT_FW_RESET_CHIP) {
3844 return -EOPNOTSUPP; /* only request, fail hard */
3845 }
3846 }
3847
3848 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) {
3849 /* This feature is not supported in older firmware versions */
3850 if (bp->hwrm_spec_code >= 0x10803) {
3851 if (!bnxt_firmware_reset_ap(dev)) {
3852 netdev_info(dev, "Reset application processor successful.\n");
3853 reload = true;
3854 *flags &= ~BNXT_FW_RESET_AP;
3855 }
3856 } else if (req == BNXT_FW_RESET_AP) {
3857 return -EOPNOTSUPP; /* only request, fail hard */
3858 }
3859 }
3860
3861 if (reload)
3862 netdev_info(dev, "Reload driver to complete reset\n");
3863
3864 return 0;
3865 }
3866
bnxt_set_dump(struct net_device * dev,struct ethtool_dump * dump)3867 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
3868 {
3869 struct bnxt *bp = netdev_priv(dev);
3870
3871 if (dump->flag > BNXT_DUMP_CRASH) {
3872 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n");
3873 return -EINVAL;
3874 }
3875
3876 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) {
3877 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
3878 return -EOPNOTSUPP;
3879 }
3880
3881 bp->dump_flag = dump->flag;
3882 return 0;
3883 }
3884
bnxt_get_dump_flag(struct net_device * dev,struct ethtool_dump * dump)3885 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
3886 {
3887 struct bnxt *bp = netdev_priv(dev);
3888
3889 if (bp->hwrm_spec_code < 0x10801)
3890 return -EOPNOTSUPP;
3891
3892 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
3893 bp->ver_resp.hwrm_fw_min_8b << 16 |
3894 bp->ver_resp.hwrm_fw_bld_8b << 8 |
3895 bp->ver_resp.hwrm_fw_rsvd_8b;
3896
3897 dump->flag = bp->dump_flag;
3898 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag);
3899 return 0;
3900 }
3901
bnxt_get_dump_data(struct net_device * dev,struct ethtool_dump * dump,void * buf)3902 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
3903 void *buf)
3904 {
3905 struct bnxt *bp = netdev_priv(dev);
3906
3907 if (bp->hwrm_spec_code < 0x10801)
3908 return -EOPNOTSUPP;
3909
3910 memset(buf, 0, dump->len);
3911
3912 dump->flag = bp->dump_flag;
3913 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len);
3914 }
3915
bnxt_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)3916 static int bnxt_get_ts_info(struct net_device *dev,
3917 struct ethtool_ts_info *info)
3918 {
3919 struct bnxt *bp = netdev_priv(dev);
3920 struct bnxt_ptp_cfg *ptp;
3921
3922 ptp = bp->ptp_cfg;
3923 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3924 SOF_TIMESTAMPING_RX_SOFTWARE |
3925 SOF_TIMESTAMPING_SOFTWARE;
3926
3927 info->phc_index = -1;
3928 if (!ptp)
3929 return 0;
3930
3931 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
3932 SOF_TIMESTAMPING_RX_HARDWARE |
3933 SOF_TIMESTAMPING_RAW_HARDWARE;
3934 if (ptp->ptp_clock)
3935 info->phc_index = ptp_clock_index(ptp->ptp_clock);
3936
3937 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
3938
3939 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3940 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3941 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
3942
3943 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
3944 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL);
3945 return 0;
3946 }
3947
bnxt_ethtool_init(struct bnxt * bp)3948 void bnxt_ethtool_init(struct bnxt *bp)
3949 {
3950 struct hwrm_selftest_qlist_output *resp;
3951 struct hwrm_selftest_qlist_input *req;
3952 struct bnxt_test_info *test_info;
3953 struct net_device *dev = bp->dev;
3954 int i, rc;
3955
3956 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
3957 bnxt_get_pkgver(dev);
3958
3959 bp->num_tests = 0;
3960 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
3961 return;
3962
3963 test_info = bp->test_info;
3964 if (!test_info) {
3965 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
3966 if (!test_info)
3967 return;
3968 bp->test_info = test_info;
3969 }
3970
3971 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST))
3972 return;
3973
3974 resp = hwrm_req_hold(bp, req);
3975 rc = hwrm_req_send_silent(bp, req);
3976 if (rc)
3977 goto ethtool_init_exit;
3978
3979 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
3980 if (bp->num_tests > BNXT_MAX_TEST)
3981 bp->num_tests = BNXT_MAX_TEST;
3982
3983 test_info->offline_mask = resp->offline_tests;
3984 test_info->timeout = le16_to_cpu(resp->test_timeout);
3985 if (!test_info->timeout)
3986 test_info->timeout = HWRM_CMD_TIMEOUT;
3987 for (i = 0; i < bp->num_tests; i++) {
3988 char *str = test_info->string[i];
3989 char *fw_str = resp->test_name[i];
3990
3991 if (i == BNXT_MACLPBK_TEST_IDX) {
3992 strcpy(str, "Mac loopback test (offline)");
3993 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
3994 strcpy(str, "Phy loopback test (offline)");
3995 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
3996 strcpy(str, "Ext loopback test (offline)");
3997 } else if (i == BNXT_IRQ_TEST_IDX) {
3998 strcpy(str, "Interrupt_test (offline)");
3999 } else {
4000 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)",
4001 fw_str, test_info->offline_mask & (1 << i) ?
4002 "offline" : "online");
4003 }
4004 }
4005
4006 ethtool_init_exit:
4007 hwrm_req_drop(bp, req);
4008 }
4009
bnxt_get_eth_phy_stats(struct net_device * dev,struct ethtool_eth_phy_stats * phy_stats)4010 static void bnxt_get_eth_phy_stats(struct net_device *dev,
4011 struct ethtool_eth_phy_stats *phy_stats)
4012 {
4013 struct bnxt *bp = netdev_priv(dev);
4014 u64 *rx;
4015
4016 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
4017 return;
4018
4019 rx = bp->rx_port_stats_ext.sw_stats;
4020 phy_stats->SymbolErrorDuringCarrier =
4021 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err));
4022 }
4023
bnxt_get_eth_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * mac_stats)4024 static void bnxt_get_eth_mac_stats(struct net_device *dev,
4025 struct ethtool_eth_mac_stats *mac_stats)
4026 {
4027 struct bnxt *bp = netdev_priv(dev);
4028 u64 *rx, *tx;
4029
4030 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
4031 return;
4032
4033 rx = bp->port_stats.sw_stats;
4034 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4035
4036 mac_stats->FramesReceivedOK =
4037 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames);
4038 mac_stats->FramesTransmittedOK =
4039 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames);
4040 mac_stats->FrameCheckSequenceErrors =
4041 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
4042 mac_stats->AlignmentErrors =
4043 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
4044 mac_stats->OutOfRangeLengthField =
4045 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames);
4046 }
4047
bnxt_get_eth_ctrl_stats(struct net_device * dev,struct ethtool_eth_ctrl_stats * ctrl_stats)4048 static void bnxt_get_eth_ctrl_stats(struct net_device *dev,
4049 struct ethtool_eth_ctrl_stats *ctrl_stats)
4050 {
4051 struct bnxt *bp = netdev_priv(dev);
4052 u64 *rx;
4053
4054 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
4055 return;
4056
4057 rx = bp->port_stats.sw_stats;
4058 ctrl_stats->MACControlFramesReceived =
4059 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames);
4060 }
4061
4062 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = {
4063 { 0, 64 },
4064 { 65, 127 },
4065 { 128, 255 },
4066 { 256, 511 },
4067 { 512, 1023 },
4068 { 1024, 1518 },
4069 { 1519, 2047 },
4070 { 2048, 4095 },
4071 { 4096, 9216 },
4072 { 9217, 16383 },
4073 {}
4074 };
4075
bnxt_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)4076 static void bnxt_get_rmon_stats(struct net_device *dev,
4077 struct ethtool_rmon_stats *rmon_stats,
4078 const struct ethtool_rmon_hist_range **ranges)
4079 {
4080 struct bnxt *bp = netdev_priv(dev);
4081 u64 *rx, *tx;
4082
4083 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
4084 return;
4085
4086 rx = bp->port_stats.sw_stats;
4087 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4088
4089 rmon_stats->jabbers =
4090 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
4091 rmon_stats->oversize_pkts =
4092 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames);
4093 rmon_stats->undersize_pkts =
4094 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames);
4095
4096 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames);
4097 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames);
4098 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames);
4099 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames);
4100 rmon_stats->hist[4] =
4101 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames);
4102 rmon_stats->hist[5] =
4103 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames);
4104 rmon_stats->hist[6] =
4105 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames);
4106 rmon_stats->hist[7] =
4107 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames);
4108 rmon_stats->hist[8] =
4109 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames);
4110 rmon_stats->hist[9] =
4111 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames);
4112
4113 rmon_stats->hist_tx[0] =
4114 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames);
4115 rmon_stats->hist_tx[1] =
4116 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames);
4117 rmon_stats->hist_tx[2] =
4118 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames);
4119 rmon_stats->hist_tx[3] =
4120 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames);
4121 rmon_stats->hist_tx[4] =
4122 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames);
4123 rmon_stats->hist_tx[5] =
4124 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames);
4125 rmon_stats->hist_tx[6] =
4126 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames);
4127 rmon_stats->hist_tx[7] =
4128 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames);
4129 rmon_stats->hist_tx[8] =
4130 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames);
4131 rmon_stats->hist_tx[9] =
4132 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames);
4133
4134 *ranges = bnxt_rmon_ranges;
4135 }
4136
bnxt_get_link_ext_stats(struct net_device * dev,struct ethtool_link_ext_stats * stats)4137 static void bnxt_get_link_ext_stats(struct net_device *dev,
4138 struct ethtool_link_ext_stats *stats)
4139 {
4140 struct bnxt *bp = netdev_priv(dev);
4141 u64 *rx;
4142
4143 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
4144 return;
4145
4146 rx = bp->rx_port_stats_ext.sw_stats;
4147 stats->link_down_events =
4148 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events));
4149 }
4150
bnxt_ethtool_free(struct bnxt * bp)4151 void bnxt_ethtool_free(struct bnxt *bp)
4152 {
4153 kfree(bp->test_info);
4154 bp->test_info = NULL;
4155 }
4156
4157 const struct ethtool_ops bnxt_ethtool_ops = {
4158 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
4159 ETHTOOL_COALESCE_MAX_FRAMES |
4160 ETHTOOL_COALESCE_USECS_IRQ |
4161 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
4162 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
4163 ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
4164 ETHTOOL_COALESCE_USE_CQE,
4165 .get_link_ksettings = bnxt_get_link_ksettings,
4166 .set_link_ksettings = bnxt_set_link_ksettings,
4167 .get_fec_stats = bnxt_get_fec_stats,
4168 .get_fecparam = bnxt_get_fecparam,
4169 .set_fecparam = bnxt_set_fecparam,
4170 .get_pause_stats = bnxt_get_pause_stats,
4171 .get_pauseparam = bnxt_get_pauseparam,
4172 .set_pauseparam = bnxt_set_pauseparam,
4173 .get_drvinfo = bnxt_get_drvinfo,
4174 .get_regs_len = bnxt_get_regs_len,
4175 .get_regs = bnxt_get_regs,
4176 .get_wol = bnxt_get_wol,
4177 .set_wol = bnxt_set_wol,
4178 .get_coalesce = bnxt_get_coalesce,
4179 .set_coalesce = bnxt_set_coalesce,
4180 .get_msglevel = bnxt_get_msglevel,
4181 .set_msglevel = bnxt_set_msglevel,
4182 .get_sset_count = bnxt_get_sset_count,
4183 .get_strings = bnxt_get_strings,
4184 .get_ethtool_stats = bnxt_get_ethtool_stats,
4185 .set_ringparam = bnxt_set_ringparam,
4186 .get_ringparam = bnxt_get_ringparam,
4187 .get_channels = bnxt_get_channels,
4188 .set_channels = bnxt_set_channels,
4189 .get_rxnfc = bnxt_get_rxnfc,
4190 .set_rxnfc = bnxt_set_rxnfc,
4191 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
4192 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
4193 .get_rxfh = bnxt_get_rxfh,
4194 .set_rxfh = bnxt_set_rxfh,
4195 .flash_device = bnxt_flash_device,
4196 .get_eeprom_len = bnxt_get_eeprom_len,
4197 .get_eeprom = bnxt_get_eeprom,
4198 .set_eeprom = bnxt_set_eeprom,
4199 .get_link = bnxt_get_link,
4200 .get_link_ext_stats = bnxt_get_link_ext_stats,
4201 .get_eee = bnxt_get_eee,
4202 .set_eee = bnxt_set_eee,
4203 .get_module_info = bnxt_get_module_info,
4204 .get_module_eeprom = bnxt_get_module_eeprom,
4205 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page,
4206 .nway_reset = bnxt_nway_reset,
4207 .set_phys_id = bnxt_set_phys_id,
4208 .self_test = bnxt_self_test,
4209 .get_ts_info = bnxt_get_ts_info,
4210 .reset = bnxt_reset,
4211 .set_dump = bnxt_set_dump,
4212 .get_dump_flag = bnxt_get_dump_flag,
4213 .get_dump_data = bnxt_get_dump_data,
4214 .get_eth_phy_stats = bnxt_get_eth_phy_stats,
4215 .get_eth_mac_stats = bnxt_get_eth_mac_stats,
4216 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats,
4217 .get_rmon_stats = bnxt_get_rmon_stats,
4218 };
4219