1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "dp_rx.h"
8 #include "debug.h"
9 #include "hif.h"
10
11 const struct ce_attr ath12k_host_ce_config_qcn9274[] = {
12 /* CE0: host->target HTC control and raw streams */
13 {
14 .flags = CE_ATTR_FLAGS,
15 .src_nentries = 16,
16 .src_sz_max = 2048,
17 .dest_nentries = 0,
18 },
19
20 /* CE1: target->host HTT + HTC control */
21 {
22 .flags = CE_ATTR_FLAGS,
23 .src_nentries = 0,
24 .src_sz_max = 2048,
25 .dest_nentries = 512,
26 .recv_cb = ath12k_htc_rx_completion_handler,
27 },
28
29 /* CE2: target->host WMI */
30 {
31 .flags = CE_ATTR_FLAGS,
32 .src_nentries = 0,
33 .src_sz_max = 2048,
34 .dest_nentries = 128,
35 .recv_cb = ath12k_htc_rx_completion_handler,
36 },
37
38 /* CE3: host->target WMI (mac0) */
39 {
40 .flags = CE_ATTR_FLAGS,
41 .src_nentries = 32,
42 .src_sz_max = 2048,
43 .dest_nentries = 0,
44 },
45
46 /* CE4: host->target HTT */
47 {
48 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
49 .src_nentries = 2048,
50 .src_sz_max = 256,
51 .dest_nentries = 0,
52 },
53
54 /* CE5: target->host pktlog */
55 {
56 .flags = CE_ATTR_FLAGS,
57 .src_nentries = 0,
58 .src_sz_max = 2048,
59 .dest_nentries = 512,
60 .recv_cb = ath12k_dp_htt_htc_t2h_msg_handler,
61 },
62
63 /* CE6: target autonomous hif_memcpy */
64 {
65 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
66 .src_nentries = 0,
67 .src_sz_max = 0,
68 .dest_nentries = 0,
69 },
70
71 /* CE7: host->target WMI (mac1) */
72 {
73 .flags = CE_ATTR_FLAGS,
74 .src_nentries = 32,
75 .src_sz_max = 2048,
76 .dest_nentries = 0,
77 },
78
79 /* CE8: target autonomous hif_memcpy */
80 {
81 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
82 .src_nentries = 0,
83 .src_sz_max = 0,
84 .dest_nentries = 0,
85 },
86
87 /* CE9: MHI */
88 {
89 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
90 .src_nentries = 0,
91 .src_sz_max = 0,
92 .dest_nentries = 0,
93 },
94
95 /* CE10: MHI */
96 {
97 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
98 .src_nentries = 0,
99 .src_sz_max = 0,
100 .dest_nentries = 0,
101 },
102
103 /* CE11: MHI */
104 {
105 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
106 .src_nentries = 0,
107 .src_sz_max = 0,
108 .dest_nentries = 0,
109 },
110
111 /* CE12: CV Prefetch */
112 {
113 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
114 .src_nentries = 0,
115 .src_sz_max = 0,
116 .dest_nentries = 0,
117 },
118
119 /* CE13: CV Prefetch */
120 {
121 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
122 .src_nentries = 0,
123 .src_sz_max = 0,
124 .dest_nentries = 0,
125 },
126
127 /* CE14: target->host dbg log */
128 {
129 .flags = CE_ATTR_FLAGS,
130 .src_nentries = 0,
131 .src_sz_max = 2048,
132 .dest_nentries = 512,
133 .recv_cb = ath12k_htc_rx_completion_handler,
134 },
135
136 /* CE15: reserved for future use */
137 {
138 .flags = (CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
139 .src_nentries = 0,
140 .src_sz_max = 0,
141 .dest_nentries = 0,
142 },
143 };
144
145 const struct ce_attr ath12k_host_ce_config_wcn7850[] = {
146 /* CE0: host->target HTC control and raw streams */
147 {
148 .flags = CE_ATTR_FLAGS,
149 .src_nentries = 16,
150 .src_sz_max = 2048,
151 .dest_nentries = 0,
152 },
153
154 /* CE1: target->host HTT + HTC control */
155 {
156 .flags = CE_ATTR_FLAGS,
157 .src_nentries = 0,
158 .src_sz_max = 2048,
159 .dest_nentries = 512,
160 .recv_cb = ath12k_htc_rx_completion_handler,
161 },
162
163 /* CE2: target->host WMI */
164 {
165 .flags = CE_ATTR_FLAGS,
166 .src_nentries = 0,
167 .src_sz_max = 2048,
168 .dest_nentries = 64,
169 .recv_cb = ath12k_htc_rx_completion_handler,
170 },
171
172 /* CE3: host->target WMI (mac0) */
173 {
174 .flags = CE_ATTR_FLAGS,
175 .src_nentries = 32,
176 .src_sz_max = 2048,
177 .dest_nentries = 0,
178 },
179
180 /* CE4: host->target HTT */
181 {
182 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
183 .src_nentries = 2048,
184 .src_sz_max = 256,
185 .dest_nentries = 0,
186 },
187
188 /* CE5: target->host pktlog */
189 {
190 .flags = CE_ATTR_FLAGS,
191 .src_nentries = 0,
192 .src_sz_max = 0,
193 .dest_nentries = 0,
194 },
195
196 /* CE6: target autonomous hif_memcpy */
197 {
198 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
199 .src_nentries = 0,
200 .src_sz_max = 0,
201 .dest_nentries = 0,
202 },
203
204 /* CE7: host->target WMI (mac1) */
205 {
206 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
207 .src_nentries = 0,
208 .src_sz_max = 2048,
209 .dest_nentries = 0,
210 },
211
212 /* CE8: target autonomous hif_memcpy */
213 {
214 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
215 .src_nentries = 0,
216 .src_sz_max = 0,
217 .dest_nentries = 0,
218 },
219
220 };
221
ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe * pipe,struct sk_buff * skb,dma_addr_t paddr)222 static int ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe *pipe,
223 struct sk_buff *skb, dma_addr_t paddr)
224 {
225 struct ath12k_base *ab = pipe->ab;
226 struct ath12k_ce_ring *ring = pipe->dest_ring;
227 struct hal_srng *srng;
228 unsigned int write_index;
229 unsigned int nentries_mask = ring->nentries_mask;
230 struct hal_ce_srng_dest_desc *desc;
231 int ret;
232
233 lockdep_assert_held(&ab->ce.ce_lock);
234
235 write_index = ring->write_index;
236
237 srng = &ab->hal.srng_list[ring->hal_ring_id];
238
239 spin_lock_bh(&srng->lock);
240
241 ath12k_hal_srng_access_begin(ab, srng);
242
243 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) {
244 ret = -ENOSPC;
245 goto exit;
246 }
247
248 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
249 if (!desc) {
250 ret = -ENOSPC;
251 goto exit;
252 }
253
254 ath12k_hal_ce_dst_set_desc(desc, paddr);
255
256 ring->skb[write_index] = skb;
257 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
258 ring->write_index = write_index;
259
260 pipe->rx_buf_needed--;
261
262 ret = 0;
263 exit:
264 ath12k_hal_srng_access_end(ab, srng);
265
266 spin_unlock_bh(&srng->lock);
267
268 return ret;
269 }
270
ath12k_ce_rx_post_pipe(struct ath12k_ce_pipe * pipe)271 static int ath12k_ce_rx_post_pipe(struct ath12k_ce_pipe *pipe)
272 {
273 struct ath12k_base *ab = pipe->ab;
274 struct sk_buff *skb;
275 dma_addr_t paddr;
276 int ret = 0;
277
278 if (!(pipe->dest_ring || pipe->status_ring))
279 return 0;
280
281 spin_lock_bh(&ab->ce.ce_lock);
282 while (pipe->rx_buf_needed) {
283 skb = dev_alloc_skb(pipe->buf_sz);
284 if (!skb) {
285 ret = -ENOMEM;
286 goto exit;
287 }
288
289 WARN_ON_ONCE(!IS_ALIGNED((unsigned long)skb->data, 4));
290
291 paddr = dma_map_single(ab->dev, skb->data,
292 skb->len + skb_tailroom(skb),
293 DMA_FROM_DEVICE);
294 if (unlikely(dma_mapping_error(ab->dev, paddr))) {
295 ath12k_warn(ab, "failed to dma map ce rx buf\n");
296 dev_kfree_skb_any(skb);
297 ret = -EIO;
298 goto exit;
299 }
300
301 ATH12K_SKB_RXCB(skb)->paddr = paddr;
302
303 ret = ath12k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr);
304 if (ret) {
305 ath12k_warn(ab, "failed to enqueue rx buf: %d\n", ret);
306 dma_unmap_single(ab->dev, paddr,
307 skb->len + skb_tailroom(skb),
308 DMA_FROM_DEVICE);
309 dev_kfree_skb_any(skb);
310 goto exit;
311 }
312 }
313
314 exit:
315 spin_unlock_bh(&ab->ce.ce_lock);
316 return ret;
317 }
318
ath12k_ce_completed_recv_next(struct ath12k_ce_pipe * pipe,struct sk_buff ** skb,int * nbytes)319 static int ath12k_ce_completed_recv_next(struct ath12k_ce_pipe *pipe,
320 struct sk_buff **skb, int *nbytes)
321 {
322 struct ath12k_base *ab = pipe->ab;
323 struct hal_ce_srng_dst_status_desc *desc;
324 struct hal_srng *srng;
325 unsigned int sw_index;
326 unsigned int nentries_mask;
327 int ret = 0;
328
329 spin_lock_bh(&ab->ce.ce_lock);
330
331 sw_index = pipe->dest_ring->sw_index;
332 nentries_mask = pipe->dest_ring->nentries_mask;
333
334 srng = &ab->hal.srng_list[pipe->status_ring->hal_ring_id];
335
336 spin_lock_bh(&srng->lock);
337
338 ath12k_hal_srng_access_begin(ab, srng);
339
340 desc = ath12k_hal_srng_dst_get_next_entry(ab, srng);
341 if (!desc) {
342 ret = -EIO;
343 goto err;
344 }
345
346 /* Make sure descriptor is read after the head pointer. */
347 dma_rmb();
348
349 *nbytes = ath12k_hal_ce_dst_status_get_length(desc);
350
351 *skb = pipe->dest_ring->skb[sw_index];
352 pipe->dest_ring->skb[sw_index] = NULL;
353
354 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
355 pipe->dest_ring->sw_index = sw_index;
356
357 pipe->rx_buf_needed++;
358 err:
359 ath12k_hal_srng_access_end(ab, srng);
360
361 spin_unlock_bh(&srng->lock);
362
363 spin_unlock_bh(&ab->ce.ce_lock);
364
365 return ret;
366 }
367
ath12k_ce_recv_process_cb(struct ath12k_ce_pipe * pipe)368 static void ath12k_ce_recv_process_cb(struct ath12k_ce_pipe *pipe)
369 {
370 struct ath12k_base *ab = pipe->ab;
371 struct sk_buff *skb;
372 struct sk_buff_head list;
373 unsigned int nbytes, max_nbytes;
374 int ret;
375
376 __skb_queue_head_init(&list);
377 while (ath12k_ce_completed_recv_next(pipe, &skb, &nbytes) == 0) {
378 max_nbytes = skb->len + skb_tailroom(skb);
379 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
380 max_nbytes, DMA_FROM_DEVICE);
381
382 if (unlikely(max_nbytes < nbytes || nbytes == 0)) {
383 ath12k_warn(ab, "unexpected rx length (nbytes %d, max %d)",
384 nbytes, max_nbytes);
385 dev_kfree_skb_any(skb);
386 continue;
387 }
388
389 skb_put(skb, nbytes);
390 __skb_queue_tail(&list, skb);
391 }
392
393 while ((skb = __skb_dequeue(&list))) {
394 ath12k_dbg(ab, ATH12K_DBG_AHB, "rx ce pipe %d len %d\n",
395 pipe->pipe_num, skb->len);
396 pipe->recv_cb(ab, skb);
397 }
398
399 ret = ath12k_ce_rx_post_pipe(pipe);
400 if (ret && ret != -ENOSPC) {
401 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
402 pipe->pipe_num, ret);
403 mod_timer(&ab->rx_replenish_retry,
404 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES);
405 }
406 }
407
ath12k_ce_completed_send_next(struct ath12k_ce_pipe * pipe)408 static struct sk_buff *ath12k_ce_completed_send_next(struct ath12k_ce_pipe *pipe)
409 {
410 struct ath12k_base *ab = pipe->ab;
411 struct hal_ce_srng_src_desc *desc;
412 struct hal_srng *srng;
413 unsigned int sw_index;
414 unsigned int nentries_mask;
415 struct sk_buff *skb;
416
417 spin_lock_bh(&ab->ce.ce_lock);
418
419 sw_index = pipe->src_ring->sw_index;
420 nentries_mask = pipe->src_ring->nentries_mask;
421
422 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
423
424 spin_lock_bh(&srng->lock);
425
426 ath12k_hal_srng_access_begin(ab, srng);
427
428 desc = ath12k_hal_srng_src_reap_next(ab, srng);
429 if (!desc) {
430 skb = ERR_PTR(-EIO);
431 goto err_unlock;
432 }
433
434 skb = pipe->src_ring->skb[sw_index];
435
436 pipe->src_ring->skb[sw_index] = NULL;
437
438 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
439 pipe->src_ring->sw_index = sw_index;
440
441 err_unlock:
442 spin_unlock_bh(&srng->lock);
443
444 spin_unlock_bh(&ab->ce.ce_lock);
445
446 return skb;
447 }
448
ath12k_ce_send_done_cb(struct ath12k_ce_pipe * pipe)449 static void ath12k_ce_send_done_cb(struct ath12k_ce_pipe *pipe)
450 {
451 struct ath12k_base *ab = pipe->ab;
452 struct sk_buff *skb;
453
454 while (!IS_ERR(skb = ath12k_ce_completed_send_next(pipe))) {
455 if (!skb)
456 continue;
457
458 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, skb->len,
459 DMA_TO_DEVICE);
460 dev_kfree_skb_any(skb);
461 }
462 }
463
ath12k_ce_srng_msi_ring_params_setup(struct ath12k_base * ab,u32 ce_id,struct hal_srng_params * ring_params)464 static void ath12k_ce_srng_msi_ring_params_setup(struct ath12k_base *ab, u32 ce_id,
465 struct hal_srng_params *ring_params)
466 {
467 u32 msi_data_start;
468 u32 msi_data_count, msi_data_idx;
469 u32 msi_irq_start;
470 u32 addr_lo;
471 u32 addr_hi;
472 int ret;
473
474 ret = ath12k_hif_get_user_msi_vector(ab, "CE",
475 &msi_data_count, &msi_data_start,
476 &msi_irq_start);
477
478 if (ret)
479 return;
480
481 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
482 ath12k_hif_get_ce_msi_idx(ab, ce_id, &msi_data_idx);
483
484 ring_params->msi_addr = addr_lo;
485 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
486 ring_params->msi_data = (msi_data_idx % msi_data_count) + msi_data_start;
487 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
488 }
489
ath12k_ce_init_ring(struct ath12k_base * ab,struct ath12k_ce_ring * ce_ring,int ce_id,enum hal_ring_type type)490 static int ath12k_ce_init_ring(struct ath12k_base *ab,
491 struct ath12k_ce_ring *ce_ring,
492 int ce_id, enum hal_ring_type type)
493 {
494 struct hal_srng_params params = { 0 };
495 int ret;
496
497 params.ring_base_paddr = ce_ring->base_addr_ce_space;
498 params.ring_base_vaddr = ce_ring->base_addr_owner_space;
499 params.num_entries = ce_ring->nentries;
500
501 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags))
502 ath12k_ce_srng_msi_ring_params_setup(ab, ce_id, ¶ms);
503
504 switch (type) {
505 case HAL_CE_SRC:
506 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags))
507 params.intr_batch_cntr_thres_entries = 1;
508 break;
509 case HAL_CE_DST:
510 params.max_buffer_len = ab->hw_params->host_ce_config[ce_id].src_sz_max;
511 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
512 params.intr_timer_thres_us = 1024;
513 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
514 params.low_threshold = ce_ring->nentries - 3;
515 }
516 break;
517 case HAL_CE_DST_STATUS:
518 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
519 params.intr_batch_cntr_thres_entries = 1;
520 params.intr_timer_thres_us = 0x1000;
521 }
522 break;
523 default:
524 ath12k_warn(ab, "Invalid CE ring type %d\n", type);
525 return -EINVAL;
526 }
527
528 /* TODO: Init other params needed by HAL to init the ring */
529
530 ret = ath12k_hal_srng_setup(ab, type, ce_id, 0, ¶ms);
531 if (ret < 0) {
532 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
533 ret, ce_id);
534 return ret;
535 }
536
537 ce_ring->hal_ring_id = ret;
538
539 return 0;
540 }
541
542 static struct ath12k_ce_ring *
ath12k_ce_alloc_ring(struct ath12k_base * ab,int nentries,int desc_sz)543 ath12k_ce_alloc_ring(struct ath12k_base *ab, int nentries, int desc_sz)
544 {
545 struct ath12k_ce_ring *ce_ring;
546 dma_addr_t base_addr;
547
548 ce_ring = kzalloc(struct_size(ce_ring, skb, nentries), GFP_KERNEL);
549 if (!ce_ring)
550 return ERR_PTR(-ENOMEM);
551
552 ce_ring->nentries = nentries;
553 ce_ring->nentries_mask = nentries - 1;
554
555 /* Legacy platforms that do not support cache
556 * coherent DMA are unsupported
557 */
558 ce_ring->base_addr_owner_space_unaligned =
559 dma_alloc_coherent(ab->dev,
560 nentries * desc_sz + CE_DESC_RING_ALIGN,
561 &base_addr, GFP_KERNEL);
562 if (!ce_ring->base_addr_owner_space_unaligned) {
563 kfree(ce_ring);
564 return ERR_PTR(-ENOMEM);
565 }
566
567 ce_ring->base_addr_ce_space_unaligned = base_addr;
568
569 ce_ring->base_addr_owner_space =
570 PTR_ALIGN(ce_ring->base_addr_owner_space_unaligned,
571 CE_DESC_RING_ALIGN);
572
573 ce_ring->base_addr_ce_space = ALIGN(ce_ring->base_addr_ce_space_unaligned,
574 CE_DESC_RING_ALIGN);
575
576 return ce_ring;
577 }
578
ath12k_ce_alloc_pipe(struct ath12k_base * ab,int ce_id)579 static int ath12k_ce_alloc_pipe(struct ath12k_base *ab, int ce_id)
580 {
581 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
582 const struct ce_attr *attr = &ab->hw_params->host_ce_config[ce_id];
583 struct ath12k_ce_ring *ring;
584 int nentries;
585 int desc_sz;
586
587 pipe->attr_flags = attr->flags;
588
589 if (attr->src_nentries) {
590 pipe->send_cb = ath12k_ce_send_done_cb;
591 nentries = roundup_pow_of_two(attr->src_nentries);
592 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
593 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
594 if (IS_ERR(ring))
595 return PTR_ERR(ring);
596 pipe->src_ring = ring;
597 }
598
599 if (attr->dest_nentries) {
600 pipe->recv_cb = attr->recv_cb;
601 nentries = roundup_pow_of_two(attr->dest_nentries);
602 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
603 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
604 if (IS_ERR(ring))
605 return PTR_ERR(ring);
606 pipe->dest_ring = ring;
607
608 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
609 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
610 if (IS_ERR(ring))
611 return PTR_ERR(ring);
612 pipe->status_ring = ring;
613 }
614
615 return 0;
616 }
617
ath12k_ce_per_engine_service(struct ath12k_base * ab,u16 ce_id)618 void ath12k_ce_per_engine_service(struct ath12k_base *ab, u16 ce_id)
619 {
620 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
621
622 if (pipe->send_cb)
623 pipe->send_cb(pipe);
624
625 if (pipe->recv_cb)
626 ath12k_ce_recv_process_cb(pipe);
627 }
628
ath12k_ce_poll_send_completed(struct ath12k_base * ab,u8 pipe_id)629 void ath12k_ce_poll_send_completed(struct ath12k_base *ab, u8 pipe_id)
630 {
631 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
632
633 if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && pipe->send_cb)
634 pipe->send_cb(pipe);
635 }
636
ath12k_ce_send(struct ath12k_base * ab,struct sk_buff * skb,u8 pipe_id,u16 transfer_id)637 int ath12k_ce_send(struct ath12k_base *ab, struct sk_buff *skb, u8 pipe_id,
638 u16 transfer_id)
639 {
640 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
641 struct hal_ce_srng_src_desc *desc;
642 struct hal_srng *srng;
643 unsigned int write_index, sw_index;
644 unsigned int nentries_mask;
645 int ret = 0;
646 u8 byte_swap_data = 0;
647 int num_used;
648
649 /* Check if some entries could be regained by handling tx completion if
650 * the CE has interrupts disabled and the used entries is more than the
651 * defined usage threshold.
652 */
653 if (pipe->attr_flags & CE_ATTR_DIS_INTR) {
654 spin_lock_bh(&ab->ce.ce_lock);
655 write_index = pipe->src_ring->write_index;
656
657 sw_index = pipe->src_ring->sw_index;
658
659 if (write_index >= sw_index)
660 num_used = write_index - sw_index;
661 else
662 num_used = pipe->src_ring->nentries - sw_index +
663 write_index;
664
665 spin_unlock_bh(&ab->ce.ce_lock);
666
667 if (num_used > ATH12K_CE_USAGE_THRESHOLD)
668 ath12k_ce_poll_send_completed(ab, pipe->pipe_num);
669 }
670
671 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags))
672 return -ESHUTDOWN;
673
674 spin_lock_bh(&ab->ce.ce_lock);
675
676 write_index = pipe->src_ring->write_index;
677 nentries_mask = pipe->src_ring->nentries_mask;
678
679 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
680
681 spin_lock_bh(&srng->lock);
682
683 ath12k_hal_srng_access_begin(ab, srng);
684
685 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) {
686 ath12k_hal_srng_access_end(ab, srng);
687 ret = -ENOBUFS;
688 goto unlock;
689 }
690
691 desc = ath12k_hal_srng_src_get_next_reaped(ab, srng);
692 if (!desc) {
693 ath12k_hal_srng_access_end(ab, srng);
694 ret = -ENOBUFS;
695 goto unlock;
696 }
697
698 if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA)
699 byte_swap_data = 1;
700
701 ath12k_hal_ce_src_set_desc(desc, ATH12K_SKB_CB(skb)->paddr,
702 skb->len, transfer_id, byte_swap_data);
703
704 pipe->src_ring->skb[write_index] = skb;
705 pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask,
706 write_index);
707
708 ath12k_hal_srng_access_end(ab, srng);
709
710 unlock:
711 spin_unlock_bh(&srng->lock);
712
713 spin_unlock_bh(&ab->ce.ce_lock);
714
715 return ret;
716 }
717
ath12k_ce_rx_pipe_cleanup(struct ath12k_ce_pipe * pipe)718 static void ath12k_ce_rx_pipe_cleanup(struct ath12k_ce_pipe *pipe)
719 {
720 struct ath12k_base *ab = pipe->ab;
721 struct ath12k_ce_ring *ring = pipe->dest_ring;
722 struct sk_buff *skb;
723 int i;
724
725 if (!(ring && pipe->buf_sz))
726 return;
727
728 for (i = 0; i < ring->nentries; i++) {
729 skb = ring->skb[i];
730 if (!skb)
731 continue;
732
733 ring->skb[i] = NULL;
734 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
735 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
736 dev_kfree_skb_any(skb);
737 }
738 }
739
ath12k_ce_cleanup_pipes(struct ath12k_base * ab)740 void ath12k_ce_cleanup_pipes(struct ath12k_base *ab)
741 {
742 struct ath12k_ce_pipe *pipe;
743 int pipe_num;
744
745 for (pipe_num = 0; pipe_num < ab->hw_params->ce_count; pipe_num++) {
746 pipe = &ab->ce.ce_pipe[pipe_num];
747 ath12k_ce_rx_pipe_cleanup(pipe);
748
749 /* Cleanup any src CE's which have interrupts disabled */
750 ath12k_ce_poll_send_completed(ab, pipe_num);
751
752 /* NOTE: Should we also clean up tx buffer in all pipes? */
753 }
754 }
755
ath12k_ce_rx_post_buf(struct ath12k_base * ab)756 void ath12k_ce_rx_post_buf(struct ath12k_base *ab)
757 {
758 struct ath12k_ce_pipe *pipe;
759 int i;
760 int ret;
761
762 for (i = 0; i < ab->hw_params->ce_count; i++) {
763 pipe = &ab->ce.ce_pipe[i];
764 ret = ath12k_ce_rx_post_pipe(pipe);
765 if (ret) {
766 if (ret == -ENOSPC)
767 continue;
768
769 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
770 i, ret);
771 mod_timer(&ab->rx_replenish_retry,
772 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES);
773
774 return;
775 }
776 }
777 }
778
ath12k_ce_rx_replenish_retry(struct timer_list * t)779 void ath12k_ce_rx_replenish_retry(struct timer_list *t)
780 {
781 struct ath12k_base *ab = from_timer(ab, t, rx_replenish_retry);
782
783 ath12k_ce_rx_post_buf(ab);
784 }
785
ath12k_ce_shadow_config(struct ath12k_base * ab)786 static void ath12k_ce_shadow_config(struct ath12k_base *ab)
787 {
788 int i;
789
790 for (i = 0; i < ab->hw_params->ce_count; i++) {
791 if (ab->hw_params->host_ce_config[i].src_nentries)
792 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_SRC, i);
793
794 if (ab->hw_params->host_ce_config[i].dest_nentries) {
795 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST, i);
796 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST_STATUS, i);
797 }
798 }
799 }
800
ath12k_ce_get_shadow_config(struct ath12k_base * ab,u32 ** shadow_cfg,u32 * shadow_cfg_len)801 void ath12k_ce_get_shadow_config(struct ath12k_base *ab,
802 u32 **shadow_cfg, u32 *shadow_cfg_len)
803 {
804 if (!ab->hw_params->supports_shadow_regs)
805 return;
806
807 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
808
809 /* shadow is already configured */
810 if (*shadow_cfg_len)
811 return;
812
813 /* shadow isn't configured yet, configure now.
814 * non-CE srngs are configured firstly, then
815 * all CE srngs.
816 */
817 ath12k_hal_srng_shadow_config(ab);
818 ath12k_ce_shadow_config(ab);
819
820 /* get the shadow configuration */
821 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
822 }
823
ath12k_ce_init_pipes(struct ath12k_base * ab)824 int ath12k_ce_init_pipes(struct ath12k_base *ab)
825 {
826 struct ath12k_ce_pipe *pipe;
827 int i;
828 int ret;
829
830 ath12k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v3,
831 &ab->qmi.ce_cfg.shadow_reg_v3_len);
832
833 for (i = 0; i < ab->hw_params->ce_count; i++) {
834 pipe = &ab->ce.ce_pipe[i];
835
836 if (pipe->src_ring) {
837 ret = ath12k_ce_init_ring(ab, pipe->src_ring, i,
838 HAL_CE_SRC);
839 if (ret) {
840 ath12k_warn(ab, "failed to init src ring: %d\n",
841 ret);
842 /* Should we clear any partial init */
843 return ret;
844 }
845
846 pipe->src_ring->write_index = 0;
847 pipe->src_ring->sw_index = 0;
848 }
849
850 if (pipe->dest_ring) {
851 ret = ath12k_ce_init_ring(ab, pipe->dest_ring, i,
852 HAL_CE_DST);
853 if (ret) {
854 ath12k_warn(ab, "failed to init dest ring: %d\n",
855 ret);
856 /* Should we clear any partial init */
857 return ret;
858 }
859
860 pipe->rx_buf_needed = pipe->dest_ring->nentries ?
861 pipe->dest_ring->nentries - 2 : 0;
862
863 pipe->dest_ring->write_index = 0;
864 pipe->dest_ring->sw_index = 0;
865 }
866
867 if (pipe->status_ring) {
868 ret = ath12k_ce_init_ring(ab, pipe->status_ring, i,
869 HAL_CE_DST_STATUS);
870 if (ret) {
871 ath12k_warn(ab, "failed to init dest status ing: %d\n",
872 ret);
873 /* Should we clear any partial init */
874 return ret;
875 }
876
877 pipe->status_ring->write_index = 0;
878 pipe->status_ring->sw_index = 0;
879 }
880 }
881
882 return 0;
883 }
884
ath12k_ce_free_pipes(struct ath12k_base * ab)885 void ath12k_ce_free_pipes(struct ath12k_base *ab)
886 {
887 struct ath12k_ce_pipe *pipe;
888 int desc_sz;
889 int i;
890
891 for (i = 0; i < ab->hw_params->ce_count; i++) {
892 pipe = &ab->ce.ce_pipe[i];
893
894 if (pipe->src_ring) {
895 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
896 dma_free_coherent(ab->dev,
897 pipe->src_ring->nentries * desc_sz +
898 CE_DESC_RING_ALIGN,
899 pipe->src_ring->base_addr_owner_space,
900 pipe->src_ring->base_addr_ce_space);
901 kfree(pipe->src_ring);
902 pipe->src_ring = NULL;
903 }
904
905 if (pipe->dest_ring) {
906 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
907 dma_free_coherent(ab->dev,
908 pipe->dest_ring->nentries * desc_sz +
909 CE_DESC_RING_ALIGN,
910 pipe->dest_ring->base_addr_owner_space,
911 pipe->dest_ring->base_addr_ce_space);
912 kfree(pipe->dest_ring);
913 pipe->dest_ring = NULL;
914 }
915
916 if (pipe->status_ring) {
917 desc_sz =
918 ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
919 dma_free_coherent(ab->dev,
920 pipe->status_ring->nentries * desc_sz +
921 CE_DESC_RING_ALIGN,
922 pipe->status_ring->base_addr_owner_space,
923 pipe->status_ring->base_addr_ce_space);
924 kfree(pipe->status_ring);
925 pipe->status_ring = NULL;
926 }
927 }
928 }
929
ath12k_ce_alloc_pipes(struct ath12k_base * ab)930 int ath12k_ce_alloc_pipes(struct ath12k_base *ab)
931 {
932 struct ath12k_ce_pipe *pipe;
933 int i;
934 int ret;
935 const struct ce_attr *attr;
936
937 spin_lock_init(&ab->ce.ce_lock);
938
939 for (i = 0; i < ab->hw_params->ce_count; i++) {
940 attr = &ab->hw_params->host_ce_config[i];
941 pipe = &ab->ce.ce_pipe[i];
942 pipe->pipe_num = i;
943 pipe->ab = ab;
944 pipe->buf_sz = attr->src_sz_max;
945
946 ret = ath12k_ce_alloc_pipe(ab, i);
947 if (ret) {
948 /* Free any partial successful allocation */
949 ath12k_ce_free_pipes(ab);
950 return ret;
951 }
952 }
953
954 return 0;
955 }
956
ath12k_ce_get_attr_flags(struct ath12k_base * ab,int ce_id)957 int ath12k_ce_get_attr_flags(struct ath12k_base *ab, int ce_id)
958 {
959 if (ce_id >= ab->hw_params->ce_count)
960 return -EINVAL;
961
962 return ab->hw_params->host_ce_config[ce_id].flags;
963 }
964