xref: /openbmc/linux/drivers/net/wireless/ath/ath11k/dp_rx.c (revision af9b2ff010f593d81e2f5fb04155e9fc25b9dfd0)
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "debugfs_htt_stats.h"
14 #include "debugfs_sta.h"
15 #include "hal_desc.h"
16 #include "hw.h"
17 #include "dp_rx.h"
18 #include "hal_rx.h"
19 #include "dp_tx.h"
20 #include "peer.h"
21 
22 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23 
24 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)25 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
26 {
27 	return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
28 }
29 
30 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)31 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
32 							struct hal_rx_desc *desc)
33 {
34 	if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
35 		return HAL_ENCRYPT_TYPE_OPEN;
36 
37 	return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
38 }
39 
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)40 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
41 						      struct hal_rx_desc *desc)
42 {
43 	return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
44 }
45 
46 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)47 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
48 					    struct hal_rx_desc *desc)
49 {
50 	return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
51 }
52 
53 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)54 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
55 					      struct hal_rx_desc *desc)
56 {
57 	return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
58 }
59 
60 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)61 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
62 					      struct hal_rx_desc *desc)
63 {
64 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
65 }
66 
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)67 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
68 						      struct hal_rx_desc *desc)
69 {
70 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
71 }
72 
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)73 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
74 							struct sk_buff *skb)
75 {
76 	struct ieee80211_hdr *hdr;
77 
78 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
79 	return ieee80211_has_morefrags(hdr->frame_control);
80 }
81 
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)82 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
83 						    struct sk_buff *skb)
84 {
85 	struct ieee80211_hdr *hdr;
86 
87 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
88 	return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
89 }
90 
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)91 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
92 						   struct hal_rx_desc *desc)
93 {
94 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
95 }
96 
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)97 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
98 					       struct hal_rx_desc *desc)
99 {
100 	return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
101 }
102 
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)103 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
104 {
105 	return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
106 			   __le32_to_cpu(attn->info2));
107 }
108 
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)109 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
110 {
111 	return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
112 			   __le32_to_cpu(attn->info1));
113 }
114 
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)115 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
116 {
117 	return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
118 			   __le32_to_cpu(attn->info1));
119 }
120 
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)121 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
122 {
123 	return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
124 			  __le32_to_cpu(attn->info2)) ==
125 		RX_DESC_DECRYPT_STATUS_CODE_OK);
126 }
127 
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)128 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
129 {
130 	u32 info = __le32_to_cpu(attn->info1);
131 	u32 errmap = 0;
132 
133 	if (info & RX_ATTENTION_INFO1_FCS_ERR)
134 		errmap |= DP_RX_MPDU_ERR_FCS;
135 
136 	if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
137 		errmap |= DP_RX_MPDU_ERR_DECRYPT;
138 
139 	if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
140 		errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
141 
142 	if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
143 		errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
144 
145 	if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
146 		errmap |= DP_RX_MPDU_ERR_OVERFLOW;
147 
148 	if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
149 		errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
150 
151 	if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
152 		errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
153 
154 	return errmap;
155 }
156 
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
158 					     struct hal_rx_desc *desc)
159 {
160 	struct rx_attention *rx_attention;
161 	u32 errmap;
162 
163 	rx_attention = ath11k_dp_rx_get_attention(ab, desc);
164 	errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
165 
166 	return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
167 }
168 
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
170 						     struct hal_rx_desc *desc)
171 {
172 	return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
173 }
174 
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
176 					       struct hal_rx_desc *desc)
177 {
178 	return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
179 }
180 
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
182 						    struct hal_rx_desc *desc)
183 {
184 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
185 }
186 
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
188 						 struct hal_rx_desc *desc)
189 {
190 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
191 }
192 
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
194 						 struct hal_rx_desc *desc)
195 {
196 	return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
197 }
198 
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
200 						    struct hal_rx_desc *desc)
201 {
202 	return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
203 }
204 
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
206 					       struct hal_rx_desc *desc)
207 {
208 	return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
209 }
210 
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
212 					       struct hal_rx_desc *desc)
213 {
214 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
215 }
216 
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)217 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
218 						    struct hal_rx_desc *desc)
219 {
220 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
221 }
222 
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)223 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
224 					       struct hal_rx_desc *desc)
225 {
226 	return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
227 }
228 
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)229 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
230 						      struct hal_rx_desc *desc)
231 {
232 	return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
233 }
234 
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)235 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
236 					      struct hal_rx_desc *desc)
237 {
238 	return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
239 }
240 
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)241 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
242 					   struct hal_rx_desc *fdesc,
243 					   struct hal_rx_desc *ldesc)
244 {
245 	ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
246 }
247 
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)248 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
249 {
250 	return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
251 			 __le32_to_cpu(attn->info1));
252 }
253 
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)254 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
255 						struct hal_rx_desc *rx_desc)
256 {
257 	u8 *rx_pkt_hdr;
258 
259 	rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
260 
261 	return rx_pkt_hdr;
262 }
263 
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)264 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
265 					       struct hal_rx_desc *rx_desc)
266 {
267 	u32 tlv_tag;
268 
269 	tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
270 
271 	return tlv_tag == HAL_RX_MPDU_START;
272 }
273 
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)274 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
275 					      struct hal_rx_desc *rx_desc)
276 {
277 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
278 }
279 
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)280 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
281 						 struct hal_rx_desc *desc,
282 						 u16 len)
283 {
284 	ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
285 }
286 
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)287 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
288 					struct hal_rx_desc *desc)
289 {
290 	struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
291 
292 	return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
293 		(!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
294 		 __le32_to_cpu(attn->info1)));
295 }
296 
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)297 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
298 					     struct hal_rx_desc *desc)
299 {
300 	return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
301 }
302 
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)303 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
304 					     struct hal_rx_desc *desc)
305 {
306 	return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
307 }
308 
ath11k_dp_service_mon_ring(struct timer_list * t)309 static void ath11k_dp_service_mon_ring(struct timer_list *t)
310 {
311 	struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
312 	int i;
313 
314 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
315 		ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
316 
317 	mod_timer(&ab->mon_reap_timer, jiffies +
318 		  msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
319 }
320 
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)321 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
322 {
323 	int i, reaped = 0;
324 	unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
325 
326 	do {
327 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
328 			reaped += ath11k_dp_rx_process_mon_rings(ab, i,
329 								 NULL,
330 								 DP_MON_SERVICE_BUDGET);
331 
332 		/* nothing more to reap */
333 		if (reaped < DP_MON_SERVICE_BUDGET)
334 			return 0;
335 
336 	} while (time_before(jiffies, timeout));
337 
338 	ath11k_warn(ab, "dp mon ring purge timeout");
339 
340 	return -ETIMEDOUT;
341 }
342 
343 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)344 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
345 			       struct dp_rxdma_ring *rx_ring,
346 			       int req_entries,
347 			       enum hal_rx_buf_return_buf_manager mgr)
348 {
349 	struct hal_srng *srng;
350 	u32 *desc;
351 	struct sk_buff *skb;
352 	int num_free;
353 	int num_remain;
354 	int buf_id;
355 	u32 cookie;
356 	dma_addr_t paddr;
357 
358 	req_entries = min(req_entries, rx_ring->bufs_max);
359 
360 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
361 
362 	spin_lock_bh(&srng->lock);
363 
364 	ath11k_hal_srng_access_begin(ab, srng);
365 
366 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
367 	if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
368 		req_entries = num_free;
369 
370 	req_entries = min(num_free, req_entries);
371 	num_remain = req_entries;
372 
373 	while (num_remain > 0) {
374 		skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
375 				    DP_RX_BUFFER_ALIGN_SIZE);
376 		if (!skb)
377 			break;
378 
379 		if (!IS_ALIGNED((unsigned long)skb->data,
380 				DP_RX_BUFFER_ALIGN_SIZE)) {
381 			skb_pull(skb,
382 				 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
383 				 skb->data);
384 		}
385 
386 		paddr = dma_map_single(ab->dev, skb->data,
387 				       skb->len + skb_tailroom(skb),
388 				       DMA_FROM_DEVICE);
389 		if (dma_mapping_error(ab->dev, paddr))
390 			goto fail_free_skb;
391 
392 		spin_lock_bh(&rx_ring->idr_lock);
393 		buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
394 				   (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
395 		spin_unlock_bh(&rx_ring->idr_lock);
396 		if (buf_id <= 0)
397 			goto fail_dma_unmap;
398 
399 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
400 		if (!desc)
401 			goto fail_idr_remove;
402 
403 		ATH11K_SKB_RXCB(skb)->paddr = paddr;
404 
405 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
406 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
407 
408 		num_remain--;
409 
410 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
411 	}
412 
413 	ath11k_hal_srng_access_end(ab, srng);
414 
415 	spin_unlock_bh(&srng->lock);
416 
417 	return req_entries - num_remain;
418 
419 fail_idr_remove:
420 	spin_lock_bh(&rx_ring->idr_lock);
421 	idr_remove(&rx_ring->bufs_idr, buf_id);
422 	spin_unlock_bh(&rx_ring->idr_lock);
423 fail_dma_unmap:
424 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
425 			 DMA_FROM_DEVICE);
426 fail_free_skb:
427 	dev_kfree_skb_any(skb);
428 
429 	ath11k_hal_srng_access_end(ab, srng);
430 
431 	spin_unlock_bh(&srng->lock);
432 
433 	return req_entries - num_remain;
434 }
435 
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)436 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
437 					 struct dp_rxdma_ring *rx_ring)
438 {
439 	struct sk_buff *skb;
440 	int buf_id;
441 
442 	spin_lock_bh(&rx_ring->idr_lock);
443 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 		idr_remove(&rx_ring->bufs_idr, buf_id);
445 		/* TODO: Understand where internal driver does this dma_unmap
446 		 * of rxdma_buffer.
447 		 */
448 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 				 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 		dev_kfree_skb_any(skb);
451 	}
452 
453 	idr_destroy(&rx_ring->bufs_idr);
454 	spin_unlock_bh(&rx_ring->idr_lock);
455 
456 	return 0;
457 }
458 
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)459 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
460 {
461 	struct ath11k_pdev_dp *dp = &ar->dp;
462 	struct ath11k_base *ab = ar->ab;
463 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
464 	int i;
465 
466 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
467 
468 	rx_ring = &dp->rxdma_mon_buf_ring;
469 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
470 
471 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
472 		rx_ring = &dp->rx_mon_status_refill_ring[i];
473 		ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
474 	}
475 
476 	return 0;
477 }
478 
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)479 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
480 					  struct dp_rxdma_ring *rx_ring,
481 					  u32 ringtype)
482 {
483 	struct ath11k_pdev_dp *dp = &ar->dp;
484 	int num_entries;
485 
486 	num_entries = rx_ring->refill_buf_ring.size /
487 		ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
488 
489 	rx_ring->bufs_max = num_entries;
490 	ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
491 				   ar->ab->hw_params.hal_params->rx_buf_rbm);
492 	return 0;
493 }
494 
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)495 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
496 {
497 	struct ath11k_pdev_dp *dp = &ar->dp;
498 	struct ath11k_base *ab = ar->ab;
499 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
500 	int i;
501 
502 	ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
503 
504 	if (ar->ab->hw_params.rxdma1_enable) {
505 		rx_ring = &dp->rxdma_mon_buf_ring;
506 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
507 	}
508 
509 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
510 		rx_ring = &dp->rx_mon_status_refill_ring[i];
511 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
512 	}
513 
514 	return 0;
515 }
516 
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)517 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
518 {
519 	struct ath11k_pdev_dp *dp = &ar->dp;
520 	struct ath11k_base *ab = ar->ab;
521 	int i;
522 
523 	ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
524 
525 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
526 		if (ab->hw_params.rx_mac_buf_ring)
527 			ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
528 
529 		ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
530 		ath11k_dp_srng_cleanup(ab,
531 				       &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
532 	}
533 
534 	ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
535 }
536 
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)537 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
538 {
539 	struct ath11k_dp *dp = &ab->dp;
540 	int i;
541 
542 	for (i = 0; i < DP_REO_DST_RING_MAX; i++)
543 		ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
544 }
545 
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)546 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
547 {
548 	struct ath11k_dp *dp = &ab->dp;
549 	int ret;
550 	int i;
551 
552 	for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
553 		ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
554 					   HAL_REO_DST, i, 0,
555 					   DP_REO_DST_RING_SIZE);
556 		if (ret) {
557 			ath11k_warn(ab, "failed to setup reo_dst_ring\n");
558 			goto err_reo_cleanup;
559 		}
560 	}
561 
562 	return 0;
563 
564 err_reo_cleanup:
565 	ath11k_dp_pdev_reo_cleanup(ab);
566 
567 	return ret;
568 }
569 
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)570 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
571 {
572 	struct ath11k_pdev_dp *dp = &ar->dp;
573 	struct ath11k_base *ab = ar->ab;
574 	struct dp_srng *srng = NULL;
575 	int i;
576 	int ret;
577 
578 	ret = ath11k_dp_srng_setup(ar->ab,
579 				   &dp->rx_refill_buf_ring.refill_buf_ring,
580 				   HAL_RXDMA_BUF, 0,
581 				   dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
582 	if (ret) {
583 		ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
584 		return ret;
585 	}
586 
587 	if (ar->ab->hw_params.rx_mac_buf_ring) {
588 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
589 			ret = ath11k_dp_srng_setup(ar->ab,
590 						   &dp->rx_mac_buf_ring[i],
591 						   HAL_RXDMA_BUF, 1,
592 						   dp->mac_id + i, 1024);
593 			if (ret) {
594 				ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
595 					    i);
596 				return ret;
597 			}
598 		}
599 	}
600 
601 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
602 		ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
603 					   HAL_RXDMA_DST, 0, dp->mac_id + i,
604 					   DP_RXDMA_ERR_DST_RING_SIZE);
605 		if (ret) {
606 			ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
607 			return ret;
608 		}
609 	}
610 
611 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
612 		srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
613 		ret = ath11k_dp_srng_setup(ar->ab,
614 					   srng,
615 					   HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
616 					   DP_RXDMA_MON_STATUS_RING_SIZE);
617 		if (ret) {
618 			ath11k_warn(ar->ab,
619 				    "failed to setup rx_mon_status_refill_ring %d\n", i);
620 			return ret;
621 		}
622 	}
623 
624 	/* if rxdma1_enable is false, then it doesn't need
625 	 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
626 	 * and rxdma_mon_desc_ring.
627 	 * init reap timer for QCA6390.
628 	 */
629 	if (!ar->ab->hw_params.rxdma1_enable) {
630 		//init mon status buffer reap timer
631 		timer_setup(&ar->ab->mon_reap_timer,
632 			    ath11k_dp_service_mon_ring, 0);
633 		return 0;
634 	}
635 
636 	ret = ath11k_dp_srng_setup(ar->ab,
637 				   &dp->rxdma_mon_buf_ring.refill_buf_ring,
638 				   HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
639 				   DP_RXDMA_MONITOR_BUF_RING_SIZE);
640 	if (ret) {
641 		ath11k_warn(ar->ab,
642 			    "failed to setup HAL_RXDMA_MONITOR_BUF\n");
643 		return ret;
644 	}
645 
646 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
647 				   HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
648 				   DP_RXDMA_MONITOR_DST_RING_SIZE);
649 	if (ret) {
650 		ath11k_warn(ar->ab,
651 			    "failed to setup HAL_RXDMA_MONITOR_DST\n");
652 		return ret;
653 	}
654 
655 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
656 				   HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
657 				   DP_RXDMA_MONITOR_DESC_RING_SIZE);
658 	if (ret) {
659 		ath11k_warn(ar->ab,
660 			    "failed to setup HAL_RXDMA_MONITOR_DESC\n");
661 		return ret;
662 	}
663 
664 	return 0;
665 }
666 
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)667 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
668 {
669 	struct ath11k_dp *dp = &ab->dp;
670 	struct dp_reo_cmd *cmd, *tmp;
671 	struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
672 	struct dp_rx_tid *rx_tid;
673 
674 	spin_lock_bh(&dp->reo_cmd_lock);
675 	list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
676 		list_del(&cmd->list);
677 		rx_tid = &cmd->data;
678 		if (rx_tid->vaddr) {
679 			dma_unmap_single(ab->dev, rx_tid->paddr,
680 					 rx_tid->size, DMA_BIDIRECTIONAL);
681 			kfree(rx_tid->vaddr);
682 			rx_tid->vaddr = NULL;
683 		}
684 		kfree(cmd);
685 	}
686 
687 	list_for_each_entry_safe(cmd_cache, tmp_cache,
688 				 &dp->reo_cmd_cache_flush_list, list) {
689 		list_del(&cmd_cache->list);
690 		dp->reo_cmd_cache_flush_count--;
691 		rx_tid = &cmd_cache->data;
692 		if (rx_tid->vaddr) {
693 			dma_unmap_single(ab->dev, rx_tid->paddr,
694 					 rx_tid->size, DMA_BIDIRECTIONAL);
695 			kfree(rx_tid->vaddr);
696 			rx_tid->vaddr = NULL;
697 		}
698 		kfree(cmd_cache);
699 	}
700 	spin_unlock_bh(&dp->reo_cmd_lock);
701 }
702 
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)703 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
704 				   enum hal_reo_cmd_status status)
705 {
706 	struct dp_rx_tid *rx_tid = ctx;
707 
708 	if (status != HAL_REO_CMD_SUCCESS)
709 		ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
710 			    rx_tid->tid, status);
711 	if (rx_tid->vaddr) {
712 		dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
713 				 DMA_BIDIRECTIONAL);
714 		kfree(rx_tid->vaddr);
715 		rx_tid->vaddr = NULL;
716 	}
717 }
718 
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 				      struct dp_rx_tid *rx_tid)
721 {
722 	struct ath11k_hal_reo_cmd cmd = {0};
723 	unsigned long tot_desc_sz, desc_sz;
724 	int ret;
725 
726 	tot_desc_sz = rx_tid->size;
727 	desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728 
729 	while (tot_desc_sz > desc_sz) {
730 		tot_desc_sz -= desc_sz;
731 		cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 						HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 						NULL);
736 		if (ret)
737 			ath11k_warn(ab,
738 				    "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 				    rx_tid->tid, ret);
740 	}
741 
742 	memset(&cmd, 0, sizeof(cmd));
743 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 	ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 					HAL_REO_CMD_FLUSH_CACHE,
748 					&cmd, ath11k_dp_reo_cmd_free);
749 	if (ret) {
750 		ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 			   rx_tid->tid, ret);
752 		dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
753 				 DMA_BIDIRECTIONAL);
754 		kfree(rx_tid->vaddr);
755 		rx_tid->vaddr = NULL;
756 	}
757 }
758 
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)759 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
760 				      enum hal_reo_cmd_status status)
761 {
762 	struct ath11k_base *ab = dp->ab;
763 	struct dp_rx_tid *rx_tid = ctx;
764 	struct dp_reo_cache_flush_elem *elem, *tmp;
765 
766 	if (status == HAL_REO_CMD_DRAIN) {
767 		goto free_desc;
768 	} else if (status != HAL_REO_CMD_SUCCESS) {
769 		/* Shouldn't happen! Cleanup in case of other failure? */
770 		ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
771 			    rx_tid->tid, status);
772 		return;
773 	}
774 
775 	elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
776 	if (!elem)
777 		goto free_desc;
778 
779 	elem->ts = jiffies;
780 	memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
781 
782 	spin_lock_bh(&dp->reo_cmd_lock);
783 	list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
784 	dp->reo_cmd_cache_flush_count++;
785 
786 	/* Flush and invalidate aged REO desc from HW cache */
787 	list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
788 				 list) {
789 		if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
790 		    time_after(jiffies, elem->ts +
791 			       msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
792 			list_del(&elem->list);
793 			dp->reo_cmd_cache_flush_count--;
794 			spin_unlock_bh(&dp->reo_cmd_lock);
795 
796 			ath11k_dp_reo_cache_flush(ab, &elem->data);
797 			kfree(elem);
798 			spin_lock_bh(&dp->reo_cmd_lock);
799 		}
800 	}
801 	spin_unlock_bh(&dp->reo_cmd_lock);
802 
803 	return;
804 free_desc:
805 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
806 			 DMA_BIDIRECTIONAL);
807 	kfree(rx_tid->vaddr);
808 	rx_tid->vaddr = NULL;
809 }
810 
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)811 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
812 			       struct ath11k_peer *peer, u8 tid)
813 {
814 	struct ath11k_hal_reo_cmd cmd = {0};
815 	struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
816 	int ret;
817 
818 	if (!rx_tid->active)
819 		return;
820 
821 	rx_tid->active = false;
822 
823 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 	cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 					ath11k_dp_rx_tid_del_func);
830 	if (ret) {
831 		if (ret != -ESHUTDOWN)
832 			ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
833 				   tid, ret);
834 		dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
835 				 DMA_BIDIRECTIONAL);
836 		kfree(rx_tid->vaddr);
837 		rx_tid->vaddr = NULL;
838 	}
839 
840 	rx_tid->paddr = 0;
841 	rx_tid->size = 0;
842 }
843 
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)844 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
845 					 u32 *link_desc,
846 					 enum hal_wbm_rel_bm_act action)
847 {
848 	struct ath11k_dp *dp = &ab->dp;
849 	struct hal_srng *srng;
850 	u32 *desc;
851 	int ret = 0;
852 
853 	srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
854 
855 	spin_lock_bh(&srng->lock);
856 
857 	ath11k_hal_srng_access_begin(ab, srng);
858 
859 	desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
860 	if (!desc) {
861 		ret = -ENOBUFS;
862 		goto exit;
863 	}
864 
865 	ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
866 					 action);
867 
868 exit:
869 	ath11k_hal_srng_access_end(ab, srng);
870 
871 	spin_unlock_bh(&srng->lock);
872 
873 	return ret;
874 }
875 
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)876 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
877 {
878 	struct ath11k_base *ab = rx_tid->ab;
879 
880 	lockdep_assert_held(&ab->base_lock);
881 
882 	if (rx_tid->dst_ring_desc) {
883 		if (rel_link_desc)
884 			ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
885 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
886 		kfree(rx_tid->dst_ring_desc);
887 		rx_tid->dst_ring_desc = NULL;
888 	}
889 
890 	rx_tid->cur_sn = 0;
891 	rx_tid->last_frag_no = 0;
892 	rx_tid->rx_frag_bitmap = 0;
893 	__skb_queue_purge(&rx_tid->rx_frags);
894 }
895 
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)896 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
897 {
898 	struct dp_rx_tid *rx_tid;
899 	int i;
900 
901 	lockdep_assert_held(&ar->ab->base_lock);
902 
903 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
904 		rx_tid = &peer->rx_tid[i];
905 
906 		spin_unlock_bh(&ar->ab->base_lock);
907 		del_timer_sync(&rx_tid->frag_timer);
908 		spin_lock_bh(&ar->ab->base_lock);
909 
910 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
911 	}
912 }
913 
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)914 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
915 {
916 	struct dp_rx_tid *rx_tid;
917 	int i;
918 
919 	lockdep_assert_held(&ar->ab->base_lock);
920 
921 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
922 		rx_tid = &peer->rx_tid[i];
923 
924 		ath11k_peer_rx_tid_delete(ar, peer, i);
925 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
926 
927 		spin_unlock_bh(&ar->ab->base_lock);
928 		del_timer_sync(&rx_tid->frag_timer);
929 		spin_lock_bh(&ar->ab->base_lock);
930 	}
931 }
932 
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)933 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
934 					 struct ath11k_peer *peer,
935 					 struct dp_rx_tid *rx_tid,
936 					 u32 ba_win_sz, u16 ssn,
937 					 bool update_ssn)
938 {
939 	struct ath11k_hal_reo_cmd cmd = {0};
940 	int ret;
941 
942 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
943 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
944 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
945 	cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
946 	cmd.ba_window_size = ba_win_sz;
947 
948 	if (update_ssn) {
949 		cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
950 		cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
951 	}
952 
953 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
954 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
955 					NULL);
956 	if (ret) {
957 		ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
958 			    rx_tid->tid, ret);
959 		return ret;
960 	}
961 
962 	rx_tid->ba_win_sz = ba_win_sz;
963 
964 	return 0;
965 }
966 
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)967 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
968 				      const u8 *peer_mac, int vdev_id, u8 tid)
969 {
970 	struct ath11k_peer *peer;
971 	struct dp_rx_tid *rx_tid;
972 
973 	spin_lock_bh(&ab->base_lock);
974 
975 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
976 	if (!peer) {
977 		ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
978 		goto unlock_exit;
979 	}
980 
981 	rx_tid = &peer->rx_tid[tid];
982 	if (!rx_tid->active)
983 		goto unlock_exit;
984 
985 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
986 			 DMA_BIDIRECTIONAL);
987 	kfree(rx_tid->vaddr);
988 	rx_tid->vaddr = NULL;
989 
990 	rx_tid->active = false;
991 
992 unlock_exit:
993 	spin_unlock_bh(&ab->base_lock);
994 }
995 
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)996 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
997 			     u8 tid, u32 ba_win_sz, u16 ssn,
998 			     enum hal_pn_type pn_type)
999 {
1000 	struct ath11k_base *ab = ar->ab;
1001 	struct ath11k_peer *peer;
1002 	struct dp_rx_tid *rx_tid;
1003 	u32 hw_desc_sz;
1004 	u32 *addr_aligned;
1005 	void *vaddr;
1006 	dma_addr_t paddr;
1007 	int ret;
1008 
1009 	spin_lock_bh(&ab->base_lock);
1010 
1011 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1012 	if (!peer) {
1013 		ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
1014 			    peer_mac);
1015 		spin_unlock_bh(&ab->base_lock);
1016 		return -ENOENT;
1017 	}
1018 
1019 	rx_tid = &peer->rx_tid[tid];
1020 	/* Update the tid queue if it is already setup */
1021 	if (rx_tid->active) {
1022 		paddr = rx_tid->paddr;
1023 		ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1024 						    ba_win_sz, ssn, true);
1025 		spin_unlock_bh(&ab->base_lock);
1026 		if (ret) {
1027 			ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
1028 				    peer_mac, tid, ret);
1029 			return ret;
1030 		}
1031 
1032 		ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1033 							     peer_mac, paddr,
1034 							     tid, 1, ba_win_sz);
1035 		if (ret)
1036 			ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
1037 				    peer_mac, tid, ret);
1038 		return ret;
1039 	}
1040 
1041 	rx_tid->tid = tid;
1042 
1043 	rx_tid->ba_win_sz = ba_win_sz;
1044 
1045 	/* TODO: Optimize the memory allocation for qos tid based on
1046 	 * the actual BA window size in REO tid update path.
1047 	 */
1048 	if (tid == HAL_DESC_REO_NON_QOS_TID)
1049 		hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1050 	else
1051 		hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1052 
1053 	vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
1054 	if (!vaddr) {
1055 		spin_unlock_bh(&ab->base_lock);
1056 		return -ENOMEM;
1057 	}
1058 
1059 	addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
1060 
1061 	ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
1062 				   ssn, pn_type);
1063 
1064 	paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1065 			       DMA_BIDIRECTIONAL);
1066 
1067 	ret = dma_mapping_error(ab->dev, paddr);
1068 	if (ret) {
1069 		spin_unlock_bh(&ab->base_lock);
1070 		ath11k_warn(ab, "failed to setup dma map for peer %pM rx tid %d: %d\n",
1071 			    peer_mac, tid, ret);
1072 		goto err_mem_free;
1073 	}
1074 
1075 	rx_tid->vaddr = vaddr;
1076 	rx_tid->paddr = paddr;
1077 	rx_tid->size = hw_desc_sz;
1078 	rx_tid->active = true;
1079 
1080 	spin_unlock_bh(&ab->base_lock);
1081 
1082 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1083 						     paddr, tid, 1, ba_win_sz);
1084 	if (ret) {
1085 		ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
1086 			    peer_mac, tid, ret);
1087 		ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1088 	}
1089 
1090 	return ret;
1091 
1092 err_mem_free:
1093 	kfree(rx_tid->vaddr);
1094 	rx_tid->vaddr = NULL;
1095 
1096 	return ret;
1097 }
1098 
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1099 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1100 			     struct ieee80211_ampdu_params *params)
1101 {
1102 	struct ath11k_base *ab = ar->ab;
1103 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1104 	int vdev_id = arsta->arvif->vdev_id;
1105 	int ret;
1106 
1107 	ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1108 				       params->tid, params->buf_size,
1109 				       params->ssn, arsta->pn_type);
1110 	if (ret)
1111 		ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1112 
1113 	return ret;
1114 }
1115 
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1116 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1117 			    struct ieee80211_ampdu_params *params)
1118 {
1119 	struct ath11k_base *ab = ar->ab;
1120 	struct ath11k_peer *peer;
1121 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1122 	int vdev_id = arsta->arvif->vdev_id;
1123 	dma_addr_t paddr;
1124 	bool active;
1125 	int ret;
1126 
1127 	spin_lock_bh(&ab->base_lock);
1128 
1129 	peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1130 	if (!peer) {
1131 		ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1132 		spin_unlock_bh(&ab->base_lock);
1133 		return -ENOENT;
1134 	}
1135 
1136 	paddr = peer->rx_tid[params->tid].paddr;
1137 	active = peer->rx_tid[params->tid].active;
1138 
1139 	if (!active) {
1140 		spin_unlock_bh(&ab->base_lock);
1141 		return 0;
1142 	}
1143 
1144 	ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1145 	spin_unlock_bh(&ab->base_lock);
1146 	if (ret) {
1147 		ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1148 			    params->tid, ret);
1149 		return ret;
1150 	}
1151 
1152 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1153 						     params->sta->addr, paddr,
1154 						     params->tid, 1, 1);
1155 	if (ret)
1156 		ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1157 			    ret);
1158 
1159 	return ret;
1160 }
1161 
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1162 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1163 				       const u8 *peer_addr,
1164 				       enum set_key_cmd key_cmd,
1165 				       struct ieee80211_key_conf *key)
1166 {
1167 	struct ath11k *ar = arvif->ar;
1168 	struct ath11k_base *ab = ar->ab;
1169 	struct ath11k_hal_reo_cmd cmd = {0};
1170 	struct ath11k_peer *peer;
1171 	struct dp_rx_tid *rx_tid;
1172 	u8 tid;
1173 	int ret = 0;
1174 
1175 	/* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1176 	 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1177 	 * for now.
1178 	 */
1179 	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1180 		return 0;
1181 
1182 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1183 	cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1184 		    HAL_REO_CMD_UPD0_PN_SIZE |
1185 		    HAL_REO_CMD_UPD0_PN_VALID |
1186 		    HAL_REO_CMD_UPD0_PN_CHECK |
1187 		    HAL_REO_CMD_UPD0_SVLD;
1188 
1189 	switch (key->cipher) {
1190 	case WLAN_CIPHER_SUITE_TKIP:
1191 	case WLAN_CIPHER_SUITE_CCMP:
1192 	case WLAN_CIPHER_SUITE_CCMP_256:
1193 	case WLAN_CIPHER_SUITE_GCMP:
1194 	case WLAN_CIPHER_SUITE_GCMP_256:
1195 		if (key_cmd == SET_KEY) {
1196 			cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1197 			cmd.pn_size = 48;
1198 		}
1199 		break;
1200 	default:
1201 		break;
1202 	}
1203 
1204 	spin_lock_bh(&ab->base_lock);
1205 
1206 	peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1207 	if (!peer) {
1208 		ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1209 		spin_unlock_bh(&ab->base_lock);
1210 		return -ENOENT;
1211 	}
1212 
1213 	for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1214 		rx_tid = &peer->rx_tid[tid];
1215 		if (!rx_tid->active)
1216 			continue;
1217 		cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1218 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1219 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1220 						HAL_REO_CMD_UPDATE_RX_QUEUE,
1221 						&cmd, NULL);
1222 		if (ret) {
1223 			ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1224 				    tid, ret);
1225 			break;
1226 		}
1227 	}
1228 
1229 	spin_unlock_bh(&ab->base_lock);
1230 
1231 	return ret;
1232 }
1233 
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1234 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1235 					     u16 peer_id)
1236 {
1237 	int i;
1238 
1239 	for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1240 		if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1241 			if (peer_id == ppdu_stats->user_stats[i].peer_id)
1242 				return i;
1243 		} else {
1244 			return i;
1245 		}
1246 	}
1247 
1248 	return -EINVAL;
1249 }
1250 
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1251 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1252 					   u16 tag, u16 len, const void *ptr,
1253 					   void *data)
1254 {
1255 	struct htt_ppdu_stats_info *ppdu_info;
1256 	struct htt_ppdu_user_stats *user_stats;
1257 	int cur_user;
1258 	u16 peer_id;
1259 
1260 	ppdu_info = (struct htt_ppdu_stats_info *)data;
1261 
1262 	switch (tag) {
1263 	case HTT_PPDU_STATS_TAG_COMMON:
1264 		if (len < sizeof(struct htt_ppdu_stats_common)) {
1265 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1266 				    len, tag);
1267 			return -EINVAL;
1268 		}
1269 		memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1270 		       sizeof(struct htt_ppdu_stats_common));
1271 		break;
1272 	case HTT_PPDU_STATS_TAG_USR_RATE:
1273 		if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1274 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1275 				    len, tag);
1276 			return -EINVAL;
1277 		}
1278 
1279 		peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1280 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1281 						      peer_id);
1282 		if (cur_user < 0)
1283 			return -EINVAL;
1284 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1285 		user_stats->peer_id = peer_id;
1286 		user_stats->is_valid_peer_id = true;
1287 		memcpy((void *)&user_stats->rate, ptr,
1288 		       sizeof(struct htt_ppdu_stats_user_rate));
1289 		user_stats->tlv_flags |= BIT(tag);
1290 		break;
1291 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1292 		if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1293 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1294 				    len, tag);
1295 			return -EINVAL;
1296 		}
1297 
1298 		peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1299 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1300 						      peer_id);
1301 		if (cur_user < 0)
1302 			return -EINVAL;
1303 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1304 		user_stats->peer_id = peer_id;
1305 		user_stats->is_valid_peer_id = true;
1306 		memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1307 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1308 		user_stats->tlv_flags |= BIT(tag);
1309 		break;
1310 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1311 		if (len <
1312 		    sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1313 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1314 				    len, tag);
1315 			return -EINVAL;
1316 		}
1317 
1318 		peer_id =
1319 		((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1320 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1321 						      peer_id);
1322 		if (cur_user < 0)
1323 			return -EINVAL;
1324 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1325 		user_stats->peer_id = peer_id;
1326 		user_stats->is_valid_peer_id = true;
1327 		memcpy((void *)&user_stats->ack_ba, ptr,
1328 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1329 		user_stats->tlv_flags |= BIT(tag);
1330 		break;
1331 	}
1332 	return 0;
1333 }
1334 
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1335 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1336 			   int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1337 				       const void *ptr, void *data),
1338 			   void *data)
1339 {
1340 	const struct htt_tlv *tlv;
1341 	const void *begin = ptr;
1342 	u16 tlv_tag, tlv_len;
1343 	int ret = -EINVAL;
1344 
1345 	while (len > 0) {
1346 		if (len < sizeof(*tlv)) {
1347 			ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1348 				   ptr - begin, len, sizeof(*tlv));
1349 			return -EINVAL;
1350 		}
1351 		tlv = (struct htt_tlv *)ptr;
1352 		tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1353 		tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1354 		ptr += sizeof(*tlv);
1355 		len -= sizeof(*tlv);
1356 
1357 		if (tlv_len > len) {
1358 			ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1359 				   tlv_tag, ptr - begin, len, tlv_len);
1360 			return -EINVAL;
1361 		}
1362 		ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1363 		if (ret == -ENOMEM)
1364 			return ret;
1365 
1366 		ptr += tlv_len;
1367 		len -= tlv_len;
1368 	}
1369 	return 0;
1370 }
1371 
1372 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1373 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1374 				struct htt_ppdu_stats *ppdu_stats, u8 user)
1375 {
1376 	struct ath11k_base *ab = ar->ab;
1377 	struct ath11k_peer *peer;
1378 	struct ieee80211_sta *sta;
1379 	struct ath11k_sta *arsta;
1380 	struct htt_ppdu_stats_user_rate *user_rate;
1381 	struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1382 	struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1383 	struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1384 	int ret;
1385 	u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1386 	u32 succ_bytes = 0;
1387 	u16 rate = 0, succ_pkts = 0;
1388 	u32 tx_duration = 0;
1389 	u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1390 	bool is_ampdu = false;
1391 
1392 	if (!usr_stats)
1393 		return;
1394 
1395 	if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1396 		return;
1397 
1398 	if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1399 		is_ampdu =
1400 			HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1401 
1402 	if (usr_stats->tlv_flags &
1403 	    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1404 		succ_bytes = usr_stats->ack_ba.success_bytes;
1405 		succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1406 				      usr_stats->ack_ba.info);
1407 		tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1408 				usr_stats->ack_ba.info);
1409 	}
1410 
1411 	if (common->fes_duration_us)
1412 		tx_duration = common->fes_duration_us;
1413 
1414 	user_rate = &usr_stats->rate;
1415 	flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1416 	bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1417 	nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1418 	mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1419 	sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1420 	dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1421 
1422 	/* Note: If host configured fixed rates and in some other special
1423 	 * cases, the broadcast/management frames are sent in different rates.
1424 	 * Firmware rate's control to be skipped for this?
1425 	 */
1426 
1427 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1428 		ath11k_warn(ab, "Invalid HE mcs %d peer stats",  mcs);
1429 		return;
1430 	}
1431 
1432 	if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1433 		ath11k_warn(ab, "Invalid VHT mcs %d peer stats",  mcs);
1434 		return;
1435 	}
1436 
1437 	if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1438 		ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1439 			    mcs, nss);
1440 		return;
1441 	}
1442 
1443 	if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1444 		ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1445 							    flags,
1446 							    &rate_idx,
1447 							    &rate);
1448 		if (ret < 0)
1449 			return;
1450 	}
1451 
1452 	rcu_read_lock();
1453 	spin_lock_bh(&ab->base_lock);
1454 	peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1455 
1456 	if (!peer || !peer->sta) {
1457 		spin_unlock_bh(&ab->base_lock);
1458 		rcu_read_unlock();
1459 		return;
1460 	}
1461 
1462 	sta = peer->sta;
1463 	arsta = (struct ath11k_sta *)sta->drv_priv;
1464 
1465 	memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1466 
1467 	switch (flags) {
1468 	case WMI_RATE_PREAMBLE_OFDM:
1469 		arsta->txrate.legacy = rate;
1470 		break;
1471 	case WMI_RATE_PREAMBLE_CCK:
1472 		arsta->txrate.legacy = rate;
1473 		break;
1474 	case WMI_RATE_PREAMBLE_HT:
1475 		arsta->txrate.mcs = mcs + 8 * (nss - 1);
1476 		arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1477 		if (sgi)
1478 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1479 		break;
1480 	case WMI_RATE_PREAMBLE_VHT:
1481 		arsta->txrate.mcs = mcs;
1482 		arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1483 		if (sgi)
1484 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1485 		break;
1486 	case WMI_RATE_PREAMBLE_HE:
1487 		arsta->txrate.mcs = mcs;
1488 		arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1489 		arsta->txrate.he_dcm = dcm;
1490 		arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1491 		arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1492 						((user_rate->ru_end -
1493 						 user_rate->ru_start) + 1);
1494 		break;
1495 	}
1496 
1497 	arsta->txrate.nss = nss;
1498 
1499 	arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1500 	arsta->tx_duration += tx_duration;
1501 	memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1502 
1503 	/* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1504 	 * So skip peer stats update for mgmt packets.
1505 	 */
1506 	if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1507 		memset(peer_stats, 0, sizeof(*peer_stats));
1508 		peer_stats->succ_pkts = succ_pkts;
1509 		peer_stats->succ_bytes = succ_bytes;
1510 		peer_stats->is_ampdu = is_ampdu;
1511 		peer_stats->duration = tx_duration;
1512 		peer_stats->ba_fails =
1513 			HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1514 			HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1515 
1516 		if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1517 			ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1518 	}
1519 
1520 	spin_unlock_bh(&ab->base_lock);
1521 	rcu_read_unlock();
1522 }
1523 
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1524 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1525 					 struct htt_ppdu_stats *ppdu_stats)
1526 {
1527 	u8 user;
1528 
1529 	for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1530 		ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1531 }
1532 
1533 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1534 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1535 							u32 ppdu_id)
1536 {
1537 	struct htt_ppdu_stats_info *ppdu_info;
1538 
1539 	lockdep_assert_held(&ar->data_lock);
1540 
1541 	if (!list_empty(&ar->ppdu_stats_info)) {
1542 		list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1543 			if (ppdu_info->ppdu_id == ppdu_id)
1544 				return ppdu_info;
1545 		}
1546 
1547 		if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1548 			ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1549 						     typeof(*ppdu_info), list);
1550 			list_del(&ppdu_info->list);
1551 			ar->ppdu_stat_list_depth--;
1552 			ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1553 			kfree(ppdu_info);
1554 		}
1555 	}
1556 
1557 	ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1558 	if (!ppdu_info)
1559 		return NULL;
1560 
1561 	list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1562 	ar->ppdu_stat_list_depth++;
1563 
1564 	return ppdu_info;
1565 }
1566 
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1567 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1568 				      struct sk_buff *skb)
1569 {
1570 	struct ath11k_htt_ppdu_stats_msg *msg;
1571 	struct htt_ppdu_stats_info *ppdu_info;
1572 	struct ath11k *ar;
1573 	int ret;
1574 	u8 pdev_id;
1575 	u32 ppdu_id, len;
1576 
1577 	msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1578 	len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1579 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1580 	ppdu_id = msg->ppdu_id;
1581 
1582 	rcu_read_lock();
1583 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1584 	if (!ar) {
1585 		ret = -EINVAL;
1586 		goto out;
1587 	}
1588 
1589 	if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1590 		trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1591 
1592 	spin_lock_bh(&ar->data_lock);
1593 	ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1594 	if (!ppdu_info) {
1595 		ret = -EINVAL;
1596 		goto out_unlock_data;
1597 	}
1598 
1599 	ppdu_info->ppdu_id = ppdu_id;
1600 	ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1601 				     ath11k_htt_tlv_ppdu_stats_parse,
1602 				     (void *)ppdu_info);
1603 	if (ret) {
1604 		ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1605 		goto out_unlock_data;
1606 	}
1607 
1608 out_unlock_data:
1609 	spin_unlock_bh(&ar->data_lock);
1610 
1611 out:
1612 	rcu_read_unlock();
1613 
1614 	return ret;
1615 }
1616 
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1617 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1618 {
1619 	struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1620 	struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1621 	struct ath11k *ar;
1622 	u8 pdev_id;
1623 
1624 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1625 
1626 	rcu_read_lock();
1627 
1628 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1629 	if (!ar) {
1630 		ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1631 		goto out;
1632 	}
1633 
1634 	trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1635 				ar->ab->pktlog_defs_checksum);
1636 
1637 out:
1638 	rcu_read_unlock();
1639 }
1640 
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1641 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1642 						  struct sk_buff *skb)
1643 {
1644 	u32 *data = (u32 *)skb->data;
1645 	u8 pdev_id, ring_type, ring_id, pdev_idx;
1646 	u16 hp, tp;
1647 	u32 backpressure_time;
1648 	struct ath11k_bp_stats *bp_stats;
1649 
1650 	pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1651 	ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1652 	ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1653 	++data;
1654 
1655 	hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1656 	tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1657 	++data;
1658 
1659 	backpressure_time = *data;
1660 
1661 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1662 		   pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1663 
1664 	if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1665 		if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1666 			return;
1667 
1668 		bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1669 	} else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1670 		pdev_idx = DP_HW2SW_MACID(pdev_id);
1671 
1672 		if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1673 			return;
1674 
1675 		bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1676 	} else {
1677 		ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1678 			    ring_type);
1679 		return;
1680 	}
1681 
1682 	spin_lock_bh(&ab->base_lock);
1683 	bp_stats->hp = hp;
1684 	bp_stats->tp = tp;
1685 	bp_stats->count++;
1686 	bp_stats->jiffies = jiffies;
1687 	spin_unlock_bh(&ab->base_lock);
1688 }
1689 
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1690 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1691 				       struct sk_buff *skb)
1692 {
1693 	struct ath11k_dp *dp = &ab->dp;
1694 	struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1695 	enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1696 	u16 peer_id;
1697 	u8 vdev_id;
1698 	u8 mac_addr[ETH_ALEN];
1699 	u16 peer_mac_h16;
1700 	u16 ast_hash;
1701 	u16 hw_peer_id;
1702 
1703 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1704 
1705 	switch (type) {
1706 	case HTT_T2H_MSG_TYPE_VERSION_CONF:
1707 		dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1708 						  resp->version_msg.version);
1709 		dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1710 						  resp->version_msg.version);
1711 		complete(&dp->htt_tgt_version_received);
1712 		break;
1713 	case HTT_T2H_MSG_TYPE_PEER_MAP:
1714 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1715 				    resp->peer_map_ev.info);
1716 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1717 				    resp->peer_map_ev.info);
1718 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1719 					 resp->peer_map_ev.info1);
1720 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1721 				       peer_mac_h16, mac_addr);
1722 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1723 		break;
1724 	case HTT_T2H_MSG_TYPE_PEER_MAP2:
1725 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1726 				    resp->peer_map_ev.info);
1727 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1728 				    resp->peer_map_ev.info);
1729 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1730 					 resp->peer_map_ev.info1);
1731 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1732 				       peer_mac_h16, mac_addr);
1733 		ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1734 				     resp->peer_map_ev.info2);
1735 		hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1736 				       resp->peer_map_ev.info1);
1737 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1738 				      hw_peer_id);
1739 		break;
1740 	case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1741 	case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1742 		peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1743 				    resp->peer_unmap_ev.info);
1744 		ath11k_peer_unmap_event(ab, peer_id);
1745 		break;
1746 	case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1747 		ath11k_htt_pull_ppdu_stats(ab, skb);
1748 		break;
1749 	case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1750 		ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1751 		break;
1752 	case HTT_T2H_MSG_TYPE_PKTLOG:
1753 		ath11k_htt_pktlog(ab, skb);
1754 		break;
1755 	case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1756 		ath11k_htt_backpressure_event_handler(ab, skb);
1757 		break;
1758 	default:
1759 		ath11k_warn(ab, "htt event %d not handled\n", type);
1760 		break;
1761 	}
1762 
1763 	dev_kfree_skb_any(skb);
1764 }
1765 
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1766 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1767 				      struct sk_buff_head *msdu_list,
1768 				      struct sk_buff *first, struct sk_buff *last,
1769 				      u8 l3pad_bytes, int msdu_len)
1770 {
1771 	struct ath11k_base *ab = ar->ab;
1772 	struct sk_buff *skb;
1773 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1774 	int buf_first_hdr_len, buf_first_len;
1775 	struct hal_rx_desc *ldesc;
1776 	int space_extra, rem_len, buf_len;
1777 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1778 
1779 	/* As the msdu is spread across multiple rx buffers,
1780 	 * find the offset to the start of msdu for computing
1781 	 * the length of the msdu in the first buffer.
1782 	 */
1783 	buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1784 	buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1785 
1786 	if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1787 		skb_put(first, buf_first_hdr_len + msdu_len);
1788 		skb_pull(first, buf_first_hdr_len);
1789 		return 0;
1790 	}
1791 
1792 	ldesc = (struct hal_rx_desc *)last->data;
1793 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1794 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1795 
1796 	/* MSDU spans over multiple buffers because the length of the MSDU
1797 	 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1798 	 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1799 	 */
1800 	skb_put(first, DP_RX_BUFFER_SIZE);
1801 	skb_pull(first, buf_first_hdr_len);
1802 
1803 	/* When an MSDU spread over multiple buffers attention, MSDU_END and
1804 	 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1805 	 */
1806 	ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1807 
1808 	space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1809 	if (space_extra > 0 &&
1810 	    (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1811 		/* Free up all buffers of the MSDU */
1812 		while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1813 			rxcb = ATH11K_SKB_RXCB(skb);
1814 			if (!rxcb->is_continuation) {
1815 				dev_kfree_skb_any(skb);
1816 				break;
1817 			}
1818 			dev_kfree_skb_any(skb);
1819 		}
1820 		return -ENOMEM;
1821 	}
1822 
1823 	rem_len = msdu_len - buf_first_len;
1824 	while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1825 		rxcb = ATH11K_SKB_RXCB(skb);
1826 		if (rxcb->is_continuation)
1827 			buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1828 		else
1829 			buf_len = rem_len;
1830 
1831 		if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1832 			WARN_ON_ONCE(1);
1833 			dev_kfree_skb_any(skb);
1834 			return -EINVAL;
1835 		}
1836 
1837 		skb_put(skb, buf_len + hal_rx_desc_sz);
1838 		skb_pull(skb, hal_rx_desc_sz);
1839 		skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1840 					  buf_len);
1841 		dev_kfree_skb_any(skb);
1842 
1843 		rem_len -= buf_len;
1844 		if (!rxcb->is_continuation)
1845 			break;
1846 	}
1847 
1848 	return 0;
1849 }
1850 
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1851 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1852 						      struct sk_buff *first)
1853 {
1854 	struct sk_buff *skb;
1855 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1856 
1857 	if (!rxcb->is_continuation)
1858 		return first;
1859 
1860 	skb_queue_walk(msdu_list, skb) {
1861 		rxcb = ATH11K_SKB_RXCB(skb);
1862 		if (!rxcb->is_continuation)
1863 			return skb;
1864 	}
1865 
1866 	return NULL;
1867 }
1868 
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1869 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1870 {
1871 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1872 	struct rx_attention *rx_attention;
1873 	bool ip_csum_fail, l4_csum_fail;
1874 
1875 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1876 	ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1877 	l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1878 
1879 	msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1880 			  CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1881 }
1882 
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1883 int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
1884 {
1885 	switch (enctype) {
1886 	case HAL_ENCRYPT_TYPE_OPEN:
1887 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1888 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1889 		return 0;
1890 	case HAL_ENCRYPT_TYPE_CCMP_128:
1891 		return IEEE80211_CCMP_MIC_LEN;
1892 	case HAL_ENCRYPT_TYPE_CCMP_256:
1893 		return IEEE80211_CCMP_256_MIC_LEN;
1894 	case HAL_ENCRYPT_TYPE_GCMP_128:
1895 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1896 		return IEEE80211_GCMP_MIC_LEN;
1897 	case HAL_ENCRYPT_TYPE_WEP_40:
1898 	case HAL_ENCRYPT_TYPE_WEP_104:
1899 	case HAL_ENCRYPT_TYPE_WEP_128:
1900 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1901 	case HAL_ENCRYPT_TYPE_WAPI:
1902 		break;
1903 	}
1904 
1905 	ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1906 	return 0;
1907 }
1908 
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1909 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1910 					 enum hal_encrypt_type enctype)
1911 {
1912 	switch (enctype) {
1913 	case HAL_ENCRYPT_TYPE_OPEN:
1914 		return 0;
1915 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1916 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1917 		return IEEE80211_TKIP_IV_LEN;
1918 	case HAL_ENCRYPT_TYPE_CCMP_128:
1919 		return IEEE80211_CCMP_HDR_LEN;
1920 	case HAL_ENCRYPT_TYPE_CCMP_256:
1921 		return IEEE80211_CCMP_256_HDR_LEN;
1922 	case HAL_ENCRYPT_TYPE_GCMP_128:
1923 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1924 		return IEEE80211_GCMP_HDR_LEN;
1925 	case HAL_ENCRYPT_TYPE_WEP_40:
1926 	case HAL_ENCRYPT_TYPE_WEP_104:
1927 	case HAL_ENCRYPT_TYPE_WEP_128:
1928 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1929 	case HAL_ENCRYPT_TYPE_WAPI:
1930 		break;
1931 	}
1932 
1933 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1934 	return 0;
1935 }
1936 
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1937 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1938 				       enum hal_encrypt_type enctype)
1939 {
1940 	switch (enctype) {
1941 	case HAL_ENCRYPT_TYPE_OPEN:
1942 	case HAL_ENCRYPT_TYPE_CCMP_128:
1943 	case HAL_ENCRYPT_TYPE_CCMP_256:
1944 	case HAL_ENCRYPT_TYPE_GCMP_128:
1945 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1946 		return 0;
1947 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1948 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1949 		return IEEE80211_TKIP_ICV_LEN;
1950 	case HAL_ENCRYPT_TYPE_WEP_40:
1951 	case HAL_ENCRYPT_TYPE_WEP_104:
1952 	case HAL_ENCRYPT_TYPE_WEP_128:
1953 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1954 	case HAL_ENCRYPT_TYPE_WAPI:
1955 		break;
1956 	}
1957 
1958 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1959 	return 0;
1960 }
1961 
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1962 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1963 					 struct sk_buff *msdu,
1964 					 u8 *first_hdr,
1965 					 enum hal_encrypt_type enctype,
1966 					 struct ieee80211_rx_status *status)
1967 {
1968 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1969 	u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1970 	struct ieee80211_hdr *hdr;
1971 	size_t hdr_len;
1972 	u8 da[ETH_ALEN];
1973 	u8 sa[ETH_ALEN];
1974 	u16 qos_ctl = 0;
1975 	u8 *qos;
1976 
1977 	/* copy SA & DA and pull decapped header */
1978 	hdr = (struct ieee80211_hdr *)msdu->data;
1979 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
1980 	ether_addr_copy(da, ieee80211_get_DA(hdr));
1981 	ether_addr_copy(sa, ieee80211_get_SA(hdr));
1982 	skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1983 
1984 	if (rxcb->is_first_msdu) {
1985 		/* original 802.11 header is valid for the first msdu
1986 		 * hence we can reuse the same header
1987 		 */
1988 		hdr = (struct ieee80211_hdr *)first_hdr;
1989 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
1990 
1991 		/* Each A-MSDU subframe will be reported as a separate MSDU,
1992 		 * so strip the A-MSDU bit from QoS Ctl.
1993 		 */
1994 		if (ieee80211_is_data_qos(hdr->frame_control)) {
1995 			qos = ieee80211_get_qos_ctl(hdr);
1996 			qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1997 		}
1998 	} else {
1999 		/*  Rebuild qos header if this is a middle/last msdu */
2000 		hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
2001 
2002 		/* Reset the order bit as the HT_Control header is stripped */
2003 		hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
2004 
2005 		qos_ctl = rxcb->tid;
2006 
2007 		if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
2008 			qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2009 
2010 		/* TODO Add other QoS ctl fields when required */
2011 
2012 		/* copy decap header before overwriting for reuse below */
2013 		memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2014 	}
2015 
2016 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2017 		memcpy(skb_push(msdu,
2018 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2019 		       (void *)hdr + hdr_len,
2020 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2021 	}
2022 
2023 	if (!rxcb->is_first_msdu) {
2024 		memcpy(skb_push(msdu,
2025 				IEEE80211_QOS_CTL_LEN), &qos_ctl,
2026 				IEEE80211_QOS_CTL_LEN);
2027 		memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2028 		return;
2029 	}
2030 
2031 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2032 
2033 	/* original 802.11 header has a different DA and in
2034 	 * case of 4addr it may also have different SA
2035 	 */
2036 	hdr = (struct ieee80211_hdr *)msdu->data;
2037 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2038 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2039 }
2040 
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2041 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2042 				       enum hal_encrypt_type enctype,
2043 				       struct ieee80211_rx_status *status,
2044 				       bool decrypted)
2045 {
2046 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2047 	struct ieee80211_hdr *hdr;
2048 	size_t hdr_len;
2049 	size_t crypto_len;
2050 
2051 	if (!rxcb->is_first_msdu ||
2052 	    !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2053 		WARN_ON_ONCE(1);
2054 		return;
2055 	}
2056 
2057 	skb_trim(msdu, msdu->len - FCS_LEN);
2058 
2059 	if (!decrypted)
2060 		return;
2061 
2062 	hdr = (void *)msdu->data;
2063 
2064 	/* Tail */
2065 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2066 		skb_trim(msdu, msdu->len -
2067 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2068 
2069 		skb_trim(msdu, msdu->len -
2070 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2071 	} else {
2072 		/* MIC */
2073 		if (status->flag & RX_FLAG_MIC_STRIPPED)
2074 			skb_trim(msdu, msdu->len -
2075 				 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2076 
2077 		/* ICV */
2078 		if (status->flag & RX_FLAG_ICV_STRIPPED)
2079 			skb_trim(msdu, msdu->len -
2080 				 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2081 	}
2082 
2083 	/* MMIC */
2084 	if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2085 	    !ieee80211_has_morefrags(hdr->frame_control) &&
2086 	    enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2087 		skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2088 
2089 	/* Head */
2090 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2091 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2092 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2093 
2094 		memmove((void *)msdu->data + crypto_len,
2095 			(void *)msdu->data, hdr_len);
2096 		skb_pull(msdu, crypto_len);
2097 	}
2098 }
2099 
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2100 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2101 					 struct sk_buff *msdu,
2102 					 enum hal_encrypt_type enctype)
2103 {
2104 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2105 	struct ieee80211_hdr *hdr;
2106 	size_t hdr_len, crypto_len;
2107 	void *rfc1042;
2108 	bool is_amsdu;
2109 
2110 	is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2111 	hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2112 	rfc1042 = hdr;
2113 
2114 	if (rxcb->is_first_msdu) {
2115 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2116 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2117 
2118 		rfc1042 += hdr_len + crypto_len;
2119 	}
2120 
2121 	if (is_amsdu)
2122 		rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2123 
2124 	return rfc1042;
2125 }
2126 
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2127 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2128 				       struct sk_buff *msdu,
2129 				       u8 *first_hdr,
2130 				       enum hal_encrypt_type enctype,
2131 				       struct ieee80211_rx_status *status)
2132 {
2133 	struct ieee80211_hdr *hdr;
2134 	struct ethhdr *eth;
2135 	size_t hdr_len;
2136 	u8 da[ETH_ALEN];
2137 	u8 sa[ETH_ALEN];
2138 	void *rfc1042;
2139 
2140 	rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2141 	if (WARN_ON_ONCE(!rfc1042))
2142 		return;
2143 
2144 	/* pull decapped header and copy SA & DA */
2145 	eth = (struct ethhdr *)msdu->data;
2146 	ether_addr_copy(da, eth->h_dest);
2147 	ether_addr_copy(sa, eth->h_source);
2148 	skb_pull(msdu, sizeof(struct ethhdr));
2149 
2150 	/* push rfc1042/llc/snap */
2151 	memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2152 	       sizeof(struct ath11k_dp_rfc1042_hdr));
2153 
2154 	/* push original 802.11 header */
2155 	hdr = (struct ieee80211_hdr *)first_hdr;
2156 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2157 
2158 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2159 		memcpy(skb_push(msdu,
2160 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2161 		       (void *)hdr + hdr_len,
2162 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2163 	}
2164 
2165 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2166 
2167 	/* original 802.11 header has a different DA and in
2168 	 * case of 4addr it may also have different SA
2169 	 */
2170 	hdr = (struct ieee80211_hdr *)msdu->data;
2171 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2172 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2173 }
2174 
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2175 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2176 				   struct hal_rx_desc *rx_desc,
2177 				   enum hal_encrypt_type enctype,
2178 				   struct ieee80211_rx_status *status,
2179 				   bool decrypted)
2180 {
2181 	u8 *first_hdr;
2182 	u8 decap;
2183 	struct ethhdr *ehdr;
2184 
2185 	first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2186 	decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2187 
2188 	switch (decap) {
2189 	case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2190 		ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2191 					     enctype, status);
2192 		break;
2193 	case DP_RX_DECAP_TYPE_RAW:
2194 		ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2195 					   decrypted);
2196 		break;
2197 	case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2198 		ehdr = (struct ethhdr *)msdu->data;
2199 
2200 		/* mac80211 allows fast path only for authorized STA */
2201 		if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2202 			ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2203 			ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2204 						   enctype, status);
2205 			break;
2206 		}
2207 
2208 		/* PN for mcast packets will be validated in mac80211;
2209 		 * remove eth header and add 802.11 header.
2210 		 */
2211 		if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2212 			ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2213 						   enctype, status);
2214 		break;
2215 	case DP_RX_DECAP_TYPE_8023:
2216 		/* TODO: Handle undecap for these formats */
2217 		break;
2218 	}
2219 }
2220 
2221 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2222 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2223 {
2224 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2225 	struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2226 	struct ath11k_peer *peer = NULL;
2227 
2228 	lockdep_assert_held(&ab->base_lock);
2229 
2230 	if (rxcb->peer_id)
2231 		peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2232 
2233 	if (peer)
2234 		return peer;
2235 
2236 	if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2237 		return NULL;
2238 
2239 	peer = ath11k_peer_find_by_addr(ab,
2240 					ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2241 	return peer;
2242 }
2243 
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2244 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2245 				struct sk_buff *msdu,
2246 				struct hal_rx_desc *rx_desc,
2247 				struct ieee80211_rx_status *rx_status)
2248 {
2249 	bool  fill_crypto_hdr;
2250 	enum hal_encrypt_type enctype;
2251 	bool is_decrypted = false;
2252 	struct ath11k_skb_rxcb *rxcb;
2253 	struct ieee80211_hdr *hdr;
2254 	struct ath11k_peer *peer;
2255 	struct rx_attention *rx_attention;
2256 	u32 err_bitmap;
2257 
2258 	/* PN for multicast packets will be checked in mac80211 */
2259 	rxcb = ATH11K_SKB_RXCB(msdu);
2260 	fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2261 	rxcb->is_mcbc = fill_crypto_hdr;
2262 
2263 	if (rxcb->is_mcbc) {
2264 		rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2265 		rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2266 	}
2267 
2268 	spin_lock_bh(&ar->ab->base_lock);
2269 	peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2270 	if (peer) {
2271 		if (rxcb->is_mcbc)
2272 			enctype = peer->sec_type_grp;
2273 		else
2274 			enctype = peer->sec_type;
2275 	} else {
2276 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2277 	}
2278 	spin_unlock_bh(&ar->ab->base_lock);
2279 
2280 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2281 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2282 	if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2283 		is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2284 
2285 	/* Clear per-MPDU flags while leaving per-PPDU flags intact */
2286 	rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2287 			     RX_FLAG_MMIC_ERROR |
2288 			     RX_FLAG_DECRYPTED |
2289 			     RX_FLAG_IV_STRIPPED |
2290 			     RX_FLAG_MMIC_STRIPPED);
2291 
2292 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2293 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2294 	if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2295 		rx_status->flag |= RX_FLAG_MMIC_ERROR;
2296 
2297 	if (is_decrypted) {
2298 		rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2299 
2300 		if (fill_crypto_hdr)
2301 			rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2302 					RX_FLAG_ICV_STRIPPED;
2303 		else
2304 			rx_status->flag |= RX_FLAG_IV_STRIPPED |
2305 					   RX_FLAG_PN_VALIDATED;
2306 	}
2307 
2308 	ath11k_dp_rx_h_csum_offload(ar, msdu);
2309 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2310 			       enctype, rx_status, is_decrypted);
2311 
2312 	if (!is_decrypted || fill_crypto_hdr)
2313 		return;
2314 
2315 	if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2316 	    DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2317 		hdr = (void *)msdu->data;
2318 		hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2319 	}
2320 }
2321 
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2322 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2323 				struct ieee80211_rx_status *rx_status)
2324 {
2325 	struct ieee80211_supported_band *sband;
2326 	enum rx_msdu_start_pkt_type pkt_type;
2327 	u8 bw;
2328 	u8 rate_mcs, nss;
2329 	u8 sgi;
2330 	bool is_cck, is_ldpc;
2331 
2332 	pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2333 	bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2334 	rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2335 	nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2336 	sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2337 
2338 	switch (pkt_type) {
2339 	case RX_MSDU_START_PKT_TYPE_11A:
2340 	case RX_MSDU_START_PKT_TYPE_11B:
2341 		is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2342 		sband = &ar->mac.sbands[rx_status->band];
2343 		rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2344 								is_cck);
2345 		break;
2346 	case RX_MSDU_START_PKT_TYPE_11N:
2347 		rx_status->encoding = RX_ENC_HT;
2348 		if (rate_mcs > ATH11K_HT_MCS_MAX) {
2349 			ath11k_warn(ar->ab,
2350 				    "Received with invalid mcs in HT mode %d\n",
2351 				     rate_mcs);
2352 			break;
2353 		}
2354 		rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2355 		if (sgi)
2356 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2357 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2358 		break;
2359 	case RX_MSDU_START_PKT_TYPE_11AC:
2360 		rx_status->encoding = RX_ENC_VHT;
2361 		rx_status->rate_idx = rate_mcs;
2362 		if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2363 			ath11k_warn(ar->ab,
2364 				    "Received with invalid mcs in VHT mode %d\n",
2365 				     rate_mcs);
2366 			break;
2367 		}
2368 		rx_status->nss = nss;
2369 		if (sgi)
2370 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2371 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2372 		is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2373 		if (is_ldpc)
2374 			rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2375 		break;
2376 	case RX_MSDU_START_PKT_TYPE_11AX:
2377 		rx_status->rate_idx = rate_mcs;
2378 		if (rate_mcs > ATH11K_HE_MCS_MAX) {
2379 			ath11k_warn(ar->ab,
2380 				    "Received with invalid mcs in HE mode %d\n",
2381 				    rate_mcs);
2382 			break;
2383 		}
2384 		rx_status->encoding = RX_ENC_HE;
2385 		rx_status->nss = nss;
2386 		rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2387 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2388 		break;
2389 	}
2390 }
2391 
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2392 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2393 				struct ieee80211_rx_status *rx_status)
2394 {
2395 	u8 channel_num;
2396 	u32 center_freq, meta_data;
2397 	struct ieee80211_channel *channel;
2398 
2399 	rx_status->freq = 0;
2400 	rx_status->rate_idx = 0;
2401 	rx_status->nss = 0;
2402 	rx_status->encoding = RX_ENC_LEGACY;
2403 	rx_status->bw = RATE_INFO_BW_20;
2404 
2405 	rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2406 
2407 	meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2408 	channel_num = meta_data;
2409 	center_freq = meta_data >> 16;
2410 
2411 	if (center_freq >= ATH11K_MIN_6G_FREQ &&
2412 	    center_freq <= ATH11K_MAX_6G_FREQ) {
2413 		rx_status->band = NL80211_BAND_6GHZ;
2414 		rx_status->freq = center_freq;
2415 	} else if (channel_num >= 1 && channel_num <= 14) {
2416 		rx_status->band = NL80211_BAND_2GHZ;
2417 	} else if (channel_num >= 36 && channel_num <= 177) {
2418 		rx_status->band = NL80211_BAND_5GHZ;
2419 	} else {
2420 		spin_lock_bh(&ar->data_lock);
2421 		channel = ar->rx_channel;
2422 		if (channel) {
2423 			rx_status->band = channel->band;
2424 			channel_num =
2425 				ieee80211_frequency_to_channel(channel->center_freq);
2426 		}
2427 		spin_unlock_bh(&ar->data_lock);
2428 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2429 				rx_desc, sizeof(struct hal_rx_desc));
2430 	}
2431 
2432 	if (rx_status->band != NL80211_BAND_6GHZ)
2433 		rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2434 								 rx_status->band);
2435 
2436 	ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2437 }
2438 
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2439 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2440 				      struct sk_buff *msdu,
2441 				      struct ieee80211_rx_status *status)
2442 {
2443 	static const struct ieee80211_radiotap_he known = {
2444 		.data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2445 				     IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2446 		.data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2447 	};
2448 	struct ieee80211_rx_status *rx_status;
2449 	struct ieee80211_radiotap_he *he = NULL;
2450 	struct ieee80211_sta *pubsta = NULL;
2451 	struct ath11k_peer *peer;
2452 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2453 	u8 decap = DP_RX_DECAP_TYPE_RAW;
2454 	bool is_mcbc = rxcb->is_mcbc;
2455 	bool is_eapol = rxcb->is_eapol;
2456 
2457 	if (status->encoding == RX_ENC_HE &&
2458 	    !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2459 	    !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2460 		he = skb_push(msdu, sizeof(known));
2461 		memcpy(he, &known, sizeof(known));
2462 		status->flag |= RX_FLAG_RADIOTAP_HE;
2463 	}
2464 
2465 	if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2466 		decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2467 
2468 	spin_lock_bh(&ar->ab->base_lock);
2469 	peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2470 	if (peer && peer->sta)
2471 		pubsta = peer->sta;
2472 	spin_unlock_bh(&ar->ab->base_lock);
2473 
2474 	ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2475 		   "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2476 		   msdu,
2477 		   msdu->len,
2478 		   peer ? peer->addr : NULL,
2479 		   rxcb->tid,
2480 		   is_mcbc ? "mcast" : "ucast",
2481 		   rxcb->seq_no,
2482 		   (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2483 		   (status->encoding == RX_ENC_HT) ? "ht" : "",
2484 		   (status->encoding == RX_ENC_VHT) ? "vht" : "",
2485 		   (status->encoding == RX_ENC_HE) ? "he" : "",
2486 		   (status->bw == RATE_INFO_BW_40) ? "40" : "",
2487 		   (status->bw == RATE_INFO_BW_80) ? "80" : "",
2488 		   (status->bw == RATE_INFO_BW_160) ? "160" : "",
2489 		   status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2490 		   status->rate_idx,
2491 		   status->nss,
2492 		   status->freq,
2493 		   status->band, status->flag,
2494 		   !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2495 		   !!(status->flag & RX_FLAG_MMIC_ERROR),
2496 		   !!(status->flag & RX_FLAG_AMSDU_MORE));
2497 
2498 	ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2499 			msdu->data, msdu->len);
2500 
2501 	rx_status = IEEE80211_SKB_RXCB(msdu);
2502 	*rx_status = *status;
2503 
2504 	/* TODO: trace rx packet */
2505 
2506 	/* PN for multicast packets are not validate in HW,
2507 	 * so skip 802.3 rx path
2508 	 * Also, fast_rx expects the STA to be authorized, hence
2509 	 * eapol packets are sent in slow path.
2510 	 */
2511 	if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2512 	    !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2513 		rx_status->flag |= RX_FLAG_8023;
2514 
2515 	ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2516 }
2517 
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2518 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2519 				     struct sk_buff *msdu,
2520 				     struct sk_buff_head *msdu_list,
2521 				     struct ieee80211_rx_status *rx_status)
2522 {
2523 	struct ath11k_base *ab = ar->ab;
2524 	struct hal_rx_desc *rx_desc, *lrx_desc;
2525 	struct rx_attention *rx_attention;
2526 	struct ath11k_skb_rxcb *rxcb;
2527 	struct sk_buff *last_buf;
2528 	u8 l3_pad_bytes;
2529 	u8 *hdr_status;
2530 	u16 msdu_len;
2531 	int ret;
2532 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2533 
2534 	last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2535 	if (!last_buf) {
2536 		ath11k_warn(ab,
2537 			    "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2538 		ret = -EIO;
2539 		goto free_out;
2540 	}
2541 
2542 	rx_desc = (struct hal_rx_desc *)msdu->data;
2543 	if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2544 		ath11k_warn(ar->ab, "msdu len not valid\n");
2545 		ret = -EIO;
2546 		goto free_out;
2547 	}
2548 
2549 	lrx_desc = (struct hal_rx_desc *)last_buf->data;
2550 	rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2551 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2552 		ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2553 		ret = -EIO;
2554 		goto free_out;
2555 	}
2556 
2557 	rxcb = ATH11K_SKB_RXCB(msdu);
2558 	rxcb->rx_desc = rx_desc;
2559 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2560 	l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2561 
2562 	if (rxcb->is_frag) {
2563 		skb_pull(msdu, hal_rx_desc_sz);
2564 	} else if (!rxcb->is_continuation) {
2565 		if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2566 			hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2567 			ret = -EINVAL;
2568 			ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2569 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2570 					sizeof(struct ieee80211_hdr));
2571 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2572 					sizeof(struct hal_rx_desc));
2573 			goto free_out;
2574 		}
2575 		skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2576 		skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2577 	} else {
2578 		ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2579 						 msdu, last_buf,
2580 						 l3_pad_bytes, msdu_len);
2581 		if (ret) {
2582 			ath11k_warn(ab,
2583 				    "failed to coalesce msdu rx buffer%d\n", ret);
2584 			goto free_out;
2585 		}
2586 	}
2587 
2588 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2589 	ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2590 
2591 	rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2592 
2593 	return 0;
2594 
2595 free_out:
2596 	return ret;
2597 }
2598 
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2599 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2600 						  struct napi_struct *napi,
2601 						  struct sk_buff_head *msdu_list,
2602 						  int mac_id)
2603 {
2604 	struct sk_buff *msdu;
2605 	struct ath11k *ar;
2606 	struct ieee80211_rx_status rx_status = {0};
2607 	int ret;
2608 
2609 	if (skb_queue_empty(msdu_list))
2610 		return;
2611 
2612 	if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2613 		__skb_queue_purge(msdu_list);
2614 		return;
2615 	}
2616 
2617 	ar = ab->pdevs[mac_id].ar;
2618 	if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2619 		__skb_queue_purge(msdu_list);
2620 		return;
2621 	}
2622 
2623 	while ((msdu = __skb_dequeue(msdu_list))) {
2624 		ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2625 		if (unlikely(ret)) {
2626 			ath11k_dbg(ab, ATH11K_DBG_DATA,
2627 				   "Unable to process msdu %d", ret);
2628 			dev_kfree_skb_any(msdu);
2629 			continue;
2630 		}
2631 
2632 		ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2633 	}
2634 }
2635 
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2636 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2637 			 struct napi_struct *napi, int budget)
2638 {
2639 	struct ath11k_dp *dp = &ab->dp;
2640 	struct dp_rxdma_ring *rx_ring;
2641 	int num_buffs_reaped[MAX_RADIOS] = {0};
2642 	struct sk_buff_head msdu_list[MAX_RADIOS];
2643 	struct ath11k_skb_rxcb *rxcb;
2644 	int total_msdu_reaped = 0;
2645 	struct hal_srng *srng;
2646 	struct sk_buff *msdu;
2647 	bool done = false;
2648 	int buf_id, mac_id;
2649 	struct ath11k *ar;
2650 	struct hal_reo_dest_ring *desc;
2651 	enum hal_reo_dest_ring_push_reason push_reason;
2652 	u32 cookie, info0, rx_msdu_info0, rx_mpdu_info0;
2653 	int i;
2654 
2655 	for (i = 0; i < MAX_RADIOS; i++)
2656 		__skb_queue_head_init(&msdu_list[i]);
2657 
2658 	srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2659 
2660 	spin_lock_bh(&srng->lock);
2661 
2662 try_again:
2663 	ath11k_hal_srng_access_begin(ab, srng);
2664 
2665 	/* Make sure descriptor is read after the head pointer. */
2666 	dma_rmb();
2667 
2668 	while (likely(desc =
2669 	      (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2670 									     srng))) {
2671 		cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2672 				   READ_ONCE(desc->buf_addr_info.info1));
2673 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2674 				   cookie);
2675 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2676 
2677 		if (unlikely(buf_id == 0))
2678 			continue;
2679 
2680 		ar = ab->pdevs[mac_id].ar;
2681 		rx_ring = &ar->dp.rx_refill_buf_ring;
2682 		spin_lock_bh(&rx_ring->idr_lock);
2683 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2684 		if (unlikely(!msdu)) {
2685 			ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2686 				    buf_id);
2687 			spin_unlock_bh(&rx_ring->idr_lock);
2688 			continue;
2689 		}
2690 
2691 		idr_remove(&rx_ring->bufs_idr, buf_id);
2692 		spin_unlock_bh(&rx_ring->idr_lock);
2693 
2694 		rxcb = ATH11K_SKB_RXCB(msdu);
2695 		dma_unmap_single(ab->dev, rxcb->paddr,
2696 				 msdu->len + skb_tailroom(msdu),
2697 				 DMA_FROM_DEVICE);
2698 
2699 		num_buffs_reaped[mac_id]++;
2700 
2701 		info0 = READ_ONCE(desc->info0);
2702 		push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2703 					info0);
2704 		if (unlikely(push_reason !=
2705 			     HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2706 			dev_kfree_skb_any(msdu);
2707 			ab->soc_stats.hal_reo_error[ring_id]++;
2708 			continue;
2709 		}
2710 
2711 		rx_msdu_info0 = READ_ONCE(desc->rx_msdu_info.info0);
2712 		rx_mpdu_info0 = READ_ONCE(desc->rx_mpdu_info.info0);
2713 
2714 		rxcb->is_first_msdu = !!(rx_msdu_info0 &
2715 					 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2716 		rxcb->is_last_msdu = !!(rx_msdu_info0 &
2717 					RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2718 		rxcb->is_continuation = !!(rx_msdu_info0 &
2719 					   RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2720 		rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2721 					  READ_ONCE(desc->rx_mpdu_info.meta_data));
2722 		rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2723 					 rx_mpdu_info0);
2724 		rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2725 				      info0);
2726 
2727 		rxcb->mac_id = mac_id;
2728 		__skb_queue_tail(&msdu_list[mac_id], msdu);
2729 
2730 		if (rxcb->is_continuation) {
2731 			done = false;
2732 		} else {
2733 			total_msdu_reaped++;
2734 			done = true;
2735 		}
2736 
2737 		if (total_msdu_reaped >= budget)
2738 			break;
2739 	}
2740 
2741 	/* Hw might have updated the head pointer after we cached it.
2742 	 * In this case, even though there are entries in the ring we'll
2743 	 * get rx_desc NULL. Give the read another try with updated cached
2744 	 * head pointer so that we can reap complete MPDU in the current
2745 	 * rx processing.
2746 	 */
2747 	if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2748 		ath11k_hal_srng_access_end(ab, srng);
2749 		goto try_again;
2750 	}
2751 
2752 	ath11k_hal_srng_access_end(ab, srng);
2753 
2754 	spin_unlock_bh(&srng->lock);
2755 
2756 	if (unlikely(!total_msdu_reaped))
2757 		goto exit;
2758 
2759 	for (i = 0; i < ab->num_radios; i++) {
2760 		if (!num_buffs_reaped[i])
2761 			continue;
2762 
2763 		ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2764 
2765 		ar = ab->pdevs[i].ar;
2766 		rx_ring = &ar->dp.rx_refill_buf_ring;
2767 
2768 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2769 					   ab->hw_params.hal_params->rx_buf_rbm);
2770 	}
2771 exit:
2772 	return total_msdu_reaped;
2773 }
2774 
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2775 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2776 					   struct hal_rx_mon_ppdu_info *ppdu_info)
2777 {
2778 	struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2779 	u32 num_msdu;
2780 	int i;
2781 
2782 	if (!rx_stats)
2783 		return;
2784 
2785 	arsta->rssi_comb = ppdu_info->rssi_comb;
2786 	ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2787 
2788 	num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2789 		   ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2790 
2791 	rx_stats->num_msdu += num_msdu;
2792 	rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2793 				    ppdu_info->tcp_ack_msdu_count;
2794 	rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2795 	rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2796 
2797 	if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2798 	    ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2799 		ppdu_info->nss = 1;
2800 		ppdu_info->mcs = HAL_RX_MAX_MCS;
2801 		ppdu_info->tid = IEEE80211_NUM_TIDS;
2802 	}
2803 
2804 	if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2805 		rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2806 
2807 	if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2808 		rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2809 
2810 	if (ppdu_info->gi < HAL_RX_GI_MAX)
2811 		rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2812 
2813 	if (ppdu_info->bw < HAL_RX_BW_MAX)
2814 		rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2815 
2816 	if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2817 		rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2818 
2819 	if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2820 		rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2821 
2822 	if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2823 		rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2824 
2825 	if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2826 		rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2827 
2828 	if (ppdu_info->is_stbc)
2829 		rx_stats->stbc_count += num_msdu;
2830 
2831 	if (ppdu_info->beamformed)
2832 		rx_stats->beamformed_count += num_msdu;
2833 
2834 	if (ppdu_info->num_mpdu_fcs_ok > 1)
2835 		rx_stats->ampdu_msdu_count += num_msdu;
2836 	else
2837 		rx_stats->non_ampdu_msdu_count += num_msdu;
2838 
2839 	rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2840 	rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2841 	rx_stats->dcm_count += ppdu_info->dcm;
2842 	rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2843 
2844 	arsta->rssi_comb = ppdu_info->rssi_comb;
2845 
2846 	BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2847 			     ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2848 
2849 	for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2850 		arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2851 
2852 	rx_stats->rx_duration += ppdu_info->rx_duration;
2853 	arsta->rx_duration = rx_stats->rx_duration;
2854 }
2855 
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2856 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2857 							 struct dp_rxdma_ring *rx_ring,
2858 							 int *buf_id)
2859 {
2860 	struct sk_buff *skb;
2861 	dma_addr_t paddr;
2862 
2863 	skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2864 			    DP_RX_BUFFER_ALIGN_SIZE);
2865 
2866 	if (!skb)
2867 		goto fail_alloc_skb;
2868 
2869 	if (!IS_ALIGNED((unsigned long)skb->data,
2870 			DP_RX_BUFFER_ALIGN_SIZE)) {
2871 		skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2872 			 skb->data);
2873 	}
2874 
2875 	paddr = dma_map_single(ab->dev, skb->data,
2876 			       skb->len + skb_tailroom(skb),
2877 			       DMA_FROM_DEVICE);
2878 	if (unlikely(dma_mapping_error(ab->dev, paddr)))
2879 		goto fail_free_skb;
2880 
2881 	spin_lock_bh(&rx_ring->idr_lock);
2882 	*buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2883 			    rx_ring->bufs_max, GFP_ATOMIC);
2884 	spin_unlock_bh(&rx_ring->idr_lock);
2885 	if (*buf_id < 0)
2886 		goto fail_dma_unmap;
2887 
2888 	ATH11K_SKB_RXCB(skb)->paddr = paddr;
2889 	return skb;
2890 
2891 fail_dma_unmap:
2892 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2893 			 DMA_FROM_DEVICE);
2894 fail_free_skb:
2895 	dev_kfree_skb_any(skb);
2896 fail_alloc_skb:
2897 	return NULL;
2898 }
2899 
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2900 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2901 					   struct dp_rxdma_ring *rx_ring,
2902 					   int req_entries,
2903 					   enum hal_rx_buf_return_buf_manager mgr)
2904 {
2905 	struct hal_srng *srng;
2906 	u32 *desc;
2907 	struct sk_buff *skb;
2908 	int num_free;
2909 	int num_remain;
2910 	int buf_id;
2911 	u32 cookie;
2912 	dma_addr_t paddr;
2913 
2914 	req_entries = min(req_entries, rx_ring->bufs_max);
2915 
2916 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2917 
2918 	spin_lock_bh(&srng->lock);
2919 
2920 	ath11k_hal_srng_access_begin(ab, srng);
2921 
2922 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2923 
2924 	req_entries = min(num_free, req_entries);
2925 	num_remain = req_entries;
2926 
2927 	while (num_remain > 0) {
2928 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2929 							&buf_id);
2930 		if (!skb)
2931 			break;
2932 		paddr = ATH11K_SKB_RXCB(skb)->paddr;
2933 
2934 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2935 		if (!desc)
2936 			goto fail_desc_get;
2937 
2938 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2939 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2940 
2941 		num_remain--;
2942 
2943 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2944 	}
2945 
2946 	ath11k_hal_srng_access_end(ab, srng);
2947 
2948 	spin_unlock_bh(&srng->lock);
2949 
2950 	return req_entries - num_remain;
2951 
2952 fail_desc_get:
2953 	spin_lock_bh(&rx_ring->idr_lock);
2954 	idr_remove(&rx_ring->bufs_idr, buf_id);
2955 	spin_unlock_bh(&rx_ring->idr_lock);
2956 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2957 			 DMA_FROM_DEVICE);
2958 	dev_kfree_skb_any(skb);
2959 	ath11k_hal_srng_access_end(ab, srng);
2960 	spin_unlock_bh(&srng->lock);
2961 
2962 	return req_entries - num_remain;
2963 }
2964 
2965 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2966 
2967 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2968 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2969 					 struct hal_tlv_hdr *tlv)
2970 {
2971 	struct hal_rx_ppdu_start *ppdu_start;
2972 	u16 ppdu_id_diff, ppdu_id, tlv_len;
2973 	u8 *ptr;
2974 
2975 	/* PPDU id is part of second tlv, move ptr to second tlv */
2976 	tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
2977 	ptr = (u8 *)tlv;
2978 	ptr += sizeof(*tlv) + tlv_len;
2979 	tlv = (struct hal_tlv_hdr *)ptr;
2980 
2981 	if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
2982 		return;
2983 
2984 	ptr += sizeof(*tlv);
2985 	ppdu_start = (struct hal_rx_ppdu_start *)ptr;
2986 	ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
2987 			    __le32_to_cpu(ppdu_start->info0));
2988 
2989 	if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
2990 		pmon->buf_state = DP_MON_STATUS_LEAD;
2991 		ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
2992 		if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2993 			pmon->buf_state = DP_MON_STATUS_LAG;
2994 	} else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
2995 		pmon->buf_state = DP_MON_STATUS_LAG;
2996 		ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
2997 		if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2998 			pmon->buf_state = DP_MON_STATUS_LEAD;
2999 	}
3000 }
3001 
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)3002 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
3003 					     int *budget, struct sk_buff_head *skb_list)
3004 {
3005 	struct ath11k *ar;
3006 	const struct ath11k_hw_hal_params *hal_params;
3007 	struct ath11k_pdev_dp *dp;
3008 	struct dp_rxdma_ring *rx_ring;
3009 	struct ath11k_mon_data *pmon;
3010 	struct hal_srng *srng;
3011 	void *rx_mon_status_desc;
3012 	struct sk_buff *skb;
3013 	struct ath11k_skb_rxcb *rxcb;
3014 	struct hal_tlv_hdr *tlv;
3015 	u32 cookie;
3016 	int buf_id, srng_id;
3017 	dma_addr_t paddr;
3018 	u8 rbm;
3019 	int num_buffs_reaped = 0;
3020 
3021 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3022 	dp = &ar->dp;
3023 	pmon = &dp->mon_data;
3024 	srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3025 	rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3026 
3027 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3028 
3029 	spin_lock_bh(&srng->lock);
3030 
3031 	ath11k_hal_srng_access_begin(ab, srng);
3032 	while (*budget) {
3033 		*budget -= 1;
3034 		rx_mon_status_desc =
3035 			ath11k_hal_srng_src_peek(ab, srng);
3036 		if (!rx_mon_status_desc) {
3037 			pmon->buf_state = DP_MON_STATUS_REPLINISH;
3038 			break;
3039 		}
3040 
3041 		ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3042 						&cookie, &rbm);
3043 		if (paddr) {
3044 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3045 
3046 			spin_lock_bh(&rx_ring->idr_lock);
3047 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
3048 			spin_unlock_bh(&rx_ring->idr_lock);
3049 
3050 			if (!skb) {
3051 				ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3052 					    buf_id);
3053 				pmon->buf_state = DP_MON_STATUS_REPLINISH;
3054 				goto move_next;
3055 			}
3056 
3057 			rxcb = ATH11K_SKB_RXCB(skb);
3058 
3059 			dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3060 						skb->len + skb_tailroom(skb),
3061 						DMA_FROM_DEVICE);
3062 
3063 			tlv = (struct hal_tlv_hdr *)skb->data;
3064 			if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3065 					HAL_RX_STATUS_BUFFER_DONE) {
3066 				ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
3067 					    FIELD_GET(HAL_TLV_HDR_TAG,
3068 						      tlv->tl), buf_id);
3069 				/* If done status is missing, hold onto status
3070 				 * ring until status is done for this status
3071 				 * ring buffer.
3072 				 * Keep HP in mon_status_ring unchanged,
3073 				 * and break from here.
3074 				 * Check status for same buffer for next time
3075 				 */
3076 				pmon->buf_state = DP_MON_STATUS_NO_DMA;
3077 				break;
3078 			}
3079 
3080 			spin_lock_bh(&rx_ring->idr_lock);
3081 			idr_remove(&rx_ring->bufs_idr, buf_id);
3082 			spin_unlock_bh(&rx_ring->idr_lock);
3083 			if (ab->hw_params.full_monitor_mode) {
3084 				ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3085 				if (paddr == pmon->mon_status_paddr)
3086 					pmon->buf_state = DP_MON_STATUS_MATCH;
3087 			}
3088 
3089 			dma_unmap_single(ab->dev, rxcb->paddr,
3090 					 skb->len + skb_tailroom(skb),
3091 					 DMA_FROM_DEVICE);
3092 
3093 			__skb_queue_tail(skb_list, skb);
3094 		} else {
3095 			pmon->buf_state = DP_MON_STATUS_REPLINISH;
3096 		}
3097 move_next:
3098 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3099 							&buf_id);
3100 
3101 		if (!skb) {
3102 			hal_params = ab->hw_params.hal_params;
3103 			ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3104 							hal_params->rx_buf_rbm);
3105 			num_buffs_reaped++;
3106 			break;
3107 		}
3108 		rxcb = ATH11K_SKB_RXCB(skb);
3109 
3110 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3111 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3112 
3113 		ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3114 						cookie,
3115 						ab->hw_params.hal_params->rx_buf_rbm);
3116 		ath11k_hal_srng_src_get_next_entry(ab, srng);
3117 		num_buffs_reaped++;
3118 	}
3119 	ath11k_hal_srng_access_end(ab, srng);
3120 	spin_unlock_bh(&srng->lock);
3121 
3122 	return num_buffs_reaped;
3123 }
3124 
ath11k_dp_rx_frag_timer(struct timer_list * timer)3125 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3126 {
3127 	struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
3128 
3129 	spin_lock_bh(&rx_tid->ab->base_lock);
3130 	if (rx_tid->last_frag_no &&
3131 	    rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3132 		spin_unlock_bh(&rx_tid->ab->base_lock);
3133 		return;
3134 	}
3135 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3136 	spin_unlock_bh(&rx_tid->ab->base_lock);
3137 }
3138 
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3139 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3140 {
3141 	struct ath11k_base *ab = ar->ab;
3142 	struct crypto_shash *tfm;
3143 	struct ath11k_peer *peer;
3144 	struct dp_rx_tid *rx_tid;
3145 	int i;
3146 
3147 	tfm = crypto_alloc_shash("michael_mic", 0, 0);
3148 	if (IS_ERR(tfm)) {
3149 		ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n",
3150 			    PTR_ERR(tfm));
3151 		return PTR_ERR(tfm);
3152 	}
3153 
3154 	spin_lock_bh(&ab->base_lock);
3155 
3156 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3157 	if (!peer) {
3158 		ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3159 		spin_unlock_bh(&ab->base_lock);
3160 		crypto_free_shash(tfm);
3161 		return -ENOENT;
3162 	}
3163 
3164 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3165 		rx_tid = &peer->rx_tid[i];
3166 		rx_tid->ab = ab;
3167 		timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3168 		skb_queue_head_init(&rx_tid->rx_frags);
3169 	}
3170 
3171 	peer->tfm_mmic = tfm;
3172 	peer->dp_setup_done = true;
3173 	spin_unlock_bh(&ab->base_lock);
3174 
3175 	return 0;
3176 }
3177 
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3178 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3179 				      struct ieee80211_hdr *hdr, u8 *data,
3180 				      size_t data_len, u8 *mic)
3181 {
3182 	SHASH_DESC_ON_STACK(desc, tfm);
3183 	u8 mic_hdr[16] = {0};
3184 	u8 tid = 0;
3185 	int ret;
3186 
3187 	if (!tfm)
3188 		return -EINVAL;
3189 
3190 	desc->tfm = tfm;
3191 
3192 	ret = crypto_shash_setkey(tfm, key, 8);
3193 	if (ret)
3194 		goto out;
3195 
3196 	ret = crypto_shash_init(desc);
3197 	if (ret)
3198 		goto out;
3199 
3200 	/* TKIP MIC header */
3201 	memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3202 	memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3203 	if (ieee80211_is_data_qos(hdr->frame_control))
3204 		tid = ieee80211_get_tid(hdr);
3205 	mic_hdr[12] = tid;
3206 
3207 	ret = crypto_shash_update(desc, mic_hdr, 16);
3208 	if (ret)
3209 		goto out;
3210 	ret = crypto_shash_update(desc, data, data_len);
3211 	if (ret)
3212 		goto out;
3213 	ret = crypto_shash_final(desc, mic);
3214 out:
3215 	shash_desc_zero(desc);
3216 	return ret;
3217 }
3218 
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3219 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3220 					  struct sk_buff *msdu)
3221 {
3222 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3223 	struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3224 	struct ieee80211_key_conf *key_conf;
3225 	struct ieee80211_hdr *hdr;
3226 	u8 mic[IEEE80211_CCMP_MIC_LEN];
3227 	int head_len, tail_len, ret;
3228 	size_t data_len;
3229 	u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3230 	u8 *key, *data;
3231 	u8 key_idx;
3232 
3233 	if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3234 	    HAL_ENCRYPT_TYPE_TKIP_MIC)
3235 		return 0;
3236 
3237 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3238 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
3239 	head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3240 	tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3241 
3242 	if (!is_multicast_ether_addr(hdr->addr1))
3243 		key_idx = peer->ucast_keyidx;
3244 	else
3245 		key_idx = peer->mcast_keyidx;
3246 
3247 	key_conf = peer->keys[key_idx];
3248 
3249 	data = msdu->data + head_len;
3250 	data_len = msdu->len - head_len - tail_len;
3251 	key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3252 
3253 	ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3254 	if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3255 		goto mic_fail;
3256 
3257 	return 0;
3258 
3259 mic_fail:
3260 	(ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3261 	(ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3262 
3263 	rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3264 		    RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3265 	skb_pull(msdu, hal_rx_desc_sz);
3266 
3267 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3268 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3269 			       HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3270 	ieee80211_rx(ar->hw, msdu);
3271 	return -EINVAL;
3272 }
3273 
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3274 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3275 					enum hal_encrypt_type enctype, u32 flags)
3276 {
3277 	struct ieee80211_hdr *hdr;
3278 	size_t hdr_len;
3279 	size_t crypto_len;
3280 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3281 
3282 	if (!flags)
3283 		return;
3284 
3285 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3286 
3287 	if (flags & RX_FLAG_MIC_STRIPPED)
3288 		skb_trim(msdu, msdu->len -
3289 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3290 
3291 	if (flags & RX_FLAG_ICV_STRIPPED)
3292 		skb_trim(msdu, msdu->len -
3293 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3294 
3295 	if (flags & RX_FLAG_IV_STRIPPED) {
3296 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
3297 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3298 
3299 		memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3300 			(void *)msdu->data + hal_rx_desc_sz, hdr_len);
3301 		skb_pull(msdu, crypto_len);
3302 	}
3303 }
3304 
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3305 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3306 				 struct ath11k_peer *peer,
3307 				 struct dp_rx_tid *rx_tid,
3308 				 struct sk_buff **defrag_skb)
3309 {
3310 	struct hal_rx_desc *rx_desc;
3311 	struct sk_buff *skb, *first_frag, *last_frag;
3312 	struct ieee80211_hdr *hdr;
3313 	struct rx_attention *rx_attention;
3314 	enum hal_encrypt_type enctype;
3315 	bool is_decrypted = false;
3316 	int msdu_len = 0;
3317 	int extra_space;
3318 	u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3319 
3320 	first_frag = skb_peek(&rx_tid->rx_frags);
3321 	last_frag = skb_peek_tail(&rx_tid->rx_frags);
3322 
3323 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3324 		flags = 0;
3325 		rx_desc = (struct hal_rx_desc *)skb->data;
3326 		hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3327 
3328 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3329 		if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3330 			rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3331 			is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3332 		}
3333 
3334 		if (is_decrypted) {
3335 			if (skb != first_frag)
3336 				flags |=  RX_FLAG_IV_STRIPPED;
3337 			if (skb != last_frag)
3338 				flags |= RX_FLAG_ICV_STRIPPED |
3339 					 RX_FLAG_MIC_STRIPPED;
3340 		}
3341 
3342 		/* RX fragments are always raw packets */
3343 		if (skb != last_frag)
3344 			skb_trim(skb, skb->len - FCS_LEN);
3345 		ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3346 
3347 		if (skb != first_frag)
3348 			skb_pull(skb, hal_rx_desc_sz +
3349 				      ieee80211_hdrlen(hdr->frame_control));
3350 		msdu_len += skb->len;
3351 	}
3352 
3353 	extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3354 	if (extra_space > 0 &&
3355 	    (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3356 		return -ENOMEM;
3357 
3358 	__skb_unlink(first_frag, &rx_tid->rx_frags);
3359 	while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3360 		skb_put_data(first_frag, skb->data, skb->len);
3361 		dev_kfree_skb_any(skb);
3362 	}
3363 
3364 	hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3365 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3366 	ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3367 
3368 	if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3369 		first_frag = NULL;
3370 
3371 	*defrag_skb = first_frag;
3372 	return 0;
3373 }
3374 
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3375 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3376 					      struct sk_buff *defrag_skb)
3377 {
3378 	struct ath11k_base *ab = ar->ab;
3379 	struct ath11k_pdev_dp *dp = &ar->dp;
3380 	struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3381 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3382 	struct hal_reo_entrance_ring *reo_ent_ring;
3383 	struct hal_reo_dest_ring *reo_dest_ring;
3384 	struct dp_link_desc_bank *link_desc_banks;
3385 	struct hal_rx_msdu_link *msdu_link;
3386 	struct hal_rx_msdu_details *msdu0;
3387 	struct hal_srng *srng;
3388 	dma_addr_t paddr;
3389 	u32 desc_bank, msdu_info, mpdu_info;
3390 	u32 dst_idx, cookie, hal_rx_desc_sz;
3391 	int ret, buf_id;
3392 
3393 	hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3394 	link_desc_banks = ab->dp.link_desc_banks;
3395 	reo_dest_ring = rx_tid->dst_ring_desc;
3396 
3397 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3398 	msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3399 			(paddr - link_desc_banks[desc_bank].paddr));
3400 	msdu0 = &msdu_link->msdu_link[0];
3401 	dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3402 	memset(msdu0, 0, sizeof(*msdu0));
3403 
3404 	msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3405 		    FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3406 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3407 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3408 			       defrag_skb->len - hal_rx_desc_sz) |
3409 		    FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3410 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3411 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3412 	msdu0->rx_msdu_info.info0 = msdu_info;
3413 
3414 	/* change msdu len in hal rx desc */
3415 	ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3416 
3417 	paddr = dma_map_single(ab->dev, defrag_skb->data,
3418 			       defrag_skb->len + skb_tailroom(defrag_skb),
3419 			       DMA_TO_DEVICE);
3420 	if (dma_mapping_error(ab->dev, paddr))
3421 		return -ENOMEM;
3422 
3423 	spin_lock_bh(&rx_refill_ring->idr_lock);
3424 	buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3425 			   rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3426 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3427 	if (buf_id < 0) {
3428 		ret = -ENOMEM;
3429 		goto err_unmap_dma;
3430 	}
3431 
3432 	ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3433 	cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3434 		 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3435 
3436 	ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3437 					ab->hw_params.hal_params->rx_buf_rbm);
3438 
3439 	/* Fill mpdu details into reo entrance ring */
3440 	srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3441 
3442 	spin_lock_bh(&srng->lock);
3443 	ath11k_hal_srng_access_begin(ab, srng);
3444 
3445 	reo_ent_ring = (struct hal_reo_entrance_ring *)
3446 			ath11k_hal_srng_src_get_next_entry(ab, srng);
3447 	if (!reo_ent_ring) {
3448 		ath11k_hal_srng_access_end(ab, srng);
3449 		spin_unlock_bh(&srng->lock);
3450 		ret = -ENOSPC;
3451 		goto err_free_idr;
3452 	}
3453 	memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3454 
3455 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3456 	ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3457 					HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3458 
3459 	mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3460 		    FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3461 		    FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3462 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3463 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3464 		    FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3465 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3466 
3467 	reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3468 	reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3469 	reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3470 	reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3471 					 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3472 						   reo_dest_ring->info0)) |
3473 			      FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3474 	ath11k_hal_srng_access_end(ab, srng);
3475 	spin_unlock_bh(&srng->lock);
3476 
3477 	return 0;
3478 
3479 err_free_idr:
3480 	spin_lock_bh(&rx_refill_ring->idr_lock);
3481 	idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3482 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3483 err_unmap_dma:
3484 	dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3485 			 DMA_TO_DEVICE);
3486 	return ret;
3487 }
3488 
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3489 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3490 				    struct sk_buff *a, struct sk_buff *b)
3491 {
3492 	int frag1, frag2;
3493 
3494 	frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3495 	frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3496 
3497 	return frag1 - frag2;
3498 }
3499 
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3500 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3501 				      struct sk_buff_head *frag_list,
3502 				      struct sk_buff *cur_frag)
3503 {
3504 	struct sk_buff *skb;
3505 	int cmp;
3506 
3507 	skb_queue_walk(frag_list, skb) {
3508 		cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3509 		if (cmp < 0)
3510 			continue;
3511 		__skb_queue_before(frag_list, skb, cur_frag);
3512 		return;
3513 	}
3514 	__skb_queue_tail(frag_list, cur_frag);
3515 }
3516 
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3517 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3518 {
3519 	struct ieee80211_hdr *hdr;
3520 	u64 pn = 0;
3521 	u8 *ehdr;
3522 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3523 
3524 	hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3525 	ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3526 
3527 	pn = ehdr[0];
3528 	pn |= (u64)ehdr[1] << 8;
3529 	pn |= (u64)ehdr[4] << 16;
3530 	pn |= (u64)ehdr[5] << 24;
3531 	pn |= (u64)ehdr[6] << 32;
3532 	pn |= (u64)ehdr[7] << 40;
3533 
3534 	return pn;
3535 }
3536 
3537 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3538 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3539 {
3540 	enum hal_encrypt_type encrypt_type;
3541 	struct sk_buff *first_frag, *skb;
3542 	struct hal_rx_desc *desc;
3543 	u64 last_pn;
3544 	u64 cur_pn;
3545 
3546 	first_frag = skb_peek(&rx_tid->rx_frags);
3547 	desc = (struct hal_rx_desc *)first_frag->data;
3548 
3549 	encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3550 	if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3551 	    encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3552 	    encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3553 	    encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3554 		return true;
3555 
3556 	last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3557 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3558 		if (skb == first_frag)
3559 			continue;
3560 
3561 		cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3562 		if (cur_pn != last_pn + 1)
3563 			return false;
3564 		last_pn = cur_pn;
3565 	}
3566 	return true;
3567 }
3568 
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3569 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3570 				    struct sk_buff *msdu,
3571 				    u32 *ring_desc)
3572 {
3573 	struct ath11k_base *ab = ar->ab;
3574 	struct hal_rx_desc *rx_desc;
3575 	struct ath11k_peer *peer;
3576 	struct dp_rx_tid *rx_tid;
3577 	struct sk_buff *defrag_skb = NULL;
3578 	u32 peer_id;
3579 	u16 seqno, frag_no;
3580 	u8 tid;
3581 	int ret = 0;
3582 	bool more_frags;
3583 	bool is_mcbc;
3584 
3585 	rx_desc = (struct hal_rx_desc *)msdu->data;
3586 	peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3587 	tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3588 	seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3589 	frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3590 	more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3591 	is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3592 
3593 	/* Multicast/Broadcast fragments are not expected */
3594 	if (is_mcbc)
3595 		return -EINVAL;
3596 
3597 	if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3598 	    !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3599 	    tid > IEEE80211_NUM_TIDS)
3600 		return -EINVAL;
3601 
3602 	/* received unfragmented packet in reo
3603 	 * exception ring, this shouldn't happen
3604 	 * as these packets typically come from
3605 	 * reo2sw srngs.
3606 	 */
3607 	if (WARN_ON_ONCE(!frag_no && !more_frags))
3608 		return -EINVAL;
3609 
3610 	spin_lock_bh(&ab->base_lock);
3611 	peer = ath11k_peer_find_by_id(ab, peer_id);
3612 	if (!peer) {
3613 		ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3614 			    peer_id);
3615 		ret = -ENOENT;
3616 		goto out_unlock;
3617 	}
3618 	if (!peer->dp_setup_done) {
3619 		ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3620 			    peer->addr, peer_id);
3621 		ret = -ENOENT;
3622 		goto out_unlock;
3623 	}
3624 
3625 	rx_tid = &peer->rx_tid[tid];
3626 
3627 	if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3628 	    skb_queue_empty(&rx_tid->rx_frags)) {
3629 		/* Flush stored fragments and start a new sequence */
3630 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
3631 		rx_tid->cur_sn = seqno;
3632 	}
3633 
3634 	if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3635 		/* Fragment already present */
3636 		ret = -EINVAL;
3637 		goto out_unlock;
3638 	}
3639 
3640 	if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
3641 		__skb_queue_tail(&rx_tid->rx_frags, msdu);
3642 	else
3643 		ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3644 
3645 	rx_tid->rx_frag_bitmap |= BIT(frag_no);
3646 	if (!more_frags)
3647 		rx_tid->last_frag_no = frag_no;
3648 
3649 	if (frag_no == 0) {
3650 		rx_tid->dst_ring_desc = kmemdup(ring_desc,
3651 						sizeof(*rx_tid->dst_ring_desc),
3652 						GFP_ATOMIC);
3653 		if (!rx_tid->dst_ring_desc) {
3654 			ret = -ENOMEM;
3655 			goto out_unlock;
3656 		}
3657 	} else {
3658 		ath11k_dp_rx_link_desc_return(ab, ring_desc,
3659 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3660 	}
3661 
3662 	if (!rx_tid->last_frag_no ||
3663 	    rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3664 		mod_timer(&rx_tid->frag_timer, jiffies +
3665 					       ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3666 		goto out_unlock;
3667 	}
3668 
3669 	spin_unlock_bh(&ab->base_lock);
3670 	del_timer_sync(&rx_tid->frag_timer);
3671 	spin_lock_bh(&ab->base_lock);
3672 
3673 	peer = ath11k_peer_find_by_id(ab, peer_id);
3674 	if (!peer)
3675 		goto err_frags_cleanup;
3676 
3677 	if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3678 		goto err_frags_cleanup;
3679 
3680 	if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3681 		goto err_frags_cleanup;
3682 
3683 	if (!defrag_skb)
3684 		goto err_frags_cleanup;
3685 
3686 	if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3687 		goto err_frags_cleanup;
3688 
3689 	ath11k_dp_rx_frags_cleanup(rx_tid, false);
3690 	goto out_unlock;
3691 
3692 err_frags_cleanup:
3693 	dev_kfree_skb_any(defrag_skb);
3694 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3695 out_unlock:
3696 	spin_unlock_bh(&ab->base_lock);
3697 	return ret;
3698 }
3699 
3700 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3701 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3702 {
3703 	struct ath11k_pdev_dp *dp = &ar->dp;
3704 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3705 	struct sk_buff *msdu;
3706 	struct ath11k_skb_rxcb *rxcb;
3707 	struct hal_rx_desc *rx_desc;
3708 	u8 *hdr_status;
3709 	u16 msdu_len;
3710 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3711 
3712 	spin_lock_bh(&rx_ring->idr_lock);
3713 	msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3714 	if (!msdu) {
3715 		ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3716 			    buf_id);
3717 		spin_unlock_bh(&rx_ring->idr_lock);
3718 		return -EINVAL;
3719 	}
3720 
3721 	idr_remove(&rx_ring->bufs_idr, buf_id);
3722 	spin_unlock_bh(&rx_ring->idr_lock);
3723 
3724 	rxcb = ATH11K_SKB_RXCB(msdu);
3725 	dma_unmap_single(ar->ab->dev, rxcb->paddr,
3726 			 msdu->len + skb_tailroom(msdu),
3727 			 DMA_FROM_DEVICE);
3728 
3729 	if (drop) {
3730 		dev_kfree_skb_any(msdu);
3731 		return 0;
3732 	}
3733 
3734 	rcu_read_lock();
3735 	if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3736 		dev_kfree_skb_any(msdu);
3737 		goto exit;
3738 	}
3739 
3740 	if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3741 		dev_kfree_skb_any(msdu);
3742 		goto exit;
3743 	}
3744 
3745 	rx_desc = (struct hal_rx_desc *)msdu->data;
3746 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3747 	if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3748 		hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3749 		ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3750 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3751 				sizeof(struct ieee80211_hdr));
3752 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3753 				sizeof(struct hal_rx_desc));
3754 		dev_kfree_skb_any(msdu);
3755 		goto exit;
3756 	}
3757 
3758 	skb_put(msdu, hal_rx_desc_sz + msdu_len);
3759 
3760 	if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3761 		dev_kfree_skb_any(msdu);
3762 		ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3763 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3764 	}
3765 exit:
3766 	rcu_read_unlock();
3767 	return 0;
3768 }
3769 
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3770 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3771 			     int budget)
3772 {
3773 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3774 	struct dp_link_desc_bank *link_desc_banks;
3775 	enum hal_rx_buf_return_buf_manager rbm;
3776 	int tot_n_bufs_reaped, quota, ret, i;
3777 	int n_bufs_reaped[MAX_RADIOS] = {0};
3778 	struct dp_rxdma_ring *rx_ring;
3779 	struct dp_srng *reo_except;
3780 	u32 desc_bank, num_msdus;
3781 	struct hal_srng *srng;
3782 	struct ath11k_dp *dp;
3783 	void *link_desc_va;
3784 	int buf_id, mac_id;
3785 	struct ath11k *ar;
3786 	dma_addr_t paddr;
3787 	u32 *desc;
3788 	bool is_frag;
3789 	u8 drop = 0;
3790 
3791 	tot_n_bufs_reaped = 0;
3792 	quota = budget;
3793 
3794 	dp = &ab->dp;
3795 	reo_except = &dp->reo_except_ring;
3796 	link_desc_banks = dp->link_desc_banks;
3797 
3798 	srng = &ab->hal.srng_list[reo_except->ring_id];
3799 
3800 	spin_lock_bh(&srng->lock);
3801 
3802 	ath11k_hal_srng_access_begin(ab, srng);
3803 
3804 	while (budget &&
3805 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3806 		struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3807 
3808 		ab->soc_stats.err_ring_pkts++;
3809 		ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3810 						    &desc_bank);
3811 		if (ret) {
3812 			ath11k_warn(ab, "failed to parse error reo desc %d\n",
3813 				    ret);
3814 			continue;
3815 		}
3816 		link_desc_va = link_desc_banks[desc_bank].vaddr +
3817 			       (paddr - link_desc_banks[desc_bank].paddr);
3818 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3819 						 &rbm);
3820 		if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3821 		    rbm != HAL_RX_BUF_RBM_SW1_BM &&
3822 		    rbm != HAL_RX_BUF_RBM_SW3_BM) {
3823 			ab->soc_stats.invalid_rbm++;
3824 			ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3825 			ath11k_dp_rx_link_desc_return(ab, desc,
3826 						      HAL_WBM_REL_BM_ACT_REL_MSDU);
3827 			continue;
3828 		}
3829 
3830 		is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3831 
3832 		/* Process only rx fragments with one msdu per link desc below, and drop
3833 		 * msdu's indicated due to error reasons.
3834 		 */
3835 		if (!is_frag || num_msdus > 1) {
3836 			drop = 1;
3837 			/* Return the link desc back to wbm idle list */
3838 			ath11k_dp_rx_link_desc_return(ab, desc,
3839 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3840 		}
3841 
3842 		for (i = 0; i < num_msdus; i++) {
3843 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3844 					   msdu_cookies[i]);
3845 
3846 			mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3847 					   msdu_cookies[i]);
3848 
3849 			ar = ab->pdevs[mac_id].ar;
3850 
3851 			if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3852 				n_bufs_reaped[mac_id]++;
3853 				tot_n_bufs_reaped++;
3854 			}
3855 		}
3856 
3857 		if (tot_n_bufs_reaped >= quota) {
3858 			tot_n_bufs_reaped = quota;
3859 			goto exit;
3860 		}
3861 
3862 		budget = quota - tot_n_bufs_reaped;
3863 	}
3864 
3865 exit:
3866 	ath11k_hal_srng_access_end(ab, srng);
3867 
3868 	spin_unlock_bh(&srng->lock);
3869 
3870 	for (i = 0; i <  ab->num_radios; i++) {
3871 		if (!n_bufs_reaped[i])
3872 			continue;
3873 
3874 		ar = ab->pdevs[i].ar;
3875 		rx_ring = &ar->dp.rx_refill_buf_ring;
3876 
3877 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3878 					   ab->hw_params.hal_params->rx_buf_rbm);
3879 	}
3880 
3881 	return tot_n_bufs_reaped;
3882 }
3883 
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3884 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3885 					     int msdu_len,
3886 					     struct sk_buff_head *msdu_list)
3887 {
3888 	struct sk_buff *skb, *tmp;
3889 	struct ath11k_skb_rxcb *rxcb;
3890 	int n_buffs;
3891 
3892 	n_buffs = DIV_ROUND_UP(msdu_len,
3893 			       (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3894 
3895 	skb_queue_walk_safe(msdu_list, skb, tmp) {
3896 		rxcb = ATH11K_SKB_RXCB(skb);
3897 		if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3898 		    rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3899 			if (!n_buffs)
3900 				break;
3901 			__skb_unlink(skb, msdu_list);
3902 			dev_kfree_skb_any(skb);
3903 			n_buffs--;
3904 		}
3905 	}
3906 }
3907 
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3908 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3909 				      struct ieee80211_rx_status *status,
3910 				      struct sk_buff_head *msdu_list)
3911 {
3912 	u16 msdu_len;
3913 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3914 	struct rx_attention *rx_attention;
3915 	u8 l3pad_bytes;
3916 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3917 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3918 
3919 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3920 
3921 	if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3922 		/* First buffer will be freed by the caller, so deduct it's length */
3923 		msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3924 		ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3925 		return -EINVAL;
3926 	}
3927 
3928 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3929 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3930 		ath11k_warn(ar->ab,
3931 			    "msdu_done bit not set in null_q_des processing\n");
3932 		__skb_queue_purge(msdu_list);
3933 		return -EIO;
3934 	}
3935 
3936 	/* Handle NULL queue descriptor violations arising out a missing
3937 	 * REO queue for a given peer or a given TID. This typically
3938 	 * may happen if a packet is received on a QOS enabled TID before the
3939 	 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3940 	 * it may also happen for MC/BC frames if they are not routed to the
3941 	 * non-QOS TID queue, in the absence of any other default TID queue.
3942 	 * This error can show up both in a REO destination or WBM release ring.
3943 	 */
3944 
3945 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3946 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3947 
3948 	if (rxcb->is_frag) {
3949 		skb_pull(msdu, hal_rx_desc_sz);
3950 	} else {
3951 		l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3952 
3953 		if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3954 			return -EINVAL;
3955 
3956 		skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3957 		skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3958 	}
3959 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3960 
3961 	ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3962 
3963 	rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
3964 
3965 	/* Please note that caller will having the access to msdu and completing
3966 	 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3967 	 */
3968 
3969 	return 0;
3970 }
3971 
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3972 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3973 				   struct ieee80211_rx_status *status,
3974 				   struct sk_buff_head *msdu_list)
3975 {
3976 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3977 	bool drop = false;
3978 
3979 	ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3980 
3981 	switch (rxcb->err_code) {
3982 	case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3983 		if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3984 			drop = true;
3985 		break;
3986 	case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3987 		/* TODO: Do not drop PN failed packets in the driver;
3988 		 * instead, it is good to drop such packets in mac80211
3989 		 * after incrementing the replay counters.
3990 		 */
3991 		fallthrough;
3992 	default:
3993 		/* TODO: Review other errors and process them to mac80211
3994 		 * as appropriate.
3995 		 */
3996 		drop = true;
3997 		break;
3998 	}
3999 
4000 	return drop;
4001 }
4002 
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4003 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
4004 					struct ieee80211_rx_status *status)
4005 {
4006 	u16 msdu_len;
4007 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4008 	u8 l3pad_bytes;
4009 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4010 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4011 
4012 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4013 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4014 
4015 	l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4016 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4017 	skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4018 	skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4019 
4020 	ath11k_dp_rx_h_ppdu(ar, desc, status);
4021 
4022 	status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4023 			 RX_FLAG_DECRYPTED);
4024 
4025 	ath11k_dp_rx_h_undecap(ar, msdu, desc,
4026 			       HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4027 }
4028 
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4029 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar,  struct sk_buff *msdu,
4030 				     struct ieee80211_rx_status *status)
4031 {
4032 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4033 	bool drop = false;
4034 
4035 	ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4036 
4037 	switch (rxcb->err_code) {
4038 	case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4039 		ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4040 		break;
4041 	default:
4042 		/* TODO: Review other rxdma error code to check if anything is
4043 		 * worth reporting to mac80211
4044 		 */
4045 		drop = true;
4046 		break;
4047 	}
4048 
4049 	return drop;
4050 }
4051 
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4052 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4053 				 struct napi_struct *napi,
4054 				 struct sk_buff *msdu,
4055 				 struct sk_buff_head *msdu_list)
4056 {
4057 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4058 	struct ieee80211_rx_status rxs = {0};
4059 	bool drop = true;
4060 
4061 	switch (rxcb->err_rel_src) {
4062 	case HAL_WBM_REL_SRC_MODULE_REO:
4063 		drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4064 		break;
4065 	case HAL_WBM_REL_SRC_MODULE_RXDMA:
4066 		drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4067 		break;
4068 	default:
4069 		/* msdu will get freed */
4070 		break;
4071 	}
4072 
4073 	if (drop) {
4074 		dev_kfree_skb_any(msdu);
4075 		return;
4076 	}
4077 
4078 	ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4079 }
4080 
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4081 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4082 				 struct napi_struct *napi, int budget)
4083 {
4084 	struct ath11k *ar;
4085 	struct ath11k_dp *dp = &ab->dp;
4086 	struct dp_rxdma_ring *rx_ring;
4087 	struct hal_rx_wbm_rel_info err_info;
4088 	struct hal_srng *srng;
4089 	struct sk_buff *msdu;
4090 	struct sk_buff_head msdu_list[MAX_RADIOS];
4091 	struct ath11k_skb_rxcb *rxcb;
4092 	u32 *rx_desc;
4093 	int buf_id, mac_id;
4094 	int num_buffs_reaped[MAX_RADIOS] = {0};
4095 	int total_num_buffs_reaped = 0;
4096 	int ret, i;
4097 
4098 	for (i = 0; i < ab->num_radios; i++)
4099 		__skb_queue_head_init(&msdu_list[i]);
4100 
4101 	srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4102 
4103 	spin_lock_bh(&srng->lock);
4104 
4105 	ath11k_hal_srng_access_begin(ab, srng);
4106 
4107 	while (budget) {
4108 		rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4109 		if (!rx_desc)
4110 			break;
4111 
4112 		ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4113 		if (ret) {
4114 			ath11k_warn(ab,
4115 				    "failed to parse rx error in wbm_rel ring desc %d\n",
4116 				    ret);
4117 			continue;
4118 		}
4119 
4120 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4121 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4122 
4123 		ar = ab->pdevs[mac_id].ar;
4124 		rx_ring = &ar->dp.rx_refill_buf_ring;
4125 
4126 		spin_lock_bh(&rx_ring->idr_lock);
4127 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4128 		if (!msdu) {
4129 			ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4130 				    buf_id, mac_id);
4131 			spin_unlock_bh(&rx_ring->idr_lock);
4132 			continue;
4133 		}
4134 
4135 		idr_remove(&rx_ring->bufs_idr, buf_id);
4136 		spin_unlock_bh(&rx_ring->idr_lock);
4137 
4138 		rxcb = ATH11K_SKB_RXCB(msdu);
4139 		dma_unmap_single(ab->dev, rxcb->paddr,
4140 				 msdu->len + skb_tailroom(msdu),
4141 				 DMA_FROM_DEVICE);
4142 
4143 		num_buffs_reaped[mac_id]++;
4144 		total_num_buffs_reaped++;
4145 		budget--;
4146 
4147 		if (err_info.push_reason !=
4148 		    HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4149 			dev_kfree_skb_any(msdu);
4150 			continue;
4151 		}
4152 
4153 		rxcb->err_rel_src = err_info.err_rel_src;
4154 		rxcb->err_code = err_info.err_code;
4155 		rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4156 		__skb_queue_tail(&msdu_list[mac_id], msdu);
4157 	}
4158 
4159 	ath11k_hal_srng_access_end(ab, srng);
4160 
4161 	spin_unlock_bh(&srng->lock);
4162 
4163 	if (!total_num_buffs_reaped)
4164 		goto done;
4165 
4166 	for (i = 0; i <  ab->num_radios; i++) {
4167 		if (!num_buffs_reaped[i])
4168 			continue;
4169 
4170 		ar = ab->pdevs[i].ar;
4171 		rx_ring = &ar->dp.rx_refill_buf_ring;
4172 
4173 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4174 					   ab->hw_params.hal_params->rx_buf_rbm);
4175 	}
4176 
4177 	rcu_read_lock();
4178 	for (i = 0; i <  ab->num_radios; i++) {
4179 		if (!rcu_dereference(ab->pdevs_active[i])) {
4180 			__skb_queue_purge(&msdu_list[i]);
4181 			continue;
4182 		}
4183 
4184 		ar = ab->pdevs[i].ar;
4185 
4186 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4187 			__skb_queue_purge(&msdu_list[i]);
4188 			continue;
4189 		}
4190 
4191 		while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4192 			ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4193 	}
4194 	rcu_read_unlock();
4195 done:
4196 	return total_num_buffs_reaped;
4197 }
4198 
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4199 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4200 {
4201 	struct ath11k *ar;
4202 	struct dp_srng *err_ring;
4203 	struct dp_rxdma_ring *rx_ring;
4204 	struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4205 	struct hal_srng *srng;
4206 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4207 	enum hal_rx_buf_return_buf_manager rbm;
4208 	enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4209 	struct ath11k_skb_rxcb *rxcb;
4210 	struct sk_buff *skb;
4211 	struct hal_reo_entrance_ring *entr_ring;
4212 	void *desc;
4213 	int num_buf_freed = 0;
4214 	int quota = budget;
4215 	dma_addr_t paddr;
4216 	u32 desc_bank;
4217 	void *link_desc_va;
4218 	int num_msdus;
4219 	int i;
4220 	int buf_id;
4221 
4222 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4223 	err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4224 									  mac_id)];
4225 	rx_ring = &ar->dp.rx_refill_buf_ring;
4226 
4227 	srng = &ab->hal.srng_list[err_ring->ring_id];
4228 
4229 	spin_lock_bh(&srng->lock);
4230 
4231 	ath11k_hal_srng_access_begin(ab, srng);
4232 
4233 	while (quota-- &&
4234 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4235 		ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4236 
4237 		entr_ring = (struct hal_reo_entrance_ring *)desc;
4238 		rxdma_err_code =
4239 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4240 				  entr_ring->info1);
4241 		ab->soc_stats.rxdma_error[rxdma_err_code]++;
4242 
4243 		link_desc_va = link_desc_banks[desc_bank].vaddr +
4244 			       (paddr - link_desc_banks[desc_bank].paddr);
4245 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4246 						 msdu_cookies, &rbm);
4247 
4248 		for (i = 0; i < num_msdus; i++) {
4249 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4250 					   msdu_cookies[i]);
4251 
4252 			spin_lock_bh(&rx_ring->idr_lock);
4253 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
4254 			if (!skb) {
4255 				ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4256 					    buf_id);
4257 				spin_unlock_bh(&rx_ring->idr_lock);
4258 				continue;
4259 			}
4260 
4261 			idr_remove(&rx_ring->bufs_idr, buf_id);
4262 			spin_unlock_bh(&rx_ring->idr_lock);
4263 
4264 			rxcb = ATH11K_SKB_RXCB(skb);
4265 			dma_unmap_single(ab->dev, rxcb->paddr,
4266 					 skb->len + skb_tailroom(skb),
4267 					 DMA_FROM_DEVICE);
4268 			dev_kfree_skb_any(skb);
4269 
4270 			num_buf_freed++;
4271 		}
4272 
4273 		ath11k_dp_rx_link_desc_return(ab, desc,
4274 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4275 	}
4276 
4277 	ath11k_hal_srng_access_end(ab, srng);
4278 
4279 	spin_unlock_bh(&srng->lock);
4280 
4281 	if (num_buf_freed)
4282 		ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4283 					   ab->hw_params.hal_params->rx_buf_rbm);
4284 
4285 	return budget - quota;
4286 }
4287 
ath11k_dp_process_reo_status(struct ath11k_base * ab)4288 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4289 {
4290 	struct ath11k_dp *dp = &ab->dp;
4291 	struct hal_srng *srng;
4292 	struct dp_reo_cmd *cmd, *tmp;
4293 	bool found = false;
4294 	u32 *reo_desc;
4295 	u16 tag;
4296 	struct hal_reo_status reo_status;
4297 
4298 	srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4299 
4300 	memset(&reo_status, 0, sizeof(reo_status));
4301 
4302 	spin_lock_bh(&srng->lock);
4303 
4304 	ath11k_hal_srng_access_begin(ab, srng);
4305 
4306 	while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4307 		tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4308 
4309 		switch (tag) {
4310 		case HAL_REO_GET_QUEUE_STATS_STATUS:
4311 			ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4312 							  &reo_status);
4313 			break;
4314 		case HAL_REO_FLUSH_QUEUE_STATUS:
4315 			ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4316 							  &reo_status);
4317 			break;
4318 		case HAL_REO_FLUSH_CACHE_STATUS:
4319 			ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4320 							  &reo_status);
4321 			break;
4322 		case HAL_REO_UNBLOCK_CACHE_STATUS:
4323 			ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4324 							  &reo_status);
4325 			break;
4326 		case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4327 			ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4328 								 &reo_status);
4329 			break;
4330 		case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4331 			ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4332 								  &reo_status);
4333 			break;
4334 		case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4335 			ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4336 								  &reo_status);
4337 			break;
4338 		default:
4339 			ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4340 			continue;
4341 		}
4342 
4343 		spin_lock_bh(&dp->reo_cmd_lock);
4344 		list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4345 			if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4346 				found = true;
4347 				list_del(&cmd->list);
4348 				break;
4349 			}
4350 		}
4351 		spin_unlock_bh(&dp->reo_cmd_lock);
4352 
4353 		if (found) {
4354 			cmd->handler(dp, (void *)&cmd->data,
4355 				     reo_status.uniform_hdr.cmd_status);
4356 			kfree(cmd);
4357 		}
4358 
4359 		found = false;
4360 	}
4361 
4362 	ath11k_hal_srng_access_end(ab, srng);
4363 
4364 	spin_unlock_bh(&srng->lock);
4365 }
4366 
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4367 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4368 {
4369 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4370 
4371 	ath11k_dp_rx_pdev_srng_free(ar);
4372 	ath11k_dp_rxdma_pdev_buf_free(ar);
4373 }
4374 
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4375 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4376 {
4377 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4378 	struct ath11k_pdev_dp *dp = &ar->dp;
4379 	u32 ring_id;
4380 	int i;
4381 	int ret;
4382 
4383 	ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4384 	if (ret) {
4385 		ath11k_warn(ab, "failed to setup rx srngs\n");
4386 		return ret;
4387 	}
4388 
4389 	ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4390 	if (ret) {
4391 		ath11k_warn(ab, "failed to setup rxdma ring\n");
4392 		return ret;
4393 	}
4394 
4395 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4396 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4397 	if (ret) {
4398 		ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4399 			    ret);
4400 		return ret;
4401 	}
4402 
4403 	if (ab->hw_params.rx_mac_buf_ring) {
4404 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4405 			ring_id = dp->rx_mac_buf_ring[i].ring_id;
4406 			ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4407 							  mac_id + i, HAL_RXDMA_BUF);
4408 			if (ret) {
4409 				ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4410 					    i, ret);
4411 				return ret;
4412 			}
4413 		}
4414 	}
4415 
4416 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4417 		ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4418 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4419 						  mac_id + i, HAL_RXDMA_DST);
4420 		if (ret) {
4421 			ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4422 				    i, ret);
4423 			return ret;
4424 		}
4425 	}
4426 
4427 	if (!ab->hw_params.rxdma1_enable)
4428 		goto config_refill_ring;
4429 
4430 	ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4431 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4432 					  mac_id, HAL_RXDMA_MONITOR_BUF);
4433 	if (ret) {
4434 		ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4435 			    ret);
4436 		return ret;
4437 	}
4438 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4439 					  dp->rxdma_mon_dst_ring.ring_id,
4440 					  mac_id, HAL_RXDMA_MONITOR_DST);
4441 	if (ret) {
4442 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4443 			    ret);
4444 		return ret;
4445 	}
4446 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4447 					  dp->rxdma_mon_desc_ring.ring_id,
4448 					  mac_id, HAL_RXDMA_MONITOR_DESC);
4449 	if (ret) {
4450 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4451 			    ret);
4452 		return ret;
4453 	}
4454 
4455 config_refill_ring:
4456 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4457 		ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4458 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4459 						  HAL_RXDMA_MONITOR_STATUS);
4460 		if (ret) {
4461 			ath11k_warn(ab,
4462 				    "failed to configure mon_status_refill_ring%d %d\n",
4463 				    i, ret);
4464 			return ret;
4465 		}
4466 	}
4467 
4468 	return 0;
4469 }
4470 
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4471 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4472 {
4473 	if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4474 		*frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4475 		*total_len -= *frag_len;
4476 	} else {
4477 		*frag_len = *total_len;
4478 		*total_len = 0;
4479 	}
4480 }
4481 
4482 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4483 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4484 					  void *p_last_buf_addr_info,
4485 					  u8 mac_id)
4486 {
4487 	struct ath11k_pdev_dp *dp = &ar->dp;
4488 	struct dp_srng *dp_srng;
4489 	void *hal_srng;
4490 	void *src_srng_desc;
4491 	int ret = 0;
4492 
4493 	if (ar->ab->hw_params.rxdma1_enable) {
4494 		dp_srng = &dp->rxdma_mon_desc_ring;
4495 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4496 	} else {
4497 		dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4498 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4499 	}
4500 
4501 	ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4502 
4503 	src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4504 
4505 	if (src_srng_desc) {
4506 		struct ath11k_buffer_addr *src_desc =
4507 				(struct ath11k_buffer_addr *)src_srng_desc;
4508 
4509 		*src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4510 	} else {
4511 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4512 			   "Monitor Link Desc Ring %d Full", mac_id);
4513 		ret = -ENOMEM;
4514 	}
4515 
4516 	ath11k_hal_srng_access_end(ar->ab, hal_srng);
4517 	return ret;
4518 }
4519 
4520 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4521 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4522 					 dma_addr_t *paddr, u32 *sw_cookie,
4523 					 u8 *rbm,
4524 					 void **pp_buf_addr_info)
4525 {
4526 	struct hal_rx_msdu_link *msdu_link =
4527 			(struct hal_rx_msdu_link *)rx_msdu_link_desc;
4528 	struct ath11k_buffer_addr *buf_addr_info;
4529 
4530 	buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4531 
4532 	ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4533 
4534 	*pp_buf_addr_info = (void *)buf_addr_info;
4535 }
4536 
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4537 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4538 {
4539 	if (skb->len > len) {
4540 		skb_trim(skb, len);
4541 	} else {
4542 		if (skb_tailroom(skb) < len - skb->len) {
4543 			if ((pskb_expand_head(skb, 0,
4544 					      len - skb->len - skb_tailroom(skb),
4545 					      GFP_ATOMIC))) {
4546 				dev_kfree_skb_any(skb);
4547 				return -ENOMEM;
4548 			}
4549 		}
4550 		skb_put(skb, (len - skb->len));
4551 	}
4552 	return 0;
4553 }
4554 
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4555 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4556 					void *msdu_link_desc,
4557 					struct hal_rx_msdu_list *msdu_list,
4558 					u16 *num_msdus)
4559 {
4560 	struct hal_rx_msdu_details *msdu_details = NULL;
4561 	struct rx_msdu_desc *msdu_desc_info = NULL;
4562 	struct hal_rx_msdu_link *msdu_link = NULL;
4563 	int i;
4564 	u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4565 	u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4566 	u8  tmp  = 0;
4567 
4568 	msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc;
4569 	msdu_details = &msdu_link->msdu_link[0];
4570 
4571 	for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4572 		if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4573 			      msdu_details[i].buf_addr_info.info0) == 0) {
4574 			msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4575 			msdu_desc_info->info0 |= last;
4576 			;
4577 			break;
4578 		}
4579 		msdu_desc_info = &msdu_details[i].rx_msdu_info;
4580 
4581 		if (!i)
4582 			msdu_desc_info->info0 |= first;
4583 		else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4584 			msdu_desc_info->info0 |= last;
4585 		msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4586 		msdu_list->msdu_info[i].msdu_len =
4587 			 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4588 		msdu_list->sw_cookie[i] =
4589 			FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4590 				  msdu_details[i].buf_addr_info.info1);
4591 		tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4592 				msdu_details[i].buf_addr_info.info1);
4593 		msdu_list->rbm[i] = tmp;
4594 	}
4595 	*num_msdus = i;
4596 }
4597 
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4598 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4599 					u32 *rx_bufs_used)
4600 {
4601 	u32 ret = 0;
4602 
4603 	if ((*ppdu_id < msdu_ppdu_id) &&
4604 	    ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4605 		*ppdu_id = msdu_ppdu_id;
4606 		ret = msdu_ppdu_id;
4607 	} else if ((*ppdu_id > msdu_ppdu_id) &&
4608 		((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4609 		/* mon_dst is behind than mon_status
4610 		 * skip dst_ring and free it
4611 		 */
4612 		*rx_bufs_used += 1;
4613 		*ppdu_id = msdu_ppdu_id;
4614 		ret = msdu_ppdu_id;
4615 	}
4616 	return ret;
4617 }
4618 
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4619 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4620 				      bool *is_frag, u32 *total_len,
4621 				      u32 *frag_len, u32 *msdu_cnt)
4622 {
4623 	if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4624 		if (!*is_frag) {
4625 			*total_len = info->msdu_len;
4626 			*is_frag = true;
4627 		}
4628 		ath11k_dp_mon_set_frag_len(total_len,
4629 					   frag_len);
4630 	} else {
4631 		if (*is_frag) {
4632 			ath11k_dp_mon_set_frag_len(total_len,
4633 						   frag_len);
4634 		} else {
4635 			*frag_len = info->msdu_len;
4636 		}
4637 		*is_frag = false;
4638 		*msdu_cnt -= 1;
4639 	}
4640 }
4641 
4642 static u32
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4643 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4644 			  void *ring_entry, struct sk_buff **head_msdu,
4645 			  struct sk_buff **tail_msdu, u32 *npackets,
4646 			  u32 *ppdu_id)
4647 {
4648 	struct ath11k_pdev_dp *dp = &ar->dp;
4649 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4650 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4651 	struct sk_buff *msdu = NULL, *last = NULL;
4652 	struct hal_rx_msdu_list msdu_list;
4653 	void *p_buf_addr_info, *p_last_buf_addr_info;
4654 	struct hal_rx_desc *rx_desc;
4655 	void *rx_msdu_link_desc;
4656 	dma_addr_t paddr;
4657 	u16 num_msdus = 0;
4658 	u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4659 	u32 rx_bufs_used = 0, i = 0;
4660 	u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4661 	u32 total_len = 0, frag_len = 0;
4662 	bool is_frag, is_first_msdu;
4663 	bool drop_mpdu = false;
4664 	struct ath11k_skb_rxcb *rxcb;
4665 	struct hal_reo_entrance_ring *ent_desc =
4666 			(struct hal_reo_entrance_ring *)ring_entry;
4667 	int buf_id;
4668 	u32 rx_link_buf_info[2];
4669 	u8 rbm;
4670 
4671 	if (!ar->ab->hw_params.rxdma1_enable)
4672 		rx_ring = &dp->rx_refill_buf_ring;
4673 
4674 	ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4675 					    &sw_cookie,
4676 					    &p_last_buf_addr_info, &rbm,
4677 					    &msdu_cnt);
4678 
4679 	if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4680 		      ent_desc->info1) ==
4681 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4682 		u8 rxdma_err =
4683 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4684 				  ent_desc->info1);
4685 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4686 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4687 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4688 			drop_mpdu = true;
4689 			pmon->rx_mon_stats.dest_mpdu_drop++;
4690 		}
4691 	}
4692 
4693 	is_frag = false;
4694 	is_first_msdu = true;
4695 
4696 	do {
4697 		if (pmon->mon_last_linkdesc_paddr == paddr) {
4698 			pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4699 			return rx_bufs_used;
4700 		}
4701 
4702 		if (ar->ab->hw_params.rxdma1_enable)
4703 			rx_msdu_link_desc =
4704 				(void *)pmon->link_desc_banks[sw_cookie].vaddr +
4705 				(paddr - pmon->link_desc_banks[sw_cookie].paddr);
4706 		else
4707 			rx_msdu_link_desc =
4708 				(void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4709 				(paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4710 
4711 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4712 					    &num_msdus);
4713 
4714 		for (i = 0; i < num_msdus; i++) {
4715 			u32 l2_hdr_offset;
4716 
4717 			if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4718 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4719 					   "i %d last_cookie %d is same\n",
4720 					   i, pmon->mon_last_buf_cookie);
4721 				drop_mpdu = true;
4722 				pmon->rx_mon_stats.dup_mon_buf_cnt++;
4723 				continue;
4724 			}
4725 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4726 					   msdu_list.sw_cookie[i]);
4727 
4728 			spin_lock_bh(&rx_ring->idr_lock);
4729 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4730 			spin_unlock_bh(&rx_ring->idr_lock);
4731 			if (!msdu) {
4732 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4733 					   "msdu_pop: invalid buf_id %d\n", buf_id);
4734 				break;
4735 			}
4736 			rxcb = ATH11K_SKB_RXCB(msdu);
4737 			if (!rxcb->unmapped) {
4738 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
4739 						 msdu->len +
4740 						 skb_tailroom(msdu),
4741 						 DMA_FROM_DEVICE);
4742 				rxcb->unmapped = 1;
4743 			}
4744 			if (drop_mpdu) {
4745 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4746 					   "i %d drop msdu %p *ppdu_id %x\n",
4747 					   i, msdu, *ppdu_id);
4748 				dev_kfree_skb_any(msdu);
4749 				msdu = NULL;
4750 				goto next_msdu;
4751 			}
4752 
4753 			rx_desc = (struct hal_rx_desc *)msdu->data;
4754 
4755 			rx_pkt_offset = sizeof(struct hal_rx_desc);
4756 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4757 
4758 			if (is_first_msdu) {
4759 				if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4760 					drop_mpdu = true;
4761 					dev_kfree_skb_any(msdu);
4762 					msdu = NULL;
4763 					pmon->mon_last_linkdesc_paddr = paddr;
4764 					goto next_msdu;
4765 				}
4766 
4767 				msdu_ppdu_id =
4768 					ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4769 
4770 				if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4771 								 ppdu_id,
4772 								 &rx_bufs_used)) {
4773 					if (rx_bufs_used) {
4774 						drop_mpdu = true;
4775 						dev_kfree_skb_any(msdu);
4776 						msdu = NULL;
4777 						goto next_msdu;
4778 					}
4779 					return rx_bufs_used;
4780 				}
4781 				pmon->mon_last_linkdesc_paddr = paddr;
4782 				is_first_msdu = false;
4783 			}
4784 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4785 						  &is_frag, &total_len,
4786 						  &frag_len, &msdu_cnt);
4787 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4788 
4789 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4790 
4791 			if (!(*head_msdu))
4792 				*head_msdu = msdu;
4793 			else if (last)
4794 				last->next = msdu;
4795 
4796 			last = msdu;
4797 next_msdu:
4798 			pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4799 			rx_bufs_used++;
4800 			spin_lock_bh(&rx_ring->idr_lock);
4801 			idr_remove(&rx_ring->bufs_idr, buf_id);
4802 			spin_unlock_bh(&rx_ring->idr_lock);
4803 		}
4804 
4805 		ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4806 
4807 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4808 						    &sw_cookie, &rbm,
4809 						    &p_buf_addr_info);
4810 
4811 		if (ar->ab->hw_params.rxdma1_enable) {
4812 			if (ath11k_dp_rx_monitor_link_desc_return(ar,
4813 								  p_last_buf_addr_info,
4814 								  dp->mac_id))
4815 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4816 					   "dp_rx_monitor_link_desc_return failed");
4817 		} else {
4818 			ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4819 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4820 		}
4821 
4822 		p_last_buf_addr_info = p_buf_addr_info;
4823 
4824 	} while (paddr && msdu_cnt);
4825 
4826 	if (last)
4827 		last->next = NULL;
4828 
4829 	*tail_msdu = msdu;
4830 
4831 	if (msdu_cnt == 0)
4832 		*npackets = 1;
4833 
4834 	return rx_bufs_used;
4835 }
4836 
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4837 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4838 {
4839 	u32 rx_pkt_offset, l2_hdr_offset;
4840 
4841 	rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4842 	l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4843 						      (struct hal_rx_desc *)msdu->data);
4844 	skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4845 }
4846 
4847 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4848 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4849 			    u32 mac_id, struct sk_buff *head_msdu,
4850 			    struct sk_buff *last_msdu,
4851 			    struct ieee80211_rx_status *rxs, bool *fcs_err)
4852 {
4853 	struct ath11k_base *ab = ar->ab;
4854 	struct sk_buff *msdu, *prev_buf;
4855 	struct hal_rx_desc *rx_desc;
4856 	char *hdr_desc;
4857 	u8 *dest, decap_format;
4858 	struct ieee80211_hdr_3addr *wh;
4859 	struct rx_attention *rx_attention;
4860 	u32 err_bitmap;
4861 
4862 	if (!head_msdu)
4863 		goto err_merge_fail;
4864 
4865 	rx_desc = (struct hal_rx_desc *)head_msdu->data;
4866 	rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4867 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4868 
4869 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4870 		*fcs_err = true;
4871 
4872 	if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4873 		return NULL;
4874 
4875 	decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4876 
4877 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4878 
4879 	if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4880 		ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4881 
4882 		prev_buf = head_msdu;
4883 		msdu = head_msdu->next;
4884 
4885 		while (msdu) {
4886 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4887 
4888 			prev_buf = msdu;
4889 			msdu = msdu->next;
4890 		}
4891 
4892 		prev_buf->next = NULL;
4893 
4894 		skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4895 	} else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4896 		u8 qos_pkt = 0;
4897 
4898 		rx_desc = (struct hal_rx_desc *)head_msdu->data;
4899 		hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4900 
4901 		/* Base size */
4902 		wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4903 
4904 		if (ieee80211_is_data_qos(wh->frame_control))
4905 			qos_pkt = 1;
4906 
4907 		msdu = head_msdu;
4908 
4909 		while (msdu) {
4910 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4911 			if (qos_pkt) {
4912 				dest = skb_push(msdu, sizeof(__le16));
4913 				if (!dest)
4914 					goto err_merge_fail;
4915 				memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
4916 			}
4917 			prev_buf = msdu;
4918 			msdu = msdu->next;
4919 		}
4920 		dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4921 		if (!dest)
4922 			goto err_merge_fail;
4923 
4924 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4925 			   "mpdu_buf %p mpdu_buf->len %u",
4926 			   prev_buf, prev_buf->len);
4927 	} else {
4928 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4929 			   "decap format %d is not supported!\n",
4930 			   decap_format);
4931 		goto err_merge_fail;
4932 	}
4933 
4934 	return head_msdu;
4935 
4936 err_merge_fail:
4937 	return NULL;
4938 }
4939 
4940 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4941 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
4942 				u8 *rtap_buf)
4943 {
4944 	u32 rtap_len = 0;
4945 
4946 	put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
4947 	rtap_len += 2;
4948 
4949 	put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
4950 	rtap_len += 2;
4951 
4952 	put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
4953 	rtap_len += 2;
4954 
4955 	put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
4956 	rtap_len += 2;
4957 
4958 	put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
4959 	rtap_len += 2;
4960 
4961 	put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
4962 }
4963 
4964 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4965 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
4966 				   u8 *rtap_buf)
4967 {
4968 	u32 rtap_len = 0;
4969 
4970 	put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
4971 	rtap_len += 2;
4972 
4973 	put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
4974 	rtap_len += 2;
4975 
4976 	rtap_buf[rtap_len] = rx_status->he_RU[0];
4977 	rtap_len += 1;
4978 
4979 	rtap_buf[rtap_len] = rx_status->he_RU[1];
4980 	rtap_len += 1;
4981 
4982 	rtap_buf[rtap_len] = rx_status->he_RU[2];
4983 	rtap_len += 1;
4984 
4985 	rtap_buf[rtap_len] = rx_status->he_RU[3];
4986 }
4987 
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)4988 static void ath11k_update_radiotap(struct ath11k *ar,
4989 				   struct hal_rx_mon_ppdu_info *ppduinfo,
4990 				   struct sk_buff *mon_skb,
4991 				   struct ieee80211_rx_status *rxs)
4992 {
4993 	struct ieee80211_supported_band *sband;
4994 	u8 *ptr = NULL;
4995 
4996 	rxs->flag |= RX_FLAG_MACTIME_START;
4997 	rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
4998 
4999 	if (ppduinfo->nss)
5000 		rxs->nss = ppduinfo->nss;
5001 
5002 	if (ppduinfo->he_mu_flags) {
5003 		rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
5004 		rxs->encoding = RX_ENC_HE;
5005 		ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
5006 		ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
5007 	} else if (ppduinfo->he_flags) {
5008 		rxs->flag |= RX_FLAG_RADIOTAP_HE;
5009 		rxs->encoding = RX_ENC_HE;
5010 		ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
5011 		ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
5012 		rxs->rate_idx = ppduinfo->rate;
5013 	} else if (ppduinfo->vht_flags) {
5014 		rxs->encoding = RX_ENC_VHT;
5015 		rxs->rate_idx = ppduinfo->rate;
5016 	} else if (ppduinfo->ht_flags) {
5017 		rxs->encoding = RX_ENC_HT;
5018 		rxs->rate_idx = ppduinfo->rate;
5019 	} else {
5020 		rxs->encoding = RX_ENC_LEGACY;
5021 		sband = &ar->mac.sbands[rxs->band];
5022 		rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5023 							  ppduinfo->cck_flag);
5024 	}
5025 
5026 	rxs->mactime = ppduinfo->tsft;
5027 }
5028 
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5029 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5030 				    struct sk_buff *head_msdu,
5031 				    struct hal_rx_mon_ppdu_info *ppduinfo,
5032 				    struct sk_buff *tail_msdu,
5033 				    struct napi_struct *napi)
5034 {
5035 	struct ath11k_pdev_dp *dp = &ar->dp;
5036 	struct sk_buff *mon_skb, *skb_next, *header;
5037 	struct ieee80211_rx_status *rxs = &dp->rx_status;
5038 	bool fcs_err = false;
5039 
5040 	mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5041 					      tail_msdu, rxs, &fcs_err);
5042 
5043 	if (!mon_skb)
5044 		goto mon_deliver_fail;
5045 
5046 	header = mon_skb;
5047 
5048 	rxs->flag = 0;
5049 
5050 	if (fcs_err)
5051 		rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5052 
5053 	do {
5054 		skb_next = mon_skb->next;
5055 		if (!skb_next)
5056 			rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5057 		else
5058 			rxs->flag |= RX_FLAG_AMSDU_MORE;
5059 
5060 		if (mon_skb == header) {
5061 			header = NULL;
5062 			rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5063 		} else {
5064 			rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5065 		}
5066 		rxs->flag |= RX_FLAG_ONLY_MONITOR;
5067 		ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5068 
5069 		ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5070 		mon_skb = skb_next;
5071 	} while (mon_skb);
5072 	rxs->flag = 0;
5073 
5074 	return 0;
5075 
5076 mon_deliver_fail:
5077 	mon_skb = head_msdu;
5078 	while (mon_skb) {
5079 		skb_next = mon_skb->next;
5080 		dev_kfree_skb_any(mon_skb);
5081 		mon_skb = skb_next;
5082 	}
5083 	return -EINVAL;
5084 }
5085 
5086 /* The destination ring processing is stuck if the destination is not
5087  * moving while status ring moves 16 PPDU. The destination ring processing
5088  * skips this destination ring PPDU as a workaround.
5089  */
5090 #define MON_DEST_RING_STUCK_MAX_CNT 16
5091 
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5092 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5093 					  u32 quota, struct napi_struct *napi)
5094 {
5095 	struct ath11k_pdev_dp *dp = &ar->dp;
5096 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5097 	const struct ath11k_hw_hal_params *hal_params;
5098 	void *ring_entry;
5099 	void *mon_dst_srng;
5100 	u32 ppdu_id;
5101 	u32 rx_bufs_used;
5102 	u32 ring_id;
5103 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5104 	u32	 npackets = 0;
5105 	u32 mpdu_rx_bufs_used;
5106 
5107 	if (ar->ab->hw_params.rxdma1_enable)
5108 		ring_id = dp->rxdma_mon_dst_ring.ring_id;
5109 	else
5110 		ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5111 
5112 	mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5113 
5114 	if (!mon_dst_srng) {
5115 		ath11k_warn(ar->ab,
5116 			    "HAL Monitor Destination Ring Init Failed -- %p",
5117 			    mon_dst_srng);
5118 		return;
5119 	}
5120 
5121 	spin_lock_bh(&pmon->mon_lock);
5122 
5123 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5124 
5125 	ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5126 	rx_bufs_used = 0;
5127 	rx_mon_stats = &pmon->rx_mon_stats;
5128 
5129 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5130 		struct sk_buff *head_msdu, *tail_msdu;
5131 
5132 		head_msdu = NULL;
5133 		tail_msdu = NULL;
5134 
5135 		mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5136 							      &head_msdu,
5137 							      &tail_msdu,
5138 							      &npackets, &ppdu_id);
5139 
5140 		rx_bufs_used += mpdu_rx_bufs_used;
5141 
5142 		if (mpdu_rx_bufs_used) {
5143 			dp->mon_dest_ring_stuck_cnt = 0;
5144 		} else {
5145 			dp->mon_dest_ring_stuck_cnt++;
5146 			rx_mon_stats->dest_mon_not_reaped++;
5147 		}
5148 
5149 		if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5150 			rx_mon_stats->dest_mon_stuck++;
5151 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5152 				   "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5153 				   pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5154 				   dp->mon_dest_ring_stuck_cnt,
5155 				   rx_mon_stats->dest_mon_not_reaped,
5156 				   rx_mon_stats->dest_mon_stuck);
5157 			pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5158 			continue;
5159 		}
5160 
5161 		if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5162 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5163 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5164 				   "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5165 				   ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5166 				   rx_mon_stats->dest_mon_not_reaped,
5167 				   rx_mon_stats->dest_mon_stuck);
5168 			break;
5169 		}
5170 		if (head_msdu && tail_msdu) {
5171 			ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5172 						 &pmon->mon_ppdu_info,
5173 						 tail_msdu, napi);
5174 			rx_mon_stats->dest_mpdu_done++;
5175 		}
5176 
5177 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5178 								mon_dst_srng);
5179 	}
5180 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5181 
5182 	spin_unlock_bh(&pmon->mon_lock);
5183 
5184 	if (rx_bufs_used) {
5185 		rx_mon_stats->dest_ppdu_done++;
5186 		hal_params = ar->ab->hw_params.hal_params;
5187 
5188 		if (ar->ab->hw_params.rxdma1_enable)
5189 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5190 						   &dp->rxdma_mon_buf_ring,
5191 						   rx_bufs_used,
5192 						   hal_params->rx_buf_rbm);
5193 		else
5194 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5195 						   &dp->rx_refill_buf_ring,
5196 						   rx_bufs_used,
5197 						   hal_params->rx_buf_rbm);
5198 	}
5199 }
5200 
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5201 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5202 				    struct napi_struct *napi, int budget)
5203 {
5204 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5205 	enum hal_rx_mon_status hal_status;
5206 	struct sk_buff *skb;
5207 	struct sk_buff_head skb_list;
5208 	struct ath11k_peer *peer;
5209 	struct ath11k_sta *arsta;
5210 	int num_buffs_reaped = 0;
5211 	u32 rx_buf_sz;
5212 	u16 log_type;
5213 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5214 	struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5215 	struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5216 
5217 	__skb_queue_head_init(&skb_list);
5218 
5219 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5220 							     &skb_list);
5221 	if (!num_buffs_reaped)
5222 		goto exit;
5223 
5224 	memset(ppdu_info, 0, sizeof(*ppdu_info));
5225 	ppdu_info->peer_id = HAL_INVALID_PEERID;
5226 
5227 	while ((skb = __skb_dequeue(&skb_list))) {
5228 		if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5229 			log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5230 			rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5231 		} else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5232 			log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5233 			rx_buf_sz = DP_RX_BUFFER_SIZE;
5234 		} else {
5235 			log_type = ATH11K_PKTLOG_TYPE_INVALID;
5236 			rx_buf_sz = 0;
5237 		}
5238 
5239 		if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5240 			trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5241 
5242 		memset(ppdu_info, 0, sizeof(*ppdu_info));
5243 		ppdu_info->peer_id = HAL_INVALID_PEERID;
5244 		hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5245 
5246 		if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5247 		    pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5248 		    hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5249 			rx_mon_stats->status_ppdu_done++;
5250 			pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5251 			if (!ab->hw_params.full_monitor_mode) {
5252 				ath11k_dp_rx_mon_dest_process(ar, mac_id,
5253 							      budget, napi);
5254 				pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5255 			}
5256 		}
5257 
5258 		if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5259 		    hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5260 			dev_kfree_skb_any(skb);
5261 			continue;
5262 		}
5263 
5264 		rcu_read_lock();
5265 		spin_lock_bh(&ab->base_lock);
5266 		peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5267 
5268 		if (!peer || !peer->sta) {
5269 			ath11k_dbg(ab, ATH11K_DBG_DATA,
5270 				   "failed to find the peer with peer_id %d\n",
5271 				   ppdu_info->peer_id);
5272 			goto next_skb;
5273 		}
5274 
5275 		arsta = (struct ath11k_sta *)peer->sta->drv_priv;
5276 		ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5277 
5278 		if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5279 			trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5280 
5281 next_skb:
5282 		spin_unlock_bh(&ab->base_lock);
5283 		rcu_read_unlock();
5284 
5285 		dev_kfree_skb_any(skb);
5286 		memset(ppdu_info, 0, sizeof(*ppdu_info));
5287 		ppdu_info->peer_id = HAL_INVALID_PEERID;
5288 	}
5289 exit:
5290 	return num_buffs_reaped;
5291 }
5292 
5293 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5294 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5295 			       void *ring_entry, struct sk_buff **head_msdu,
5296 			       struct sk_buff **tail_msdu,
5297 			       struct hal_sw_mon_ring_entries *sw_mon_entries)
5298 {
5299 	struct ath11k_pdev_dp *dp = &ar->dp;
5300 	struct ath11k_mon_data *pmon = &dp->mon_data;
5301 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5302 	struct sk_buff *msdu = NULL, *last = NULL;
5303 	struct hal_sw_monitor_ring *sw_desc = ring_entry;
5304 	struct hal_rx_msdu_list msdu_list;
5305 	struct hal_rx_desc *rx_desc;
5306 	struct ath11k_skb_rxcb *rxcb;
5307 	void *rx_msdu_link_desc;
5308 	void *p_buf_addr_info, *p_last_buf_addr_info;
5309 	int buf_id, i = 0;
5310 	u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5311 	u32 rx_bufs_used = 0, msdu_cnt = 0;
5312 	u32 total_len = 0, frag_len = 0, sw_cookie;
5313 	u16 num_msdus = 0;
5314 	u8 rxdma_err, rbm;
5315 	bool is_frag, is_first_msdu;
5316 	bool drop_mpdu = false;
5317 
5318 	ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5319 
5320 	sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5321 	sw_mon_entries->end_of_ppdu = false;
5322 	sw_mon_entries->drop_ppdu = false;
5323 	p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5324 	msdu_cnt = sw_mon_entries->msdu_cnt;
5325 
5326 	sw_mon_entries->end_of_ppdu =
5327 		FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5328 	if (sw_mon_entries->end_of_ppdu)
5329 		return rx_bufs_used;
5330 
5331 	if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5332 		      sw_desc->info0) ==
5333 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5334 		rxdma_err =
5335 			FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5336 				  sw_desc->info0);
5337 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5338 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5339 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5340 			pmon->rx_mon_stats.dest_mpdu_drop++;
5341 			drop_mpdu = true;
5342 		}
5343 	}
5344 
5345 	is_frag = false;
5346 	is_first_msdu = true;
5347 
5348 	do {
5349 		rx_msdu_link_desc =
5350 			(u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5351 			(sw_mon_entries->mon_dst_paddr -
5352 			 pmon->link_desc_banks[sw_cookie].paddr);
5353 
5354 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5355 					    &num_msdus);
5356 
5357 		for (i = 0; i < num_msdus; i++) {
5358 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5359 					   msdu_list.sw_cookie[i]);
5360 
5361 			spin_lock_bh(&rx_ring->idr_lock);
5362 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5363 			if (!msdu) {
5364 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5365 					   "full mon msdu_pop: invalid buf_id %d\n",
5366 					    buf_id);
5367 				spin_unlock_bh(&rx_ring->idr_lock);
5368 				break;
5369 			}
5370 			idr_remove(&rx_ring->bufs_idr, buf_id);
5371 			spin_unlock_bh(&rx_ring->idr_lock);
5372 
5373 			rxcb = ATH11K_SKB_RXCB(msdu);
5374 			if (!rxcb->unmapped) {
5375 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
5376 						 msdu->len +
5377 						 skb_tailroom(msdu),
5378 						 DMA_FROM_DEVICE);
5379 				rxcb->unmapped = 1;
5380 			}
5381 			if (drop_mpdu) {
5382 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5383 					   "full mon: i %d drop msdu %p *ppdu_id %x\n",
5384 					   i, msdu, sw_mon_entries->ppdu_id);
5385 				dev_kfree_skb_any(msdu);
5386 				msdu_cnt--;
5387 				goto next_msdu;
5388 			}
5389 
5390 			rx_desc = (struct hal_rx_desc *)msdu->data;
5391 
5392 			rx_pkt_offset = sizeof(struct hal_rx_desc);
5393 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5394 
5395 			if (is_first_msdu) {
5396 				if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5397 					drop_mpdu = true;
5398 					dev_kfree_skb_any(msdu);
5399 					msdu = NULL;
5400 					goto next_msdu;
5401 				}
5402 				is_first_msdu = false;
5403 			}
5404 
5405 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5406 						  &is_frag, &total_len,
5407 						  &frag_len, &msdu_cnt);
5408 
5409 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5410 
5411 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5412 
5413 			if (!(*head_msdu))
5414 				*head_msdu = msdu;
5415 			else if (last)
5416 				last->next = msdu;
5417 
5418 			last = msdu;
5419 next_msdu:
5420 			rx_bufs_used++;
5421 		}
5422 
5423 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5424 						    &sw_mon_entries->mon_dst_paddr,
5425 						    &sw_mon_entries->mon_dst_sw_cookie,
5426 						    &rbm,
5427 						    &p_buf_addr_info);
5428 
5429 		if (ath11k_dp_rx_monitor_link_desc_return(ar,
5430 							  p_last_buf_addr_info,
5431 							  dp->mac_id))
5432 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5433 				   "full mon: dp_rx_monitor_link_desc_return failed\n");
5434 
5435 		p_last_buf_addr_info = p_buf_addr_info;
5436 
5437 	} while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5438 
5439 	if (last)
5440 		last->next = NULL;
5441 
5442 	*tail_msdu = msdu;
5443 
5444 	return rx_bufs_used;
5445 }
5446 
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5447 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5448 					      struct dp_full_mon_mpdu *mon_mpdu,
5449 					      struct sk_buff *head,
5450 					      struct sk_buff *tail)
5451 {
5452 	mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
5453 	if (!mon_mpdu)
5454 		return -ENOMEM;
5455 
5456 	list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5457 	mon_mpdu->head = head;
5458 	mon_mpdu->tail = tail;
5459 
5460 	return 0;
5461 }
5462 
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5463 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5464 					    struct dp_full_mon_mpdu *mon_mpdu)
5465 {
5466 	struct dp_full_mon_mpdu *tmp;
5467 	struct sk_buff *tmp_msdu, *skb_next;
5468 
5469 	if (list_empty(&dp->dp_full_mon_mpdu_list))
5470 		return;
5471 
5472 	list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5473 		list_del(&mon_mpdu->list);
5474 
5475 		tmp_msdu = mon_mpdu->head;
5476 		while (tmp_msdu) {
5477 			skb_next = tmp_msdu->next;
5478 			dev_kfree_skb_any(tmp_msdu);
5479 			tmp_msdu = skb_next;
5480 		}
5481 
5482 		kfree(mon_mpdu);
5483 	}
5484 }
5485 
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5486 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5487 					      int mac_id,
5488 					      struct ath11k_mon_data *pmon,
5489 					      struct napi_struct *napi)
5490 {
5491 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5492 	struct dp_full_mon_mpdu *tmp;
5493 	struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5494 	struct sk_buff *head_msdu, *tail_msdu;
5495 	struct ath11k_base *ab = ar->ab;
5496 	struct ath11k_dp *dp = &ab->dp;
5497 	int ret;
5498 
5499 	rx_mon_stats = &pmon->rx_mon_stats;
5500 
5501 	list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5502 		list_del(&mon_mpdu->list);
5503 		head_msdu = mon_mpdu->head;
5504 		tail_msdu = mon_mpdu->tail;
5505 		if (head_msdu && tail_msdu) {
5506 			ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5507 						       &pmon->mon_ppdu_info,
5508 						       tail_msdu, napi);
5509 			rx_mon_stats->dest_mpdu_done++;
5510 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5511 		}
5512 		kfree(mon_mpdu);
5513 	}
5514 
5515 	return ret;
5516 }
5517 
5518 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5519 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5520 					  struct napi_struct *napi, int budget)
5521 {
5522 	struct ath11k *ar = ab->pdevs[mac_id].ar;
5523 	struct ath11k_pdev_dp *dp = &ar->dp;
5524 	struct ath11k_mon_data *pmon = &dp->mon_data;
5525 	struct hal_sw_mon_ring_entries *sw_mon_entries;
5526 	int quota = 0, work = 0, count;
5527 
5528 	sw_mon_entries = &pmon->sw_mon_entries;
5529 
5530 	while (pmon->hold_mon_dst_ring) {
5531 		quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5532 							napi, 1);
5533 		if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5534 			count = sw_mon_entries->status_buf_count;
5535 			if (count > 1) {
5536 				quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5537 									 napi, count);
5538 			}
5539 
5540 			ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5541 							   pmon, napi);
5542 			pmon->hold_mon_dst_ring = false;
5543 		} else if (!pmon->mon_status_paddr ||
5544 			   pmon->buf_state == DP_MON_STATUS_LEAD) {
5545 			sw_mon_entries->drop_ppdu = true;
5546 			pmon->hold_mon_dst_ring = false;
5547 		}
5548 
5549 		if (!quota)
5550 			break;
5551 
5552 		work += quota;
5553 	}
5554 
5555 	if (sw_mon_entries->drop_ppdu)
5556 		ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5557 
5558 	return work;
5559 }
5560 
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5561 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5562 					 struct napi_struct *napi, int budget)
5563 {
5564 	struct ath11k *ar = ab->pdevs[mac_id].ar;
5565 	struct ath11k_pdev_dp *dp = &ar->dp;
5566 	struct ath11k_mon_data *pmon = &dp->mon_data;
5567 	struct hal_sw_mon_ring_entries *sw_mon_entries;
5568 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5569 	struct sk_buff *head_msdu, *tail_msdu;
5570 	void *mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5571 	void *ring_entry;
5572 	u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5573 	int quota = 0, ret;
5574 	bool break_dst_ring = false;
5575 
5576 	spin_lock_bh(&pmon->mon_lock);
5577 
5578 	sw_mon_entries = &pmon->sw_mon_entries;
5579 	rx_mon_stats = &pmon->rx_mon_stats;
5580 
5581 	if (pmon->hold_mon_dst_ring) {
5582 		spin_unlock_bh(&pmon->mon_lock);
5583 		goto reap_status_ring;
5584 	}
5585 
5586 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5587 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5588 		head_msdu = NULL;
5589 		tail_msdu = NULL;
5590 
5591 		mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5592 								   &head_msdu,
5593 								   &tail_msdu,
5594 								   sw_mon_entries);
5595 		rx_bufs_used += mpdu_rx_bufs_used;
5596 
5597 		if (!sw_mon_entries->end_of_ppdu) {
5598 			if (head_msdu) {
5599 				ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5600 									 pmon->mon_mpdu,
5601 									 head_msdu,
5602 									 tail_msdu);
5603 				if (ret)
5604 					break_dst_ring = true;
5605 			}
5606 
5607 			goto next_entry;
5608 		} else {
5609 			if (!sw_mon_entries->ppdu_id &&
5610 			    !sw_mon_entries->mon_status_paddr) {
5611 				break_dst_ring = true;
5612 				goto next_entry;
5613 			}
5614 		}
5615 
5616 		rx_mon_stats->dest_ppdu_done++;
5617 		pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5618 		pmon->buf_state = DP_MON_STATUS_LAG;
5619 		pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5620 		pmon->hold_mon_dst_ring = true;
5621 next_entry:
5622 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5623 								mon_dst_srng);
5624 		if (break_dst_ring)
5625 			break;
5626 	}
5627 
5628 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5629 	spin_unlock_bh(&pmon->mon_lock);
5630 
5631 	if (rx_bufs_used) {
5632 		ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5633 					   &dp->rxdma_mon_buf_ring,
5634 					   rx_bufs_used,
5635 					   HAL_RX_BUF_RBM_SW3_BM);
5636 	}
5637 
5638 reap_status_ring:
5639 	quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5640 							  napi, budget);
5641 
5642 	return quota;
5643 }
5644 
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5645 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5646 				   struct napi_struct *napi, int budget)
5647 {
5648 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5649 	int ret = 0;
5650 
5651 	if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5652 	    ab->hw_params.full_monitor_mode)
5653 		ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5654 	else
5655 		ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5656 
5657 	return ret;
5658 }
5659 
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5660 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5661 {
5662 	struct ath11k_pdev_dp *dp = &ar->dp;
5663 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5664 
5665 	skb_queue_head_init(&pmon->rx_status_q);
5666 
5667 	pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5668 
5669 	memset(&pmon->rx_mon_stats, 0,
5670 	       sizeof(pmon->rx_mon_stats));
5671 	return 0;
5672 }
5673 
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5674 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5675 {
5676 	struct ath11k_pdev_dp *dp = &ar->dp;
5677 	struct ath11k_mon_data *pmon = &dp->mon_data;
5678 	struct hal_srng *mon_desc_srng = NULL;
5679 	struct dp_srng *dp_srng;
5680 	int ret = 0;
5681 	u32 n_link_desc = 0;
5682 
5683 	ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5684 	if (ret) {
5685 		ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5686 		return ret;
5687 	}
5688 
5689 	/* if rxdma1_enable is false, no need to setup
5690 	 * rxdma_mon_desc_ring.
5691 	 */
5692 	if (!ar->ab->hw_params.rxdma1_enable)
5693 		return 0;
5694 
5695 	dp_srng = &dp->rxdma_mon_desc_ring;
5696 	n_link_desc = dp_srng->size /
5697 		ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5698 	mon_desc_srng =
5699 		&ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5700 
5701 	ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5702 					HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5703 					n_link_desc);
5704 	if (ret) {
5705 		ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5706 		return ret;
5707 	}
5708 	pmon->mon_last_linkdesc_paddr = 0;
5709 	pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5710 	spin_lock_init(&pmon->mon_lock);
5711 
5712 	return 0;
5713 }
5714 
ath11k_dp_mon_link_free(struct ath11k * ar)5715 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5716 {
5717 	struct ath11k_pdev_dp *dp = &ar->dp;
5718 	struct ath11k_mon_data *pmon = &dp->mon_data;
5719 
5720 	ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5721 				    HAL_RXDMA_MONITOR_DESC,
5722 				    &dp->rxdma_mon_desc_ring);
5723 	return 0;
5724 }
5725 
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5726 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5727 {
5728 	ath11k_dp_mon_link_free(ar);
5729 	return 0;
5730 }
5731 
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5732 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5733 {
5734 	/* start reap timer */
5735 	mod_timer(&ab->mon_reap_timer,
5736 		  jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5737 
5738 	return 0;
5739 }
5740 
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5741 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5742 {
5743 	int ret;
5744 
5745 	if (stop_timer)
5746 		del_timer_sync(&ab->mon_reap_timer);
5747 
5748 	/* reap all the monitor related rings */
5749 	ret = ath11k_dp_purge_mon_ring(ab);
5750 	if (ret) {
5751 		ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5752 		return ret;
5753 	}
5754 
5755 	return 0;
5756 }
5757