1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bits.h>
7 #include <linux/clk.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/property.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/remoteproc/qcom_rproc.h>
16 #include <linux/of_address.h>
17 #include <linux/iommu.h>
18
19 #include "ce.h"
20 #include "coredump.h"
21 #include "debug.h"
22 #include "hif.h"
23 #include "htc.h"
24 #include "snoc.h"
25
26 #define ATH10K_SNOC_RX_POST_RETRY_MS 50
27 #define CE_POLL_PIPE 4
28 #define ATH10K_SNOC_WAKE_IRQ 2
29
30 static char *const ce_name[] = {
31 "WLAN_CE_0",
32 "WLAN_CE_1",
33 "WLAN_CE_2",
34 "WLAN_CE_3",
35 "WLAN_CE_4",
36 "WLAN_CE_5",
37 "WLAN_CE_6",
38 "WLAN_CE_7",
39 "WLAN_CE_8",
40 "WLAN_CE_9",
41 "WLAN_CE_10",
42 "WLAN_CE_11",
43 };
44
45 static const char * const ath10k_regulators[] = {
46 "vdd-0.8-cx-mx",
47 "vdd-1.8-xo",
48 "vdd-1.3-rfa",
49 "vdd-3.3-ch0",
50 "vdd-3.3-ch1",
51 };
52
53 static const char * const ath10k_clocks[] = {
54 "cxo_ref_clk_pin", "qdss",
55 };
56
57 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
58 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
59 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
60 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
61 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
62 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
63
64 static const struct ath10k_snoc_drv_priv drv_priv = {
65 .hw_rev = ATH10K_HW_WCN3990,
66 .dma_mask = DMA_BIT_MASK(35),
67 .msa_size = 0x100000,
68 };
69
70 #define WCN3990_SRC_WR_IDX_OFFSET 0x3C
71 #define WCN3990_DST_WR_IDX_OFFSET 0x40
72
73 static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map[] = {
74 {
75 .ce_id = __cpu_to_le16(0),
76 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
77 },
78
79 {
80 .ce_id = __cpu_to_le16(3),
81 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
82 },
83
84 {
85 .ce_id = __cpu_to_le16(4),
86 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
87 },
88
89 {
90 .ce_id = __cpu_to_le16(5),
91 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
92 },
93
94 {
95 .ce_id = __cpu_to_le16(7),
96 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
97 },
98
99 {
100 .ce_id = __cpu_to_le16(1),
101 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
102 },
103
104 {
105 .ce_id = __cpu_to_le16(2),
106 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
107 },
108
109 {
110 .ce_id = __cpu_to_le16(7),
111 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
112 },
113
114 {
115 .ce_id = __cpu_to_le16(8),
116 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
117 },
118
119 {
120 .ce_id = __cpu_to_le16(9),
121 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
122 },
123
124 {
125 .ce_id = __cpu_to_le16(10),
126 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
127 },
128
129 {
130 .ce_id = __cpu_to_le16(11),
131 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
132 },
133 };
134
135 static struct ce_attr host_ce_config_wlan[] = {
136 /* CE0: host->target HTC control streams */
137 {
138 .flags = CE_ATTR_FLAGS,
139 .src_nentries = 16,
140 .src_sz_max = 2048,
141 .dest_nentries = 0,
142 .send_cb = ath10k_snoc_htc_tx_cb,
143 },
144
145 /* CE1: target->host HTT + HTC control */
146 {
147 .flags = CE_ATTR_FLAGS,
148 .src_nentries = 0,
149 .src_sz_max = 2048,
150 .dest_nentries = 512,
151 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
152 },
153
154 /* CE2: target->host WMI */
155 {
156 .flags = CE_ATTR_FLAGS,
157 .src_nentries = 0,
158 .src_sz_max = 2048,
159 .dest_nentries = 64,
160 .recv_cb = ath10k_snoc_htc_rx_cb,
161 },
162
163 /* CE3: host->target WMI */
164 {
165 .flags = CE_ATTR_FLAGS,
166 .src_nentries = 32,
167 .src_sz_max = 2048,
168 .dest_nentries = 0,
169 .send_cb = ath10k_snoc_htc_tx_cb,
170 },
171
172 /* CE4: host->target HTT */
173 {
174 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
175 .src_nentries = 2048,
176 .src_sz_max = 256,
177 .dest_nentries = 0,
178 .send_cb = ath10k_snoc_htt_tx_cb,
179 },
180
181 /* CE5: target->host HTT (ipa_uc->target ) */
182 {
183 .flags = CE_ATTR_FLAGS,
184 .src_nentries = 0,
185 .src_sz_max = 512,
186 .dest_nentries = 512,
187 .recv_cb = ath10k_snoc_htt_rx_cb,
188 },
189
190 /* CE6: target autonomous hif_memcpy */
191 {
192 .flags = CE_ATTR_FLAGS,
193 .src_nentries = 0,
194 .src_sz_max = 0,
195 .dest_nentries = 0,
196 },
197
198 /* CE7: ce_diag, the Diagnostic Window */
199 {
200 .flags = CE_ATTR_FLAGS,
201 .src_nentries = 2,
202 .src_sz_max = 2048,
203 .dest_nentries = 2,
204 },
205
206 /* CE8: Target to uMC */
207 {
208 .flags = CE_ATTR_FLAGS,
209 .src_nentries = 0,
210 .src_sz_max = 2048,
211 .dest_nentries = 128,
212 },
213
214 /* CE9 target->host HTT */
215 {
216 .flags = CE_ATTR_FLAGS,
217 .src_nentries = 0,
218 .src_sz_max = 2048,
219 .dest_nentries = 512,
220 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
221 },
222
223 /* CE10: target->host HTT */
224 {
225 .flags = CE_ATTR_FLAGS,
226 .src_nentries = 0,
227 .src_sz_max = 2048,
228 .dest_nentries = 512,
229 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
230 },
231
232 /* CE11: target -> host PKTLOG */
233 {
234 .flags = CE_ATTR_FLAGS,
235 .src_nentries = 0,
236 .src_sz_max = 2048,
237 .dest_nentries = 512,
238 .recv_cb = ath10k_snoc_pktlog_rx_cb,
239 },
240 };
241
242 static struct ce_pipe_config target_ce_config_wlan[] = {
243 /* CE0: host->target HTC control and raw streams */
244 {
245 .pipenum = __cpu_to_le32(0),
246 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
247 .nentries = __cpu_to_le32(32),
248 .nbytes_max = __cpu_to_le32(2048),
249 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
250 .reserved = __cpu_to_le32(0),
251 },
252
253 /* CE1: target->host HTT + HTC control */
254 {
255 .pipenum = __cpu_to_le32(1),
256 .pipedir = __cpu_to_le32(PIPEDIR_IN),
257 .nentries = __cpu_to_le32(32),
258 .nbytes_max = __cpu_to_le32(2048),
259 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
260 .reserved = __cpu_to_le32(0),
261 },
262
263 /* CE2: target->host WMI */
264 {
265 .pipenum = __cpu_to_le32(2),
266 .pipedir = __cpu_to_le32(PIPEDIR_IN),
267 .nentries = __cpu_to_le32(64),
268 .nbytes_max = __cpu_to_le32(2048),
269 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
270 .reserved = __cpu_to_le32(0),
271 },
272
273 /* CE3: host->target WMI */
274 {
275 .pipenum = __cpu_to_le32(3),
276 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
277 .nentries = __cpu_to_le32(32),
278 .nbytes_max = __cpu_to_le32(2048),
279 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
280 .reserved = __cpu_to_le32(0),
281 },
282
283 /* CE4: host->target HTT */
284 {
285 .pipenum = __cpu_to_le32(4),
286 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
287 .nentries = __cpu_to_le32(256),
288 .nbytes_max = __cpu_to_le32(256),
289 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
290 .reserved = __cpu_to_le32(0),
291 },
292
293 /* CE5: target->host HTT (HIF->HTT) */
294 {
295 .pipenum = __cpu_to_le32(5),
296 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
297 .nentries = __cpu_to_le32(1024),
298 .nbytes_max = __cpu_to_le32(64),
299 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
300 .reserved = __cpu_to_le32(0),
301 },
302
303 /* CE6: Reserved for target autonomous hif_memcpy */
304 {
305 .pipenum = __cpu_to_le32(6),
306 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
307 .nentries = __cpu_to_le32(32),
308 .nbytes_max = __cpu_to_le32(16384),
309 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
310 .reserved = __cpu_to_le32(0),
311 },
312
313 /* CE7 used only by Host */
314 {
315 .pipenum = __cpu_to_le32(7),
316 .pipedir = __cpu_to_le32(4),
317 .nentries = __cpu_to_le32(0),
318 .nbytes_max = __cpu_to_le32(0),
319 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
320 .reserved = __cpu_to_le32(0),
321 },
322
323 /* CE8 Target to uMC */
324 {
325 .pipenum = __cpu_to_le32(8),
326 .pipedir = __cpu_to_le32(PIPEDIR_IN),
327 .nentries = __cpu_to_le32(32),
328 .nbytes_max = __cpu_to_le32(2048),
329 .flags = __cpu_to_le32(0),
330 .reserved = __cpu_to_le32(0),
331 },
332
333 /* CE9 target->host HTT */
334 {
335 .pipenum = __cpu_to_le32(9),
336 .pipedir = __cpu_to_le32(PIPEDIR_IN),
337 .nentries = __cpu_to_le32(32),
338 .nbytes_max = __cpu_to_le32(2048),
339 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
340 .reserved = __cpu_to_le32(0),
341 },
342
343 /* CE10 target->host HTT */
344 {
345 .pipenum = __cpu_to_le32(10),
346 .pipedir = __cpu_to_le32(PIPEDIR_IN),
347 .nentries = __cpu_to_le32(32),
348 .nbytes_max = __cpu_to_le32(2048),
349 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
350 .reserved = __cpu_to_le32(0),
351 },
352
353 /* CE11 target autonomous qcache memcpy */
354 {
355 .pipenum = __cpu_to_le32(11),
356 .pipedir = __cpu_to_le32(PIPEDIR_IN),
357 .nentries = __cpu_to_le32(32),
358 .nbytes_max = __cpu_to_le32(2048),
359 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
360 .reserved = __cpu_to_le32(0),
361 },
362 };
363
364 static struct ce_service_to_pipe target_service_to_ce_map_wlan[] = {
365 {
366 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
367 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
368 __cpu_to_le32(3),
369 },
370 {
371 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
372 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
373 __cpu_to_le32(2),
374 },
375 {
376 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
377 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
378 __cpu_to_le32(3),
379 },
380 {
381 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
382 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
383 __cpu_to_le32(2),
384 },
385 {
386 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
387 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
388 __cpu_to_le32(3),
389 },
390 {
391 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
392 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
393 __cpu_to_le32(2),
394 },
395 {
396 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
397 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
398 __cpu_to_le32(3),
399 },
400 {
401 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
402 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
403 __cpu_to_le32(2),
404 },
405 {
406 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
407 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
408 __cpu_to_le32(3),
409 },
410 {
411 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
412 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
413 __cpu_to_le32(2),
414 },
415 {
416 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
417 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
418 __cpu_to_le32(0),
419 },
420 {
421 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
422 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
423 __cpu_to_le32(2),
424 },
425 { /* not used */
426 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
427 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
428 __cpu_to_le32(0),
429 },
430 { /* not used */
431 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
432 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
433 __cpu_to_le32(2),
434 },
435 {
436 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
437 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
438 __cpu_to_le32(4),
439 },
440 {
441 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
442 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
443 __cpu_to_le32(1),
444 },
445 { /* not used */
446 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
447 __cpu_to_le32(PIPEDIR_OUT),
448 __cpu_to_le32(5),
449 },
450 { /* in = DL = target -> host */
451 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG),
452 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
453 __cpu_to_le32(9),
454 },
455 { /* in = DL = target -> host */
456 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG),
457 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
458 __cpu_to_le32(10),
459 },
460 { /* in = DL = target -> host pktlog */
461 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG),
462 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
463 __cpu_to_le32(11),
464 },
465 /* (Additions here) */
466
467 { /* must be last */
468 __cpu_to_le32(0),
469 __cpu_to_le32(0),
470 __cpu_to_le32(0),
471 },
472 };
473
ath10k_snoc_write32(struct ath10k * ar,u32 offset,u32 value)474 static void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value)
475 {
476 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
477
478 iowrite32(value, ar_snoc->mem + offset);
479 }
480
ath10k_snoc_read32(struct ath10k * ar,u32 offset)481 static u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset)
482 {
483 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
484 u32 val;
485
486 val = ioread32(ar_snoc->mem + offset);
487
488 return val;
489 }
490
__ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe * pipe)491 static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe)
492 {
493 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
494 struct ath10k *ar = pipe->hif_ce_state;
495 struct ath10k_ce *ce = ath10k_ce_priv(ar);
496 struct sk_buff *skb;
497 dma_addr_t paddr;
498 int ret;
499
500 skb = dev_alloc_skb(pipe->buf_sz);
501 if (!skb)
502 return -ENOMEM;
503
504 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
505
506 paddr = dma_map_single(ar->dev, skb->data,
507 skb->len + skb_tailroom(skb),
508 DMA_FROM_DEVICE);
509 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
510 ath10k_warn(ar, "failed to dma map snoc rx buf\n");
511 dev_kfree_skb_any(skb);
512 return -EIO;
513 }
514
515 ATH10K_SKB_RXCB(skb)->paddr = paddr;
516
517 spin_lock_bh(&ce->ce_lock);
518 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
519 spin_unlock_bh(&ce->ce_lock);
520 if (ret) {
521 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
522 DMA_FROM_DEVICE);
523 dev_kfree_skb_any(skb);
524 return ret;
525 }
526
527 return 0;
528 }
529
ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe * pipe)530 static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe)
531 {
532 struct ath10k *ar = pipe->hif_ce_state;
533 struct ath10k_ce *ce = ath10k_ce_priv(ar);
534 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
535 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
536 int ret, num;
537
538 if (pipe->buf_sz == 0)
539 return;
540
541 if (!ce_pipe->dest_ring)
542 return;
543
544 spin_lock_bh(&ce->ce_lock);
545 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
546 spin_unlock_bh(&ce->ce_lock);
547 while (num--) {
548 ret = __ath10k_snoc_rx_post_buf(pipe);
549 if (ret) {
550 if (ret == -ENOSPC)
551 break;
552 ath10k_warn(ar, "failed to post rx buf: %d\n", ret);
553 mod_timer(&ar_snoc->rx_post_retry, jiffies +
554 ATH10K_SNOC_RX_POST_RETRY_MS);
555 break;
556 }
557 }
558 }
559
ath10k_snoc_rx_post(struct ath10k * ar)560 static void ath10k_snoc_rx_post(struct ath10k *ar)
561 {
562 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
563 int i;
564
565 for (i = 0; i < CE_COUNT; i++)
566 ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]);
567 }
568
ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe * ce_state,void (* callback)(struct ath10k * ar,struct sk_buff * skb))569 static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state,
570 void (*callback)(struct ath10k *ar,
571 struct sk_buff *skb))
572 {
573 struct ath10k *ar = ce_state->ar;
574 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
575 struct ath10k_snoc_pipe *pipe_info = &ar_snoc->pipe_info[ce_state->id];
576 struct sk_buff *skb;
577 struct sk_buff_head list;
578 void *transfer_context;
579 unsigned int nbytes, max_nbytes;
580
581 __skb_queue_head_init(&list);
582 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
583 &nbytes) == 0) {
584 skb = transfer_context;
585 max_nbytes = skb->len + skb_tailroom(skb);
586 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
587 max_nbytes, DMA_FROM_DEVICE);
588
589 if (unlikely(max_nbytes < nbytes)) {
590 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)\n",
591 nbytes, max_nbytes);
592 dev_kfree_skb_any(skb);
593 continue;
594 }
595
596 skb_put(skb, nbytes);
597 __skb_queue_tail(&list, skb);
598 }
599
600 while ((skb = __skb_dequeue(&list))) {
601 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n",
602 ce_state->id, skb->len);
603
604 callback(ar, skb);
605 }
606
607 ath10k_snoc_rx_post_pipe(pipe_info);
608 }
609
ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe * ce_state)610 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
611 {
612 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
613 }
614
ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe * ce_state)615 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
616 {
617 /* CE4 polling needs to be done whenever CE pipe which transports
618 * HTT Rx (target->host) is processed.
619 */
620 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
621
622 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
623 }
624
625 /* Called by lower (CE) layer when data is received from the Target.
626 * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data.
627 */
ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe * ce_state)628 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
629 {
630 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
631 }
632
ath10k_snoc_htt_rx_deliver(struct ath10k * ar,struct sk_buff * skb)633 static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
634 {
635 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
636 ath10k_htt_t2h_msg_handler(ar, skb);
637 }
638
ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe * ce_state)639 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
640 {
641 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
642 ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver);
643 }
644
ath10k_snoc_rx_replenish_retry(struct timer_list * t)645 static void ath10k_snoc_rx_replenish_retry(struct timer_list *t)
646 {
647 struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry);
648 struct ath10k *ar = ar_snoc->ar;
649
650 ath10k_snoc_rx_post(ar);
651 }
652
ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe * ce_state)653 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
654 {
655 struct ath10k *ar = ce_state->ar;
656 struct sk_buff_head list;
657 struct sk_buff *skb;
658
659 __skb_queue_head_init(&list);
660 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
661 if (!skb)
662 continue;
663
664 __skb_queue_tail(&list, skb);
665 }
666
667 while ((skb = __skb_dequeue(&list)))
668 ath10k_htc_tx_completion_handler(ar, skb);
669 }
670
ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe * ce_state)671 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
672 {
673 struct ath10k *ar = ce_state->ar;
674 struct sk_buff *skb;
675
676 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
677 if (!skb)
678 continue;
679
680 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
681 skb->len, DMA_TO_DEVICE);
682 ath10k_htt_hif_tx_complete(ar, skb);
683 }
684 }
685
ath10k_snoc_hif_tx_sg(struct ath10k * ar,u8 pipe_id,struct ath10k_hif_sg_item * items,int n_items)686 static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
687 struct ath10k_hif_sg_item *items, int n_items)
688 {
689 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
690 struct ath10k_ce *ce = ath10k_ce_priv(ar);
691 struct ath10k_snoc_pipe *snoc_pipe;
692 struct ath10k_ce_pipe *ce_pipe;
693 int err, i = 0;
694
695 snoc_pipe = &ar_snoc->pipe_info[pipe_id];
696 ce_pipe = snoc_pipe->ce_hdl;
697 spin_lock_bh(&ce->ce_lock);
698
699 for (i = 0; i < n_items - 1; i++) {
700 ath10k_dbg(ar, ATH10K_DBG_SNOC,
701 "snoc tx item %d paddr %pad len %d n_items %d\n",
702 i, &items[i].paddr, items[i].len, n_items);
703
704 err = ath10k_ce_send_nolock(ce_pipe,
705 items[i].transfer_context,
706 items[i].paddr,
707 items[i].len,
708 items[i].transfer_id,
709 CE_SEND_FLAG_GATHER);
710 if (err)
711 goto err;
712 }
713
714 ath10k_dbg(ar, ATH10K_DBG_SNOC,
715 "snoc tx item %d paddr %pad len %d n_items %d\n",
716 i, &items[i].paddr, items[i].len, n_items);
717
718 err = ath10k_ce_send_nolock(ce_pipe,
719 items[i].transfer_context,
720 items[i].paddr,
721 items[i].len,
722 items[i].transfer_id,
723 0);
724 if (err)
725 goto err;
726
727 spin_unlock_bh(&ce->ce_lock);
728
729 return 0;
730
731 err:
732 for (; i > 0; i--)
733 __ath10k_ce_send_revert(ce_pipe);
734
735 spin_unlock_bh(&ce->ce_lock);
736 return err;
737 }
738
ath10k_snoc_hif_get_target_info(struct ath10k * ar,struct bmi_target_info * target_info)739 static int ath10k_snoc_hif_get_target_info(struct ath10k *ar,
740 struct bmi_target_info *target_info)
741 {
742 target_info->version = ATH10K_HW_WCN3990;
743 target_info->type = ATH10K_HW_WCN3990;
744
745 return 0;
746 }
747
ath10k_snoc_hif_get_free_queue_number(struct ath10k * ar,u8 pipe)748 static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
749 {
750 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
751
752 ath10k_dbg(ar, ATH10K_DBG_SNOC, "hif get free queue number\n");
753
754 return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl);
755 }
756
ath10k_snoc_hif_send_complete_check(struct ath10k * ar,u8 pipe,int force)757 static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe,
758 int force)
759 {
760 int resources;
761
762 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif send complete check\n");
763
764 if (!force) {
765 resources = ath10k_snoc_hif_get_free_queue_number(ar, pipe);
766
767 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
768 return;
769 }
770 ath10k_ce_per_engine_service(ar, pipe);
771 }
772
ath10k_snoc_hif_map_service_to_pipe(struct ath10k * ar,u16 service_id,u8 * ul_pipe,u8 * dl_pipe)773 static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar,
774 u16 service_id,
775 u8 *ul_pipe, u8 *dl_pipe)
776 {
777 const struct ce_service_to_pipe *entry;
778 bool ul_set = false, dl_set = false;
779 int i;
780
781 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif map service\n");
782
783 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
784 entry = &target_service_to_ce_map_wlan[i];
785
786 if (__le32_to_cpu(entry->service_id) != service_id)
787 continue;
788
789 switch (__le32_to_cpu(entry->pipedir)) {
790 case PIPEDIR_NONE:
791 break;
792 case PIPEDIR_IN:
793 WARN_ON(dl_set);
794 *dl_pipe = __le32_to_cpu(entry->pipenum);
795 dl_set = true;
796 break;
797 case PIPEDIR_OUT:
798 WARN_ON(ul_set);
799 *ul_pipe = __le32_to_cpu(entry->pipenum);
800 ul_set = true;
801 break;
802 case PIPEDIR_INOUT:
803 WARN_ON(dl_set);
804 WARN_ON(ul_set);
805 *dl_pipe = __le32_to_cpu(entry->pipenum);
806 *ul_pipe = __le32_to_cpu(entry->pipenum);
807 dl_set = true;
808 ul_set = true;
809 break;
810 }
811 }
812
813 if (!ul_set || !dl_set)
814 return -ENOENT;
815
816 return 0;
817 }
818
ath10k_snoc_hif_get_default_pipe(struct ath10k * ar,u8 * ul_pipe,u8 * dl_pipe)819 static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar,
820 u8 *ul_pipe, u8 *dl_pipe)
821 {
822 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif get default pipe\n");
823
824 (void)ath10k_snoc_hif_map_service_to_pipe(ar,
825 ATH10K_HTC_SVC_ID_RSVD_CTRL,
826 ul_pipe, dl_pipe);
827 }
828
ath10k_snoc_irq_disable(struct ath10k * ar)829 static inline void ath10k_snoc_irq_disable(struct ath10k *ar)
830 {
831 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
832 int id;
833
834 for (id = 0; id < CE_COUNT_MAX; id++)
835 disable_irq(ar_snoc->ce_irqs[id].irq_line);
836 }
837
ath10k_snoc_irq_enable(struct ath10k * ar)838 static inline void ath10k_snoc_irq_enable(struct ath10k *ar)
839 {
840 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
841 int id;
842
843 for (id = 0; id < CE_COUNT_MAX; id++)
844 enable_irq(ar_snoc->ce_irqs[id].irq_line);
845 }
846
ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe * snoc_pipe)847 static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
848 {
849 struct ath10k_ce_pipe *ce_pipe;
850 struct ath10k_ce_ring *ce_ring;
851 struct sk_buff *skb;
852 struct ath10k *ar;
853 int i;
854
855 ar = snoc_pipe->hif_ce_state;
856 ce_pipe = snoc_pipe->ce_hdl;
857 ce_ring = ce_pipe->dest_ring;
858
859 if (!ce_ring)
860 return;
861
862 if (!snoc_pipe->buf_sz)
863 return;
864
865 for (i = 0; i < ce_ring->nentries; i++) {
866 skb = ce_ring->per_transfer_context[i];
867 if (!skb)
868 continue;
869
870 ce_ring->per_transfer_context[i] = NULL;
871
872 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
873 skb->len + skb_tailroom(skb),
874 DMA_FROM_DEVICE);
875 dev_kfree_skb_any(skb);
876 }
877 }
878
ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe * snoc_pipe)879 static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
880 {
881 struct ath10k_ce_pipe *ce_pipe;
882 struct ath10k_ce_ring *ce_ring;
883 struct sk_buff *skb;
884 struct ath10k *ar;
885 int i;
886
887 ar = snoc_pipe->hif_ce_state;
888 ce_pipe = snoc_pipe->ce_hdl;
889 ce_ring = ce_pipe->src_ring;
890
891 if (!ce_ring)
892 return;
893
894 if (!snoc_pipe->buf_sz)
895 return;
896
897 for (i = 0; i < ce_ring->nentries; i++) {
898 skb = ce_ring->per_transfer_context[i];
899 if (!skb)
900 continue;
901
902 ce_ring->per_transfer_context[i] = NULL;
903
904 ath10k_htc_tx_completion_handler(ar, skb);
905 }
906 }
907
ath10k_snoc_buffer_cleanup(struct ath10k * ar)908 static void ath10k_snoc_buffer_cleanup(struct ath10k *ar)
909 {
910 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
911 struct ath10k_snoc_pipe *pipe_info;
912 int pipe_num;
913
914 del_timer_sync(&ar_snoc->rx_post_retry);
915 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
916 pipe_info = &ar_snoc->pipe_info[pipe_num];
917 ath10k_snoc_rx_pipe_cleanup(pipe_info);
918 ath10k_snoc_tx_pipe_cleanup(pipe_info);
919 }
920 }
921
ath10k_snoc_hif_stop(struct ath10k * ar)922 static void ath10k_snoc_hif_stop(struct ath10k *ar)
923 {
924 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags))
925 ath10k_snoc_irq_disable(ar);
926
927 ath10k_core_napi_sync_disable(ar);
928 ath10k_snoc_buffer_cleanup(ar);
929 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
930 }
931
ath10k_snoc_hif_start(struct ath10k * ar)932 static int ath10k_snoc_hif_start(struct ath10k *ar)
933 {
934 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
935
936 bitmap_clear(ar_snoc->pending_ce_irqs, 0, CE_COUNT_MAX);
937
938 dev_set_threaded(&ar->napi_dev, true);
939 ath10k_core_napi_enable(ar);
940 /* IRQs are left enabled when we restart due to a firmware crash */
941 if (!test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
942 ath10k_snoc_irq_enable(ar);
943 ath10k_snoc_rx_post(ar);
944
945 clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
946
947 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
948
949 return 0;
950 }
951
ath10k_snoc_init_pipes(struct ath10k * ar)952 static int ath10k_snoc_init_pipes(struct ath10k *ar)
953 {
954 int i, ret;
955
956 for (i = 0; i < CE_COUNT; i++) {
957 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
958 if (ret) {
959 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
960 i, ret);
961 return ret;
962 }
963 }
964
965 return 0;
966 }
967
ath10k_snoc_wlan_enable(struct ath10k * ar,enum ath10k_firmware_mode fw_mode)968 static int ath10k_snoc_wlan_enable(struct ath10k *ar,
969 enum ath10k_firmware_mode fw_mode)
970 {
971 struct ath10k_tgt_pipe_cfg tgt_cfg[CE_COUNT_MAX];
972 struct ath10k_qmi_wlan_enable_cfg cfg;
973 enum wlfw_driver_mode_enum_v01 mode;
974 int pipe_num;
975
976 for (pipe_num = 0; pipe_num < CE_COUNT_MAX; pipe_num++) {
977 tgt_cfg[pipe_num].pipe_num =
978 target_ce_config_wlan[pipe_num].pipenum;
979 tgt_cfg[pipe_num].pipe_dir =
980 target_ce_config_wlan[pipe_num].pipedir;
981 tgt_cfg[pipe_num].nentries =
982 target_ce_config_wlan[pipe_num].nentries;
983 tgt_cfg[pipe_num].nbytes_max =
984 target_ce_config_wlan[pipe_num].nbytes_max;
985 tgt_cfg[pipe_num].flags =
986 target_ce_config_wlan[pipe_num].flags;
987 tgt_cfg[pipe_num].reserved = 0;
988 }
989
990 cfg.num_ce_tgt_cfg = sizeof(target_ce_config_wlan) /
991 sizeof(struct ath10k_tgt_pipe_cfg);
992 cfg.ce_tgt_cfg = (struct ath10k_tgt_pipe_cfg *)
993 &tgt_cfg;
994 cfg.num_ce_svc_pipe_cfg = sizeof(target_service_to_ce_map_wlan) /
995 sizeof(struct ath10k_svc_pipe_cfg);
996 cfg.ce_svc_cfg = (struct ath10k_svc_pipe_cfg *)
997 &target_service_to_ce_map_wlan;
998 cfg.num_shadow_reg_cfg = ARRAY_SIZE(target_shadow_reg_cfg_map);
999 cfg.shadow_reg_cfg = (struct ath10k_shadow_reg_cfg *)
1000 &target_shadow_reg_cfg_map;
1001
1002 switch (fw_mode) {
1003 case ATH10K_FIRMWARE_MODE_NORMAL:
1004 mode = QMI_WLFW_MISSION_V01;
1005 break;
1006 case ATH10K_FIRMWARE_MODE_UTF:
1007 mode = QMI_WLFW_FTM_V01;
1008 break;
1009 default:
1010 ath10k_err(ar, "invalid firmware mode %d\n", fw_mode);
1011 return -EINVAL;
1012 }
1013
1014 return ath10k_qmi_wlan_enable(ar, &cfg, mode,
1015 NULL);
1016 }
1017
ath10k_hw_power_on(struct ath10k * ar)1018 static int ath10k_hw_power_on(struct ath10k *ar)
1019 {
1020 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1021 int ret;
1022
1023 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n");
1024
1025 ret = regulator_bulk_enable(ar_snoc->num_vregs, ar_snoc->vregs);
1026 if (ret)
1027 return ret;
1028
1029 ret = clk_bulk_prepare_enable(ar_snoc->num_clks, ar_snoc->clks);
1030 if (ret)
1031 goto vreg_off;
1032
1033 return ret;
1034
1035 vreg_off:
1036 regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1037 return ret;
1038 }
1039
ath10k_hw_power_off(struct ath10k * ar)1040 static int ath10k_hw_power_off(struct ath10k *ar)
1041 {
1042 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1043
1044 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n");
1045
1046 clk_bulk_disable_unprepare(ar_snoc->num_clks, ar_snoc->clks);
1047
1048 return regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1049 }
1050
ath10k_snoc_wlan_disable(struct ath10k * ar)1051 static void ath10k_snoc_wlan_disable(struct ath10k *ar)
1052 {
1053 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1054
1055 /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY
1056 * flags are not set, it means that the driver has restarted
1057 * due to a crash inject via debugfs. In this case, the driver
1058 * needs to restart the firmware and hence send qmi wlan disable,
1059 * during the driver restart sequence.
1060 */
1061 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags) ||
1062 !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1063 ath10k_qmi_wlan_disable(ar);
1064 }
1065
ath10k_snoc_hif_power_down(struct ath10k * ar)1066 static void ath10k_snoc_hif_power_down(struct ath10k *ar)
1067 {
1068 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
1069
1070 ath10k_snoc_wlan_disable(ar);
1071 ath10k_ce_free_rri(ar);
1072 ath10k_hw_power_off(ar);
1073 }
1074
ath10k_snoc_hif_power_up(struct ath10k * ar,enum ath10k_firmware_mode fw_mode)1075 static int ath10k_snoc_hif_power_up(struct ath10k *ar,
1076 enum ath10k_firmware_mode fw_mode)
1077 {
1078 int ret;
1079
1080 ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 driver state = %d\n",
1081 __func__, ar->state);
1082
1083 ret = ath10k_hw_power_on(ar);
1084 if (ret) {
1085 ath10k_err(ar, "failed to power on device: %d\n", ret);
1086 return ret;
1087 }
1088
1089 ret = ath10k_snoc_wlan_enable(ar, fw_mode);
1090 if (ret) {
1091 ath10k_err(ar, "failed to enable wcn3990: %d\n", ret);
1092 goto err_hw_power_off;
1093 }
1094
1095 ath10k_ce_alloc_rri(ar);
1096
1097 ret = ath10k_snoc_init_pipes(ar);
1098 if (ret) {
1099 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
1100 goto err_free_rri;
1101 }
1102
1103 ath10k_ce_enable_interrupts(ar);
1104
1105 return 0;
1106
1107 err_free_rri:
1108 ath10k_ce_free_rri(ar);
1109 ath10k_snoc_wlan_disable(ar);
1110
1111 err_hw_power_off:
1112 ath10k_hw_power_off(ar);
1113
1114 return ret;
1115 }
1116
ath10k_snoc_hif_set_target_log_mode(struct ath10k * ar,u8 fw_log_mode)1117 static int ath10k_snoc_hif_set_target_log_mode(struct ath10k *ar,
1118 u8 fw_log_mode)
1119 {
1120 u8 fw_dbg_mode;
1121
1122 if (fw_log_mode)
1123 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_CE;
1124 else
1125 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_DIAG;
1126
1127 return ath10k_qmi_set_fw_log_mode(ar, fw_dbg_mode);
1128 }
1129
1130 #ifdef CONFIG_PM
ath10k_snoc_hif_suspend(struct ath10k * ar)1131 static int ath10k_snoc_hif_suspend(struct ath10k *ar)
1132 {
1133 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1134 int ret;
1135
1136 if (!device_may_wakeup(ar->dev))
1137 return -EPERM;
1138
1139 ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1140 if (ret) {
1141 ath10k_err(ar, "failed to enable wakeup irq :%d\n", ret);
1142 return ret;
1143 }
1144
1145 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device suspended\n");
1146
1147 return ret;
1148 }
1149
ath10k_snoc_hif_resume(struct ath10k * ar)1150 static int ath10k_snoc_hif_resume(struct ath10k *ar)
1151 {
1152 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1153 int ret;
1154
1155 if (!device_may_wakeup(ar->dev))
1156 return -EPERM;
1157
1158 ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1159 if (ret) {
1160 ath10k_err(ar, "failed to disable wakeup irq: %d\n", ret);
1161 return ret;
1162 }
1163
1164 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device resumed\n");
1165
1166 return ret;
1167 }
1168 #endif
1169
1170 static const struct ath10k_hif_ops ath10k_snoc_hif_ops = {
1171 .read32 = ath10k_snoc_read32,
1172 .write32 = ath10k_snoc_write32,
1173 .start = ath10k_snoc_hif_start,
1174 .stop = ath10k_snoc_hif_stop,
1175 .map_service_to_pipe = ath10k_snoc_hif_map_service_to_pipe,
1176 .get_default_pipe = ath10k_snoc_hif_get_default_pipe,
1177 .power_up = ath10k_snoc_hif_power_up,
1178 .power_down = ath10k_snoc_hif_power_down,
1179 .tx_sg = ath10k_snoc_hif_tx_sg,
1180 .send_complete_check = ath10k_snoc_hif_send_complete_check,
1181 .get_free_queue_number = ath10k_snoc_hif_get_free_queue_number,
1182 .get_target_info = ath10k_snoc_hif_get_target_info,
1183 .set_target_log_mode = ath10k_snoc_hif_set_target_log_mode,
1184
1185 #ifdef CONFIG_PM
1186 .suspend = ath10k_snoc_hif_suspend,
1187 .resume = ath10k_snoc_hif_resume,
1188 #endif
1189 };
1190
1191 static const struct ath10k_bus_ops ath10k_snoc_bus_ops = {
1192 .read32 = ath10k_snoc_read32,
1193 .write32 = ath10k_snoc_write32,
1194 };
1195
ath10k_snoc_get_ce_id_from_irq(struct ath10k * ar,int irq)1196 static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq)
1197 {
1198 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1199 int i;
1200
1201 for (i = 0; i < CE_COUNT_MAX; i++) {
1202 if (ar_snoc->ce_irqs[i].irq_line == irq)
1203 return i;
1204 }
1205 ath10k_err(ar, "No matching CE id for irq %d\n", irq);
1206
1207 return -EINVAL;
1208 }
1209
ath10k_snoc_per_engine_handler(int irq,void * arg)1210 static irqreturn_t ath10k_snoc_per_engine_handler(int irq, void *arg)
1211 {
1212 struct ath10k *ar = arg;
1213 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1214 int ce_id = ath10k_snoc_get_ce_id_from_irq(ar, irq);
1215
1216 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) {
1217 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
1218 ce_id);
1219 return IRQ_HANDLED;
1220 }
1221
1222 ath10k_ce_disable_interrupt(ar, ce_id);
1223 set_bit(ce_id, ar_snoc->pending_ce_irqs);
1224
1225 napi_schedule(&ar->napi);
1226
1227 return IRQ_HANDLED;
1228 }
1229
ath10k_snoc_napi_poll(struct napi_struct * ctx,int budget)1230 static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget)
1231 {
1232 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
1233 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1234 int done = 0;
1235 int ce_id;
1236
1237 if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) {
1238 napi_complete(ctx);
1239 return done;
1240 }
1241
1242 for (ce_id = 0; ce_id < CE_COUNT; ce_id++)
1243 if (test_and_clear_bit(ce_id, ar_snoc->pending_ce_irqs)) {
1244 ath10k_ce_per_engine_service(ar, ce_id);
1245 ath10k_ce_enable_interrupt(ar, ce_id);
1246 }
1247
1248 done = ath10k_htt_txrx_compl_task(ar, budget);
1249
1250 if (done < budget)
1251 napi_complete(ctx);
1252
1253 return done;
1254 }
1255
ath10k_snoc_init_napi(struct ath10k * ar)1256 static void ath10k_snoc_init_napi(struct ath10k *ar)
1257 {
1258 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll);
1259 }
1260
ath10k_snoc_request_irq(struct ath10k * ar)1261 static int ath10k_snoc_request_irq(struct ath10k *ar)
1262 {
1263 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1264 int ret, id;
1265
1266 for (id = 0; id < CE_COUNT_MAX; id++) {
1267 ret = request_irq(ar_snoc->ce_irqs[id].irq_line,
1268 ath10k_snoc_per_engine_handler,
1269 IRQF_NO_AUTOEN, ce_name[id], ar);
1270 if (ret) {
1271 ath10k_err(ar,
1272 "failed to register IRQ handler for CE %d: %d\n",
1273 id, ret);
1274 goto err_irq;
1275 }
1276 }
1277
1278 return 0;
1279
1280 err_irq:
1281 for (id -= 1; id >= 0; id--)
1282 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1283
1284 return ret;
1285 }
1286
ath10k_snoc_free_irq(struct ath10k * ar)1287 static void ath10k_snoc_free_irq(struct ath10k *ar)
1288 {
1289 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1290 int id;
1291
1292 for (id = 0; id < CE_COUNT_MAX; id++)
1293 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1294 }
1295
ath10k_snoc_resource_init(struct ath10k * ar)1296 static int ath10k_snoc_resource_init(struct ath10k *ar)
1297 {
1298 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1299 struct platform_device *pdev;
1300 struct resource *res;
1301 int i, ret = 0;
1302
1303 pdev = ar_snoc->dev;
1304 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase");
1305 if (!res) {
1306 ath10k_err(ar, "Memory base not found in DT\n");
1307 return -EINVAL;
1308 }
1309
1310 ar_snoc->mem_pa = res->start;
1311 ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa,
1312 resource_size(res));
1313 if (!ar_snoc->mem) {
1314 ath10k_err(ar, "Memory base ioremap failed with physical address %pa\n",
1315 &ar_snoc->mem_pa);
1316 return -EINVAL;
1317 }
1318
1319 for (i = 0; i < CE_COUNT; i++) {
1320 ret = platform_get_irq(ar_snoc->dev, i);
1321 if (ret < 0)
1322 return ret;
1323 ar_snoc->ce_irqs[i].irq_line = ret;
1324 }
1325
1326 ret = device_property_read_u32(&pdev->dev, "qcom,xo-cal-data",
1327 &ar_snoc->xo_cal_data);
1328 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc xo-cal-data return %d\n", ret);
1329 if (ret == 0) {
1330 ar_snoc->xo_cal_supported = true;
1331 ath10k_dbg(ar, ATH10K_DBG_SNOC, "xo cal data %x\n",
1332 ar_snoc->xo_cal_data);
1333 }
1334
1335 return 0;
1336 }
1337
ath10k_snoc_quirks_init(struct ath10k * ar)1338 static void ath10k_snoc_quirks_init(struct ath10k *ar)
1339 {
1340 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1341 struct device *dev = &ar_snoc->dev->dev;
1342
1343 if (of_property_read_bool(dev->of_node, "qcom,snoc-host-cap-8bit-quirk"))
1344 set_bit(ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK, &ar_snoc->flags);
1345 }
1346
ath10k_snoc_fw_indication(struct ath10k * ar,u64 type)1347 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type)
1348 {
1349 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1350 struct ath10k_bus_params bus_params = {};
1351 int ret;
1352
1353 if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags))
1354 return 0;
1355
1356 switch (type) {
1357 case ATH10K_QMI_EVENT_FW_READY_IND:
1358 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) {
1359 ath10k_core_start_recovery(ar);
1360 break;
1361 }
1362
1363 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
1364 bus_params.chip_id = ar_snoc->target_info.soc_version;
1365 ret = ath10k_core_register(ar, &bus_params);
1366 if (ret) {
1367 ath10k_err(ar, "Failed to register driver core: %d\n",
1368 ret);
1369 return ret;
1370 }
1371 set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags);
1372 break;
1373 case ATH10K_QMI_EVENT_FW_DOWN_IND:
1374 set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
1375 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
1376 break;
1377 default:
1378 ath10k_err(ar, "invalid fw indication: %llx\n", type);
1379 return -EINVAL;
1380 }
1381
1382 return 0;
1383 }
1384
ath10k_snoc_setup_resource(struct ath10k * ar)1385 static int ath10k_snoc_setup_resource(struct ath10k *ar)
1386 {
1387 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1388 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1389 struct ath10k_snoc_pipe *pipe;
1390 int i, ret;
1391
1392 timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0);
1393 spin_lock_init(&ce->ce_lock);
1394 for (i = 0; i < CE_COUNT; i++) {
1395 pipe = &ar_snoc->pipe_info[i];
1396 pipe->ce_hdl = &ce->ce_states[i];
1397 pipe->pipe_num = i;
1398 pipe->hif_ce_state = ar;
1399
1400 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1401 if (ret) {
1402 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
1403 i, ret);
1404 return ret;
1405 }
1406
1407 pipe->buf_sz = host_ce_config_wlan[i].src_sz_max;
1408 }
1409 ath10k_snoc_init_napi(ar);
1410
1411 return 0;
1412 }
1413
ath10k_snoc_release_resource(struct ath10k * ar)1414 static void ath10k_snoc_release_resource(struct ath10k *ar)
1415 {
1416 int i;
1417
1418 netif_napi_del(&ar->napi);
1419 for (i = 0; i < CE_COUNT; i++)
1420 ath10k_ce_free_pipe(ar, i);
1421 }
1422
ath10k_msa_dump_memory(struct ath10k * ar,struct ath10k_fw_crash_data * crash_data)1423 static void ath10k_msa_dump_memory(struct ath10k *ar,
1424 struct ath10k_fw_crash_data *crash_data)
1425 {
1426 const struct ath10k_hw_mem_layout *mem_layout;
1427 const struct ath10k_mem_region *current_region;
1428 struct ath10k_dump_ram_data_hdr *hdr;
1429 size_t buf_len;
1430 u8 *buf;
1431
1432 if (!crash_data || !crash_data->ramdump_buf)
1433 return;
1434
1435 mem_layout = ath10k_coredump_get_mem_layout(ar);
1436 if (!mem_layout)
1437 return;
1438
1439 current_region = &mem_layout->region_table.regions[0];
1440
1441 buf = crash_data->ramdump_buf;
1442 buf_len = crash_data->ramdump_buf_len;
1443 memset(buf, 0, buf_len);
1444
1445 /* Reserve space for the header. */
1446 hdr = (void *)buf;
1447 buf += sizeof(*hdr);
1448 buf_len -= sizeof(*hdr);
1449
1450 hdr->region_type = cpu_to_le32(current_region->type);
1451 hdr->start = cpu_to_le32((unsigned long)ar->msa.vaddr);
1452 hdr->length = cpu_to_le32(ar->msa.mem_size);
1453
1454 if (current_region->len < ar->msa.mem_size) {
1455 memcpy(buf, ar->msa.vaddr, current_region->len);
1456 ath10k_warn(ar, "msa dump length is less than msa size %x, %x\n",
1457 current_region->len, ar->msa.mem_size);
1458 } else {
1459 memcpy(buf, ar->msa.vaddr, ar->msa.mem_size);
1460 }
1461 }
1462
ath10k_snoc_fw_crashed_dump(struct ath10k * ar)1463 void ath10k_snoc_fw_crashed_dump(struct ath10k *ar)
1464 {
1465 struct ath10k_fw_crash_data *crash_data;
1466 char guid[UUID_STRING_LEN + 1];
1467
1468 mutex_lock(&ar->dump_mutex);
1469
1470 spin_lock_bh(&ar->data_lock);
1471 ar->stats.fw_crash_counter++;
1472 spin_unlock_bh(&ar->data_lock);
1473
1474 crash_data = ath10k_coredump_new(ar);
1475
1476 if (crash_data)
1477 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1478 else
1479 scnprintf(guid, sizeof(guid), "n/a");
1480
1481 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1482 ath10k_print_driver_info(ar);
1483 ath10k_msa_dump_memory(ar, crash_data);
1484 mutex_unlock(&ar->dump_mutex);
1485 }
1486
ath10k_snoc_modem_notify(struct notifier_block * nb,unsigned long action,void * data)1487 static int ath10k_snoc_modem_notify(struct notifier_block *nb, unsigned long action,
1488 void *data)
1489 {
1490 struct ath10k_snoc *ar_snoc = container_of(nb, struct ath10k_snoc, nb);
1491 struct ath10k *ar = ar_snoc->ar;
1492 struct qcom_ssr_notify_data *notify_data = data;
1493
1494 switch (action) {
1495 case QCOM_SSR_BEFORE_POWERUP:
1496 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem starting event\n");
1497 clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1498 break;
1499
1500 case QCOM_SSR_AFTER_POWERUP:
1501 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem running event\n");
1502 break;
1503
1504 case QCOM_SSR_BEFORE_SHUTDOWN:
1505 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem %s event\n",
1506 notify_data->crashed ? "crashed" : "stopping");
1507 if (!notify_data->crashed)
1508 set_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1509 else
1510 clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1511 break;
1512
1513 case QCOM_SSR_AFTER_SHUTDOWN:
1514 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem offline event\n");
1515 break;
1516
1517 default:
1518 ath10k_err(ar, "received unrecognized event %lu\n", action);
1519 break;
1520 }
1521
1522 return NOTIFY_OK;
1523 }
1524
ath10k_modem_init(struct ath10k * ar)1525 static int ath10k_modem_init(struct ath10k *ar)
1526 {
1527 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1528 void *notifier;
1529 int ret;
1530
1531 ar_snoc->nb.notifier_call = ath10k_snoc_modem_notify;
1532
1533 notifier = qcom_register_ssr_notifier("mpss", &ar_snoc->nb);
1534 if (IS_ERR(notifier)) {
1535 ret = PTR_ERR(notifier);
1536 ath10k_err(ar, "failed to initialize modem notifier: %d\n", ret);
1537 return ret;
1538 }
1539
1540 ar_snoc->notifier = notifier;
1541
1542 return 0;
1543 }
1544
ath10k_modem_deinit(struct ath10k * ar)1545 static void ath10k_modem_deinit(struct ath10k *ar)
1546 {
1547 int ret;
1548 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1549
1550 ret = qcom_unregister_ssr_notifier(ar_snoc->notifier, &ar_snoc->nb);
1551 if (ret)
1552 ath10k_err(ar, "error %d unregistering notifier\n", ret);
1553 }
1554
ath10k_setup_msa_resources(struct ath10k * ar,u32 msa_size)1555 static int ath10k_setup_msa_resources(struct ath10k *ar, u32 msa_size)
1556 {
1557 struct device *dev = ar->dev;
1558 struct device_node *node;
1559 struct resource r;
1560 int ret;
1561
1562 node = of_parse_phandle(dev->of_node, "memory-region", 0);
1563 if (node) {
1564 ret = of_address_to_resource(node, 0, &r);
1565 of_node_put(node);
1566 if (ret) {
1567 dev_err(dev, "failed to resolve msa fixed region\n");
1568 return ret;
1569 }
1570
1571 ar->msa.paddr = r.start;
1572 ar->msa.mem_size = resource_size(&r);
1573 ar->msa.vaddr = devm_memremap(dev, ar->msa.paddr,
1574 ar->msa.mem_size,
1575 MEMREMAP_WT);
1576 if (IS_ERR(ar->msa.vaddr)) {
1577 dev_err(dev, "failed to map memory region: %pa\n",
1578 &r.start);
1579 return PTR_ERR(ar->msa.vaddr);
1580 }
1581 } else {
1582 ar->msa.vaddr = dmam_alloc_coherent(dev, msa_size,
1583 &ar->msa.paddr,
1584 GFP_KERNEL);
1585 if (!ar->msa.vaddr) {
1586 ath10k_err(ar, "failed to allocate dma memory for msa region\n");
1587 return -ENOMEM;
1588 }
1589 ar->msa.mem_size = msa_size;
1590 }
1591
1592 ath10k_dbg(ar, ATH10K_DBG_QMI, "qmi msa.paddr: %pad , msa.vaddr: 0x%p\n",
1593 &ar->msa.paddr,
1594 ar->msa.vaddr);
1595
1596 return 0;
1597 }
1598
ath10k_fw_init(struct ath10k * ar)1599 static int ath10k_fw_init(struct ath10k *ar)
1600 {
1601 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1602 struct device *host_dev = &ar_snoc->dev->dev;
1603 struct platform_device_info info;
1604 struct iommu_domain *iommu_dom;
1605 struct platform_device *pdev;
1606 struct device_node *node;
1607 int ret;
1608
1609 node = of_get_child_by_name(host_dev->of_node, "wifi-firmware");
1610 if (!node) {
1611 ar_snoc->use_tz = true;
1612 return 0;
1613 }
1614
1615 memset(&info, 0, sizeof(info));
1616 info.fwnode = &node->fwnode;
1617 info.parent = host_dev;
1618 info.name = node->name;
1619 info.dma_mask = DMA_BIT_MASK(32);
1620
1621 pdev = platform_device_register_full(&info);
1622 if (IS_ERR(pdev)) {
1623 of_node_put(node);
1624 return PTR_ERR(pdev);
1625 }
1626
1627 pdev->dev.of_node = node;
1628
1629 ret = of_dma_configure(&pdev->dev, node, true);
1630 if (ret) {
1631 ath10k_err(ar, "dma configure fail: %d\n", ret);
1632 goto err_unregister;
1633 }
1634
1635 ar_snoc->fw.dev = &pdev->dev;
1636
1637 iommu_dom = iommu_domain_alloc(&platform_bus_type);
1638 if (!iommu_dom) {
1639 ath10k_err(ar, "failed to allocate iommu domain\n");
1640 ret = -ENOMEM;
1641 goto err_unregister;
1642 }
1643
1644 ret = iommu_attach_device(iommu_dom, ar_snoc->fw.dev);
1645 if (ret) {
1646 ath10k_err(ar, "could not attach device: %d\n", ret);
1647 goto err_iommu_free;
1648 }
1649
1650 ar_snoc->fw.iommu_domain = iommu_dom;
1651 ar_snoc->fw.fw_start_addr = ar->msa.paddr;
1652
1653 ret = iommu_map(iommu_dom, ar_snoc->fw.fw_start_addr,
1654 ar->msa.paddr, ar->msa.mem_size,
1655 IOMMU_READ | IOMMU_WRITE, GFP_KERNEL);
1656 if (ret) {
1657 ath10k_err(ar, "failed to map firmware region: %d\n", ret);
1658 goto err_iommu_detach;
1659 }
1660
1661 of_node_put(node);
1662
1663 return 0;
1664
1665 err_iommu_detach:
1666 iommu_detach_device(iommu_dom, ar_snoc->fw.dev);
1667
1668 err_iommu_free:
1669 iommu_domain_free(iommu_dom);
1670
1671 err_unregister:
1672 platform_device_unregister(pdev);
1673 of_node_put(node);
1674
1675 return ret;
1676 }
1677
ath10k_fw_deinit(struct ath10k * ar)1678 static int ath10k_fw_deinit(struct ath10k *ar)
1679 {
1680 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1681 const size_t mapped_size = ar_snoc->fw.mapped_mem_size;
1682 struct iommu_domain *iommu;
1683 size_t unmapped_size;
1684
1685 if (ar_snoc->use_tz)
1686 return 0;
1687
1688 iommu = ar_snoc->fw.iommu_domain;
1689
1690 unmapped_size = iommu_unmap(iommu, ar_snoc->fw.fw_start_addr,
1691 mapped_size);
1692 if (unmapped_size != mapped_size)
1693 ath10k_err(ar, "failed to unmap firmware: %zu\n",
1694 unmapped_size);
1695
1696 iommu_detach_device(iommu, ar_snoc->fw.dev);
1697 iommu_domain_free(iommu);
1698
1699 platform_device_unregister(to_platform_device(ar_snoc->fw.dev));
1700
1701 return 0;
1702 }
1703
1704 static const struct of_device_id ath10k_snoc_dt_match[] = {
1705 { .compatible = "qcom,wcn3990-wifi",
1706 .data = &drv_priv,
1707 },
1708 { }
1709 };
1710 MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match);
1711
ath10k_snoc_probe(struct platform_device * pdev)1712 static int ath10k_snoc_probe(struct platform_device *pdev)
1713 {
1714 const struct ath10k_snoc_drv_priv *drv_data;
1715 struct ath10k_snoc *ar_snoc;
1716 struct device *dev;
1717 struct ath10k *ar;
1718 u32 msa_size;
1719 int ret;
1720 u32 i;
1721
1722 dev = &pdev->dev;
1723 drv_data = device_get_match_data(dev);
1724 if (!drv_data) {
1725 dev_err(dev, "failed to find matching device tree id\n");
1726 return -EINVAL;
1727 }
1728
1729 ret = dma_set_mask_and_coherent(dev, drv_data->dma_mask);
1730 if (ret) {
1731 dev_err(dev, "failed to set dma mask: %d\n", ret);
1732 return ret;
1733 }
1734
1735 ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC,
1736 drv_data->hw_rev, &ath10k_snoc_hif_ops);
1737 if (!ar) {
1738 dev_err(dev, "failed to allocate core\n");
1739 return -ENOMEM;
1740 }
1741
1742 ar_snoc = ath10k_snoc_priv(ar);
1743 ar_snoc->dev = pdev;
1744 platform_set_drvdata(pdev, ar);
1745 ar_snoc->ar = ar;
1746 ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops;
1747 ar->ce_priv = &ar_snoc->ce;
1748 msa_size = drv_data->msa_size;
1749
1750 ath10k_snoc_quirks_init(ar);
1751
1752 ret = ath10k_snoc_resource_init(ar);
1753 if (ret) {
1754 ath10k_warn(ar, "failed to initialize resource: %d\n", ret);
1755 goto err_core_destroy;
1756 }
1757
1758 ret = ath10k_snoc_setup_resource(ar);
1759 if (ret) {
1760 ath10k_warn(ar, "failed to setup resource: %d\n", ret);
1761 goto err_core_destroy;
1762 }
1763 ret = ath10k_snoc_request_irq(ar);
1764 if (ret) {
1765 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
1766 goto err_release_resource;
1767 }
1768
1769 ar_snoc->num_vregs = ARRAY_SIZE(ath10k_regulators);
1770 ar_snoc->vregs = devm_kcalloc(&pdev->dev, ar_snoc->num_vregs,
1771 sizeof(*ar_snoc->vregs), GFP_KERNEL);
1772 if (!ar_snoc->vregs) {
1773 ret = -ENOMEM;
1774 goto err_free_irq;
1775 }
1776 for (i = 0; i < ar_snoc->num_vregs; i++)
1777 ar_snoc->vregs[i].supply = ath10k_regulators[i];
1778
1779 ret = devm_regulator_bulk_get(&pdev->dev, ar_snoc->num_vregs,
1780 ar_snoc->vregs);
1781 if (ret < 0)
1782 goto err_free_irq;
1783
1784 ar_snoc->num_clks = ARRAY_SIZE(ath10k_clocks);
1785 ar_snoc->clks = devm_kcalloc(&pdev->dev, ar_snoc->num_clks,
1786 sizeof(*ar_snoc->clks), GFP_KERNEL);
1787 if (!ar_snoc->clks) {
1788 ret = -ENOMEM;
1789 goto err_free_irq;
1790 }
1791
1792 for (i = 0; i < ar_snoc->num_clks; i++)
1793 ar_snoc->clks[i].id = ath10k_clocks[i];
1794
1795 ret = devm_clk_bulk_get_optional(&pdev->dev, ar_snoc->num_clks,
1796 ar_snoc->clks);
1797 if (ret)
1798 goto err_free_irq;
1799
1800 ret = ath10k_setup_msa_resources(ar, msa_size);
1801 if (ret) {
1802 ath10k_warn(ar, "failed to setup msa resources: %d\n", ret);
1803 goto err_free_irq;
1804 }
1805
1806 ret = ath10k_fw_init(ar);
1807 if (ret) {
1808 ath10k_err(ar, "failed to initialize firmware: %d\n", ret);
1809 goto err_free_irq;
1810 }
1811
1812 ret = ath10k_qmi_init(ar, msa_size);
1813 if (ret) {
1814 ath10k_warn(ar, "failed to register wlfw qmi client: %d\n", ret);
1815 goto err_fw_deinit;
1816 }
1817
1818 ret = ath10k_modem_init(ar);
1819 if (ret)
1820 goto err_qmi_deinit;
1821
1822 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc probe\n");
1823
1824 return 0;
1825
1826 err_qmi_deinit:
1827 ath10k_qmi_deinit(ar);
1828
1829 err_fw_deinit:
1830 ath10k_fw_deinit(ar);
1831
1832 err_free_irq:
1833 ath10k_snoc_free_irq(ar);
1834
1835 err_release_resource:
1836 ath10k_snoc_release_resource(ar);
1837
1838 err_core_destroy:
1839 ath10k_core_destroy(ar);
1840
1841 return ret;
1842 }
1843
ath10k_snoc_free_resources(struct ath10k * ar)1844 static int ath10k_snoc_free_resources(struct ath10k *ar)
1845 {
1846 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1847
1848 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc free resources\n");
1849
1850 set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags);
1851
1852 ath10k_core_unregister(ar);
1853 ath10k_fw_deinit(ar);
1854 ath10k_snoc_free_irq(ar);
1855 ath10k_snoc_release_resource(ar);
1856 ath10k_modem_deinit(ar);
1857 ath10k_qmi_deinit(ar);
1858 ath10k_core_destroy(ar);
1859
1860 return 0;
1861 }
1862
ath10k_snoc_remove(struct platform_device * pdev)1863 static void ath10k_snoc_remove(struct platform_device *pdev)
1864 {
1865 struct ath10k *ar = platform_get_drvdata(pdev);
1866 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1867
1868 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc remove\n");
1869
1870 reinit_completion(&ar->driver_recovery);
1871
1872 if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1873 wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ);
1874
1875 ath10k_snoc_free_resources(ar);
1876 }
1877
ath10k_snoc_shutdown(struct platform_device * pdev)1878 static void ath10k_snoc_shutdown(struct platform_device *pdev)
1879 {
1880 struct ath10k *ar = platform_get_drvdata(pdev);
1881
1882 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc shutdown\n");
1883 ath10k_snoc_free_resources(ar);
1884 }
1885
1886 static struct platform_driver ath10k_snoc_driver = {
1887 .probe = ath10k_snoc_probe,
1888 .remove_new = ath10k_snoc_remove,
1889 .shutdown = ath10k_snoc_shutdown,
1890 .driver = {
1891 .name = "ath10k_snoc",
1892 .of_match_table = ath10k_snoc_dt_match,
1893 },
1894 };
1895 module_platform_driver(ath10k_snoc_driver);
1896
1897 MODULE_AUTHOR("Qualcomm");
1898 MODULE_LICENSE("Dual BSD/GPL");
1899 MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices");
1900