1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_eeprom.h"
18 #include "hw/block/flash.h"
19 #include "hw/i2c/i2c_mux_pca954x.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/gpio/pca9552.h"
22 #include "hw/nvram/eeprom_at24c.h"
23 #include "hw/sensor/tmp105.h"
24 #include "hw/misc/led.h"
25 #include "hw/qdev-properties.h"
26 #include "system/block-backend.h"
27 #include "system/reset.h"
28 #include "hw/loader.h"
29 #include "qemu/error-report.h"
30 #include "qemu/datadir.h"
31 #include "qemu/units.h"
32 #include "hw/qdev-clock.h"
33 #include "system/system.h"
34
35 static struct arm_boot_info aspeed_board_binfo = {
36 .board_id = -1, /* device-tree-only board */
37 };
38
39 struct AspeedMachineState {
40 /* Private */
41 MachineState parent_obj;
42 /* Public */
43
44 AspeedSoCState *soc;
45 MemoryRegion boot_rom;
46 bool mmio_exec;
47 uint32_t uart_chosen;
48 char *fmc_model;
49 char *spi_model;
50 uint32_t hw_strap1;
51 };
52
53 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
54 #if HOST_LONG_BITS == 32
55 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
56 #else
57 #define ASPEED_RAM_SIZE(sz) (sz)
58 #endif
59
60 /* Palmetto hardware value: 0x120CE416 */
61 #define PALMETTO_BMC_HW_STRAP1 ( \
62 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
63 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
64 SCU_AST2400_HW_STRAP_ACPI_DIS | \
65 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
66 SCU_HW_STRAP_VGA_CLASS_CODE | \
67 SCU_HW_STRAP_LPC_RESET_PIN | \
68 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
69 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
70 SCU_HW_STRAP_SPI_WIDTH | \
71 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
72 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
73
74 /* TODO: Find the actual hardware value */
75 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
76 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
77 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
78 SCU_AST2400_HW_STRAP_ACPI_DIS | \
79 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
80 SCU_HW_STRAP_VGA_CLASS_CODE | \
81 SCU_HW_STRAP_LPC_RESET_PIN | \
82 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
83 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
84 SCU_HW_STRAP_SPI_WIDTH | \
85 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
86 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
87
88 /* TODO: Find the actual hardware value */
89 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
90 AST2500_HW_STRAP1_DEFAULTS | \
91 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
92 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
93 SCU_AST2500_HW_STRAP_UART_DEBUG | \
94 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
95 SCU_HW_STRAP_SPI_WIDTH | \
96 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
97
98 /* AST2500 evb hardware value: 0xF100C2E6 */
99 #define AST2500_EVB_HW_STRAP1 (( \
100 AST2500_HW_STRAP1_DEFAULTS | \
101 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
102 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
103 SCU_AST2500_HW_STRAP_UART_DEBUG | \
104 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
105 SCU_HW_STRAP_MAC1_RGMII | \
106 SCU_HW_STRAP_MAC0_RGMII) & \
107 ~SCU_HW_STRAP_2ND_BOOT_WDT)
108
109 /* Romulus hardware value: 0xF10AD206 */
110 #define ROMULUS_BMC_HW_STRAP1 ( \
111 AST2500_HW_STRAP1_DEFAULTS | \
112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
114 SCU_AST2500_HW_STRAP_UART_DEBUG | \
115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
116 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
117 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
118
119 /* Sonorapass hardware value: 0xF100D216 */
120 #define SONORAPASS_BMC_HW_STRAP1 ( \
121 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
122 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
123 SCU_AST2500_HW_STRAP_UART_DEBUG | \
124 SCU_AST2500_HW_STRAP_RESERVED28 | \
125 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
126 SCU_HW_STRAP_VGA_CLASS_CODE | \
127 SCU_HW_STRAP_LPC_RESET_PIN | \
128 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
129 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
130 SCU_HW_STRAP_VGA_BIOS_ROM | \
131 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
132 SCU_AST2500_HW_STRAP_RESERVED1)
133
134 #define G220A_BMC_HW_STRAP1 ( \
135 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
136 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
137 SCU_AST2500_HW_STRAP_UART_DEBUG | \
138 SCU_AST2500_HW_STRAP_RESERVED28 | \
139 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
140 SCU_HW_STRAP_2ND_BOOT_WDT | \
141 SCU_HW_STRAP_VGA_CLASS_CODE | \
142 SCU_HW_STRAP_LPC_RESET_PIN | \
143 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
144 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
145 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
146 SCU_AST2500_HW_STRAP_RESERVED1)
147
148 /* FP5280G2 hardware value: 0XF100D286 */
149 #define FP5280G2_BMC_HW_STRAP1 ( \
150 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
151 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
152 SCU_AST2500_HW_STRAP_UART_DEBUG | \
153 SCU_AST2500_HW_STRAP_RESERVED28 | \
154 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
155 SCU_HW_STRAP_VGA_CLASS_CODE | \
156 SCU_HW_STRAP_LPC_RESET_PIN | \
157 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
158 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
159 SCU_HW_STRAP_MAC1_RGMII | \
160 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
161 SCU_AST2500_HW_STRAP_RESERVED1)
162
163 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
164 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
165
166 /* Quanta-Q71l hardware value */
167 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
168 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
169 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
170 SCU_AST2400_HW_STRAP_ACPI_DIS | \
171 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
172 SCU_HW_STRAP_VGA_CLASS_CODE | \
173 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
174 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
175 SCU_HW_STRAP_SPI_WIDTH | \
176 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
177 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
178
179 /* AST2600 evb hardware value */
180 #define AST2600_EVB_HW_STRAP1 0x000000C0
181 #define AST2600_EVB_HW_STRAP2 0x00000003
182
183 #ifdef TARGET_AARCH64
184 /* AST2700 evb hardware value */
185 /* SCU HW Strap1 */
186 #define AST2700_EVB_HW_STRAP1 0x00000800
187 /* SCUIO HW Strap1 */
188 #define AST2700_EVB_HW_STRAP2 0x00000700
189 #endif
190
191 /* Rainier hardware value: (QEMU prototype) */
192 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
193 #define RAINIER_BMC_HW_STRAP2 0x80000848
194
195 /* Fuji hardware value */
196 #define FUJI_BMC_HW_STRAP1 0x00000000
197 #define FUJI_BMC_HW_STRAP2 0x00000000
198
199 /* Bletchley hardware value */
200 /* TODO: Leave same as EVB for now. */
201 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
202 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
203
204 /* Qualcomm DC-SCM hardware value */
205 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
206 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
207
208 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
209 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
210 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
211 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
212 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
213 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
214 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
215
aspeed_write_smpboot(ARMCPU * cpu,const struct arm_boot_info * info)216 static void aspeed_write_smpboot(ARMCPU *cpu,
217 const struct arm_boot_info *info)
218 {
219 AddressSpace *as = arm_boot_address_space(cpu, info);
220 static const ARMInsnFixup poll_mailbox_ready[] = {
221 /*
222 * r2 = per-cpu go sign value
223 * r1 = AST_SMP_MBOX_FIELD_ENTRY
224 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
225 */
226 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
227 { 0xe21000ff }, /* ands r0, r0, #255 */
228 { 0xe59f201c }, /* ldr r2, [pc, #28] */
229 { 0xe1822000 }, /* orr r2, r2, r0 */
230
231 { 0xe59f1018 }, /* ldr r1, [pc, #24] */
232 { 0xe59f0018 }, /* ldr r0, [pc, #24] */
233
234 { 0xe320f002 }, /* wfe */
235 { 0xe5904000 }, /* ldr r4, [r0] */
236 { 0xe1520004 }, /* cmp r2, r4 */
237 { 0x1afffffb }, /* bne <wfe> */
238 { 0xe591f000 }, /* ldr pc, [r1] */
239 { AST_SMP_MBOX_GOSIGN },
240 { AST_SMP_MBOX_FIELD_ENTRY },
241 { AST_SMP_MBOX_FIELD_GOSIGN },
242 { 0, FIXUP_TERMINATOR }
243 };
244 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
245
246 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
247 poll_mailbox_ready, fixupcontext);
248 }
249
aspeed_reset_secondary(ARMCPU * cpu,const struct arm_boot_info * info)250 static void aspeed_reset_secondary(ARMCPU *cpu,
251 const struct arm_boot_info *info)
252 {
253 AddressSpace *as = arm_boot_address_space(cpu, info);
254 CPUState *cs = CPU(cpu);
255
256 /* info->smp_bootreg_addr */
257 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
258 MEMTXATTRS_UNSPECIFIED, NULL);
259 cpu_set_pc(cs, info->smp_loader_start);
260 }
261
write_boot_rom(BlockBackend * blk,hwaddr addr,size_t rom_size,Error ** errp)262 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
263 Error **errp)
264 {
265 g_autofree void *storage = NULL;
266 int64_t size;
267
268 /*
269 * The block backend size should have already been 'validated' by
270 * the creation of the m25p80 object.
271 */
272 size = blk_getlength(blk);
273 if (size <= 0) {
274 error_setg(errp, "failed to get flash size");
275 return;
276 }
277
278 if (rom_size > size) {
279 rom_size = size;
280 }
281
282 storage = g_malloc0(rom_size);
283 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
284 error_setg(errp, "failed to read the initial flash content");
285 return;
286 }
287
288 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
289 }
290
291 /*
292 * Create a ROM and copy the flash contents at the expected address
293 * (0x0). Boots faster than execute-in-place.
294 */
aspeed_install_boot_rom(AspeedMachineState * bmc,BlockBackend * blk,uint64_t rom_size)295 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
296 uint64_t rom_size)
297 {
298 AspeedSoCState *soc = bmc->soc;
299 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);
300
301 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
302 &error_abort);
303 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
304 &bmc->boot_rom, 1);
305 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
306 rom_size, &error_abort);
307 }
308
309 /*
310 * This function locates the vbootrom image file specified via the command line
311 * using the -bios option. It loads the specified image into the vbootrom
312 * memory region and handles errors if the file cannot be found or loaded.
313 */
aspeed_load_vbootrom(MachineState * machine,uint64_t rom_size,Error ** errp)314 static void aspeed_load_vbootrom(MachineState *machine, uint64_t rom_size,
315 Error **errp)
316 {
317 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
318 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
319 const char *bios_name = machine->firmware ?: amc->vbootrom_name;
320 g_autofree char *filename = NULL;
321 AspeedSoCState *soc = bmc->soc;
322 int ret;
323
324 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
325 if (!filename) {
326 error_setg(errp, "Could not find vbootrom image '%s'", bios_name);
327 return;
328 }
329
330 ret = load_image_mr(filename, &soc->vbootrom);
331 if (ret < 0) {
332 error_setg(errp, "Failed to load vbootrom image '%s'", bios_name);
333 return;
334 }
335 }
336
aspeed_board_init_flashes(AspeedSMCState * s,const char * flashtype,unsigned int count,int unit0)337 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
338 unsigned int count, int unit0)
339 {
340 int i;
341
342 if (!flashtype) {
343 return;
344 }
345
346 for (i = 0; i < count; ++i) {
347 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
348 DeviceState *dev;
349
350 dev = qdev_new(flashtype);
351 if (dinfo) {
352 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
353 }
354 qdev_prop_set_uint8(dev, "cs", i);
355 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
356 }
357 }
358
sdhci_attach_drive(SDHCIState * sdhci,DriveInfo * dinfo,bool emmc,bool boot_emmc)359 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc,
360 bool boot_emmc)
361 {
362 DeviceState *card;
363
364 if (!dinfo) {
365 return;
366 }
367 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD);
368
369 /*
370 * Force the boot properties of the eMMC device only when the
371 * machine is strapped to boot from eMMC. Without these
372 * settings, the machine would not boot.
373 *
374 * This also allows the machine to use an eMMC device without
375 * boot areas when booting from the flash device (or -kernel)
376 * Ideally, the device and its properties should be defined on
377 * the command line.
378 */
379 if (emmc && boot_emmc) {
380 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB);
381 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3);
382 }
383 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
384 &error_fatal);
385 qdev_realize_and_unref(card,
386 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
387 &error_fatal);
388 }
389
connect_serial_hds_to_uarts(AspeedMachineState * bmc)390 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
391 {
392 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
393 AspeedSoCState *s = bmc->soc;
394 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
395 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
396
397 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
398 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) {
399 if (uart == uart_chosen) {
400 continue;
401 }
402 aspeed_soc_uart_set_chr(s, uart, serial_hd(i++));
403 }
404 }
405
aspeed_machine_init(MachineState * machine)406 static void aspeed_machine_init(MachineState *machine)
407 {
408 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
409 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
410 AspeedSoCClass *sc;
411 int i;
412 DriveInfo *emmc0 = NULL;
413 uint64_t rom_size;
414 bool boot_emmc;
415
416 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
417 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
418 object_unref(OBJECT(bmc->soc));
419 sc = ASPEED_SOC_GET_CLASS(bmc->soc);
420
421 /*
422 * This will error out if the RAM size is not supported by the
423 * memory controller of the SoC.
424 */
425 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
426 &error_fatal);
427
428 for (i = 0; i < sc->macs_num; i++) {
429 if ((amc->macs_mask & (1 << i)) &&
430 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]),
431 true, NULL)) {
432 break; /* No configs left; stop asking */
433 }
434 }
435
436 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1,
437 &error_abort);
438 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
439 &error_abort);
440 object_property_set_link(OBJECT(bmc->soc), "memory",
441 OBJECT(get_system_memory()), &error_abort);
442 object_property_set_link(OBJECT(bmc->soc), "dram",
443 OBJECT(machine->ram), &error_abort);
444 if (amc->sdhci_wp_inverted) {
445 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
446 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]),
447 "wp-inverted", true, &error_abort);
448 }
449 }
450 if (machine->kernel_filename) {
451 /*
452 * When booting with a -kernel command line there is no u-boot
453 * that runs to unlock the SCU. In this case set the default to
454 * be unlocked as the kernel expects
455 */
456 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
457 ASPEED_SCU_PROT_KEY, &error_abort);
458 }
459 connect_serial_hds_to_uarts(bmc);
460 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
461
462 if (defaults_enabled()) {
463 aspeed_board_init_flashes(&bmc->soc->fmc,
464 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
465 amc->num_cs, 0);
466 aspeed_board_init_flashes(&bmc->soc->spi[0],
467 bmc->spi_model ? bmc->spi_model : amc->spi_model,
468 1, amc->num_cs);
469 }
470
471 if (machine->kernel_filename && sc->num_cpus > 1) {
472 /* With no u-boot we must set up a boot stub for the secondary CPU */
473 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
474 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
475 0x80, &error_abort);
476 memory_region_add_subregion(get_system_memory(),
477 AST_SMP_MAILBOX_BASE, smpboot);
478
479 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
480 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
481 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
482 }
483
484 aspeed_board_binfo.ram_size = machine->ram_size;
485 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
486
487 if (amc->i2c_init) {
488 amc->i2c_init(bmc);
489 }
490
491 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) {
492 sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
493 drive_get(IF_SD, 0, i), false, false);
494 }
495
496 boot_emmc = sc->boot_from_emmc(bmc->soc);
497
498 if (bmc->soc->emmc.num_slots && defaults_enabled()) {
499 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots);
500 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc);
501 }
502
503 if (!bmc->mmio_exec) {
504 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
505 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
506
507 if (fmc0 && !boot_emmc) {
508 rom_size = memory_region_size(&bmc->soc->spi_boot);
509 aspeed_install_boot_rom(bmc, fmc0, rom_size);
510 } else if (emmc0) {
511 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB);
512 }
513 }
514
515 if (amc->vbootrom) {
516 rom_size = memory_region_size(&bmc->soc->vbootrom);
517 aspeed_load_vbootrom(machine, rom_size, &error_abort);
518 }
519
520 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
521 }
522
palmetto_bmc_i2c_init(AspeedMachineState * bmc)523 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
524 {
525 AspeedSoCState *soc = bmc->soc;
526 DeviceState *dev;
527 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
528
529 /*
530 * The palmetto platform expects a ds3231 RTC but a ds1338 is
531 * enough to provide basic RTC features. Alarms will be missing
532 */
533 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
534
535 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
536 eeprom_buf);
537
538 /* add a TMP423 temperature sensor */
539 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
540 "tmp423", 0x4c));
541 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
542 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
543 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
544 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
545 }
546
quanta_q71l_bmc_i2c_init(AspeedMachineState * bmc)547 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
548 {
549 AspeedSoCState *soc = bmc->soc;
550
551 /*
552 * The quanta-q71l platform expects tmp75s which are compatible with
553 * tmp105s.
554 */
555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
556 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
557 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
558
559 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
560 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
561 /* TODO: Add Memory Riser i2c mux and eeproms. */
562
563 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
565
566 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
567
568 /* i2c-7 */
569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
570 /* - i2c@0: pmbus@59 */
571 /* - i2c@1: pmbus@58 */
572 /* - i2c@2: pmbus@58 */
573 /* - i2c@3: pmbus@59 */
574
575 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
576 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
577 }
578
ast2500_evb_i2c_init(AspeedMachineState * bmc)579 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
580 {
581 AspeedSoCState *soc = bmc->soc;
582 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
583
584 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
585 eeprom_buf);
586
587 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
588 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
589 TYPE_TMP105, 0x4d);
590 }
591
ast2600_evb_i2c_init(AspeedMachineState * bmc)592 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
593 {
594 AspeedSoCState *soc = bmc->soc;
595 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
596
597 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
598 eeprom_buf);
599
600 /* LM75 is compatible with TMP105 driver */
601 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
602 TYPE_TMP105, 0x4d);
603 }
604
yosemitev2_bmc_i2c_init(AspeedMachineState * bmc)605 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
606 {
607 AspeedSoCState *soc = bmc->soc;
608
609 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
610 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
611 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
612 /* TMP421 */
613 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
614 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
615 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
616
617 }
618
romulus_bmc_i2c_init(AspeedMachineState * bmc)619 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
620 {
621 AspeedSoCState *soc = bmc->soc;
622
623 /*
624 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
625 * good enough
626 */
627 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
628 }
629
tiogapass_bmc_i2c_init(AspeedMachineState * bmc)630 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
631 {
632 AspeedSoCState *soc = bmc->soc;
633
634 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
635 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
636 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
637 /* TMP421 */
638 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
639 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
640 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
641 }
642
create_pca9552(AspeedSoCState * soc,int bus_id,int addr)643 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
644 {
645 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
646 TYPE_PCA9552, addr);
647 }
648
sonorapass_bmc_i2c_init(AspeedMachineState * bmc)649 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
650 {
651 AspeedSoCState *soc = bmc->soc;
652
653 /* bus 2 : */
654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
655 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
656 /* bus 2 : pca9546 @ 0x73 */
657
658 /* bus 3 : pca9548 @ 0x70 */
659
660 /* bus 4 : */
661 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
662 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
663 eeprom4_54);
664 /* PCA9539 @ 0x76, but PCA9552 is compatible */
665 create_pca9552(soc, 4, 0x76);
666 /* PCA9539 @ 0x77, but PCA9552 is compatible */
667 create_pca9552(soc, 4, 0x77);
668
669 /* bus 6 : */
670 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
671 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
672 /* bus 6 : pca9546 @ 0x73 */
673
674 /* bus 8 : */
675 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
676 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
677 eeprom8_56);
678 create_pca9552(soc, 8, 0x60);
679 create_pca9552(soc, 8, 0x61);
680 /* bus 8 : adc128d818 @ 0x1d */
681 /* bus 8 : adc128d818 @ 0x1f */
682
683 /*
684 * bus 13 : pca9548 @ 0x71
685 * - channel 3:
686 * - tmm421 @ 0x4c
687 * - tmp421 @ 0x4e
688 * - tmp421 @ 0x4f
689 */
690
691 }
692
witherspoon_bmc_i2c_init(AspeedMachineState * bmc)693 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
694 {
695 static const struct {
696 unsigned gpio_id;
697 LEDColor color;
698 const char *description;
699 bool gpio_polarity;
700 } pca1_leds[] = {
701 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
702 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
703 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
704 };
705 AspeedSoCState *soc = bmc->soc;
706 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
707 DeviceState *dev;
708 LEDState *led;
709
710 /* Bus 3: TODO bmp280@77 */
711 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
712 qdev_prop_set_string(dev, "description", "pca1");
713 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
714 aspeed_i2c_get_bus(&soc->i2c, 3),
715 &error_fatal);
716
717 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
718 led = led_create_simple(OBJECT(bmc),
719 pca1_leds[i].gpio_polarity,
720 pca1_leds[i].color,
721 pca1_leds[i].description);
722 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
723 qdev_get_gpio_in(DEVICE(led), 0));
724 }
725
726 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
727 0x68);
728 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
729 0x69);
730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
731
732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
733 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
734 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x70);
735 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x71);
736
737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
738 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x70);
739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x71);
740
741 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
742 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
743 0x4a);
744
745 /*
746 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
747 * good enough
748 */
749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
750
751 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
752 eeprom_buf);
753 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
754 qdev_prop_set_string(dev, "description", "pca0");
755 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
756 aspeed_i2c_get_bus(&soc->i2c, 11),
757 &error_fatal);
758 /* Bus 11: TODO ucd90160@64 */
759 }
760
g220a_bmc_i2c_init(AspeedMachineState * bmc)761 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
762 {
763 AspeedSoCState *soc = bmc->soc;
764 DeviceState *dev;
765
766 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
767 "emc1413", 0x4c));
768 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
769 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
770 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
771
772 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
773 "emc1413", 0x4c));
774 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
775 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
776 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
777
778 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
779 "emc1413", 0x4c));
780 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
781 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
782 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
783
784 static uint8_t eeprom_buf[2 * 1024] = {
785 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
786 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
787 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
788 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
789 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
790 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
791 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
792 };
793 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
794 eeprom_buf);
795 }
796
fp5280g2_bmc_i2c_init(AspeedMachineState * bmc)797 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
798 {
799 AspeedSoCState *soc = bmc->soc;
800 I2CSlave *i2c_mux;
801
802 /* The at24c256 */
803 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
804
805 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
807 0x48);
808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
809 0x49);
810
811 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
812 "pca9546", 0x70);
813 /* It expects a TMP112 but a TMP105 is compatible */
814 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
815 0x4a);
816
817 /* It expects a ds3232 but a ds1338 is good enough */
818 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
819
820 /* It expects a pca9555 but a pca9552 is compatible */
821 create_pca9552(soc, 8, 0x30);
822 }
823
rainier_bmc_i2c_init(AspeedMachineState * bmc)824 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
825 {
826 AspeedSoCState *soc = bmc->soc;
827 I2CSlave *i2c_mux;
828
829 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
830
831 create_pca9552(soc, 3, 0x61);
832
833 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
834 0x68);
835 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
836 0x69);
837 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
838 0x6a);
839 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
840 0x6b);
841
842 /* The rainier expects a TMP275 but a TMP105 is compatible */
843 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
844 0x48);
845 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
846 0x49);
847 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
848 0x4a);
849 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
850 "pca9546", 0x70);
851 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
852 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
853 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
854 create_pca9552(soc, 4, 0x60);
855
856 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
857 0x48);
858 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
859 0x49);
860 create_pca9552(soc, 5, 0x60);
861 create_pca9552(soc, 5, 0x61);
862 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
863 "pca9546", 0x70);
864 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
865 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
866
867 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
868 0x48);
869 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
870 0x4a);
871 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
872 0x4b);
873 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
874 "pca9546", 0x70);
875 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
876 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
877 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
878 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
879
880 create_pca9552(soc, 7, 0x30);
881 create_pca9552(soc, 7, 0x31);
882 create_pca9552(soc, 7, 0x32);
883 create_pca9552(soc, 7, 0x33);
884 create_pca9552(soc, 7, 0x60);
885 create_pca9552(soc, 7, 0x61);
886 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
887 /* Bus 7: TODO si7021-a20@20 */
888 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
889 0x48);
890 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
891 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
892 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
893
894 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
895 0x48);
896 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
897 0x4a);
898 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
899 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
900 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
901 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
902 create_pca9552(soc, 8, 0x60);
903 create_pca9552(soc, 8, 0x61);
904 /* Bus 8: ucd90320@11 */
905 /* Bus 8: ucd90320@b */
906 /* Bus 8: ucd90320@c */
907
908 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x42);
909 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x43);
910 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x44);
911 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x72);
912 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x73);
913 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x74);
914 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
915 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
916 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
917
918 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x42);
919 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x43);
920 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x44);
921 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x72);
922 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x73);
923 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x74);
924 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
925 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
926 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
927
928 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
929 0x48);
930 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
931 0x49);
932 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
933 "pca9546", 0x70);
934 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
935 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
936 create_pca9552(soc, 11, 0x60);
937
938
939 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
940 create_pca9552(soc, 13, 0x60);
941
942 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
943 create_pca9552(soc, 14, 0x60);
944
945 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
946 create_pca9552(soc, 15, 0x60);
947 }
948
get_pca9548_channels(I2CBus * bus,uint8_t mux_addr,I2CBus ** channels)949 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
950 I2CBus **channels)
951 {
952 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
953 for (int i = 0; i < 8; i++) {
954 channels[i] = pca954x_i2c_get_bus(mux, i);
955 }
956 }
957
958 #define TYPE_LM75 TYPE_TMP105
959 #define TYPE_TMP75 TYPE_TMP105
960 #define TYPE_TMP422 "tmp422"
961
fuji_bmc_i2c_init(AspeedMachineState * bmc)962 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
963 {
964 AspeedSoCState *soc = bmc->soc;
965 I2CBus *i2c[144] = {};
966
967 for (int i = 0; i < 16; i++) {
968 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
969 }
970 I2CBus *i2c180 = i2c[2];
971 I2CBus *i2c480 = i2c[8];
972 I2CBus *i2c600 = i2c[11];
973
974 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
975 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
976 /* NOTE: The device tree skips [32, 40) in the alias numbering */
977 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
978 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
979 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
980 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
981 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
982 for (int i = 0; i < 8; i++) {
983 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
984 }
985
986 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
987 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
988
989 /*
990 * EEPROM 24c64 size is 64Kbits or 8 Kbytes
991 * 24c02 size is 2Kbits or 256 bytes
992 */
993 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
994 at24c_eeprom_init(i2c[20], 0x50, 256);
995 at24c_eeprom_init(i2c[22], 0x52, 256);
996
997 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
998 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
999 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
1000 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
1001
1002 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
1003 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
1004
1005 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
1006 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
1007 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
1008 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
1009
1010 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
1011 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
1012
1013 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
1014 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
1015 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
1016 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
1017 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
1018 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
1019 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
1020
1021 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
1022 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
1023 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
1024 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
1025 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
1026 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
1027 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
1028 at24c_eeprom_init(i2c[28], 0x50, 256);
1029
1030 for (int i = 0; i < 8; i++) {
1031 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
1032 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
1033 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
1034 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
1035 }
1036 }
1037
1038 #define TYPE_TMP421 "tmp421"
1039
bletchley_bmc_i2c_init(AspeedMachineState * bmc)1040 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
1041 {
1042 AspeedSoCState *soc = bmc->soc;
1043 I2CBus *i2c[13] = {};
1044 for (int i = 0; i < 13; i++) {
1045 if ((i == 8) || (i == 11)) {
1046 continue;
1047 }
1048 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1049 }
1050
1051 /* Bus 0 - 5 all have the same config. */
1052 for (int i = 0; i < 6; i++) {
1053 /* Missing model: ti,ina230 @ 0x45 */
1054 /* Missing model: mps,mp5023 @ 0x40 */
1055 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
1056 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
1057 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
1058 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
1059 /* Missing model: fsc,fusb302 @ 0x22 */
1060 }
1061
1062 /* Bus 6 */
1063 at24c_eeprom_init(i2c[6], 0x56, 65536);
1064 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
1065 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
1066
1067
1068 /* Bus 7 */
1069 at24c_eeprom_init(i2c[7], 0x54, 65536);
1070
1071 /* Bus 9 */
1072 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
1073
1074 /* Bus 10 */
1075 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
1076 /* Missing model: ti,hdc1080 @ 0x40 */
1077 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
1078
1079 /* Bus 12 */
1080 /* Missing model: adi,adm1278 @ 0x11 */
1081 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
1082 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
1083 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
1084 }
1085
fby35_i2c_init(AspeedMachineState * bmc)1086 static void fby35_i2c_init(AspeedMachineState *bmc)
1087 {
1088 AspeedSoCState *soc = bmc->soc;
1089 I2CBus *i2c[16];
1090
1091 for (int i = 0; i < 16; i++) {
1092 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1093 }
1094
1095 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
1096 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
1097 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
1098 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
1099 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
1100 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
1101
1102 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
1103 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
1104 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
1105 fby35_nic_fruid_len);
1106 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
1107 fby35_bb_fruid_len);
1108 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
1109 fby35_bmc_fruid_len);
1110
1111 /*
1112 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
1113 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
1114 * each.
1115 */
1116 }
1117
qcom_dc_scm_bmc_i2c_init(AspeedMachineState * bmc)1118 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
1119 {
1120 AspeedSoCState *soc = bmc->soc;
1121
1122 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1123 }
1124
qcom_dc_scm_firework_i2c_init(AspeedMachineState * bmc)1125 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1126 {
1127 AspeedSoCState *soc = bmc->soc;
1128 I2CSlave *therm_mux, *cpuvr_mux;
1129
1130 /* Create the generic DC-SCM hardware */
1131 qcom_dc_scm_bmc_i2c_init(bmc);
1132
1133 /* Now create the Firework specific hardware */
1134
1135 /* I2C7 CPUVR MUX */
1136 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1137 "pca9546", 0x70);
1138 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1139 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1140 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1141 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1142
1143 /* I2C8 Thermal Diodes*/
1144 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1145 "pca9548", 0x70);
1146 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1147 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1148 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1149 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1150 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1151
1152 /* I2C9 Fan Controller (MAX31785) */
1153 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1154 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1155 }
1156
aspeed_get_mmio_exec(Object * obj,Error ** errp)1157 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1158 {
1159 return ASPEED_MACHINE(obj)->mmio_exec;
1160 }
1161
aspeed_set_mmio_exec(Object * obj,bool value,Error ** errp)1162 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1163 {
1164 ASPEED_MACHINE(obj)->mmio_exec = value;
1165 }
1166
aspeed_machine_instance_init(Object * obj)1167 static void aspeed_machine_instance_init(Object *obj)
1168 {
1169 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj);
1170
1171 ASPEED_MACHINE(obj)->mmio_exec = false;
1172 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1;
1173 }
1174
aspeed_get_fmc_model(Object * obj,Error ** errp)1175 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1176 {
1177 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1178 return g_strdup(bmc->fmc_model);
1179 }
1180
aspeed_set_fmc_model(Object * obj,const char * value,Error ** errp)1181 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1182 {
1183 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1184
1185 g_free(bmc->fmc_model);
1186 bmc->fmc_model = g_strdup(value);
1187 }
1188
aspeed_get_spi_model(Object * obj,Error ** errp)1189 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1190 {
1191 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1192 return g_strdup(bmc->spi_model);
1193 }
1194
aspeed_set_spi_model(Object * obj,const char * value,Error ** errp)1195 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1196 {
1197 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1198
1199 g_free(bmc->spi_model);
1200 bmc->spi_model = g_strdup(value);
1201 }
1202
aspeed_get_bmc_console(Object * obj,Error ** errp)1203 static char *aspeed_get_bmc_console(Object *obj, Error **errp)
1204 {
1205 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1206 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1207 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
1208
1209 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen));
1210 }
1211
aspeed_set_bmc_console(Object * obj,const char * value,Error ** errp)1212 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
1213 {
1214 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1215 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1216 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1217 int val;
1218 int uart_first = aspeed_uart_first(sc);
1219 int uart_last = aspeed_uart_last(sc);
1220
1221 if (sscanf(value, "uart%u", &val) != 1) {
1222 error_setg(errp, "Bad value for \"uart\" property");
1223 return;
1224 }
1225
1226 /* The number of UART depends on the SoC */
1227 if (val < uart_first || val > uart_last) {
1228 error_setg(errp, "\"uart\" should be in range [%d - %d]",
1229 uart_first, uart_last);
1230 return;
1231 }
1232 bmc->uart_chosen = val + ASPEED_DEV_UART0;
1233 }
1234
aspeed_machine_class_props_init(ObjectClass * oc)1235 static void aspeed_machine_class_props_init(ObjectClass *oc)
1236 {
1237 object_class_property_add_bool(oc, "execute-in-place",
1238 aspeed_get_mmio_exec,
1239 aspeed_set_mmio_exec);
1240 object_class_property_set_description(oc, "execute-in-place",
1241 "boot directly from CE0 flash device");
1242
1243 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console,
1244 aspeed_set_bmc_console);
1245 object_class_property_set_description(oc, "bmc-console",
1246 "Change the default UART to \"uartX\"");
1247
1248 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1249 aspeed_set_fmc_model);
1250 object_class_property_set_description(oc, "fmc-model",
1251 "Change the FMC Flash model");
1252 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1253 aspeed_set_spi_model);
1254 object_class_property_set_description(oc, "spi-model",
1255 "Change the SPI Flash model");
1256 }
1257
aspeed_machine_class_init_cpus_defaults(MachineClass * mc)1258 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
1259 {
1260 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
1261 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1262
1263 mc->default_cpus = sc->num_cpus;
1264 mc->min_cpus = sc->num_cpus;
1265 mc->max_cpus = sc->num_cpus;
1266 mc->valid_cpu_types = sc->valid_cpu_types;
1267 }
1268
aspeed_machine_ast2600_get_boot_from_emmc(Object * obj,Error ** errp)1269 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp)
1270 {
1271 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1272
1273 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC);
1274 }
1275
aspeed_machine_ast2600_set_boot_from_emmc(Object * obj,bool value,Error ** errp)1276 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value,
1277 Error **errp)
1278 {
1279 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1280
1281 if (value) {
1282 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1283 } else {
1284 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1285 }
1286 }
1287
aspeed_machine_ast2600_class_emmc_init(ObjectClass * oc)1288 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc)
1289 {
1290 object_class_property_add_bool(oc, "boot-emmc",
1291 aspeed_machine_ast2600_get_boot_from_emmc,
1292 aspeed_machine_ast2600_set_boot_from_emmc);
1293 object_class_property_set_description(oc, "boot-emmc",
1294 "Set or unset boot from EMMC");
1295 }
1296
aspeed_machine_class_init(ObjectClass * oc,void * data)1297 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1298 {
1299 MachineClass *mc = MACHINE_CLASS(oc);
1300 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1301
1302 mc->init = aspeed_machine_init;
1303 mc->no_floppy = 1;
1304 mc->no_cdrom = 1;
1305 mc->no_parallel = 1;
1306 mc->default_ram_id = "ram";
1307 amc->macs_mask = ASPEED_MAC0_ON;
1308 amc->uart_default = ASPEED_DEV_UART5;
1309
1310 aspeed_machine_class_props_init(oc);
1311 }
1312
aspeed_machine_palmetto_class_init(ObjectClass * oc,void * data)1313 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1314 {
1315 MachineClass *mc = MACHINE_CLASS(oc);
1316 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1317
1318 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1319 amc->soc_name = "ast2400-a1";
1320 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1321 amc->fmc_model = "n25q256a";
1322 amc->spi_model = "mx25l25635f";
1323 amc->num_cs = 1;
1324 amc->i2c_init = palmetto_bmc_i2c_init;
1325 mc->auto_create_sdcard = true;
1326 mc->default_ram_size = 256 * MiB;
1327 aspeed_machine_class_init_cpus_defaults(mc);
1328 };
1329
aspeed_machine_quanta_q71l_class_init(ObjectClass * oc,void * data)1330 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1331 {
1332 MachineClass *mc = MACHINE_CLASS(oc);
1333 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1334
1335 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1336 amc->soc_name = "ast2400-a1";
1337 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1338 amc->fmc_model = "n25q256a";
1339 amc->spi_model = "mx25l25635e";
1340 amc->num_cs = 1;
1341 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1342 mc->auto_create_sdcard = true;
1343 mc->default_ram_size = 128 * MiB;
1344 aspeed_machine_class_init_cpus_defaults(mc);
1345 }
1346
aspeed_machine_supermicrox11_bmc_class_init(ObjectClass * oc,void * data)1347 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1348 void *data)
1349 {
1350 MachineClass *mc = MACHINE_CLASS(oc);
1351 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1352
1353 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1354 amc->soc_name = "ast2400-a1";
1355 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1356 amc->fmc_model = "mx25l25635e";
1357 amc->spi_model = "mx25l25635e";
1358 amc->num_cs = 1;
1359 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1360 amc->i2c_init = palmetto_bmc_i2c_init;
1361 mc->auto_create_sdcard = true;
1362 mc->default_ram_size = 256 * MiB;
1363 aspeed_machine_class_init_cpus_defaults(mc);
1364 }
1365
aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass * oc,void * data)1366 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1367 void *data)
1368 {
1369 MachineClass *mc = MACHINE_CLASS(oc);
1370 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1371
1372 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1373 amc->soc_name = "ast2500-a1";
1374 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1375 amc->fmc_model = "mx25l25635e";
1376 amc->spi_model = "mx25l25635e";
1377 amc->num_cs = 1;
1378 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1379 amc->i2c_init = palmetto_bmc_i2c_init;
1380 mc->auto_create_sdcard = true;
1381 mc->default_ram_size = 512 * MiB;
1382 aspeed_machine_class_init_cpus_defaults(mc);
1383 }
1384
aspeed_machine_ast2500_evb_class_init(ObjectClass * oc,void * data)1385 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1386 {
1387 MachineClass *mc = MACHINE_CLASS(oc);
1388 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1389
1390 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1391 amc->soc_name = "ast2500-a1";
1392 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1393 amc->fmc_model = "mx25l25635e";
1394 amc->spi_model = "mx25l25635f";
1395 amc->num_cs = 1;
1396 amc->i2c_init = ast2500_evb_i2c_init;
1397 mc->auto_create_sdcard = true;
1398 mc->default_ram_size = 512 * MiB;
1399 aspeed_machine_class_init_cpus_defaults(mc);
1400 };
1401
aspeed_machine_yosemitev2_class_init(ObjectClass * oc,void * data)1402 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1403 {
1404 MachineClass *mc = MACHINE_CLASS(oc);
1405 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1406
1407 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
1408 amc->soc_name = "ast2500-a1";
1409 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1410 amc->hw_strap2 = 0;
1411 amc->fmc_model = "n25q256a";
1412 amc->spi_model = "mx25l25635e";
1413 amc->num_cs = 2;
1414 amc->i2c_init = yosemitev2_bmc_i2c_init;
1415 mc->auto_create_sdcard = true;
1416 mc->default_ram_size = 512 * MiB;
1417 aspeed_machine_class_init_cpus_defaults(mc);
1418 };
1419
aspeed_machine_romulus_class_init(ObjectClass * oc,void * data)1420 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1421 {
1422 MachineClass *mc = MACHINE_CLASS(oc);
1423 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1424
1425 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1426 amc->soc_name = "ast2500-a1";
1427 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1428 amc->fmc_model = "n25q256a";
1429 amc->spi_model = "mx66l1g45g";
1430 amc->num_cs = 2;
1431 amc->i2c_init = romulus_bmc_i2c_init;
1432 mc->auto_create_sdcard = true;
1433 mc->default_ram_size = 512 * MiB;
1434 aspeed_machine_class_init_cpus_defaults(mc);
1435 };
1436
aspeed_machine_tiogapass_class_init(ObjectClass * oc,void * data)1437 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1438 {
1439 MachineClass *mc = MACHINE_CLASS(oc);
1440 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1441
1442 mc->desc = "Facebook Tiogapass BMC (ARM1176)";
1443 amc->soc_name = "ast2500-a1";
1444 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1445 amc->hw_strap2 = 0;
1446 amc->fmc_model = "n25q256a";
1447 amc->spi_model = "mx25l25635e";
1448 amc->num_cs = 2;
1449 amc->i2c_init = tiogapass_bmc_i2c_init;
1450 mc->auto_create_sdcard = true;
1451 mc->default_ram_size = 1 * GiB;
1452 aspeed_machine_class_init_cpus_defaults(mc);
1453 };
1454
aspeed_machine_sonorapass_class_init(ObjectClass * oc,void * data)1455 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1456 {
1457 MachineClass *mc = MACHINE_CLASS(oc);
1458 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1459
1460 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1461 amc->soc_name = "ast2500-a1";
1462 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1463 amc->fmc_model = "mx66l1g45g";
1464 amc->spi_model = "mx66l1g45g";
1465 amc->num_cs = 2;
1466 amc->i2c_init = sonorapass_bmc_i2c_init;
1467 mc->auto_create_sdcard = true;
1468 mc->default_ram_size = 512 * MiB;
1469 aspeed_machine_class_init_cpus_defaults(mc);
1470 };
1471
aspeed_machine_witherspoon_class_init(ObjectClass * oc,void * data)1472 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1473 {
1474 MachineClass *mc = MACHINE_CLASS(oc);
1475 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1476
1477 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1478 amc->soc_name = "ast2500-a1";
1479 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1480 amc->fmc_model = "mx25l25635f";
1481 amc->spi_model = "mx66l1g45g";
1482 amc->num_cs = 2;
1483 amc->i2c_init = witherspoon_bmc_i2c_init;
1484 mc->auto_create_sdcard = true;
1485 mc->default_ram_size = 512 * MiB;
1486 aspeed_machine_class_init_cpus_defaults(mc);
1487 };
1488
aspeed_machine_ast2600_evb_class_init(ObjectClass * oc,void * data)1489 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1490 {
1491 MachineClass *mc = MACHINE_CLASS(oc);
1492 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1493
1494 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1495 amc->soc_name = "ast2600-a3";
1496 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1497 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1498 amc->fmc_model = "mx66u51235f";
1499 amc->spi_model = "mx66u51235f";
1500 amc->num_cs = 1;
1501 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1502 ASPEED_MAC3_ON;
1503 amc->sdhci_wp_inverted = true;
1504 amc->i2c_init = ast2600_evb_i2c_init;
1505 mc->auto_create_sdcard = true;
1506 mc->default_ram_size = 1 * GiB;
1507 aspeed_machine_class_init_cpus_defaults(mc);
1508 aspeed_machine_ast2600_class_emmc_init(oc);
1509 };
1510
aspeed_machine_g220a_class_init(ObjectClass * oc,void * data)1511 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1512 {
1513 MachineClass *mc = MACHINE_CLASS(oc);
1514 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1515
1516 mc->desc = "Bytedance G220A BMC (ARM1176)";
1517 amc->soc_name = "ast2500-a1";
1518 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1519 amc->fmc_model = "n25q512a";
1520 amc->spi_model = "mx25l25635e";
1521 amc->num_cs = 2;
1522 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1523 amc->i2c_init = g220a_bmc_i2c_init;
1524 mc->auto_create_sdcard = true;
1525 mc->default_ram_size = 1024 * MiB;
1526 aspeed_machine_class_init_cpus_defaults(mc);
1527 };
1528
aspeed_machine_fp5280g2_class_init(ObjectClass * oc,void * data)1529 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1530 {
1531 MachineClass *mc = MACHINE_CLASS(oc);
1532 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1533
1534 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1535 amc->soc_name = "ast2500-a1";
1536 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1537 amc->fmc_model = "n25q512a";
1538 amc->spi_model = "mx25l25635e";
1539 amc->num_cs = 2;
1540 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1541 amc->i2c_init = fp5280g2_bmc_i2c_init;
1542 mc->auto_create_sdcard = true;
1543 mc->default_ram_size = 512 * MiB;
1544 aspeed_machine_class_init_cpus_defaults(mc);
1545 };
1546
aspeed_machine_rainier_class_init(ObjectClass * oc,void * data)1547 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1548 {
1549 MachineClass *mc = MACHINE_CLASS(oc);
1550 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1551
1552 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1553 amc->soc_name = "ast2600-a3";
1554 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1555 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1556 amc->fmc_model = "mx66l1g45g";
1557 amc->spi_model = "mx66l1g45g";
1558 amc->num_cs = 2;
1559 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1560 amc->i2c_init = rainier_bmc_i2c_init;
1561 mc->auto_create_sdcard = true;
1562 mc->default_ram_size = 1 * GiB;
1563 aspeed_machine_class_init_cpus_defaults(mc);
1564 aspeed_machine_ast2600_class_emmc_init(oc);
1565 };
1566
1567 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1568
aspeed_machine_fuji_class_init(ObjectClass * oc,void * data)1569 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1570 {
1571 MachineClass *mc = MACHINE_CLASS(oc);
1572 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1573
1574 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1575 amc->soc_name = "ast2600-a3";
1576 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1577 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1578 amc->fmc_model = "mx66l1g45g";
1579 amc->spi_model = "mx66l1g45g";
1580 amc->num_cs = 2;
1581 amc->macs_mask = ASPEED_MAC3_ON;
1582 amc->i2c_init = fuji_bmc_i2c_init;
1583 amc->uart_default = ASPEED_DEV_UART1;
1584 mc->auto_create_sdcard = true;
1585 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1586 aspeed_machine_class_init_cpus_defaults(mc);
1587 };
1588
1589 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1590
aspeed_machine_bletchley_class_init(ObjectClass * oc,void * data)1591 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1592 {
1593 MachineClass *mc = MACHINE_CLASS(oc);
1594 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1595
1596 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1597 amc->soc_name = "ast2600-a3";
1598 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1599 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1600 amc->fmc_model = "w25q01jvq";
1601 amc->spi_model = NULL;
1602 amc->num_cs = 2;
1603 amc->macs_mask = ASPEED_MAC2_ON;
1604 amc->i2c_init = bletchley_bmc_i2c_init;
1605 mc->auto_create_sdcard = true;
1606 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1607 aspeed_machine_class_init_cpus_defaults(mc);
1608 }
1609
fby35_reset(MachineState * state,ResetType type)1610 static void fby35_reset(MachineState *state, ResetType type)
1611 {
1612 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1613 AspeedGPIOState *gpio = &bmc->soc->gpio;
1614
1615 qemu_devices_reset(type);
1616
1617 /* Board ID: 7 (Class-1, 4 slots) */
1618 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1619 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1620 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1621 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1622
1623 /* Slot presence pins, inverse polarity. (False means present) */
1624 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1625 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1626 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1627 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1628
1629 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1630 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1631 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1632 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1633 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1634 }
1635
aspeed_machine_fby35_class_init(ObjectClass * oc,void * data)1636 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1637 {
1638 MachineClass *mc = MACHINE_CLASS(oc);
1639 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1640
1641 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1642 mc->reset = fby35_reset;
1643 amc->fmc_model = "mx66l1g45g";
1644 amc->num_cs = 2;
1645 amc->macs_mask = ASPEED_MAC3_ON;
1646 amc->i2c_init = fby35_i2c_init;
1647 mc->auto_create_sdcard = true;
1648 /* FIXME: Replace this macro with something more general */
1649 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1650 aspeed_machine_class_init_cpus_defaults(mc);
1651 }
1652
1653 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1654 /* Main SYSCLK frequency in Hz (200MHz) */
1655 #define SYSCLK_FRQ 200000000ULL
1656
aspeed_minibmc_machine_init(MachineState * machine)1657 static void aspeed_minibmc_machine_init(MachineState *machine)
1658 {
1659 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1660 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1661 Clock *sysclk;
1662
1663 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1664 clock_set_hz(sysclk, SYSCLK_FRQ);
1665
1666 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
1667 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
1668 object_unref(OBJECT(bmc->soc));
1669 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
1670
1671 object_property_set_link(OBJECT(bmc->soc), "memory",
1672 OBJECT(get_system_memory()), &error_abort);
1673 connect_serial_hds_to_uarts(bmc);
1674 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
1675
1676 if (defaults_enabled()) {
1677 aspeed_board_init_flashes(&bmc->soc->fmc,
1678 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1679 amc->num_cs,
1680 0);
1681
1682 aspeed_board_init_flashes(&bmc->soc->spi[0],
1683 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1684 amc->num_cs, amc->num_cs);
1685
1686 aspeed_board_init_flashes(&bmc->soc->spi[1],
1687 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1688 amc->num_cs, (amc->num_cs * 2));
1689 }
1690
1691 if (amc->i2c_init) {
1692 amc->i2c_init(bmc);
1693 }
1694
1695 armv7m_load_kernel(ARM_CPU(first_cpu),
1696 machine->kernel_filename,
1697 0,
1698 AST1030_INTERNAL_FLASH_SIZE);
1699 }
1700
ast1030_evb_i2c_init(AspeedMachineState * bmc)1701 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1702 {
1703 AspeedSoCState *soc = bmc->soc;
1704
1705 /* U10 24C08 connects to SDA/SCL Group 1 by default */
1706 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1707 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1708
1709 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1710 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1711 }
1712
aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass * oc,void * data)1713 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1714 void *data)
1715 {
1716 MachineClass *mc = MACHINE_CLASS(oc);
1717 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1718
1719 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1720 amc->soc_name = "ast1030-a1";
1721 amc->hw_strap1 = 0;
1722 amc->hw_strap2 = 0;
1723 mc->init = aspeed_minibmc_machine_init;
1724 amc->i2c_init = ast1030_evb_i2c_init;
1725 mc->default_ram_size = 0;
1726 amc->fmc_model = "w25q80bl";
1727 amc->spi_model = "w25q256";
1728 amc->num_cs = 2;
1729 amc->macs_mask = 0;
1730 aspeed_machine_class_init_cpus_defaults(mc);
1731 }
1732
1733 #ifdef TARGET_AARCH64
ast2700_evb_i2c_init(AspeedMachineState * bmc)1734 static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
1735 {
1736 AspeedSoCState *soc = bmc->soc;
1737
1738 /* LM75 is compatible with TMP105 driver */
1739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0),
1740 TYPE_TMP105, 0x4d);
1741 }
1742
aspeed_machine_ast2700a0_evb_class_init(ObjectClass * oc,void * data)1743 static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void *data)
1744 {
1745 MachineClass *mc = MACHINE_CLASS(oc);
1746 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1747
1748 mc->alias = "ast2700-evb";
1749 mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)";
1750 amc->soc_name = "ast2700-a0";
1751 amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
1752 amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
1753 amc->fmc_model = "w25q01jvq";
1754 amc->spi_model = "w25q512jv";
1755 amc->num_cs = 2;
1756 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
1757 amc->uart_default = ASPEED_DEV_UART12;
1758 amc->i2c_init = ast2700_evb_i2c_init;
1759 amc->vbootrom = true;
1760 amc->vbootrom_name = "ast27x0_bootrom.bin";
1761 mc->auto_create_sdcard = true;
1762 mc->default_ram_size = 1 * GiB;
1763 aspeed_machine_class_init_cpus_defaults(mc);
1764 }
1765
aspeed_machine_ast2700a1_evb_class_init(ObjectClass * oc,void * data)1766 static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, void *data)
1767 {
1768 MachineClass *mc = MACHINE_CLASS(oc);
1769 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1770
1771 mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
1772 amc->soc_name = "ast2700-a1";
1773 amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
1774 amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
1775 amc->fmc_model = "w25q01jvq";
1776 amc->spi_model = "w25q512jv";
1777 amc->num_cs = 2;
1778 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
1779 amc->uart_default = ASPEED_DEV_UART12;
1780 amc->i2c_init = ast2700_evb_i2c_init;
1781 amc->vbootrom = true;
1782 amc->vbootrom_name = "ast27x0_bootrom.bin";
1783 mc->auto_create_sdcard = true;
1784 mc->default_ram_size = 1 * GiB;
1785 aspeed_machine_class_init_cpus_defaults(mc);
1786 }
1787 #endif
1788
aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass * oc,void * data)1789 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1790 void *data)
1791 {
1792 MachineClass *mc = MACHINE_CLASS(oc);
1793 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1794
1795 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1796 amc->soc_name = "ast2600-a3";
1797 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1798 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1799 amc->fmc_model = "n25q512a";
1800 amc->spi_model = "n25q512a";
1801 amc->num_cs = 2;
1802 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1803 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1804 mc->auto_create_sdcard = true;
1805 mc->default_ram_size = 1 * GiB;
1806 aspeed_machine_class_init_cpus_defaults(mc);
1807 };
1808
aspeed_machine_qcom_firework_class_init(ObjectClass * oc,void * data)1809 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1810 void *data)
1811 {
1812 MachineClass *mc = MACHINE_CLASS(oc);
1813 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1814
1815 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1816 amc->soc_name = "ast2600-a3";
1817 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1818 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1819 amc->fmc_model = "n25q512a";
1820 amc->spi_model = "n25q512a";
1821 amc->num_cs = 2;
1822 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1823 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1824 mc->auto_create_sdcard = true;
1825 mc->default_ram_size = 1 * GiB;
1826 aspeed_machine_class_init_cpus_defaults(mc);
1827 };
1828
1829 static const TypeInfo aspeed_machine_types[] = {
1830 {
1831 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1832 .parent = TYPE_ASPEED_MACHINE,
1833 .class_init = aspeed_machine_palmetto_class_init,
1834 }, {
1835 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1836 .parent = TYPE_ASPEED_MACHINE,
1837 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1838 }, {
1839 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1840 .parent = TYPE_ASPEED_MACHINE,
1841 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
1842 }, {
1843 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1844 .parent = TYPE_ASPEED_MACHINE,
1845 .class_init = aspeed_machine_ast2500_evb_class_init,
1846 }, {
1847 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1848 .parent = TYPE_ASPEED_MACHINE,
1849 .class_init = aspeed_machine_romulus_class_init,
1850 }, {
1851 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1852 .parent = TYPE_ASPEED_MACHINE,
1853 .class_init = aspeed_machine_sonorapass_class_init,
1854 }, {
1855 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1856 .parent = TYPE_ASPEED_MACHINE,
1857 .class_init = aspeed_machine_witherspoon_class_init,
1858 }, {
1859 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1860 .parent = TYPE_ASPEED_MACHINE,
1861 .class_init = aspeed_machine_ast2600_evb_class_init,
1862 }, {
1863 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1864 .parent = TYPE_ASPEED_MACHINE,
1865 .class_init = aspeed_machine_yosemitev2_class_init,
1866 }, {
1867 .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
1868 .parent = TYPE_ASPEED_MACHINE,
1869 .class_init = aspeed_machine_tiogapass_class_init,
1870 }, {
1871 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1872 .parent = TYPE_ASPEED_MACHINE,
1873 .class_init = aspeed_machine_g220a_class_init,
1874 }, {
1875 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1876 .parent = TYPE_ASPEED_MACHINE,
1877 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
1878 }, {
1879 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1880 .parent = TYPE_ASPEED_MACHINE,
1881 .class_init = aspeed_machine_qcom_firework_class_init,
1882 }, {
1883 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1884 .parent = TYPE_ASPEED_MACHINE,
1885 .class_init = aspeed_machine_fp5280g2_class_init,
1886 }, {
1887 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1888 .parent = TYPE_ASPEED_MACHINE,
1889 .class_init = aspeed_machine_quanta_q71l_class_init,
1890 }, {
1891 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1892 .parent = TYPE_ASPEED_MACHINE,
1893 .class_init = aspeed_machine_rainier_class_init,
1894 }, {
1895 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1896 .parent = TYPE_ASPEED_MACHINE,
1897 .class_init = aspeed_machine_fuji_class_init,
1898 }, {
1899 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1900 .parent = TYPE_ASPEED_MACHINE,
1901 .class_init = aspeed_machine_bletchley_class_init,
1902 }, {
1903 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1904 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1905 .class_init = aspeed_machine_fby35_class_init,
1906 }, {
1907 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1908 .parent = TYPE_ASPEED_MACHINE,
1909 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
1910 #ifdef TARGET_AARCH64
1911 }, {
1912 .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
1913 .parent = TYPE_ASPEED_MACHINE,
1914 .class_init = aspeed_machine_ast2700a0_evb_class_init,
1915 }, {
1916 .name = MACHINE_TYPE_NAME("ast2700a1-evb"),
1917 .parent = TYPE_ASPEED_MACHINE,
1918 .class_init = aspeed_machine_ast2700a1_evb_class_init,
1919 #endif
1920 }, {
1921 .name = TYPE_ASPEED_MACHINE,
1922 .parent = TYPE_MACHINE,
1923 .instance_size = sizeof(AspeedMachineState),
1924 .instance_init = aspeed_machine_instance_init,
1925 .class_size = sizeof(AspeedMachineClass),
1926 .class_init = aspeed_machine_class_init,
1927 .abstract = true,
1928 }
1929 };
1930
1931 DEFINE_TYPES(aspeed_machine_types)
1932