xref: /openbmc/qemu/hw/misc/aspeed_hace.c (revision df9168b01941d1311d4231439491614b00695344)
1 /*
2  * ASPEED Hash and Crypto Engine
3  *
4  * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates
5  * Copyright (C) 2021 IBM Corp.
6  *
7  * Joel Stanley <joel@jms.id.au>
8  *
9  * SPDX-License-Identifier: GPL-2.0-or-later
10  */
11 
12 #include "qemu/osdep.h"
13 #include "qemu/log.h"
14 #include "qemu/error-report.h"
15 #include "hw/misc/aspeed_hace.h"
16 #include "qapi/error.h"
17 #include "migration/vmstate.h"
18 #include "crypto/hash.h"
19 #include "hw/qdev-properties.h"
20 #include "hw/irq.h"
21 
22 #define R_CRYPT_CMD     (0x10 / 4)
23 
24 #define R_STATUS        (0x1c / 4)
25 #define HASH_IRQ        BIT(9)
26 #define CRYPT_IRQ       BIT(12)
27 #define TAG_IRQ         BIT(15)
28 
29 #define R_HASH_SRC      (0x20 / 4)
30 #define R_HASH_DEST     (0x24 / 4)
31 #define R_HASH_KEY_BUFF (0x28 / 4)
32 #define R_HASH_SRC_LEN  (0x2c / 4)
33 
34 #define R_HASH_CMD      (0x30 / 4)
35 /* Hash algorithm selection */
36 #define  HASH_ALGO_MASK                 (BIT(4) | BIT(5) | BIT(6))
37 #define  HASH_ALGO_MD5                  0
38 #define  HASH_ALGO_SHA1                 BIT(5)
39 #define  HASH_ALGO_SHA224               BIT(6)
40 #define  HASH_ALGO_SHA256               (BIT(4) | BIT(6))
41 #define  HASH_ALGO_SHA512_SERIES        (BIT(5) | BIT(6))
42 /* SHA512 algorithm selection */
43 #define  SHA512_HASH_ALGO_MASK          (BIT(10) | BIT(11) | BIT(12))
44 #define  HASH_ALGO_SHA512_SHA512        0
45 #define  HASH_ALGO_SHA512_SHA384        BIT(10)
46 #define  HASH_ALGO_SHA512_SHA256        BIT(11)
47 #define  HASH_ALGO_SHA512_SHA224        (BIT(10) | BIT(11))
48 /* HMAC modes */
49 #define  HASH_HMAC_MASK                 (BIT(7) | BIT(8))
50 #define  HASH_DIGEST                    0
51 #define  HASH_DIGEST_HMAC               BIT(7)
52 #define  HASH_DIGEST_ACCUM              BIT(8)
53 #define  HASH_HMAC_KEY                  (BIT(7) | BIT(8))
54 /* Cascaded operation modes */
55 #define  HASH_ONLY                      0
56 #define  HASH_ONLY2                     BIT(0)
57 #define  HASH_CRYPT_THEN_HASH           BIT(1)
58 #define  HASH_HASH_THEN_CRYPT           (BIT(0) | BIT(1))
59 /* Other cmd bits */
60 #define  HASH_IRQ_EN                    BIT(9)
61 #define  HASH_SG_EN                     BIT(18)
62 /* Scatter-gather data list */
63 #define SG_LIST_LEN_SIZE                4
64 #define SG_LIST_LEN_MASK                0x0FFFFFFF
65 #define SG_LIST_LEN_LAST                BIT(31)
66 #define SG_LIST_ADDR_SIZE               4
67 #define SG_LIST_ADDR_MASK               0x7FFFFFFF
68 #define SG_LIST_ENTRY_SIZE              (SG_LIST_LEN_SIZE + SG_LIST_ADDR_SIZE)
69 
70 static const struct {
71     uint32_t mask;
72     QCryptoHashAlgo algo;
73 } hash_algo_map[] = {
74     { HASH_ALGO_MD5, QCRYPTO_HASH_ALGO_MD5 },
75     { HASH_ALGO_SHA1, QCRYPTO_HASH_ALGO_SHA1 },
76     { HASH_ALGO_SHA224, QCRYPTO_HASH_ALGO_SHA224 },
77     { HASH_ALGO_SHA256, QCRYPTO_HASH_ALGO_SHA256 },
78     { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512, QCRYPTO_HASH_ALGO_SHA512 },
79     { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384, QCRYPTO_HASH_ALGO_SHA384 },
80     { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256, QCRYPTO_HASH_ALGO_SHA256 },
81 };
82 
hash_algo_lookup(uint32_t reg)83 static int hash_algo_lookup(uint32_t reg)
84 {
85     int i;
86 
87     reg &= HASH_ALGO_MASK | SHA512_HASH_ALGO_MASK;
88 
89     for (i = 0; i < ARRAY_SIZE(hash_algo_map); i++) {
90         if (reg == hash_algo_map[i].mask) {
91             return hash_algo_map[i].algo;
92         }
93     }
94 
95     return -1;
96 }
97 
98 /**
99  * Check whether the request contains padding message.
100  *
101  * @param s             aspeed hace state object
102  * @param iov           iov of current request
103  * @param req_len       length of the current request
104  * @param total_msg_len length of all acc_mode requests(excluding padding msg)
105  * @param pad_offset    start offset of padding message
106  */
has_padding(AspeedHACEState * s,struct iovec * iov,hwaddr req_len,uint32_t * total_msg_len,uint32_t * pad_offset)107 static bool has_padding(AspeedHACEState *s, struct iovec *iov,
108                         hwaddr req_len, uint32_t *total_msg_len,
109                         uint32_t *pad_offset)
110 {
111     *total_msg_len = (uint32_t)(ldq_be_p(iov->iov_base + req_len - 8) / 8);
112     /*
113      * SG_LIST_LEN_LAST asserted in the request length doesn't mean it is the
114      * last request. The last request should contain padding message.
115      * We check whether message contains padding by
116      *   1. Get total message length. If the current message contains
117      *      padding, the last 8 bytes are total message length.
118      *   2. Check whether the total message length is valid.
119      *      If it is valid, the value should less than or equal to
120      *      total_req_len.
121      *   3. Current request len - padding_size to get padding offset.
122      *      The padding message's first byte should be 0x80
123      */
124     if (*total_msg_len <= s->total_req_len) {
125         uint32_t padding_size = s->total_req_len - *total_msg_len;
126         uint8_t *padding = iov->iov_base;
127 
128         if (padding_size > req_len) {
129             return false;
130         }
131 
132         *pad_offset = req_len - padding_size;
133         if (padding[*pad_offset] == 0x80) {
134             return true;
135         }
136     }
137 
138     return false;
139 }
140 
reconstruct_iov(AspeedHACEState * s,struct iovec * iov,int id,uint32_t * pad_offset)141 static int reconstruct_iov(AspeedHACEState *s, struct iovec *iov, int id,
142                            uint32_t *pad_offset)
143 {
144     int i, iov_count;
145     if (*pad_offset != 0) {
146         s->iov_cache[s->iov_count].iov_base = iov[id].iov_base;
147         s->iov_cache[s->iov_count].iov_len = *pad_offset;
148         ++s->iov_count;
149     }
150     for (i = 0; i < s->iov_count; i++) {
151         iov[i].iov_base = s->iov_cache[i].iov_base;
152         iov[i].iov_len = s->iov_cache[i].iov_len;
153     }
154     iov_count = s->iov_count;
155     s->iov_count = 0;
156     s->total_req_len = 0;
157     return iov_count;
158 }
159 
do_hash_operation(AspeedHACEState * s,int algo,bool sg_mode,bool acc_mode)160 static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
161                               bool acc_mode)
162 {
163     struct iovec iov[ASPEED_HACE_MAX_SG];
164     uint32_t total_msg_len;
165     uint32_t pad_offset;
166     g_autofree uint8_t *digest_buf = NULL;
167     size_t digest_len = 0;
168     bool sg_acc_mode_final_request = false;
169     int i;
170     void *haddr;
171     Error *local_err = NULL;
172 
173     if (acc_mode && s->hash_ctx == NULL) {
174         s->hash_ctx = qcrypto_hash_new(algo, &local_err);
175         if (s->hash_ctx == NULL) {
176             qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash failed : %s",
177                           error_get_pretty(local_err));
178             error_free(local_err);
179             return;
180         }
181     }
182 
183     if (sg_mode) {
184         uint32_t len = 0;
185 
186         for (i = 0; !(len & SG_LIST_LEN_LAST); i++) {
187             uint32_t addr, src;
188             hwaddr plen;
189 
190             if (i == ASPEED_HACE_MAX_SG) {
191                 qemu_log_mask(LOG_GUEST_ERROR,
192                         "aspeed_hace: guest failed to set end of sg list marker\n");
193                 break;
194             }
195 
196             src = s->regs[R_HASH_SRC] + (i * SG_LIST_ENTRY_SIZE);
197 
198             len = address_space_ldl_le(&s->dram_as, src,
199                                        MEMTXATTRS_UNSPECIFIED, NULL);
200 
201             addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE,
202                                         MEMTXATTRS_UNSPECIFIED, NULL);
203             addr &= SG_LIST_ADDR_MASK;
204 
205             plen = len & SG_LIST_LEN_MASK;
206             haddr = address_space_map(&s->dram_as, addr, &plen, false,
207                                       MEMTXATTRS_UNSPECIFIED);
208             if (haddr == NULL) {
209                 qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
210                 return;
211             }
212             iov[i].iov_base = haddr;
213             if (acc_mode) {
214                 s->total_req_len += plen;
215 
216                 if (has_padding(s, &iov[i], plen, &total_msg_len,
217                                 &pad_offset)) {
218                     /* Padding being present indicates the final request */
219                     sg_acc_mode_final_request = true;
220                     iov[i].iov_len = pad_offset;
221                 } else {
222                     iov[i].iov_len = plen;
223                 }
224             } else {
225                 iov[i].iov_len = plen;
226             }
227         }
228     } else {
229         hwaddr len = s->regs[R_HASH_SRC_LEN];
230 
231         haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
232                                   &len, false, MEMTXATTRS_UNSPECIFIED);
233         if (haddr == NULL) {
234             qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
235             return;
236         }
237         iov[0].iov_base = haddr;
238         iov[0].iov_len = len;
239         i = 1;
240 
241         if (s->iov_count) {
242             /*
243              * In aspeed sdk kernel driver, sg_mode is disabled in hash_final().
244              * Thus if we received a request with sg_mode disabled, it is
245              * required to check whether cache is empty. If no, we should
246              * combine cached iov and the current iov.
247              */
248             s->total_req_len += len;
249             if (has_padding(s, iov, len, &total_msg_len, &pad_offset)) {
250                 i = reconstruct_iov(s, iov, 0, &pad_offset);
251             }
252         }
253     }
254 
255     if (acc_mode) {
256         if (qcrypto_hash_updatev(s->hash_ctx, iov, i, &local_err) < 0) {
257             qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash update failed : %s",
258                           error_get_pretty(local_err));
259             error_free(local_err);
260             return;
261         }
262 
263         if (sg_acc_mode_final_request) {
264             if (qcrypto_hash_finalize_bytes(s->hash_ctx, &digest_buf,
265                                             &digest_len, &local_err)) {
266                 qemu_log_mask(LOG_GUEST_ERROR,
267                               "qcrypto hash finalize failed : %s",
268                               error_get_pretty(local_err));
269                 error_free(local_err);
270                 local_err = NULL;
271             }
272 
273             qcrypto_hash_free(s->hash_ctx);
274 
275             s->hash_ctx = NULL;
276             s->iov_count = 0;
277             s->total_req_len = 0;
278         }
279     } else if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf,
280                                    &digest_len, &local_err) < 0) {
281         qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash bytesv failed : %s",
282                       error_get_pretty(local_err));
283         error_free(local_err);
284         return;
285     }
286 
287     if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST],
288                             MEMTXATTRS_UNSPECIFIED,
289                             digest_buf, digest_len)) {
290         qemu_log_mask(LOG_GUEST_ERROR,
291                       "aspeed_hace: address space write failed\n");
292     }
293 
294     for (; i > 0; i--) {
295         address_space_unmap(&s->dram_as, iov[i - 1].iov_base,
296                             iov[i - 1].iov_len, false,
297                             iov[i - 1].iov_len);
298     }
299 
300     /*
301      * Set status bits to indicate completion. Testing shows hardware sets
302      * these irrespective of HASH_IRQ_EN.
303      */
304     s->regs[R_STATUS] |= HASH_IRQ;
305 }
306 
aspeed_hace_read(void * opaque,hwaddr addr,unsigned int size)307 static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int size)
308 {
309     AspeedHACEState *s = ASPEED_HACE(opaque);
310 
311     addr >>= 2;
312 
313     if (addr >= ASPEED_HACE_NR_REGS) {
314         qemu_log_mask(LOG_GUEST_ERROR,
315                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
316                       __func__, addr << 2);
317         return 0;
318     }
319 
320     return s->regs[addr];
321 }
322 
aspeed_hace_write(void * opaque,hwaddr addr,uint64_t data,unsigned int size)323 static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
324                               unsigned int size)
325 {
326     AspeedHACEState *s = ASPEED_HACE(opaque);
327     AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s);
328 
329     addr >>= 2;
330 
331     if (addr >= ASPEED_HACE_NR_REGS) {
332         qemu_log_mask(LOG_GUEST_ERROR,
333                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
334                       __func__, addr << 2);
335         return;
336     }
337 
338     switch (addr) {
339     case R_STATUS:
340         if (data & HASH_IRQ) {
341             data &= ~HASH_IRQ;
342 
343             if (s->regs[addr] & HASH_IRQ) {
344                 qemu_irq_lower(s->irq);
345             }
346         }
347         break;
348     case R_HASH_SRC:
349         data &= ahc->src_mask;
350         break;
351     case R_HASH_DEST:
352         data &= ahc->dest_mask;
353         break;
354     case R_HASH_KEY_BUFF:
355         data &= ahc->key_mask;
356         break;
357     case R_HASH_SRC_LEN:
358         data &= 0x0FFFFFFF;
359         break;
360     case R_HASH_CMD: {
361         int algo;
362         data &= ahc->hash_mask;
363 
364         if ((data & HASH_DIGEST_HMAC)) {
365             qemu_log_mask(LOG_UNIMP,
366                           "%s: HMAC mode not implemented\n",
367                           __func__);
368         }
369         if (data & BIT(1)) {
370             qemu_log_mask(LOG_UNIMP,
371                           "%s: Cascaded mode not implemented\n",
372                           __func__);
373         }
374         algo = hash_algo_lookup(data);
375         if (algo < 0) {
376                 qemu_log_mask(LOG_GUEST_ERROR,
377                         "%s: Invalid hash algorithm selection 0x%"PRIx64"\n",
378                         __func__, data & ahc->hash_mask);
379                 break;
380         }
381         do_hash_operation(s, algo, data & HASH_SG_EN,
382                 ((data & HASH_HMAC_MASK) == HASH_DIGEST_ACCUM));
383 
384         if (data & HASH_IRQ_EN) {
385             qemu_irq_raise(s->irq);
386         }
387         break;
388     }
389     case R_CRYPT_CMD:
390         qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n",
391                        __func__);
392         break;
393     default:
394         break;
395     }
396 
397     s->regs[addr] = data;
398 }
399 
400 static const MemoryRegionOps aspeed_hace_ops = {
401     .read = aspeed_hace_read,
402     .write = aspeed_hace_write,
403     .endianness = DEVICE_LITTLE_ENDIAN,
404     .valid = {
405         .min_access_size = 1,
406         .max_access_size = 4,
407     },
408 };
409 
aspeed_hace_reset(DeviceState * dev)410 static void aspeed_hace_reset(DeviceState *dev)
411 {
412     struct AspeedHACEState *s = ASPEED_HACE(dev);
413 
414     if (s->hash_ctx != NULL) {
415         qcrypto_hash_free(s->hash_ctx);
416         s->hash_ctx = NULL;
417     }
418 
419     memset(s->regs, 0, sizeof(s->regs));
420     s->iov_count = 0;
421     s->total_req_len = 0;
422 }
423 
aspeed_hace_realize(DeviceState * dev,Error ** errp)424 static void aspeed_hace_realize(DeviceState *dev, Error **errp)
425 {
426     AspeedHACEState *s = ASPEED_HACE(dev);
427     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
428 
429     sysbus_init_irq(sbd, &s->irq);
430 
431     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_hace_ops, s,
432             TYPE_ASPEED_HACE, 0x1000);
433 
434     if (!s->dram_mr) {
435         error_setg(errp, TYPE_ASPEED_HACE ": 'dram' link not set");
436         return;
437     }
438 
439     address_space_init(&s->dram_as, s->dram_mr, "dram");
440 
441     sysbus_init_mmio(sbd, &s->iomem);
442 }
443 
444 static Property aspeed_hace_properties[] = {
445     DEFINE_PROP_LINK("dram", AspeedHACEState, dram_mr,
446                      TYPE_MEMORY_REGION, MemoryRegion *),
447     DEFINE_PROP_END_OF_LIST(),
448 };
449 
450 
451 static const VMStateDescription vmstate_aspeed_hace = {
452     .name = TYPE_ASPEED_HACE,
453     .version_id = 1,
454     .minimum_version_id = 1,
455     .fields = (const VMStateField[]) {
456         VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS),
457         VMSTATE_UINT32(total_req_len, AspeedHACEState),
458         VMSTATE_UINT32(iov_count, AspeedHACEState),
459         VMSTATE_END_OF_LIST(),
460     }
461 };
462 
aspeed_hace_class_init(ObjectClass * klass,void * data)463 static void aspeed_hace_class_init(ObjectClass *klass, void *data)
464 {
465     DeviceClass *dc = DEVICE_CLASS(klass);
466 
467     dc->realize = aspeed_hace_realize;
468     device_class_set_legacy_reset(dc, aspeed_hace_reset);
469     device_class_set_props(dc, aspeed_hace_properties);
470     dc->vmsd = &vmstate_aspeed_hace;
471 }
472 
473 static const TypeInfo aspeed_hace_info = {
474     .name = TYPE_ASPEED_HACE,
475     .parent = TYPE_SYS_BUS_DEVICE,
476     .instance_size = sizeof(AspeedHACEState),
477     .class_init = aspeed_hace_class_init,
478     .class_size = sizeof(AspeedHACEClass)
479 };
480 
aspeed_ast2400_hace_class_init(ObjectClass * klass,void * data)481 static void aspeed_ast2400_hace_class_init(ObjectClass *klass, void *data)
482 {
483     DeviceClass *dc = DEVICE_CLASS(klass);
484     AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
485 
486     dc->desc = "AST2400 Hash and Crypto Engine";
487 
488     ahc->src_mask = 0x0FFFFFFF;
489     ahc->dest_mask = 0x0FFFFFF8;
490     ahc->key_mask = 0x0FFFFFC0;
491     ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */
492 }
493 
494 static const TypeInfo aspeed_ast2400_hace_info = {
495     .name = TYPE_ASPEED_AST2400_HACE,
496     .parent = TYPE_ASPEED_HACE,
497     .class_init = aspeed_ast2400_hace_class_init,
498 };
499 
aspeed_ast2500_hace_class_init(ObjectClass * klass,void * data)500 static void aspeed_ast2500_hace_class_init(ObjectClass *klass, void *data)
501 {
502     DeviceClass *dc = DEVICE_CLASS(klass);
503     AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
504 
505     dc->desc = "AST2500 Hash and Crypto Engine";
506 
507     ahc->src_mask = 0x3fffffff;
508     ahc->dest_mask = 0x3ffffff8;
509     ahc->key_mask = 0x3FFFFFC0;
510     ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */
511 }
512 
513 static const TypeInfo aspeed_ast2500_hace_info = {
514     .name = TYPE_ASPEED_AST2500_HACE,
515     .parent = TYPE_ASPEED_HACE,
516     .class_init = aspeed_ast2500_hace_class_init,
517 };
518 
aspeed_ast2600_hace_class_init(ObjectClass * klass,void * data)519 static void aspeed_ast2600_hace_class_init(ObjectClass *klass, void *data)
520 {
521     DeviceClass *dc = DEVICE_CLASS(klass);
522     AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
523 
524     dc->desc = "AST2600 Hash and Crypto Engine";
525 
526     ahc->src_mask = 0x7FFFFFFF;
527     ahc->dest_mask = 0x7FFFFFF8;
528     ahc->key_mask = 0x7FFFFFF8;
529     ahc->hash_mask = 0x00147FFF;
530 }
531 
532 static const TypeInfo aspeed_ast2600_hace_info = {
533     .name = TYPE_ASPEED_AST2600_HACE,
534     .parent = TYPE_ASPEED_HACE,
535     .class_init = aspeed_ast2600_hace_class_init,
536 };
537 
aspeed_ast1030_hace_class_init(ObjectClass * klass,void * data)538 static void aspeed_ast1030_hace_class_init(ObjectClass *klass, void *data)
539 {
540     DeviceClass *dc = DEVICE_CLASS(klass);
541     AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
542 
543     dc->desc = "AST1030 Hash and Crypto Engine";
544 
545     ahc->src_mask = 0x7FFFFFFF;
546     ahc->dest_mask = 0x7FFFFFF8;
547     ahc->key_mask = 0x7FFFFFF8;
548     ahc->hash_mask = 0x00147FFF;
549 }
550 
551 static const TypeInfo aspeed_ast1030_hace_info = {
552     .name = TYPE_ASPEED_AST1030_HACE,
553     .parent = TYPE_ASPEED_HACE,
554     .class_init = aspeed_ast1030_hace_class_init,
555 };
556 
aspeed_hace_register_types(void)557 static void aspeed_hace_register_types(void)
558 {
559     type_register_static(&aspeed_ast2400_hace_info);
560     type_register_static(&aspeed_ast2500_hace_info);
561     type_register_static(&aspeed_ast2600_hace_info);
562     type_register_static(&aspeed_ast1030_hace_info);
563     type_register_static(&aspeed_hace_info);
564 }
565 
566 type_init(aspeed_hace_register_types);
567