1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "amdgpu_dm_psr.h"
27 #include "dc_dmub_srv.h"
28 #include "dc.h"
29 #include "dm_helpers.h"
30 #include "amdgpu_dm.h"
31 #include "modules/power/power_helpers.h"
32
link_supports_psrsu(struct dc_link * link)33 static bool link_supports_psrsu(struct dc_link *link)
34 {
35 struct dc *dc = link->ctx->dc;
36
37 if (!dc->caps.dmcub_support)
38 return false;
39
40 if (dc->ctx->dce_version < DCN_VERSION_3_1)
41 return false;
42
43 if (!is_psr_su_specific_panel(link))
44 return false;
45
46 if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
47 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
48 return false;
49
50 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED &&
51 !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)
52 return false;
53
54 /* Temporarily disable PSR-SU to avoid glitches */
55 return false;
56 }
57
58 /*
59 * amdgpu_dm_set_psr_caps() - set link psr capabilities
60 * @link: link
61 *
62 */
amdgpu_dm_set_psr_caps(struct dc_link * link)63 void amdgpu_dm_set_psr_caps(struct dc_link *link)
64 {
65 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) {
66 link->psr_settings.psr_feature_enabled = false;
67 return;
68 }
69
70 if (link->type == dc_connection_none) {
71 link->psr_settings.psr_feature_enabled = false;
72 return;
73 }
74
75 if (link->dpcd_caps.psr_info.psr_version == 0) {
76 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
77 link->psr_settings.psr_feature_enabled = false;
78
79 } else {
80 if (link_supports_psrsu(link))
81 link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
82 else
83 link->psr_settings.psr_version = DC_PSR_VERSION_1;
84
85 link->psr_settings.psr_feature_enabled = true;
86 }
87
88 DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",
89 link->psr_settings.psr_feature_enabled,
90 link->psr_settings.psr_version,
91 link->dpcd_caps.psr_info.psr_version,
92 link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
93 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap);
94
95 }
96
97 /*
98 * amdgpu_dm_link_setup_psr() - configure psr link
99 * @stream: stream state
100 *
101 * Return: true if success
102 */
amdgpu_dm_link_setup_psr(struct dc_stream_state * stream)103 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
104 {
105 struct dc_link *link = NULL;
106 struct psr_config psr_config = {0};
107 struct psr_context psr_context = {0};
108 struct dc *dc = NULL;
109 bool ret = false;
110
111 if (stream == NULL)
112 return false;
113
114 link = stream->link;
115 dc = link->ctx->dc;
116
117 if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
118 mod_power_calc_psr_configs(&psr_config, link, stream);
119
120 /* linux DM specific updating for psr config fields */
121 psr_config.allow_smu_optimizations =
122 (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) &&
123 mod_power_only_edp(dc->current_state, stream);
124 psr_config.allow_multi_disp_optimizations =
125 (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
126
127 if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config))
128 return false;
129
130 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
131
132 }
133 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled);
134
135 return ret;
136 }
137
138 /*
139 * amdgpu_dm_psr_enable() - enable psr f/w
140 * @stream: stream state
141 *
142 * Return: true if success
143 */
amdgpu_dm_psr_enable(struct dc_stream_state * stream)144 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
145 {
146 struct dc_link *link = stream->link;
147 unsigned int vsync_rate_hz = 0;
148 struct dc_static_screen_params params = {0};
149 /* Calculate number of static frames before generating interrupt to
150 * enter PSR.
151 */
152 // Init fail safe of 2 frames static
153 unsigned int num_frames_static = 2;
154 unsigned int power_opt = 0;
155 bool psr_enable = true;
156
157 DRM_DEBUG_DRIVER("Enabling psr...\n");
158
159 vsync_rate_hz = div64_u64(div64_u64((
160 stream->timing.pix_clk_100hz * 100),
161 stream->timing.v_total),
162 stream->timing.h_total);
163
164 /* Round up
165 * Calculate number of frames such that at least 30 ms of time has
166 * passed.
167 */
168 if (vsync_rate_hz != 0) {
169 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
170
171 num_frames_static = (30000 / frame_time_microsec) + 1;
172 }
173
174 params.triggers.cursor_update = true;
175 params.triggers.overlay_update = true;
176 params.triggers.surface_update = true;
177 params.num_frames = num_frames_static;
178
179 dc_stream_set_static_screen_params(link->ctx->dc,
180 &stream, 1,
181 ¶ms);
182
183 /*
184 * Only enable static-screen optimizations for PSR1. For PSR SU, this
185 * causes vstartup interrupt issues, used by amdgpu_dm to send vblank
186 * events.
187 */
188 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
189 power_opt |= psr_power_opt_z10_static_screen;
190
191 return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
192 }
193
194 /*
195 * amdgpu_dm_psr_disable() - disable psr f/w
196 * @stream: stream state
197 *
198 * Return: true if success
199 */
amdgpu_dm_psr_disable(struct dc_stream_state * stream)200 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
201 {
202 unsigned int power_opt = 0;
203 bool psr_enable = false;
204
205 DRM_DEBUG_DRIVER("Disabling psr...\n");
206
207 return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt);
208 }
209
210 /*
211 * amdgpu_dm_psr_disable() - disable psr f/w
212 * if psr is enabled on any stream
213 *
214 * Return: true if success
215 */
amdgpu_dm_psr_disable_all(struct amdgpu_display_manager * dm)216 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
217 {
218 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
219 return dc_set_psr_allow_active(dm->dc, false);
220 }
221
222