1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Shared support code for AMD K8 northbridges and derivatives.
4 * Copyright 2006 Andi Kleen, SUSE Labs.
5 */
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/types.h>
10 #include <linux/slab.h>
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/export.h>
14 #include <linux/spinlock.h>
15 #include <linux/pci_ids.h>
16 #include <asm/amd_nb.h>
17
18 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
22 #define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
23 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
24 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
25 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
26 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
27 #define PCI_DEVICE_ID_AMD_1AH_M00H_ROOT 0x153a
28 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
29 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
30 #define PCI_DEVICE_ID_AMD_MI200_ROOT 0x14bb
31
32 #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
33 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
34 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
35 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
36 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
37 #define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4 0x1728
38 #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
39 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
40 #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
41 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
42 #define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
43 #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
44 #define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4 0x12fc
45 #define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4 0x12c4
46 #define PCI_DEVICE_ID_AMD_MI200_DF_F4 0x14d4
47
48 /* Protect the PCI config register pairs used for SMN. */
49 static DEFINE_MUTEX(smn_mutex);
50
51 static u32 *flush_words;
52
53 static const struct pci_device_id amd_root_ids[] = {
54 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
55 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
56 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
57 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
58 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
59 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
60 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_ROOT) },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
63 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_ROOT) },
64 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_ROOT) },
67 {}
68 };
69
70 #define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
71
72 static const struct pci_device_id amd_nb_misc_ids[] = {
73 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
74 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
75 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
76 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
77 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
78 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
79 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
80 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
81 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
82 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
83 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
84 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
85 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
86 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
87 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
88 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
89 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
90 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
91 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
92 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
93 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
94 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
95 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
96 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
97 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3) },
98 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3) },
99 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F3) },
100 {}
101 };
102
103 static const struct pci_device_id amd_nb_link_ids[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
105 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
106 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
107 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
108 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
109 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
110 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
111 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
112 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
113 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
114 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4) },
115 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
116 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
117 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
118 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
119 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F4) },
120 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F4) },
121 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F4) },
122 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
123 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4) },
124 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F4) },
125 {}
126 };
127
128 static const struct pci_device_id hygon_root_ids[] = {
129 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
130 {}
131 };
132
133 static const struct pci_device_id hygon_nb_misc_ids[] = {
134 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
135 {}
136 };
137
138 static const struct pci_device_id hygon_nb_link_ids[] = {
139 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
140 {}
141 };
142
143 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
144 { 0x00, 0x18, 0x20 },
145 { 0xff, 0x00, 0x20 },
146 { 0xfe, 0x00, 0x20 },
147 { }
148 };
149
150 static struct amd_northbridge_info amd_northbridges;
151
amd_nb_num(void)152 u16 amd_nb_num(void)
153 {
154 return amd_northbridges.num;
155 }
156 EXPORT_SYMBOL_GPL(amd_nb_num);
157
amd_nb_has_feature(unsigned int feature)158 bool amd_nb_has_feature(unsigned int feature)
159 {
160 return ((amd_northbridges.flags & feature) == feature);
161 }
162 EXPORT_SYMBOL_GPL(amd_nb_has_feature);
163
node_to_amd_nb(int node)164 struct amd_northbridge *node_to_amd_nb(int node)
165 {
166 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
167 }
168 EXPORT_SYMBOL_GPL(node_to_amd_nb);
169
next_northbridge(struct pci_dev * dev,const struct pci_device_id * ids)170 static struct pci_dev *next_northbridge(struct pci_dev *dev,
171 const struct pci_device_id *ids)
172 {
173 do {
174 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
175 if (!dev)
176 break;
177 } while (!pci_match_id(ids, dev));
178 return dev;
179 }
180
__amd_smn_rw(u16 node,u32 address,u32 * value,bool write)181 static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
182 {
183 struct pci_dev *root;
184 int err = -ENODEV;
185
186 if (node >= amd_northbridges.num)
187 goto out;
188
189 root = node_to_amd_nb(node)->root;
190 if (!root)
191 goto out;
192
193 mutex_lock(&smn_mutex);
194
195 err = pci_write_config_dword(root, 0x60, address);
196 if (err) {
197 pr_warn("Error programming SMN address 0x%x.\n", address);
198 goto out_unlock;
199 }
200
201 err = (write ? pci_write_config_dword(root, 0x64, *value)
202 : pci_read_config_dword(root, 0x64, value));
203 if (err)
204 pr_warn("Error %s SMN address 0x%x.\n",
205 (write ? "writing to" : "reading from"), address);
206
207 out_unlock:
208 mutex_unlock(&smn_mutex);
209
210 out:
211 return err;
212 }
213
amd_smn_read(u16 node,u32 address,u32 * value)214 int amd_smn_read(u16 node, u32 address, u32 *value)
215 {
216 int err = __amd_smn_rw(node, address, value, false);
217
218 if (PCI_POSSIBLE_ERROR(*value)) {
219 err = -ENODEV;
220 *value = 0;
221 }
222
223 return err;
224 }
225 EXPORT_SYMBOL_GPL(amd_smn_read);
226
amd_smn_write(u16 node,u32 address,u32 value)227 int amd_smn_write(u16 node, u32 address, u32 value)
228 {
229 return __amd_smn_rw(node, address, &value, true);
230 }
231 EXPORT_SYMBOL_GPL(amd_smn_write);
232
233
amd_cache_northbridges(void)234 static int amd_cache_northbridges(void)
235 {
236 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
237 const struct pci_device_id *link_ids = amd_nb_link_ids;
238 const struct pci_device_id *root_ids = amd_root_ids;
239 struct pci_dev *root, *misc, *link;
240 struct amd_northbridge *nb;
241 u16 roots_per_misc = 0;
242 u16 misc_count = 0;
243 u16 root_count = 0;
244 u16 i, j;
245
246 if (amd_northbridges.num)
247 return 0;
248
249 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
250 root_ids = hygon_root_ids;
251 misc_ids = hygon_nb_misc_ids;
252 link_ids = hygon_nb_link_ids;
253 }
254
255 misc = NULL;
256 while ((misc = next_northbridge(misc, misc_ids)))
257 misc_count++;
258
259 if (!misc_count)
260 return -ENODEV;
261
262 root = NULL;
263 while ((root = next_northbridge(root, root_ids)))
264 root_count++;
265
266 if (root_count) {
267 roots_per_misc = root_count / misc_count;
268
269 /*
270 * There should be _exactly_ N roots for each DF/SMN
271 * interface.
272 */
273 if (!roots_per_misc || (root_count % roots_per_misc)) {
274 pr_info("Unsupported AMD DF/PCI configuration found\n");
275 return -ENODEV;
276 }
277 }
278
279 nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
280 if (!nb)
281 return -ENOMEM;
282
283 amd_northbridges.nb = nb;
284 amd_northbridges.num = misc_count;
285
286 link = misc = root = NULL;
287 for (i = 0; i < amd_northbridges.num; i++) {
288 node_to_amd_nb(i)->root = root =
289 next_northbridge(root, root_ids);
290 node_to_amd_nb(i)->misc = misc =
291 next_northbridge(misc, misc_ids);
292 node_to_amd_nb(i)->link = link =
293 next_northbridge(link, link_ids);
294
295 /*
296 * If there are more PCI root devices than data fabric/
297 * system management network interfaces, then the (N)
298 * PCI roots per DF/SMN interface are functionally the
299 * same (for DF/SMN access) and N-1 are redundant. N-1
300 * PCI roots should be skipped per DF/SMN interface so
301 * the following DF/SMN interfaces get mapped to
302 * correct PCI roots.
303 */
304 for (j = 1; j < roots_per_misc; j++)
305 root = next_northbridge(root, root_ids);
306 }
307
308 if (amd_gart_present())
309 amd_northbridges.flags |= AMD_NB_GART;
310
311 /*
312 * Check for L3 cache presence.
313 */
314 if (!cpuid_edx(0x80000006))
315 return 0;
316
317 /*
318 * Some CPU families support L3 Cache Index Disable. There are some
319 * limitations because of E382 and E388 on family 0x10.
320 */
321 if (boot_cpu_data.x86 == 0x10 &&
322 boot_cpu_data.x86_model >= 0x8 &&
323 (boot_cpu_data.x86_model > 0x9 ||
324 boot_cpu_data.x86_stepping >= 0x1))
325 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
326
327 if (boot_cpu_data.x86 == 0x15)
328 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
329
330 /* L3 cache partitioning is supported on family 0x15 */
331 if (boot_cpu_data.x86 == 0x15)
332 amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
333
334 return 0;
335 }
336
337 /*
338 * Ignores subdevice/subvendor but as far as I can figure out
339 * they're useless anyways
340 */
early_is_amd_nb(u32 device)341 bool __init early_is_amd_nb(u32 device)
342 {
343 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
344 const struct pci_device_id *id;
345 u32 vendor = device & 0xffff;
346
347 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
348 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
349 return false;
350
351 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
352 misc_ids = hygon_nb_misc_ids;
353
354 device >>= 16;
355 for (id = misc_ids; id->vendor; id++)
356 if (vendor == id->vendor && device == id->device)
357 return true;
358 return false;
359 }
360
amd_get_mmconfig_range(struct resource * res)361 struct resource *amd_get_mmconfig_range(struct resource *res)
362 {
363 u64 base, msr;
364 unsigned int segn_busn_bits;
365
366 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
367 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
368 return NULL;
369
370 /* Assume CPUs from Fam10h have mmconfig, although not all VMs do */
371 if (boot_cpu_data.x86 < 0x10 ||
372 rdmsrl_safe(MSR_FAM10H_MMIO_CONF_BASE, &msr))
373 return NULL;
374
375 /* mmconfig is not enabled */
376 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
377 return NULL;
378
379 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
380
381 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
382 FAM10H_MMIO_CONF_BUSRANGE_MASK;
383
384 res->flags = IORESOURCE_MEM;
385 res->start = base;
386 res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
387 return res;
388 }
389
amd_get_subcaches(int cpu)390 int amd_get_subcaches(int cpu)
391 {
392 struct pci_dev *link = node_to_amd_nb(topology_die_id(cpu))->link;
393 unsigned int mask;
394
395 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
396 return 0;
397
398 pci_read_config_dword(link, 0x1d4, &mask);
399
400 return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
401 }
402
amd_set_subcaches(int cpu,unsigned long mask)403 int amd_set_subcaches(int cpu, unsigned long mask)
404 {
405 static unsigned int reset, ban;
406 struct amd_northbridge *nb = node_to_amd_nb(topology_die_id(cpu));
407 unsigned int reg;
408 int cuid;
409
410 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
411 return -EINVAL;
412
413 /* if necessary, collect reset state of L3 partitioning and BAN mode */
414 if (reset == 0) {
415 pci_read_config_dword(nb->link, 0x1d4, &reset);
416 pci_read_config_dword(nb->misc, 0x1b8, &ban);
417 ban &= 0x180000;
418 }
419
420 /* deactivate BAN mode if any subcaches are to be disabled */
421 if (mask != 0xf) {
422 pci_read_config_dword(nb->misc, 0x1b8, ®);
423 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
424 }
425
426 cuid = cpu_data(cpu).cpu_core_id;
427 mask <<= 4 * cuid;
428 mask |= (0xf ^ (1 << cuid)) << 26;
429
430 pci_write_config_dword(nb->link, 0x1d4, mask);
431
432 /* reset BAN mode if L3 partitioning returned to reset state */
433 pci_read_config_dword(nb->link, 0x1d4, ®);
434 if (reg == reset) {
435 pci_read_config_dword(nb->misc, 0x1b8, ®);
436 reg &= ~0x180000;
437 pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
438 }
439
440 return 0;
441 }
442
amd_cache_gart(void)443 static void amd_cache_gart(void)
444 {
445 u16 i;
446
447 if (!amd_nb_has_feature(AMD_NB_GART))
448 return;
449
450 flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
451 if (!flush_words) {
452 amd_northbridges.flags &= ~AMD_NB_GART;
453 pr_notice("Cannot initialize GART flush words, GART support disabled\n");
454 return;
455 }
456
457 for (i = 0; i != amd_northbridges.num; i++)
458 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
459 }
460
amd_flush_garts(void)461 void amd_flush_garts(void)
462 {
463 int flushed, i;
464 unsigned long flags;
465 static DEFINE_SPINLOCK(gart_lock);
466
467 if (!amd_nb_has_feature(AMD_NB_GART))
468 return;
469
470 /*
471 * Avoid races between AGP and IOMMU. In theory it's not needed
472 * but I'm not sure if the hardware won't lose flush requests
473 * when another is pending. This whole thing is so expensive anyways
474 * that it doesn't matter to serialize more. -AK
475 */
476 spin_lock_irqsave(&gart_lock, flags);
477 flushed = 0;
478 for (i = 0; i < amd_northbridges.num; i++) {
479 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
480 flush_words[i] | 1);
481 flushed++;
482 }
483 for (i = 0; i < amd_northbridges.num; i++) {
484 u32 w;
485 /* Make sure the hardware actually executed the flush*/
486 for (;;) {
487 pci_read_config_dword(node_to_amd_nb(i)->misc,
488 0x9c, &w);
489 if (!(w & 1))
490 break;
491 cpu_relax();
492 }
493 }
494 spin_unlock_irqrestore(&gart_lock, flags);
495 if (!flushed)
496 pr_notice("nothing to flush?\n");
497 }
498 EXPORT_SYMBOL_GPL(amd_flush_garts);
499
__fix_erratum_688(void * info)500 static void __fix_erratum_688(void *info)
501 {
502 #define MSR_AMD64_IC_CFG 0xC0011021
503
504 msr_set_bit(MSR_AMD64_IC_CFG, 3);
505 msr_set_bit(MSR_AMD64_IC_CFG, 14);
506 }
507
508 /* Apply erratum 688 fix so machines without a BIOS fix work. */
fix_erratum_688(void)509 static __init void fix_erratum_688(void)
510 {
511 struct pci_dev *F4;
512 u32 val;
513
514 if (boot_cpu_data.x86 != 0x14)
515 return;
516
517 if (!amd_northbridges.num)
518 return;
519
520 F4 = node_to_amd_nb(0)->link;
521 if (!F4)
522 return;
523
524 if (pci_read_config_dword(F4, 0x164, &val))
525 return;
526
527 if (val & BIT(2))
528 return;
529
530 on_each_cpu(__fix_erratum_688, NULL, 0);
531
532 pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
533 }
534
init_amd_nbs(void)535 static __init int init_amd_nbs(void)
536 {
537 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
538 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
539 return 0;
540
541 amd_cache_northbridges();
542 amd_cache_gart();
543
544 fix_erratum_688();
545
546 return 0;
547 }
548
549 /* This has to go after the PCI subsystem */
550 fs_initcall(init_amd_nbs);
551