1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/export.h>
3 #include <linux/bitops.h>
4 #include <linux/elf.h>
5 #include <linux/mm.h>
6
7 #include <linux/io.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/random.h>
11 #include <linux/topology.h>
12 #include <asm/processor.h>
13 #include <asm/apic.h>
14 #include <asm/cacheinfo.h>
15 #include <asm/cpu.h>
16 #include <asm/spec-ctrl.h>
17 #include <asm/smp.h>
18 #include <asm/numa.h>
19 #include <asm/pci-direct.h>
20 #include <asm/delay.h>
21 #include <asm/debugreg.h>
22 #include <asm/resctrl.h>
23
24 #ifdef CONFIG_X86_64
25 # include <asm/mmconfig.h>
26 #endif
27
28 #include "cpu.h"
29
30 /*
31 * nodes_per_socket: Stores the number of nodes per socket.
32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
33 * Node Identifiers[10:8]
34 */
35 static u32 nodes_per_socket = 1;
36
37 /*
38 * AMD errata checking
39 *
40 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
41 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
42 * have an OSVW id assigned, which it takes as first argument. Both take a
43 * variable number of family-specific model-stepping ranges created by
44 * AMD_MODEL_RANGE().
45 *
46 * Example:
47 *
48 * const int amd_erratum_319[] =
49 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
50 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
51 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
52 */
53
54 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
55 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
56 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
57 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
58 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
59 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
60 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
61
62 static const int amd_erratum_400[] =
63 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
64 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
65
66 static const int amd_erratum_383[] =
67 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
68
69 static const int amd_erratum_1485[] =
70 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
71 AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
72
cpu_has_amd_erratum(struct cpuinfo_x86 * cpu,const int * erratum)73 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
74 {
75 int osvw_id = *erratum++;
76 u32 range;
77 u32 ms;
78
79 if (osvw_id >= 0 && osvw_id < 65536 &&
80 cpu_has(cpu, X86_FEATURE_OSVW)) {
81 u64 osvw_len;
82
83 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
84 if (osvw_id < osvw_len) {
85 u64 osvw_bits;
86
87 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
88 osvw_bits);
89 return osvw_bits & (1ULL << (osvw_id & 0x3f));
90 }
91 }
92
93 /* OSVW unavailable or ID unknown, match family-model-stepping range */
94 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
95 while ((range = *erratum++))
96 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
97 (ms >= AMD_MODEL_RANGE_START(range)) &&
98 (ms <= AMD_MODEL_RANGE_END(range)))
99 return true;
100
101 return false;
102 }
103
rdmsrl_amd_safe(unsigned msr,unsigned long long * p)104 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
105 {
106 u32 gprs[8] = { 0 };
107 int err;
108
109 WARN_ONCE((boot_cpu_data.x86 != 0xf),
110 "%s should only be used on K8!\n", __func__);
111
112 gprs[1] = msr;
113 gprs[7] = 0x9c5a203a;
114
115 err = rdmsr_safe_regs(gprs);
116
117 *p = gprs[0] | ((u64)gprs[2] << 32);
118
119 return err;
120 }
121
wrmsrl_amd_safe(unsigned msr,unsigned long long val)122 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
123 {
124 u32 gprs[8] = { 0 };
125
126 WARN_ONCE((boot_cpu_data.x86 != 0xf),
127 "%s should only be used on K8!\n", __func__);
128
129 gprs[0] = (u32)val;
130 gprs[1] = msr;
131 gprs[2] = val >> 32;
132 gprs[7] = 0x9c5a203a;
133
134 return wrmsr_safe_regs(gprs);
135 }
136
137 /*
138 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
139 * misexecution of code under Linux. Owners of such processors should
140 * contact AMD for precise details and a CPU swap.
141 *
142 * See http://www.multimania.com/poulot/k6bug.html
143 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
144 * (Publication # 21266 Issue Date: August 1998)
145 *
146 * The following test is erm.. interesting. AMD neglected to up
147 * the chip setting when fixing the bug but they also tweaked some
148 * performance at the same time..
149 */
150
151 #ifdef CONFIG_X86_32
152 extern __visible void vide(void);
153 __asm__(".text\n"
154 ".globl vide\n"
155 ".type vide, @function\n"
156 ".align 4\n"
157 "vide: ret\n");
158 #endif
159
init_amd_k5(struct cpuinfo_x86 * c)160 static void init_amd_k5(struct cpuinfo_x86 *c)
161 {
162 #ifdef CONFIG_X86_32
163 /*
164 * General Systems BIOSen alias the cpu frequency registers
165 * of the Elan at 0x000df000. Unfortunately, one of the Linux
166 * drivers subsequently pokes it, and changes the CPU speed.
167 * Workaround : Remove the unneeded alias.
168 */
169 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
170 #define CBAR_ENB (0x80000000)
171 #define CBAR_KEY (0X000000CB)
172 if (c->x86_model == 9 || c->x86_model == 10) {
173 if (inl(CBAR) & CBAR_ENB)
174 outl(0 | CBAR_KEY, CBAR);
175 }
176 #endif
177 }
178
init_amd_k6(struct cpuinfo_x86 * c)179 static void init_amd_k6(struct cpuinfo_x86 *c)
180 {
181 #ifdef CONFIG_X86_32
182 u32 l, h;
183 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
184
185 if (c->x86_model < 6) {
186 /* Based on AMD doc 20734R - June 2000 */
187 if (c->x86_model == 0) {
188 clear_cpu_cap(c, X86_FEATURE_APIC);
189 set_cpu_cap(c, X86_FEATURE_PGE);
190 }
191 return;
192 }
193
194 if (c->x86_model == 6 && c->x86_stepping == 1) {
195 const int K6_BUG_LOOP = 1000000;
196 int n;
197 void (*f_vide)(void);
198 u64 d, d2;
199
200 pr_info("AMD K6 stepping B detected - ");
201
202 /*
203 * It looks like AMD fixed the 2.6.2 bug and improved indirect
204 * calls at the same time.
205 */
206
207 n = K6_BUG_LOOP;
208 f_vide = vide;
209 OPTIMIZER_HIDE_VAR(f_vide);
210 d = rdtsc();
211 while (n--)
212 f_vide();
213 d2 = rdtsc();
214 d = d2-d;
215
216 if (d > 20*K6_BUG_LOOP)
217 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
218 else
219 pr_cont("probably OK (after B9730xxxx).\n");
220 }
221
222 /* K6 with old style WHCR */
223 if (c->x86_model < 8 ||
224 (c->x86_model == 8 && c->x86_stepping < 8)) {
225 /* We can only write allocate on the low 508Mb */
226 if (mbytes > 508)
227 mbytes = 508;
228
229 rdmsr(MSR_K6_WHCR, l, h);
230 if ((l&0x0000FFFF) == 0) {
231 unsigned long flags;
232 l = (1<<0)|((mbytes/4)<<1);
233 local_irq_save(flags);
234 wbinvd();
235 wrmsr(MSR_K6_WHCR, l, h);
236 local_irq_restore(flags);
237 pr_info("Enabling old style K6 write allocation for %d Mb\n",
238 mbytes);
239 }
240 return;
241 }
242
243 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
244 c->x86_model == 9 || c->x86_model == 13) {
245 /* The more serious chips .. */
246
247 if (mbytes > 4092)
248 mbytes = 4092;
249
250 rdmsr(MSR_K6_WHCR, l, h);
251 if ((l&0xFFFF0000) == 0) {
252 unsigned long flags;
253 l = ((mbytes>>2)<<22)|(1<<16);
254 local_irq_save(flags);
255 wbinvd();
256 wrmsr(MSR_K6_WHCR, l, h);
257 local_irq_restore(flags);
258 pr_info("Enabling new style K6 write allocation for %d Mb\n",
259 mbytes);
260 }
261
262 return;
263 }
264
265 if (c->x86_model == 10) {
266 /* AMD Geode LX is model 10 */
267 /* placeholder for any needed mods */
268 return;
269 }
270 #endif
271 }
272
init_amd_k7(struct cpuinfo_x86 * c)273 static void init_amd_k7(struct cpuinfo_x86 *c)
274 {
275 #ifdef CONFIG_X86_32
276 u32 l, h;
277
278 /*
279 * Bit 15 of Athlon specific MSR 15, needs to be 0
280 * to enable SSE on Palomino/Morgan/Barton CPU's.
281 * If the BIOS didn't enable it already, enable it here.
282 */
283 if (c->x86_model >= 6 && c->x86_model <= 10) {
284 if (!cpu_has(c, X86_FEATURE_XMM)) {
285 pr_info("Enabling disabled K7/SSE Support.\n");
286 msr_clear_bit(MSR_K7_HWCR, 15);
287 set_cpu_cap(c, X86_FEATURE_XMM);
288 }
289 }
290
291 /*
292 * It's been determined by AMD that Athlons since model 8 stepping 1
293 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
294 * As per AMD technical note 27212 0.2
295 */
296 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
297 rdmsr(MSR_K7_CLK_CTL, l, h);
298 if ((l & 0xfff00000) != 0x20000000) {
299 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
300 l, ((l & 0x000fffff)|0x20000000));
301 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
302 }
303 }
304
305 /* calling is from identify_secondary_cpu() ? */
306 if (!c->cpu_index)
307 return;
308
309 /*
310 * Certain Athlons might work (for various values of 'work') in SMP
311 * but they are not certified as MP capable.
312 */
313 /* Athlon 660/661 is valid. */
314 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
315 (c->x86_stepping == 1)))
316 return;
317
318 /* Duron 670 is valid */
319 if ((c->x86_model == 7) && (c->x86_stepping == 0))
320 return;
321
322 /*
323 * Athlon 662, Duron 671, and Athlon >model 7 have capability
324 * bit. It's worth noting that the A5 stepping (662) of some
325 * Athlon XP's have the MP bit set.
326 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
327 * more.
328 */
329 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
330 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
331 (c->x86_model > 7))
332 if (cpu_has(c, X86_FEATURE_MP))
333 return;
334
335 /* If we get here, not a certified SMP capable AMD system. */
336
337 /*
338 * Don't taint if we are running SMP kernel on a single non-MP
339 * approved Athlon
340 */
341 WARN_ONCE(1, "WARNING: This combination of AMD"
342 " processors is not suitable for SMP.\n");
343 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
344 #endif
345 }
346
347 #ifdef CONFIG_NUMA
348 /*
349 * To workaround broken NUMA config. Read the comment in
350 * srat_detect_node().
351 */
nearby_node(int apicid)352 static int nearby_node(int apicid)
353 {
354 int i, node;
355
356 for (i = apicid - 1; i >= 0; i--) {
357 node = __apicid_to_node[i];
358 if (node != NUMA_NO_NODE && node_online(node))
359 return node;
360 }
361 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
362 node = __apicid_to_node[i];
363 if (node != NUMA_NO_NODE && node_online(node))
364 return node;
365 }
366 return first_node(node_online_map); /* Shouldn't happen */
367 }
368 #endif
369
370 /*
371 * Fix up cpu_core_id for pre-F17h systems to be in the
372 * [0 .. cores_per_node - 1] range. Not really needed but
373 * kept so as not to break existing setups.
374 */
legacy_fixup_core_id(struct cpuinfo_x86 * c)375 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
376 {
377 u32 cus_per_node;
378
379 if (c->x86 >= 0x17)
380 return;
381
382 cus_per_node = c->x86_max_cores / nodes_per_socket;
383 c->cpu_core_id %= cus_per_node;
384 }
385
386 /*
387 * Fixup core topology information for
388 * (1) AMD multi-node processors
389 * Assumption: Number of cores in each internal node is the same.
390 * (2) AMD processors supporting compute units
391 */
amd_get_topology(struct cpuinfo_x86 * c)392 static void amd_get_topology(struct cpuinfo_x86 *c)
393 {
394 int cpu = smp_processor_id();
395
396 /* get information required for multi-node processors */
397 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
398 int err;
399 u32 eax, ebx, ecx, edx;
400
401 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
402
403 c->cpu_die_id = ecx & 0xff;
404
405 if (c->x86 == 0x15)
406 c->cu_id = ebx & 0xff;
407
408 if (c->x86 >= 0x17) {
409 c->cpu_core_id = ebx & 0xff;
410
411 if (smp_num_siblings > 1)
412 c->x86_max_cores /= smp_num_siblings;
413 }
414
415 /*
416 * In case leaf B is available, use it to derive
417 * topology information.
418 */
419 err = detect_extended_topology(c);
420 if (!err)
421 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
422
423 cacheinfo_amd_init_llc_id(c, cpu);
424
425 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
426 u64 value;
427
428 rdmsrl(MSR_FAM10H_NODE_ID, value);
429 c->cpu_die_id = value & 7;
430
431 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
432 } else
433 return;
434
435 if (nodes_per_socket > 1) {
436 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
437 legacy_fixup_core_id(c);
438 }
439 }
440
441 /*
442 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
443 * Assumes number of cores is a power of two.
444 */
amd_detect_cmp(struct cpuinfo_x86 * c)445 static void amd_detect_cmp(struct cpuinfo_x86 *c)
446 {
447 unsigned bits;
448 int cpu = smp_processor_id();
449
450 bits = c->x86_coreid_bits;
451 /* Low order bits define the core id (index of core in socket) */
452 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
453 /* Convert the initial APIC ID into the socket ID */
454 c->phys_proc_id = c->initial_apicid >> bits;
455 /* use socket ID also for last level cache */
456 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
457 }
458
amd_get_nodes_per_socket(void)459 u32 amd_get_nodes_per_socket(void)
460 {
461 return nodes_per_socket;
462 }
463 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
464
srat_detect_node(struct cpuinfo_x86 * c)465 static void srat_detect_node(struct cpuinfo_x86 *c)
466 {
467 #ifdef CONFIG_NUMA
468 int cpu = smp_processor_id();
469 int node;
470 unsigned apicid = c->apicid;
471
472 node = numa_cpu_node(cpu);
473 if (node == NUMA_NO_NODE)
474 node = get_llc_id(cpu);
475
476 /*
477 * On multi-fabric platform (e.g. Numascale NumaChip) a
478 * platform-specific handler needs to be called to fixup some
479 * IDs of the CPU.
480 */
481 if (x86_cpuinit.fixup_cpu_id)
482 x86_cpuinit.fixup_cpu_id(c, node);
483
484 if (!node_online(node)) {
485 /*
486 * Two possibilities here:
487 *
488 * - The CPU is missing memory and no node was created. In
489 * that case try picking one from a nearby CPU.
490 *
491 * - The APIC IDs differ from the HyperTransport node IDs
492 * which the K8 northbridge parsing fills in. Assume
493 * they are all increased by a constant offset, but in
494 * the same order as the HT nodeids. If that doesn't
495 * result in a usable node fall back to the path for the
496 * previous case.
497 *
498 * This workaround operates directly on the mapping between
499 * APIC ID and NUMA node, assuming certain relationship
500 * between APIC ID, HT node ID and NUMA topology. As going
501 * through CPU mapping may alter the outcome, directly
502 * access __apicid_to_node[].
503 */
504 int ht_nodeid = c->initial_apicid;
505
506 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
507 node = __apicid_to_node[ht_nodeid];
508 /* Pick a nearby node */
509 if (!node_online(node))
510 node = nearby_node(apicid);
511 }
512 numa_set_node(cpu, node);
513 #endif
514 }
515
early_init_amd_mc(struct cpuinfo_x86 * c)516 static void early_init_amd_mc(struct cpuinfo_x86 *c)
517 {
518 #ifdef CONFIG_SMP
519 unsigned bits, ecx;
520
521 /* Multi core CPU? */
522 if (c->extended_cpuid_level < 0x80000008)
523 return;
524
525 ecx = cpuid_ecx(0x80000008);
526
527 c->x86_max_cores = (ecx & 0xff) + 1;
528
529 /* CPU telling us the core id bits shift? */
530 bits = (ecx >> 12) & 0xF;
531
532 /* Otherwise recompute */
533 if (bits == 0) {
534 while ((1 << bits) < c->x86_max_cores)
535 bits++;
536 }
537
538 c->x86_coreid_bits = bits;
539 #endif
540 }
541
bsp_init_amd(struct cpuinfo_x86 * c)542 static void bsp_init_amd(struct cpuinfo_x86 *c)
543 {
544 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
545
546 if (c->x86 > 0x10 ||
547 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
548 u64 val;
549
550 rdmsrl(MSR_K7_HWCR, val);
551 if (!(val & BIT(24)))
552 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
553 }
554 }
555
556 if (c->x86 == 0x15) {
557 unsigned long upperbit;
558 u32 cpuid, assoc;
559
560 cpuid = cpuid_edx(0x80000005);
561 assoc = cpuid >> 16 & 0xff;
562 upperbit = ((cpuid >> 24) << 10) / assoc;
563
564 va_align.mask = (upperbit - 1) & PAGE_MASK;
565 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
566
567 /* A random value per boot for bit slice [12:upper_bit) */
568 va_align.bits = get_random_u32() & va_align.mask;
569 }
570
571 if (cpu_has(c, X86_FEATURE_MWAITX))
572 use_mwaitx_delay();
573
574 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
575 u32 ecx;
576
577 ecx = cpuid_ecx(0x8000001e);
578 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
579 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
580 u64 value;
581
582 rdmsrl(MSR_FAM10H_NODE_ID, value);
583 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
584 }
585
586 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
587 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
588 c->x86 >= 0x15 && c->x86 <= 0x17) {
589 unsigned int bit;
590
591 switch (c->x86) {
592 case 0x15: bit = 54; break;
593 case 0x16: bit = 33; break;
594 case 0x17: bit = 10; break;
595 default: return;
596 }
597 /*
598 * Try to cache the base value so further operations can
599 * avoid RMW. If that faults, do not enable SSBD.
600 */
601 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
602 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
603 setup_force_cpu_cap(X86_FEATURE_SSBD);
604 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
605 }
606 }
607
608 resctrl_cpu_detect(c);
609
610 /* Figure out Zen generations: */
611 switch (c->x86) {
612 case 0x17: {
613 switch (c->x86_model) {
614 case 0x00 ... 0x2f:
615 case 0x50 ... 0x5f:
616 setup_force_cpu_cap(X86_FEATURE_ZEN1);
617 break;
618 case 0x30 ... 0x4f:
619 case 0x60 ... 0x7f:
620 case 0x90 ... 0x91:
621 case 0xa0 ... 0xaf:
622 setup_force_cpu_cap(X86_FEATURE_ZEN2);
623 break;
624 default:
625 goto warn;
626 }
627 break;
628 }
629 case 0x19: {
630 switch (c->x86_model) {
631 case 0x00 ... 0x0f:
632 case 0x20 ... 0x5f:
633 setup_force_cpu_cap(X86_FEATURE_ZEN3);
634 break;
635 case 0x10 ... 0x1f:
636 case 0x60 ... 0xaf:
637 setup_force_cpu_cap(X86_FEATURE_ZEN4);
638 break;
639 default:
640 goto warn;
641 }
642 break;
643 }
644 default:
645 break;
646 }
647
648 return;
649
650 warn:
651 WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model);
652 }
653
early_detect_mem_encrypt(struct cpuinfo_x86 * c)654 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
655 {
656 u64 msr;
657
658 /*
659 * BIOS support is required for SME and SEV.
660 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
661 * the SME physical address space reduction value.
662 * If BIOS has not enabled SME then don't advertise the
663 * SME feature (set in scattered.c).
664 * If the kernel has not enabled SME via any means then
665 * don't advertise the SME feature.
666 * For SEV: If BIOS has not enabled SEV then don't advertise the
667 * SEV and SEV_ES feature (set in scattered.c).
668 *
669 * In all cases, since support for SME and SEV requires long mode,
670 * don't advertise the feature under CONFIG_X86_32.
671 */
672 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
673 /* Check if memory encryption is enabled */
674 rdmsrl(MSR_AMD64_SYSCFG, msr);
675 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
676 goto clear_all;
677
678 /*
679 * Always adjust physical address bits. Even though this
680 * will be a value above 32-bits this is still done for
681 * CONFIG_X86_32 so that accurate values are reported.
682 */
683 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
684
685 if (IS_ENABLED(CONFIG_X86_32))
686 goto clear_all;
687
688 if (!sme_me_mask)
689 setup_clear_cpu_cap(X86_FEATURE_SME);
690
691 rdmsrl(MSR_K7_HWCR, msr);
692 if (!(msr & MSR_K7_HWCR_SMMLOCK))
693 goto clear_sev;
694
695 return;
696
697 clear_all:
698 setup_clear_cpu_cap(X86_FEATURE_SME);
699 clear_sev:
700 setup_clear_cpu_cap(X86_FEATURE_SEV);
701 setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
702 }
703 }
704
early_init_amd(struct cpuinfo_x86 * c)705 static void early_init_amd(struct cpuinfo_x86 *c)
706 {
707 u64 value;
708 u32 dummy;
709
710 early_init_amd_mc(c);
711
712 if (c->x86 >= 0xf)
713 set_cpu_cap(c, X86_FEATURE_K8);
714
715 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
716
717 /*
718 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
719 * with P/T states and does not stop in deep C-states
720 */
721 if (c->x86_power & (1 << 8)) {
722 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
723 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
724 }
725
726 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
727 if (c->x86_power & BIT(12))
728 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
729
730 /* Bit 14 indicates the Runtime Average Power Limit interface. */
731 if (c->x86_power & BIT(14))
732 set_cpu_cap(c, X86_FEATURE_RAPL);
733
734 #ifdef CONFIG_X86_64
735 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
736 #else
737 /* Set MTRR capability flag if appropriate */
738 if (c->x86 == 5)
739 if (c->x86_model == 13 || c->x86_model == 9 ||
740 (c->x86_model == 8 && c->x86_stepping >= 8))
741 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
742 #endif
743 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
744 /*
745 * ApicID can always be treated as an 8-bit value for AMD APIC versions
746 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
747 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
748 * after 16h.
749 */
750 if (boot_cpu_has(X86_FEATURE_APIC)) {
751 if (c->x86 > 0x16)
752 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
753 else if (c->x86 >= 0xf) {
754 /* check CPU config space for extended APIC ID */
755 unsigned int val;
756
757 val = read_pci_config(0, 24, 0, 0x68);
758 if ((val >> 17 & 0x3) == 0x3)
759 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
760 }
761 }
762 #endif
763
764 /*
765 * This is only needed to tell the kernel whether to use VMCALL
766 * and VMMCALL. VMMCALL is never executed except under virt, so
767 * we can set it unconditionally.
768 */
769 set_cpu_cap(c, X86_FEATURE_VMMCALL);
770
771 /* F16h erratum 793, CVE-2013-6885 */
772 if (c->x86 == 0x16 && c->x86_model <= 0xf)
773 msr_set_bit(MSR_AMD64_LS_CFG, 15);
774
775 /*
776 * Check whether the machine is affected by erratum 400. This is
777 * used to select the proper idle routine and to enable the check
778 * whether the machine is affected in arch_post_acpi_init(), which
779 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
780 */
781 if (cpu_has_amd_erratum(c, amd_erratum_400))
782 set_cpu_bug(c, X86_BUG_AMD_E400);
783
784 early_detect_mem_encrypt(c);
785
786 /* Re-enable TopologyExtensions if switched off by BIOS */
787 if (c->x86 == 0x15 &&
788 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
789 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
790
791 if (msr_set_bit(0xc0011005, 54) > 0) {
792 rdmsrl(0xc0011005, value);
793 if (value & BIT_64(54)) {
794 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
795 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
796 }
797 }
798 }
799
800 if (cpu_has(c, X86_FEATURE_TOPOEXT))
801 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
802
803 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) {
804 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB))
805 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
806 else if (c->x86 >= 0x19 && !wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) {
807 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
808 setup_force_cpu_cap(X86_FEATURE_SBPB);
809 }
810 }
811 }
812
init_amd_k8(struct cpuinfo_x86 * c)813 static void init_amd_k8(struct cpuinfo_x86 *c)
814 {
815 u32 level;
816 u64 value;
817
818 /* On C+ stepping K8 rep microcode works well for copy/memset */
819 level = cpuid_eax(1);
820 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
821 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
822
823 /*
824 * Some BIOSes incorrectly force this feature, but only K8 revision D
825 * (model = 0x14) and later actually support it.
826 * (AMD Erratum #110, docId: 25759).
827 */
828 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM) && !cpu_has(c, X86_FEATURE_HYPERVISOR)) {
829 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
830 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
831 value &= ~BIT_64(32);
832 wrmsrl_amd_safe(0xc001100d, value);
833 }
834 }
835
836 if (!c->x86_model_id[0])
837 strcpy(c->x86_model_id, "Hammer");
838
839 #ifdef CONFIG_SMP
840 /*
841 * Disable TLB flush filter by setting HWCR.FFDIS on K8
842 * bit 6 of msr C001_0015
843 *
844 * Errata 63 for SH-B3 steppings
845 * Errata 122 for all steppings (F+ have it disabled by default)
846 */
847 msr_set_bit(MSR_K7_HWCR, 6);
848 #endif
849 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
850 }
851
init_amd_gh(struct cpuinfo_x86 * c)852 static void init_amd_gh(struct cpuinfo_x86 *c)
853 {
854 #ifdef CONFIG_MMCONF_FAM10H
855 /* do this for boot cpu */
856 if (c == &boot_cpu_data)
857 check_enable_amd_mmconf_dmi();
858
859 fam10h_check_enable_mmcfg();
860 #endif
861
862 /*
863 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
864 * is always needed when GART is enabled, even in a kernel which has no
865 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
866 * If it doesn't, we do it here as suggested by the BKDG.
867 *
868 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
869 */
870 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
871
872 /*
873 * On family 10h BIOS may not have properly enabled WC+ support, causing
874 * it to be converted to CD memtype. This may result in performance
875 * degradation for certain nested-paging guests. Prevent this conversion
876 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
877 *
878 * NOTE: we want to use the _safe accessors so as not to #GP kvm
879 * guests on older kvm hosts.
880 */
881 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
882
883 if (cpu_has_amd_erratum(c, amd_erratum_383))
884 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
885 }
886
init_amd_ln(struct cpuinfo_x86 * c)887 static void init_amd_ln(struct cpuinfo_x86 *c)
888 {
889 /*
890 * Apply erratum 665 fix unconditionally so machines without a BIOS
891 * fix work.
892 */
893 msr_set_bit(MSR_AMD64_DE_CFG, 31);
894 }
895
896 static bool rdrand_force;
897
rdrand_cmdline(char * str)898 static int __init rdrand_cmdline(char *str)
899 {
900 if (!str)
901 return -EINVAL;
902
903 if (!strcmp(str, "force"))
904 rdrand_force = true;
905 else
906 return -EINVAL;
907
908 return 0;
909 }
910 early_param("rdrand", rdrand_cmdline);
911
clear_rdrand_cpuid_bit(struct cpuinfo_x86 * c)912 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
913 {
914 /*
915 * Saving of the MSR used to hide the RDRAND support during
916 * suspend/resume is done by arch/x86/power/cpu.c, which is
917 * dependent on CONFIG_PM_SLEEP.
918 */
919 if (!IS_ENABLED(CONFIG_PM_SLEEP))
920 return;
921
922 /*
923 * The self-test can clear X86_FEATURE_RDRAND, so check for
924 * RDRAND support using the CPUID function directly.
925 */
926 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
927 return;
928
929 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
930
931 /*
932 * Verify that the CPUID change has occurred in case the kernel is
933 * running virtualized and the hypervisor doesn't support the MSR.
934 */
935 if (cpuid_ecx(1) & BIT(30)) {
936 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
937 return;
938 }
939
940 clear_cpu_cap(c, X86_FEATURE_RDRAND);
941 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
942 }
943
init_amd_jg(struct cpuinfo_x86 * c)944 static void init_amd_jg(struct cpuinfo_x86 *c)
945 {
946 /*
947 * Some BIOS implementations do not restore proper RDRAND support
948 * across suspend and resume. Check on whether to hide the RDRAND
949 * instruction support via CPUID.
950 */
951 clear_rdrand_cpuid_bit(c);
952 }
953
init_amd_bd(struct cpuinfo_x86 * c)954 static void init_amd_bd(struct cpuinfo_x86 *c)
955 {
956 u64 value;
957
958 /*
959 * The way access filter has a performance penalty on some workloads.
960 * Disable it on the affected CPUs.
961 */
962 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
963 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
964 value |= 0x1E;
965 wrmsrl_safe(MSR_F15H_IC_CFG, value);
966 }
967 }
968
969 /*
970 * Some BIOS implementations do not restore proper RDRAND support
971 * across suspend and resume. Check on whether to hide the RDRAND
972 * instruction support via CPUID.
973 */
974 clear_rdrand_cpuid_bit(c);
975 }
976
fix_erratum_1386(struct cpuinfo_x86 * c)977 static void fix_erratum_1386(struct cpuinfo_x86 *c)
978 {
979 /*
980 * Work around Erratum 1386. The XSAVES instruction malfunctions in
981 * certain circumstances on Zen1/2 uarch, and not all parts have had
982 * updated microcode at the time of writing (March 2023).
983 *
984 * Affected parts all have no supervisor XSAVE states, meaning that
985 * the XSAVEC instruction (which works fine) is equivalent.
986 */
987 clear_cpu_cap(c, X86_FEATURE_XSAVES);
988 }
989
init_spectral_chicken(struct cpuinfo_x86 * c)990 void init_spectral_chicken(struct cpuinfo_x86 *c)
991 {
992 #ifdef CONFIG_CPU_UNRET_ENTRY
993 u64 value;
994
995 /*
996 * On Zen2 we offer this chicken (bit) on the altar of Speculation.
997 *
998 * This suppresses speculation from the middle of a basic block, i.e. it
999 * suppresses non-branch predictions.
1000 *
1001 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
1002 */
1003 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
1004 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
1005 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
1006 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
1007 }
1008 }
1009 #endif
1010 }
1011
init_amd_zn(struct cpuinfo_x86 * c)1012 static void init_amd_zn(struct cpuinfo_x86 *c)
1013 {
1014 setup_force_cpu_cap(X86_FEATURE_ZEN);
1015 #ifdef CONFIG_NUMA
1016 node_reclaim_distance = 32;
1017 #endif
1018 }
1019
init_amd_zen1(struct cpuinfo_x86 * c)1020 static void init_amd_zen1(struct cpuinfo_x86 *c)
1021 {
1022 fix_erratum_1386(c);
1023
1024 /* Fix up CPUID bits, but only if not virtualised. */
1025 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1026
1027 /* Erratum 1076: CPB feature bit not being set in CPUID. */
1028 if (!cpu_has(c, X86_FEATURE_CPB))
1029 set_cpu_cap(c, X86_FEATURE_CPB);
1030
1031 /*
1032 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
1033 * Branch Type Confusion, but predate the allocation of the
1034 * BTC_NO bit.
1035 */
1036 if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
1037 set_cpu_cap(c, X86_FEATURE_BTC_NO);
1038 }
1039
1040 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
1041 setup_force_cpu_bug(X86_BUG_DIV0);
1042
1043 /*
1044 * Turn off the Instructions Retired free counter on machines that are
1045 * susceptible to erratum #1054 "Instructions Retired Performance
1046 * Counter May Be Inaccurate".
1047 */
1048 if (c->x86_model < 0x30) {
1049 msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
1050 clear_cpu_cap(c, X86_FEATURE_IRPERF);
1051 }
1052 }
1053
cpu_has_zenbleed_microcode(void)1054 static bool cpu_has_zenbleed_microcode(void)
1055 {
1056 u32 good_rev = 0;
1057
1058 switch (boot_cpu_data.x86_model) {
1059 case 0x30 ... 0x3f: good_rev = 0x0830107b; break;
1060 case 0x60 ... 0x67: good_rev = 0x0860010c; break;
1061 case 0x68 ... 0x6f: good_rev = 0x08608107; break;
1062 case 0x70 ... 0x7f: good_rev = 0x08701033; break;
1063 case 0xa0 ... 0xaf: good_rev = 0x08a00009; break;
1064
1065 default:
1066 return false;
1067 break;
1068 }
1069
1070 if (boot_cpu_data.microcode < good_rev)
1071 return false;
1072
1073 return true;
1074 }
1075
zen2_zenbleed_check(struct cpuinfo_x86 * c)1076 static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
1077 {
1078 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
1079 return;
1080
1081 if (!cpu_has(c, X86_FEATURE_AVX))
1082 return;
1083
1084 if (!cpu_has_zenbleed_microcode()) {
1085 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
1086 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1087 } else {
1088 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1089 }
1090 }
1091
init_amd_zen2(struct cpuinfo_x86 * c)1092 static void init_amd_zen2(struct cpuinfo_x86 *c)
1093 {
1094 fix_erratum_1386(c);
1095 zen2_zenbleed_check(c);
1096 }
1097
init_amd_zen3(struct cpuinfo_x86 * c)1098 static void init_amd_zen3(struct cpuinfo_x86 *c)
1099 {
1100 }
1101
init_amd_zen4(struct cpuinfo_x86 * c)1102 static void init_amd_zen4(struct cpuinfo_x86 *c)
1103 {
1104 }
1105
init_amd(struct cpuinfo_x86 * c)1106 static void init_amd(struct cpuinfo_x86 *c)
1107 {
1108 early_init_amd(c);
1109
1110 /*
1111 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
1112 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
1113 */
1114 clear_cpu_cap(c, 0*32+31);
1115
1116 if (c->x86 >= 0x10)
1117 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
1118
1119 /* AMD FSRM also implies FSRS */
1120 if (cpu_has(c, X86_FEATURE_FSRM))
1121 set_cpu_cap(c, X86_FEATURE_FSRS);
1122
1123 /* get apicid instead of initial apic id from cpuid */
1124 c->apicid = read_apic_id();
1125
1126 /* K6s reports MCEs but don't actually have all the MSRs */
1127 if (c->x86 < 6)
1128 clear_cpu_cap(c, X86_FEATURE_MCE);
1129
1130 switch (c->x86) {
1131 case 4: init_amd_k5(c); break;
1132 case 5: init_amd_k6(c); break;
1133 case 6: init_amd_k7(c); break;
1134 case 0xf: init_amd_k8(c); break;
1135 case 0x10: init_amd_gh(c); break;
1136 case 0x12: init_amd_ln(c); break;
1137 case 0x15: init_amd_bd(c); break;
1138 case 0x16: init_amd_jg(c); break;
1139 case 0x17: init_spectral_chicken(c);
1140 fallthrough;
1141 case 0x19: init_amd_zn(c); break;
1142 }
1143
1144 if (boot_cpu_has(X86_FEATURE_ZEN1))
1145 init_amd_zen1(c);
1146 else if (boot_cpu_has(X86_FEATURE_ZEN2))
1147 init_amd_zen2(c);
1148 else if (boot_cpu_has(X86_FEATURE_ZEN3))
1149 init_amd_zen3(c);
1150 else if (boot_cpu_has(X86_FEATURE_ZEN4))
1151 init_amd_zen4(c);
1152
1153 /*
1154 * Enable workaround for FXSAVE leak on CPUs
1155 * without a XSaveErPtr feature
1156 */
1157 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
1158 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
1159
1160 cpu_detect_cache_sizes(c);
1161
1162 amd_detect_cmp(c);
1163 amd_get_topology(c);
1164 srat_detect_node(c);
1165
1166 init_amd_cacheinfo(c);
1167
1168 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) {
1169 /*
1170 * Use LFENCE for execution serialization. On families which
1171 * don't have that MSR, LFENCE is already serializing.
1172 * msr_set_bit() uses the safe accessors, too, even if the MSR
1173 * is not present.
1174 */
1175 msr_set_bit(MSR_AMD64_DE_CFG,
1176 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
1177
1178 /* A serializing LFENCE stops RDTSC speculation */
1179 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1180 }
1181
1182 /*
1183 * Family 0x12 and above processors have APIC timer
1184 * running in deep C states.
1185 */
1186 if (c->x86 > 0x11)
1187 set_cpu_cap(c, X86_FEATURE_ARAT);
1188
1189 /* 3DNow or LM implies PREFETCHW */
1190 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
1191 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
1192 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
1193
1194 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
1195 if (!cpu_feature_enabled(X86_FEATURE_XENPV))
1196 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
1197
1198 /* Enable the Instructions Retired free counter */
1199 if (cpu_has(c, X86_FEATURE_IRPERF))
1200 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
1201
1202 check_null_seg_clears_base(c);
1203
1204 /*
1205 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up
1206 * using the trampoline code and as part of it, MSR_EFER gets prepared there in
1207 * order to be replicated onto them. Regardless, set it here again, if not set,
1208 * to protect against any future refactoring/code reorganization which might
1209 * miss setting this important bit.
1210 */
1211 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
1212 cpu_has(c, X86_FEATURE_AUTOIBRS))
1213 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0);
1214
1215 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
1216 cpu_has_amd_erratum(c, amd_erratum_1485))
1217 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
1218
1219 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
1220 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
1221 }
1222
1223 #ifdef CONFIG_X86_32
amd_size_cache(struct cpuinfo_x86 * c,unsigned int size)1224 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1225 {
1226 /* AMD errata T13 (order #21922) */
1227 if (c->x86 == 6) {
1228 /* Duron Rev A0 */
1229 if (c->x86_model == 3 && c->x86_stepping == 0)
1230 size = 64;
1231 /* Tbird rev A1/A2 */
1232 if (c->x86_model == 4 &&
1233 (c->x86_stepping == 0 || c->x86_stepping == 1))
1234 size = 256;
1235 }
1236 return size;
1237 }
1238 #endif
1239
cpu_detect_tlb_amd(struct cpuinfo_x86 * c)1240 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
1241 {
1242 u32 ebx, eax, ecx, edx;
1243 u16 mask = 0xfff;
1244
1245 if (c->x86 < 0xf)
1246 return;
1247
1248 if (c->extended_cpuid_level < 0x80000006)
1249 return;
1250
1251 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1252
1253 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1254 tlb_lli_4k[ENTRIES] = ebx & mask;
1255
1256 /*
1257 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1258 * characteristics from the CPUID function 0x80000005 instead.
1259 */
1260 if (c->x86 == 0xf) {
1261 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1262 mask = 0xff;
1263 }
1264
1265 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1266 if (!((eax >> 16) & mask))
1267 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1268 else
1269 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1270
1271 /* a 4M entry uses two 2M entries */
1272 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1273
1274 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1275 if (!(eax & mask)) {
1276 /* Erratum 658 */
1277 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1278 tlb_lli_2m[ENTRIES] = 1024;
1279 } else {
1280 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1281 tlb_lli_2m[ENTRIES] = eax & 0xff;
1282 }
1283 } else
1284 tlb_lli_2m[ENTRIES] = eax & mask;
1285
1286 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1287 }
1288
1289 static const struct cpu_dev amd_cpu_dev = {
1290 .c_vendor = "AMD",
1291 .c_ident = { "AuthenticAMD" },
1292 #ifdef CONFIG_X86_32
1293 .legacy_models = {
1294 { .family = 4, .model_names =
1295 {
1296 [3] = "486 DX/2",
1297 [7] = "486 DX/2-WB",
1298 [8] = "486 DX/4",
1299 [9] = "486 DX/4-WB",
1300 [14] = "Am5x86-WT",
1301 [15] = "Am5x86-WB"
1302 }
1303 },
1304 },
1305 .legacy_cache_size = amd_size_cache,
1306 #endif
1307 .c_early_init = early_init_amd,
1308 .c_detect_tlb = cpu_detect_tlb_amd,
1309 .c_bsp_init = bsp_init_amd,
1310 .c_init = init_amd,
1311 .c_x86_vendor = X86_VENDOR_AMD,
1312 };
1313
1314 cpu_dev_register(amd_cpu_dev);
1315
1316 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask);
1317
1318 static unsigned int amd_msr_dr_addr_masks[] = {
1319 MSR_F16H_DR0_ADDR_MASK,
1320 MSR_F16H_DR1_ADDR_MASK,
1321 MSR_F16H_DR1_ADDR_MASK + 1,
1322 MSR_F16H_DR1_ADDR_MASK + 2
1323 };
1324
amd_set_dr_addr_mask(unsigned long mask,unsigned int dr)1325 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr)
1326 {
1327 int cpu = smp_processor_id();
1328
1329 if (!cpu_feature_enabled(X86_FEATURE_BPEXT))
1330 return;
1331
1332 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks)))
1333 return;
1334
1335 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask)
1336 return;
1337
1338 wrmsr(amd_msr_dr_addr_masks[dr], mask, 0);
1339 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask;
1340 }
1341
amd_get_dr_addr_mask(unsigned int dr)1342 unsigned long amd_get_dr_addr_mask(unsigned int dr)
1343 {
1344 if (!cpu_feature_enabled(X86_FEATURE_BPEXT))
1345 return 0;
1346
1347 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks)))
1348 return 0;
1349
1350 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id());
1351 }
1352 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask);
1353
amd_get_highest_perf(void)1354 u32 amd_get_highest_perf(void)
1355 {
1356 struct cpuinfo_x86 *c = &boot_cpu_data;
1357
1358 if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) ||
1359 (c->x86_model >= 0x70 && c->x86_model < 0x80)))
1360 return 166;
1361
1362 if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) ||
1363 (c->x86_model >= 0x40 && c->x86_model < 0x70)))
1364 return 166;
1365
1366 return 255;
1367 }
1368 EXPORT_SYMBOL_GPL(amd_get_highest_perf);
1369
zenbleed_check_cpu(void * unused)1370 static void zenbleed_check_cpu(void *unused)
1371 {
1372 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
1373
1374 zen2_zenbleed_check(c);
1375 }
1376
amd_check_microcode(void)1377 void amd_check_microcode(void)
1378 {
1379 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
1380 return;
1381
1382 if (cpu_feature_enabled(X86_FEATURE_ZEN2))
1383 on_each_cpu(zenbleed_check_cpu, NULL, 1);
1384 }
1385
1386 /*
1387 * Issue a DIV 0/1 insn to clear any division data from previous DIV
1388 * operations.
1389 */
amd_clear_divider(void)1390 void noinstr amd_clear_divider(void)
1391 {
1392 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0)
1393 :: "a" (0), "d" (0), "r" (1));
1394 }
1395 EXPORT_SYMBOL_GPL(amd_clear_divider);
1396