1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/iio/buffer.h>
10 #include <linux/iio/events.h>
11 #include <linux/iio/iio.h>
12 #include <linux/iio/kfifo_buf.h>
13 #include <linux/iio/sysfs.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <asm/unaligned.h>
20
21 #include "adxl367.h"
22
23 #define ADXL367_REG_DEVID 0x00
24 #define ADXL367_DEVID_AD 0xAD
25
26 #define ADXL367_REG_STATUS 0x0B
27 #define ADXL367_STATUS_INACT_MASK BIT(5)
28 #define ADXL367_STATUS_ACT_MASK BIT(4)
29 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2)
30
31 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0)
32
33 #define ADXL367_REG_X_DATA_H 0x0E
34 #define ADXL367_REG_Y_DATA_H 0x10
35 #define ADXL367_REG_Z_DATA_H 0x12
36 #define ADXL367_REG_TEMP_DATA_H 0x14
37 #define ADXL367_REG_EX_ADC_DATA_H 0x16
38 #define ADXL367_DATA_MASK GENMASK(15, 2)
39
40 #define ADXL367_TEMP_25C 165
41 #define ADXL367_TEMP_PER_C 54
42
43 #define ADXL367_VOLTAGE_OFFSET 8192
44 #define ADXL367_VOLTAGE_MAX_MV 1000
45 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0)
46
47 #define ADXL367_REG_RESET 0x1F
48 #define ADXL367_RESET_CODE 0x52
49
50 #define ADXL367_REG_THRESH_ACT_H 0x20
51 #define ADXL367_REG_THRESH_INACT_H 0x23
52 #define ADXL367_THRESH_MAX GENMASK(12, 0)
53 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6)
54 #define ADXL367_THRESH_H_MASK GENMASK(6, 0)
55 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0)
56 #define ADXL367_THRESH_L_MASK GENMASK(7, 2)
57
58 #define ADXL367_REG_TIME_ACT 0x22
59 #define ADXL367_REG_TIME_INACT_H 0x25
60 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0)
61 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0)
62 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8)
63 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0)
64 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0)
65 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0)
66
67 #define ADXL367_REG_ACT_INACT_CTL 0x27
68 #define ADXL367_ACT_EN_MASK GENMASK(1, 0)
69 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4)
70
71 #define ADXL367_REG_FIFO_CTL 0x28
72 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3)
73 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0)
74
75 #define ADXL367_REG_FIFO_SAMPLES 0x29
76 #define ADXL367_FIFO_SIZE 512
77 #define ADXL367_FIFO_MAX_WATERMARK 511
78
79 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8)
80 #define ADXL367_SAMPLES_H_MASK BIT(2)
81 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0)
82 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0)
83
84 #define ADXL367_REG_INT1_MAP 0x2A
85 #define ADXL367_INT_INACT_MASK BIT(5)
86 #define ADXL367_INT_ACT_MASK BIT(4)
87 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2)
88
89 #define ADXL367_REG_FILTER_CTL 0x2C
90 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6)
91 #define ADXL367_2G_RANGE_1G 4095
92 #define ADXL367_2G_RANGE_100MG 409
93 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0)
94
95 #define ADXL367_REG_POWER_CTL 0x2D
96 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0)
97
98 #define ADXL367_REG_ADC_CTL 0x3C
99 #define ADXL367_REG_TEMP_CTL 0x3D
100 #define ADXL367_ADC_EN_MASK BIT(0)
101
102 enum adxl367_range {
103 ADXL367_2G_RANGE,
104 ADXL367_4G_RANGE,
105 ADXL367_8G_RANGE,
106 };
107
108 enum adxl367_fifo_mode {
109 ADXL367_FIFO_MODE_DISABLED = 0b00,
110 ADXL367_FIFO_MODE_STREAM = 0b10,
111 };
112
113 enum adxl367_fifo_format {
114 ADXL367_FIFO_FORMAT_XYZ,
115 ADXL367_FIFO_FORMAT_X,
116 ADXL367_FIFO_FORMAT_Y,
117 ADXL367_FIFO_FORMAT_Z,
118 ADXL367_FIFO_FORMAT_XYZT,
119 ADXL367_FIFO_FORMAT_XT,
120 ADXL367_FIFO_FORMAT_YT,
121 ADXL367_FIFO_FORMAT_ZT,
122 ADXL367_FIFO_FORMAT_XYZA,
123 ADXL367_FIFO_FORMAT_XA,
124 ADXL367_FIFO_FORMAT_YA,
125 ADXL367_FIFO_FORMAT_ZA,
126 };
127
128 enum adxl367_op_mode {
129 ADXL367_OP_STANDBY = 0b00,
130 ADXL367_OP_MEASURE = 0b10,
131 };
132
133 enum adxl367_act_proc_mode {
134 ADXL367_LOOPED = 0b11,
135 };
136
137 enum adxl367_act_en_mode {
138 ADXL367_ACT_DISABLED = 0b00,
139 ADCL367_ACT_REF_ENABLED = 0b11,
140 };
141
142 enum adxl367_activity_type {
143 ADXL367_ACTIVITY,
144 ADXL367_INACTIVITY,
145 };
146
147 enum adxl367_odr {
148 ADXL367_ODR_12P5HZ,
149 ADXL367_ODR_25HZ,
150 ADXL367_ODR_50HZ,
151 ADXL367_ODR_100HZ,
152 ADXL367_ODR_200HZ,
153 ADXL367_ODR_400HZ,
154 };
155
156 struct adxl367_state {
157 const struct adxl367_ops *ops;
158 void *context;
159
160 struct device *dev;
161 struct regmap *regmap;
162
163 /*
164 * Synchronize access to members of driver state, and ensure atomicity
165 * of consecutive regmap operations.
166 */
167 struct mutex lock;
168
169 enum adxl367_odr odr;
170 enum adxl367_range range;
171
172 unsigned int act_threshold;
173 unsigned int act_time_ms;
174 unsigned int inact_threshold;
175 unsigned int inact_time_ms;
176
177 unsigned int fifo_set_size;
178 unsigned int fifo_watermark;
179
180 __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
181 __be16 sample_buf;
182 u8 act_threshold_buf[2];
183 u8 inact_time_buf[2];
184 u8 status_buf[3];
185 };
186
187 static const unsigned int adxl367_threshold_h_reg_tbl[] = {
188 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H,
189 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H,
190 };
191
192 static const unsigned int adxl367_act_en_shift_tbl[] = {
193 [ADXL367_ACTIVITY] = 0,
194 [ADXL367_INACTIVITY] = 2,
195 };
196
197 static const unsigned int adxl367_act_int_mask_tbl[] = {
198 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK,
199 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK,
200 };
201
202 static const int adxl367_samp_freq_tbl[][2] = {
203 [ADXL367_ODR_12P5HZ] = {12, 500000},
204 [ADXL367_ODR_25HZ] = {25, 0},
205 [ADXL367_ODR_50HZ] = {50, 0},
206 [ADXL367_ODR_100HZ] = {100, 0},
207 [ADXL367_ODR_200HZ] = {200, 0},
208 [ADXL367_ODR_400HZ] = {400, 0},
209 };
210
211 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */
212 static const int adxl367_range_scale_tbl[][2] = {
213 [ADXL367_2G_RANGE] = {0, 2394347},
214 [ADXL367_4G_RANGE] = {0, 4788695},
215 [ADXL367_8G_RANGE] = {0, 9577391},
216 };
217
218 static const int adxl367_range_scale_factor_tbl[] = {
219 [ADXL367_2G_RANGE] = 1,
220 [ADXL367_4G_RANGE] = 2,
221 [ADXL367_8G_RANGE] = 4,
222 };
223
224 enum {
225 ADXL367_X_CHANNEL_INDEX,
226 ADXL367_Y_CHANNEL_INDEX,
227 ADXL367_Z_CHANNEL_INDEX,
228 ADXL367_TEMP_CHANNEL_INDEX,
229 ADXL367_EX_ADC_CHANNEL_INDEX
230 };
231
232 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX)
233 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX)
234 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX)
235 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX)
236 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX)
237
238 static const enum adxl367_fifo_format adxl367_fifo_formats[] = {
239 ADXL367_FIFO_FORMAT_X,
240 ADXL367_FIFO_FORMAT_Y,
241 ADXL367_FIFO_FORMAT_Z,
242 ADXL367_FIFO_FORMAT_XT,
243 ADXL367_FIFO_FORMAT_YT,
244 ADXL367_FIFO_FORMAT_ZT,
245 ADXL367_FIFO_FORMAT_XA,
246 ADXL367_FIFO_FORMAT_YA,
247 ADXL367_FIFO_FORMAT_ZA,
248 ADXL367_FIFO_FORMAT_XYZ,
249 ADXL367_FIFO_FORMAT_XYZT,
250 ADXL367_FIFO_FORMAT_XYZA,
251 };
252
253 static const unsigned long adxl367_channel_masks[] = {
254 ADXL367_X_CHANNEL_MASK,
255 ADXL367_Y_CHANNEL_MASK,
256 ADXL367_Z_CHANNEL_MASK,
257 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
258 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
259 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
260 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
261 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
262 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
263 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK,
264 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
265 ADXL367_TEMP_CHANNEL_MASK,
266 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
267 ADXL367_EX_ADC_CHANNEL_MASK,
268 0,
269 };
270
adxl367_set_measure_en(struct adxl367_state * st,bool en)271 static int adxl367_set_measure_en(struct adxl367_state *st, bool en)
272 {
273 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE
274 : ADXL367_OP_STANDBY;
275 int ret;
276
277 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL,
278 ADXL367_POWER_CTL_MODE_MASK,
279 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK,
280 op_mode));
281 if (ret)
282 return ret;
283
284 /*
285 * Wait for acceleration output to settle after entering
286 * measure mode.
287 */
288 if (en)
289 msleep(100);
290
291 return 0;
292 }
293
adxl367_scale_act_thresholds(struct adxl367_state * st,enum adxl367_range old_range,enum adxl367_range new_range)294 static void adxl367_scale_act_thresholds(struct adxl367_state *st,
295 enum adxl367_range old_range,
296 enum adxl367_range new_range)
297 {
298 st->act_threshold = st->act_threshold
299 * adxl367_range_scale_factor_tbl[old_range]
300 / adxl367_range_scale_factor_tbl[new_range];
301 st->inact_threshold = st->inact_threshold
302 * adxl367_range_scale_factor_tbl[old_range]
303 / adxl367_range_scale_factor_tbl[new_range];
304 }
305
_adxl367_set_act_threshold(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int threshold)306 static int _adxl367_set_act_threshold(struct adxl367_state *st,
307 enum adxl367_activity_type act,
308 unsigned int threshold)
309 {
310 u8 reg = adxl367_threshold_h_reg_tbl[act];
311 int ret;
312
313 if (threshold > ADXL367_THRESH_MAX)
314 return -EINVAL;
315
316 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK,
317 FIELD_GET(ADXL367_THRESH_VAL_H_MASK,
318 threshold));
319 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK,
320 FIELD_GET(ADXL367_THRESH_VAL_L_MASK,
321 threshold));
322
323 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf,
324 sizeof(st->act_threshold_buf));
325 if (ret)
326 return ret;
327
328 if (act == ADXL367_ACTIVITY)
329 st->act_threshold = threshold;
330 else
331 st->inact_threshold = threshold;
332
333 return 0;
334 }
335
adxl367_set_act_threshold(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int threshold)336 static int adxl367_set_act_threshold(struct adxl367_state *st,
337 enum adxl367_activity_type act,
338 unsigned int threshold)
339 {
340 int ret;
341
342 mutex_lock(&st->lock);
343
344 ret = adxl367_set_measure_en(st, false);
345 if (ret)
346 goto out;
347
348 ret = _adxl367_set_act_threshold(st, act, threshold);
349 if (ret)
350 goto out;
351
352 ret = adxl367_set_measure_en(st, true);
353
354 out:
355 mutex_unlock(&st->lock);
356
357 return ret;
358 }
359
adxl367_set_act_proc_mode(struct adxl367_state * st,enum adxl367_act_proc_mode mode)360 static int adxl367_set_act_proc_mode(struct adxl367_state *st,
361 enum adxl367_act_proc_mode mode)
362 {
363 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
364 ADXL367_ACT_LINKLOOP_MASK,
365 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK,
366 mode));
367 }
368
adxl367_set_act_interrupt_en(struct adxl367_state * st,enum adxl367_activity_type act,bool en)369 static int adxl367_set_act_interrupt_en(struct adxl367_state *st,
370 enum adxl367_activity_type act,
371 bool en)
372 {
373 unsigned int mask = adxl367_act_int_mask_tbl[act];
374
375 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
376 mask, en ? mask : 0);
377 }
378
adxl367_get_act_interrupt_en(struct adxl367_state * st,enum adxl367_activity_type act,bool * en)379 static int adxl367_get_act_interrupt_en(struct adxl367_state *st,
380 enum adxl367_activity_type act,
381 bool *en)
382 {
383 unsigned int mask = adxl367_act_int_mask_tbl[act];
384 unsigned int val;
385 int ret;
386
387 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);
388 if (ret)
389 return ret;
390
391 *en = !!(val & mask);
392
393 return 0;
394 }
395
adxl367_set_act_en(struct adxl367_state * st,enum adxl367_activity_type act,enum adxl367_act_en_mode en)396 static int adxl367_set_act_en(struct adxl367_state *st,
397 enum adxl367_activity_type act,
398 enum adxl367_act_en_mode en)
399 {
400 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act];
401
402 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
403 ADXL367_ACT_EN_MASK << ctl_shift,
404 en << ctl_shift);
405 }
406
adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state * st,bool en)407 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,
408 bool en)
409 {
410 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
411 ADXL367_INT_FIFO_WATERMARK_MASK,
412 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0);
413 }
414
adxl367_get_fifo_mode(struct adxl367_state * st,enum adxl367_fifo_mode * fifo_mode)415 static int adxl367_get_fifo_mode(struct adxl367_state *st,
416 enum adxl367_fifo_mode *fifo_mode)
417 {
418 unsigned int val;
419 int ret;
420
421 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val);
422 if (ret)
423 return ret;
424
425 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val);
426
427 return 0;
428 }
429
adxl367_set_fifo_mode(struct adxl367_state * st,enum adxl367_fifo_mode fifo_mode)430 static int adxl367_set_fifo_mode(struct adxl367_state *st,
431 enum adxl367_fifo_mode fifo_mode)
432 {
433 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
434 ADXL367_FIFO_CTL_MODE_MASK,
435 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK,
436 fifo_mode));
437 }
438
adxl367_set_fifo_format(struct adxl367_state * st,enum adxl367_fifo_format fifo_format)439 static int adxl367_set_fifo_format(struct adxl367_state *st,
440 enum adxl367_fifo_format fifo_format)
441 {
442 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
443 ADXL367_FIFO_CTL_FORMAT_MASK,
444 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK,
445 fifo_format));
446 }
447
adxl367_set_fifo_watermark(struct adxl367_state * st,unsigned int fifo_watermark)448 static int adxl367_set_fifo_watermark(struct adxl367_state *st,
449 unsigned int fifo_watermark)
450 {
451 unsigned int fifo_samples = fifo_watermark * st->fifo_set_size;
452 unsigned int fifo_samples_h, fifo_samples_l;
453 int ret;
454
455 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK)
456 fifo_samples = ADXL367_FIFO_MAX_WATERMARK;
457
458 fifo_samples /= st->fifo_set_size;
459
460 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK,
461 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK,
462 fifo_samples));
463 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK,
464 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK,
465 fifo_samples));
466
467 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
468 ADXL367_SAMPLES_H_MASK, fifo_samples_h);
469 if (ret)
470 return ret;
471
472 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES,
473 ADXL367_SAMPLES_L_MASK, fifo_samples_l);
474 if (ret)
475 return ret;
476
477 st->fifo_watermark = fifo_watermark;
478
479 return 0;
480 }
481
adxl367_set_range(struct iio_dev * indio_dev,enum adxl367_range range)482 static int adxl367_set_range(struct iio_dev *indio_dev,
483 enum adxl367_range range)
484 {
485 struct adxl367_state *st = iio_priv(indio_dev);
486 int ret;
487
488 ret = iio_device_claim_direct_mode(indio_dev);
489 if (ret)
490 return ret;
491
492 mutex_lock(&st->lock);
493
494 ret = adxl367_set_measure_en(st, false);
495 if (ret)
496 goto out;
497
498 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
499 ADXL367_FILTER_CTL_RANGE_MASK,
500 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK,
501 range));
502 if (ret)
503 goto out;
504
505 adxl367_scale_act_thresholds(st, st->range, range);
506
507 /* Activity thresholds depend on range */
508 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
509 st->act_threshold);
510 if (ret)
511 goto out;
512
513 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
514 st->inact_threshold);
515 if (ret)
516 goto out;
517
518 ret = adxl367_set_measure_en(st, true);
519 if (ret)
520 goto out;
521
522 st->range = range;
523
524 out:
525 mutex_unlock(&st->lock);
526
527 iio_device_release_direct_mode(indio_dev);
528
529 return ret;
530 }
531
adxl367_time_ms_to_samples(struct adxl367_state * st,unsigned int ms)532 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms)
533 {
534 int freq_hz = adxl367_samp_freq_tbl[st->odr][0];
535 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1];
536 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */
537 int freq_dhz = freq_hz * 10 + freq_microhz / 100000;
538
539 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000);
540 }
541
_adxl367_set_act_time_ms(struct adxl367_state * st,unsigned int ms)542 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms)
543 {
544 unsigned int val = adxl367_time_ms_to_samples(st, ms);
545 int ret;
546
547 if (val > ADXL367_TIME_ACT_MAX)
548 val = ADXL367_TIME_ACT_MAX;
549
550 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val);
551 if (ret)
552 return ret;
553
554 st->act_time_ms = ms;
555
556 return 0;
557 }
558
_adxl367_set_inact_time_ms(struct adxl367_state * st,unsigned int ms)559 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms)
560 {
561 unsigned int val = adxl367_time_ms_to_samples(st, ms);
562 int ret;
563
564 if (val > ADXL367_TIME_INACT_MAX)
565 val = ADXL367_TIME_INACT_MAX;
566
567 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK,
568 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK,
569 val));
570 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK,
571 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK,
572 val));
573
574 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H,
575 st->inact_time_buf, sizeof(st->inact_time_buf));
576 if (ret)
577 return ret;
578
579 st->inact_time_ms = ms;
580
581 return 0;
582 }
583
adxl367_set_act_time_ms(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int ms)584 static int adxl367_set_act_time_ms(struct adxl367_state *st,
585 enum adxl367_activity_type act,
586 unsigned int ms)
587 {
588 int ret;
589
590 mutex_lock(&st->lock);
591
592 ret = adxl367_set_measure_en(st, false);
593 if (ret)
594 goto out;
595
596 if (act == ADXL367_ACTIVITY)
597 ret = _adxl367_set_act_time_ms(st, ms);
598 else
599 ret = _adxl367_set_inact_time_ms(st, ms);
600
601 if (ret)
602 goto out;
603
604 ret = adxl367_set_measure_en(st, true);
605
606 out:
607 mutex_unlock(&st->lock);
608
609 return ret;
610 }
611
_adxl367_set_odr(struct adxl367_state * st,enum adxl367_odr odr)612 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr)
613 {
614 int ret;
615
616 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
617 ADXL367_FILTER_CTL_ODR_MASK,
618 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK,
619 odr));
620 if (ret)
621 return ret;
622
623 st->odr = odr;
624
625 /* Activity timers depend on ODR */
626 ret = _adxl367_set_act_time_ms(st, st->act_time_ms);
627 if (ret)
628 return ret;
629
630 return _adxl367_set_inact_time_ms(st, st->inact_time_ms);
631 }
632
adxl367_set_odr(struct iio_dev * indio_dev,enum adxl367_odr odr)633 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr)
634 {
635 struct adxl367_state *st = iio_priv(indio_dev);
636 int ret;
637
638 ret = iio_device_claim_direct_mode(indio_dev);
639 if (ret)
640 return ret;
641
642 mutex_lock(&st->lock);
643
644 ret = adxl367_set_measure_en(st, false);
645 if (ret)
646 goto out;
647
648 ret = _adxl367_set_odr(st, odr);
649 if (ret)
650 goto out;
651
652 ret = adxl367_set_measure_en(st, true);
653
654 out:
655 mutex_unlock(&st->lock);
656
657 iio_device_release_direct_mode(indio_dev);
658
659 return ret;
660 }
661
adxl367_set_temp_adc_en(struct adxl367_state * st,unsigned int reg,bool en)662 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg,
663 bool en)
664 {
665 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK,
666 en ? ADXL367_ADC_EN_MASK : 0);
667 }
668
adxl367_set_temp_adc_reg_en(struct adxl367_state * st,unsigned int reg,bool en)669 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st,
670 unsigned int reg, bool en)
671 {
672 int ret;
673
674 switch (reg) {
675 case ADXL367_REG_TEMP_DATA_H:
676 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
677 break;
678 case ADXL367_REG_EX_ADC_DATA_H:
679 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
680 break;
681 default:
682 return 0;
683 }
684
685 if (ret)
686 return ret;
687
688 if (en)
689 msleep(100);
690
691 return 0;
692 }
693
adxl367_set_temp_adc_mask_en(struct adxl367_state * st,const unsigned long * active_scan_mask,bool en)694 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st,
695 const unsigned long *active_scan_mask,
696 bool en)
697 {
698 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK)
699 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
700 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK)
701 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
702
703 return 0;
704 }
705
adxl367_find_odr(struct adxl367_state * st,int val,int val2,enum adxl367_odr * odr)706 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,
707 enum adxl367_odr *odr)
708 {
709 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl);
710 int i;
711
712 for (i = 0; i < size; i++)
713 if (val == adxl367_samp_freq_tbl[i][0] &&
714 val2 == adxl367_samp_freq_tbl[i][1])
715 break;
716
717 if (i == size)
718 return -EINVAL;
719
720 *odr = i;
721
722 return 0;
723 }
724
adxl367_find_range(struct adxl367_state * st,int val,int val2,enum adxl367_range * range)725 static int adxl367_find_range(struct adxl367_state *st, int val, int val2,
726 enum adxl367_range *range)
727 {
728 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl);
729 int i;
730
731 for (i = 0; i < size; i++)
732 if (val == adxl367_range_scale_tbl[i][0] &&
733 val2 == adxl367_range_scale_tbl[i][1])
734 break;
735
736 if (i == size)
737 return -EINVAL;
738
739 *range = i;
740
741 return 0;
742 }
743
adxl367_read_sample(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)744 static int adxl367_read_sample(struct iio_dev *indio_dev,
745 struct iio_chan_spec const *chan,
746 int *val)
747 {
748 struct adxl367_state *st = iio_priv(indio_dev);
749 u16 sample;
750 int ret;
751
752 ret = iio_device_claim_direct_mode(indio_dev);
753 if (ret)
754 return ret;
755
756 mutex_lock(&st->lock);
757
758 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true);
759 if (ret)
760 goto out;
761
762 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf,
763 sizeof(st->sample_buf));
764 if (ret)
765 goto out;
766
767 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf));
768 *val = sign_extend32(sample, chan->scan_type.realbits - 1);
769
770 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false);
771
772 out:
773 mutex_unlock(&st->lock);
774
775 iio_device_release_direct_mode(indio_dev);
776
777 return ret ?: IIO_VAL_INT;
778 }
779
adxl367_get_status(struct adxl367_state * st,u8 * status,u16 * fifo_entries)780 static int adxl367_get_status(struct adxl367_state *st, u8 *status,
781 u16 *fifo_entries)
782 {
783 int ret;
784
785 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */
786 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS,
787 st->status_buf, sizeof(st->status_buf));
788 if (ret)
789 return ret;
790
791 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK;
792
793 *status = st->status_buf[0];
794 *fifo_entries = get_unaligned_le16(&st->status_buf[1]);
795
796 return 0;
797 }
798
adxl367_push_event(struct iio_dev * indio_dev,u8 status)799 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status)
800 {
801 unsigned int ev_dir;
802
803 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status))
804 ev_dir = IIO_EV_DIR_RISING;
805 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status))
806 ev_dir = IIO_EV_DIR_FALLING;
807 else
808 return false;
809
810 iio_push_event(indio_dev,
811 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
812 IIO_EV_TYPE_THRESH, ev_dir),
813 iio_get_time_ns(indio_dev));
814
815 return true;
816 }
817
adxl367_push_fifo_data(struct iio_dev * indio_dev,u8 status,u16 fifo_entries)818 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status,
819 u16 fifo_entries)
820 {
821 struct adxl367_state *st = iio_priv(indio_dev);
822 int ret;
823 int i;
824
825 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status))
826 return false;
827
828 fifo_entries -= fifo_entries % st->fifo_set_size;
829
830 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);
831 if (ret) {
832 dev_err(st->dev, "Failed to read FIFO: %d\n", ret);
833 return true;
834 }
835
836 for (i = 0; i < fifo_entries; i += st->fifo_set_size)
837 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
838
839 return true;
840 }
841
adxl367_irq_handler(int irq,void * private)842 static irqreturn_t adxl367_irq_handler(int irq, void *private)
843 {
844 struct iio_dev *indio_dev = private;
845 struct adxl367_state *st = iio_priv(indio_dev);
846 u16 fifo_entries;
847 bool handled;
848 u8 status;
849 int ret;
850
851 ret = adxl367_get_status(st, &status, &fifo_entries);
852 if (ret)
853 return IRQ_NONE;
854
855 handled = adxl367_push_event(indio_dev, status);
856 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries);
857
858 return handled ? IRQ_HANDLED : IRQ_NONE;
859 }
860
adxl367_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)861 static int adxl367_reg_access(struct iio_dev *indio_dev,
862 unsigned int reg,
863 unsigned int writeval,
864 unsigned int *readval)
865 {
866 struct adxl367_state *st = iio_priv(indio_dev);
867
868 if (readval)
869 return regmap_read(st->regmap, reg, readval);
870 else
871 return regmap_write(st->regmap, reg, writeval);
872 }
873
adxl367_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)874 static int adxl367_read_raw(struct iio_dev *indio_dev,
875 struct iio_chan_spec const *chan,
876 int *val, int *val2, long info)
877 {
878 struct adxl367_state *st = iio_priv(indio_dev);
879
880 switch (info) {
881 case IIO_CHAN_INFO_RAW:
882 return adxl367_read_sample(indio_dev, chan, val);
883 case IIO_CHAN_INFO_SCALE:
884 switch (chan->type) {
885 case IIO_ACCEL:
886 mutex_lock(&st->lock);
887 *val = adxl367_range_scale_tbl[st->range][0];
888 *val2 = adxl367_range_scale_tbl[st->range][1];
889 mutex_unlock(&st->lock);
890 return IIO_VAL_INT_PLUS_NANO;
891 case IIO_TEMP:
892 *val = 1000;
893 *val2 = ADXL367_TEMP_PER_C;
894 return IIO_VAL_FRACTIONAL;
895 case IIO_VOLTAGE:
896 *val = ADXL367_VOLTAGE_MAX_MV;
897 *val2 = ADXL367_VOLTAGE_MAX_RAW;
898 return IIO_VAL_FRACTIONAL;
899 default:
900 return -EINVAL;
901 }
902 case IIO_CHAN_INFO_OFFSET:
903 switch (chan->type) {
904 case IIO_TEMP:
905 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C;
906 return IIO_VAL_INT;
907 case IIO_VOLTAGE:
908 *val = ADXL367_VOLTAGE_OFFSET;
909 return IIO_VAL_INT;
910 default:
911 return -EINVAL;
912 }
913 case IIO_CHAN_INFO_SAMP_FREQ:
914 mutex_lock(&st->lock);
915 *val = adxl367_samp_freq_tbl[st->odr][0];
916 *val2 = adxl367_samp_freq_tbl[st->odr][1];
917 mutex_unlock(&st->lock);
918 return IIO_VAL_INT_PLUS_MICRO;
919 default:
920 return -EINVAL;
921 }
922 }
923
adxl367_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)924 static int adxl367_write_raw(struct iio_dev *indio_dev,
925 struct iio_chan_spec const *chan,
926 int val, int val2, long info)
927 {
928 struct adxl367_state *st = iio_priv(indio_dev);
929 int ret;
930
931 switch (info) {
932 case IIO_CHAN_INFO_SAMP_FREQ: {
933 enum adxl367_odr odr;
934
935 ret = adxl367_find_odr(st, val, val2, &odr);
936 if (ret)
937 return ret;
938
939 return adxl367_set_odr(indio_dev, odr);
940 }
941 case IIO_CHAN_INFO_SCALE: {
942 enum adxl367_range range;
943
944 ret = adxl367_find_range(st, val, val2, &range);
945 if (ret)
946 return ret;
947
948 return adxl367_set_range(indio_dev, range);
949 }
950 default:
951 return -EINVAL;
952 }
953 }
954
adxl367_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long info)955 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev,
956 struct iio_chan_spec const *chan,
957 long info)
958 {
959 switch (info) {
960 case IIO_CHAN_INFO_SCALE:
961 if (chan->type != IIO_ACCEL)
962 return -EINVAL;
963
964 return IIO_VAL_INT_PLUS_NANO;
965 default:
966 return IIO_VAL_INT_PLUS_MICRO;
967 }
968 }
969
adxl367_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)970 static int adxl367_read_avail(struct iio_dev *indio_dev,
971 struct iio_chan_spec const *chan,
972 const int **vals, int *type, int *length,
973 long info)
974 {
975 switch (info) {
976 case IIO_CHAN_INFO_SCALE:
977 if (chan->type != IIO_ACCEL)
978 return -EINVAL;
979
980 *vals = (int *)adxl367_range_scale_tbl;
981 *type = IIO_VAL_INT_PLUS_NANO;
982 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2;
983 return IIO_AVAIL_LIST;
984 case IIO_CHAN_INFO_SAMP_FREQ:
985 *vals = (int *)adxl367_samp_freq_tbl;
986 *type = IIO_VAL_INT_PLUS_MICRO;
987 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2;
988 return IIO_AVAIL_LIST;
989 default:
990 return -EINVAL;
991 }
992 }
993
adxl367_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)994 static int adxl367_read_event_value(struct iio_dev *indio_dev,
995 const struct iio_chan_spec *chan,
996 enum iio_event_type type,
997 enum iio_event_direction dir,
998 enum iio_event_info info,
999 int *val, int *val2)
1000 {
1001 struct adxl367_state *st = iio_priv(indio_dev);
1002
1003 switch (info) {
1004 case IIO_EV_INFO_VALUE: {
1005 switch (dir) {
1006 case IIO_EV_DIR_RISING:
1007 mutex_lock(&st->lock);
1008 *val = st->act_threshold;
1009 mutex_unlock(&st->lock);
1010 return IIO_VAL_INT;
1011 case IIO_EV_DIR_FALLING:
1012 mutex_lock(&st->lock);
1013 *val = st->inact_threshold;
1014 mutex_unlock(&st->lock);
1015 return IIO_VAL_INT;
1016 default:
1017 return -EINVAL;
1018 }
1019 }
1020 case IIO_EV_INFO_PERIOD:
1021 switch (dir) {
1022 case IIO_EV_DIR_RISING:
1023 mutex_lock(&st->lock);
1024 *val = st->act_time_ms;
1025 mutex_unlock(&st->lock);
1026 *val2 = 1000;
1027 return IIO_VAL_FRACTIONAL;
1028 case IIO_EV_DIR_FALLING:
1029 mutex_lock(&st->lock);
1030 *val = st->inact_time_ms;
1031 mutex_unlock(&st->lock);
1032 *val2 = 1000;
1033 return IIO_VAL_FRACTIONAL;
1034 default:
1035 return -EINVAL;
1036 }
1037 default:
1038 return -EINVAL;
1039 }
1040 }
1041
adxl367_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1042 static int adxl367_write_event_value(struct iio_dev *indio_dev,
1043 const struct iio_chan_spec *chan,
1044 enum iio_event_type type,
1045 enum iio_event_direction dir,
1046 enum iio_event_info info,
1047 int val, int val2)
1048 {
1049 struct adxl367_state *st = iio_priv(indio_dev);
1050
1051 switch (info) {
1052 case IIO_EV_INFO_VALUE:
1053 if (val < 0)
1054 return -EINVAL;
1055
1056 switch (dir) {
1057 case IIO_EV_DIR_RISING:
1058 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val);
1059 case IIO_EV_DIR_FALLING:
1060 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val);
1061 default:
1062 return -EINVAL;
1063 }
1064 case IIO_EV_INFO_PERIOD:
1065 if (val < 0)
1066 return -EINVAL;
1067
1068 val = val * 1000 + DIV_ROUND_UP(val2, 1000);
1069 switch (dir) {
1070 case IIO_EV_DIR_RISING:
1071 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val);
1072 case IIO_EV_DIR_FALLING:
1073 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val);
1074 default:
1075 return -EINVAL;
1076 }
1077 default:
1078 return -EINVAL;
1079 }
1080 }
1081
adxl367_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1082 static int adxl367_read_event_config(struct iio_dev *indio_dev,
1083 const struct iio_chan_spec *chan,
1084 enum iio_event_type type,
1085 enum iio_event_direction dir)
1086 {
1087 struct adxl367_state *st = iio_priv(indio_dev);
1088 bool en;
1089 int ret;
1090
1091 switch (dir) {
1092 case IIO_EV_DIR_RISING:
1093 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en);
1094 return ret ?: en;
1095 case IIO_EV_DIR_FALLING:
1096 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en);
1097 return ret ?: en;
1098 default:
1099 return -EINVAL;
1100 }
1101 }
1102
adxl367_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)1103 static int adxl367_write_event_config(struct iio_dev *indio_dev,
1104 const struct iio_chan_spec *chan,
1105 enum iio_event_type type,
1106 enum iio_event_direction dir,
1107 int state)
1108 {
1109 struct adxl367_state *st = iio_priv(indio_dev);
1110 enum adxl367_activity_type act;
1111 int ret;
1112
1113 switch (dir) {
1114 case IIO_EV_DIR_RISING:
1115 act = ADXL367_ACTIVITY;
1116 break;
1117 case IIO_EV_DIR_FALLING:
1118 act = ADXL367_INACTIVITY;
1119 break;
1120 default:
1121 return -EINVAL;
1122 }
1123
1124 ret = iio_device_claim_direct_mode(indio_dev);
1125 if (ret)
1126 return ret;
1127
1128 mutex_lock(&st->lock);
1129
1130 ret = adxl367_set_measure_en(st, false);
1131 if (ret)
1132 goto out;
1133
1134 ret = adxl367_set_act_interrupt_en(st, act, state);
1135 if (ret)
1136 goto out;
1137
1138 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED
1139 : ADXL367_ACT_DISABLED);
1140 if (ret)
1141 goto out;
1142
1143 ret = adxl367_set_measure_en(st, true);
1144
1145 out:
1146 mutex_unlock(&st->lock);
1147
1148 iio_device_release_direct_mode(indio_dev);
1149
1150 return ret;
1151 }
1152
adxl367_get_fifo_enabled(struct device * dev,struct device_attribute * attr,char * buf)1153 static ssize_t adxl367_get_fifo_enabled(struct device *dev,
1154 struct device_attribute *attr,
1155 char *buf)
1156 {
1157 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1158 enum adxl367_fifo_mode fifo_mode;
1159 int ret;
1160
1161 ret = adxl367_get_fifo_mode(st, &fifo_mode);
1162 if (ret)
1163 return ret;
1164
1165 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED);
1166 }
1167
adxl367_get_fifo_watermark(struct device * dev,struct device_attribute * attr,char * buf)1168 static ssize_t adxl367_get_fifo_watermark(struct device *dev,
1169 struct device_attribute *attr,
1170 char *buf)
1171 {
1172 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1173 unsigned int fifo_watermark;
1174
1175 mutex_lock(&st->lock);
1176 fifo_watermark = st->fifo_watermark;
1177 mutex_unlock(&st->lock);
1178
1179 return sysfs_emit(buf, "%d\n", fifo_watermark);
1180 }
1181
1182 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1");
1183 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max,
1184 __stringify(ADXL367_FIFO_MAX_WATERMARK));
1185 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1186 adxl367_get_fifo_watermark, NULL, 0);
1187 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1188 adxl367_get_fifo_enabled, NULL, 0);
1189
1190 static const struct iio_dev_attr *adxl367_fifo_attributes[] = {
1191 &iio_dev_attr_hwfifo_watermark_min,
1192 &iio_dev_attr_hwfifo_watermark_max,
1193 &iio_dev_attr_hwfifo_watermark,
1194 &iio_dev_attr_hwfifo_enabled,
1195 NULL,
1196 };
1197
adxl367_set_watermark(struct iio_dev * indio_dev,unsigned int val)1198 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1199 {
1200 struct adxl367_state *st = iio_priv(indio_dev);
1201 int ret;
1202
1203 if (val > ADXL367_FIFO_MAX_WATERMARK)
1204 return -EINVAL;
1205
1206 mutex_lock(&st->lock);
1207
1208 ret = adxl367_set_measure_en(st, false);
1209 if (ret)
1210 goto out;
1211
1212 ret = adxl367_set_fifo_watermark(st, val);
1213 if (ret)
1214 goto out;
1215
1216 ret = adxl367_set_measure_en(st, true);
1217
1218 out:
1219 mutex_unlock(&st->lock);
1220
1221 return ret;
1222 }
1223
adxl367_find_mask_fifo_format(const unsigned long * scan_mask,enum adxl367_fifo_format * fifo_format)1224 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask,
1225 enum adxl367_fifo_format *fifo_format)
1226 {
1227 size_t size = ARRAY_SIZE(adxl367_fifo_formats);
1228 int i;
1229
1230 for (i = 0; i < size; i++)
1231 if (*scan_mask == adxl367_channel_masks[i])
1232 break;
1233
1234 if (i == size)
1235 return false;
1236
1237 *fifo_format = adxl367_fifo_formats[i];
1238
1239 return true;
1240 }
1241
adxl367_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)1242 static int adxl367_update_scan_mode(struct iio_dev *indio_dev,
1243 const unsigned long *active_scan_mask)
1244 {
1245 struct adxl367_state *st = iio_priv(indio_dev);
1246 enum adxl367_fifo_format fifo_format;
1247 int ret;
1248
1249 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format))
1250 return -EINVAL;
1251
1252 mutex_lock(&st->lock);
1253
1254 ret = adxl367_set_measure_en(st, false);
1255 if (ret)
1256 goto out;
1257
1258 ret = adxl367_set_fifo_format(st, fifo_format);
1259 if (ret)
1260 goto out;
1261
1262 ret = adxl367_set_measure_en(st, true);
1263 if (ret)
1264 goto out;
1265
1266 st->fifo_set_size = bitmap_weight(active_scan_mask,
1267 indio_dev->masklength);
1268
1269 out:
1270 mutex_unlock(&st->lock);
1271
1272 return ret;
1273 }
1274
adxl367_buffer_postenable(struct iio_dev * indio_dev)1275 static int adxl367_buffer_postenable(struct iio_dev *indio_dev)
1276 {
1277 struct adxl367_state *st = iio_priv(indio_dev);
1278 int ret;
1279
1280 mutex_lock(&st->lock);
1281
1282 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1283 true);
1284 if (ret)
1285 goto out;
1286
1287 ret = adxl367_set_measure_en(st, false);
1288 if (ret)
1289 goto out;
1290
1291 ret = adxl367_set_fifo_watermark_interrupt_en(st, true);
1292 if (ret)
1293 goto out;
1294
1295 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM);
1296 if (ret)
1297 goto out;
1298
1299 ret = adxl367_set_measure_en(st, true);
1300
1301 out:
1302 mutex_unlock(&st->lock);
1303
1304 return ret;
1305 }
1306
adxl367_buffer_predisable(struct iio_dev * indio_dev)1307 static int adxl367_buffer_predisable(struct iio_dev *indio_dev)
1308 {
1309 struct adxl367_state *st = iio_priv(indio_dev);
1310 int ret;
1311
1312 mutex_lock(&st->lock);
1313
1314 ret = adxl367_set_measure_en(st, false);
1315 if (ret)
1316 goto out;
1317
1318 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED);
1319 if (ret)
1320 goto out;
1321
1322 ret = adxl367_set_fifo_watermark_interrupt_en(st, false);
1323 if (ret)
1324 goto out;
1325
1326 ret = adxl367_set_measure_en(st, true);
1327 if (ret)
1328 goto out;
1329
1330 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1331 false);
1332
1333 out:
1334 mutex_unlock(&st->lock);
1335
1336 return ret;
1337 }
1338
1339 static const struct iio_buffer_setup_ops adxl367_buffer_ops = {
1340 .postenable = adxl367_buffer_postenable,
1341 .predisable = adxl367_buffer_predisable,
1342 };
1343
1344 static const struct iio_info adxl367_info = {
1345 .read_raw = adxl367_read_raw,
1346 .write_raw = adxl367_write_raw,
1347 .write_raw_get_fmt = adxl367_write_raw_get_fmt,
1348 .read_avail = adxl367_read_avail,
1349 .read_event_config = adxl367_read_event_config,
1350 .write_event_config = adxl367_write_event_config,
1351 .read_event_value = adxl367_read_event_value,
1352 .write_event_value = adxl367_write_event_value,
1353 .debugfs_reg_access = adxl367_reg_access,
1354 .hwfifo_set_watermark = adxl367_set_watermark,
1355 .update_scan_mode = adxl367_update_scan_mode,
1356 };
1357
1358 static const struct iio_event_spec adxl367_events[] = {
1359 {
1360 .type = IIO_EV_TYPE_MAG_REFERENCED,
1361 .dir = IIO_EV_DIR_RISING,
1362 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1363 BIT(IIO_EV_INFO_PERIOD) |
1364 BIT(IIO_EV_INFO_VALUE),
1365 },
1366 {
1367 .type = IIO_EV_TYPE_MAG_REFERENCED,
1368 .dir = IIO_EV_DIR_FALLING,
1369 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1370 BIT(IIO_EV_INFO_PERIOD) |
1371 BIT(IIO_EV_INFO_VALUE),
1372 },
1373 };
1374
1375 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \
1376 .type = IIO_ACCEL, \
1377 .address = (reg), \
1378 .modified = 1, \
1379 .channel2 = IIO_MOD_##axis, \
1380 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1381 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1382 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
1383 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1384 .info_mask_shared_by_all_available = \
1385 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1386 .event_spec = adxl367_events, \
1387 .num_event_specs = ARRAY_SIZE(adxl367_events), \
1388 .scan_index = (index), \
1389 .scan_type = { \
1390 .sign = 's', \
1391 .realbits = 14, \
1392 .storagebits = 16, \
1393 .endianness = IIO_BE, \
1394 }, \
1395 }
1396
1397 #define ADXL367_CHANNEL(index, reg, _type) { \
1398 .type = (_type), \
1399 .address = (reg), \
1400 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1401 BIT(IIO_CHAN_INFO_OFFSET) | \
1402 BIT(IIO_CHAN_INFO_SCALE), \
1403 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1404 .scan_index = (index), \
1405 .scan_type = { \
1406 .sign = 's', \
1407 .realbits = 14, \
1408 .storagebits = 16, \
1409 .endianness = IIO_BE, \
1410 }, \
1411 }
1412
1413 static const struct iio_chan_spec adxl367_channels[] = {
1414 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X),
1415 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y),
1416 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z),
1417 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H,
1418 IIO_TEMP),
1419 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H,
1420 IIO_VOLTAGE),
1421 };
1422
adxl367_verify_devid(struct adxl367_state * st)1423 static int adxl367_verify_devid(struct adxl367_state *st)
1424 {
1425 unsigned int val;
1426 int ret;
1427
1428 ret = regmap_read(st->regmap, ADXL367_REG_DEVID, &val);
1429 if (ret)
1430 return dev_err_probe(st->dev, ret, "Failed to read dev id\n");
1431
1432 if (val != ADXL367_DEVID_AD)
1433 return dev_err_probe(st->dev, -ENODEV,
1434 "Invalid dev id 0x%02X, expected 0x%02X\n",
1435 val, ADXL367_DEVID_AD);
1436
1437 return 0;
1438 }
1439
adxl367_setup(struct adxl367_state * st)1440 static int adxl367_setup(struct adxl367_state *st)
1441 {
1442 int ret;
1443
1444 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
1445 ADXL367_2G_RANGE_1G);
1446 if (ret)
1447 return ret;
1448
1449 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
1450 ADXL367_2G_RANGE_100MG);
1451 if (ret)
1452 return ret;
1453
1454 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED);
1455 if (ret)
1456 return ret;
1457
1458 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ);
1459 if (ret)
1460 return ret;
1461
1462 ret = _adxl367_set_act_time_ms(st, 10);
1463 if (ret)
1464 return ret;
1465
1466 ret = _adxl367_set_inact_time_ms(st, 10000);
1467 if (ret)
1468 return ret;
1469
1470 return adxl367_set_measure_en(st, true);
1471 }
1472
adxl367_probe(struct device * dev,const struct adxl367_ops * ops,void * context,struct regmap * regmap,int irq)1473 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
1474 void *context, struct regmap *regmap, int irq)
1475 {
1476 static const char * const regulator_names[] = { "vdd", "vddio" };
1477 struct iio_dev *indio_dev;
1478 struct adxl367_state *st;
1479 int ret;
1480
1481 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1482 if (!indio_dev)
1483 return -ENOMEM;
1484
1485 st = iio_priv(indio_dev);
1486 st->dev = dev;
1487 st->regmap = regmap;
1488 st->context = context;
1489 st->ops = ops;
1490
1491 mutex_init(&st->lock);
1492
1493 indio_dev->channels = adxl367_channels;
1494 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels);
1495 indio_dev->available_scan_masks = adxl367_channel_masks;
1496 indio_dev->name = "adxl367";
1497 indio_dev->info = &adxl367_info;
1498 indio_dev->modes = INDIO_DIRECT_MODE;
1499
1500 ret = devm_regulator_bulk_get_enable(st->dev,
1501 ARRAY_SIZE(regulator_names),
1502 regulator_names);
1503 if (ret)
1504 return dev_err_probe(st->dev, ret,
1505 "Failed to get regulators\n");
1506
1507 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE);
1508 if (ret)
1509 return ret;
1510
1511 fsleep(15000);
1512
1513 ret = adxl367_verify_devid(st);
1514 if (ret)
1515 return ret;
1516
1517 ret = adxl367_setup(st);
1518 if (ret)
1519 return ret;
1520
1521 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,
1522 &adxl367_buffer_ops,
1523 adxl367_fifo_attributes);
1524 if (ret)
1525 return ret;
1526
1527 ret = devm_request_threaded_irq(st->dev, irq, NULL,
1528 adxl367_irq_handler, IRQF_ONESHOT,
1529 indio_dev->name, indio_dev);
1530 if (ret)
1531 return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1532
1533 return devm_iio_device_register(dev, indio_dev);
1534 }
1535 EXPORT_SYMBOL_NS_GPL(adxl367_probe, IIO_ADXL367);
1536
1537 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1538 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver");
1539 MODULE_LICENSE("GPL");
1540