1 /*
2 * Xilinx Zynq Baseboard System emulation.
3 *
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/units.h"
20 #include "qapi/error.h"
21 #include "hw/sysbus.h"
22 #include "hw/arm/boot.h"
23 #include "net/net.h"
24 #include "sysemu/sysemu.h"
25 #include "hw/boards.h"
26 #include "hw/block/flash.h"
27 #include "hw/loader.h"
28 #include "hw/adc/zynq-xadc.h"
29 #include "hw/ssi/ssi.h"
30 #include "hw/usb/chipidea.h"
31 #include "qemu/error-report.h"
32 #include "hw/sd/sdhci.h"
33 #include "hw/char/cadence_uart.h"
34 #include "hw/net/cadence_gem.h"
35 #include "hw/cpu/a9mpcore.h"
36 #include "hw/qdev-clock.h"
37 #include "hw/misc/unimp.h"
38 #include "sysemu/reset.h"
39 #include "qom/object.h"
40 #include "exec/tswap.h"
41 #include "target/arm/cpu-qom.h"
42 #include "qapi/visitor.h"
43
44 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
45 OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
46
47 /* board base frequency: 33.333333 MHz */
48 #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
49
50 #define NUM_SPI_FLASHES 4
51 #define NUM_QSPI_FLASHES 2
52 #define NUM_QSPI_BUSSES 2
53
54 #define FLASH_SIZE (64 * 1024 * 1024)
55 #define FLASH_SECTOR_SIZE (128 * 1024)
56
57 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
58
59 #define MPCORE_PERIPHBASE 0xF8F00000
60 #define ZYNQ_BOARD_MIDR 0x413FC090
61
62 static const int dma_irqs[8] = {
63 46, 47, 48, 49, 72, 73, 74, 75
64 };
65
66 #define BOARD_SETUP_ADDR 0x100
67
68 #define SLCR_LOCK_OFFSET 0x004
69 #define SLCR_UNLOCK_OFFSET 0x008
70 #define SLCR_ARM_PLL_OFFSET 0x100
71
72 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
73 #define SLCR_XILINX_LOCK_KEY 0x767b
74
75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
76
77 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
78 extract32((x), 12, 4) << 16)
79
80 /* Write immediate val to address r0 + addr. r0 should contain base offset
81 * of the SLCR block. Clobbers r1.
82 */
83
84 #define SLCR_WRITE(addr, val) \
85 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
86 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
87 0xe5801000 + (addr)
88
89 #define ZYNQ_MAX_CPUS 2
90
91 struct ZynqMachineState {
92 MachineState parent;
93 Clock *ps_clk;
94 ARMCPU *cpu[ZYNQ_MAX_CPUS];
95 uint8_t boot_mode;
96 };
97
zynq_write_board_setup(ARMCPU * cpu,const struct arm_boot_info * info)98 static void zynq_write_board_setup(ARMCPU *cpu,
99 const struct arm_boot_info *info)
100 {
101 int n;
102 uint32_t board_setup_blob[] = {
103 0xe3a004f8, /* mov r0, #0xf8000000 */
104 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
105 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
106 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
107 0xe12fff1e, /* bx lr */
108 };
109 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
110 board_setup_blob[n] = tswap32(board_setup_blob[n]);
111 }
112 rom_add_blob_fixed("board-setup", board_setup_blob,
113 sizeof(board_setup_blob), BOARD_SETUP_ADDR);
114 }
115
116 static struct arm_boot_info zynq_binfo = {};
117
gem_init(uint32_t base,qemu_irq irq)118 static void gem_init(uint32_t base, qemu_irq irq)
119 {
120 DeviceState *dev;
121 SysBusDevice *s;
122
123 dev = qdev_new(TYPE_CADENCE_GEM);
124 qemu_configure_nic_device(dev, true, NULL);
125 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort);
126 s = SYS_BUS_DEVICE(dev);
127 sysbus_realize_and_unref(s, &error_fatal);
128 sysbus_mmio_map(s, 0, base);
129 sysbus_connect_irq(s, 0, irq);
130 }
131
zynq_init_spi_flashes(uint32_t base_addr,qemu_irq irq,bool is_qspi,int unit0)132 static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
133 bool is_qspi, int unit0)
134 {
135 int unit = unit0;
136 DeviceState *dev;
137 SysBusDevice *busdev;
138 SSIBus *spi;
139 DeviceState *flash_dev;
140 int i, j;
141 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
142 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
143
144 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
145 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
146 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
147 qdev_prop_set_uint8(dev, "num-busses", num_busses);
148 busdev = SYS_BUS_DEVICE(dev);
149 sysbus_realize_and_unref(busdev, &error_fatal);
150 sysbus_mmio_map(busdev, 0, base_addr);
151 if (is_qspi) {
152 sysbus_mmio_map(busdev, 1, 0xFC000000);
153 }
154 sysbus_connect_irq(busdev, 0, irq);
155
156 for (i = 0; i < num_busses; ++i) {
157 char bus_name[16];
158 qemu_irq cs_line;
159
160 snprintf(bus_name, 16, "spi%d", i);
161 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
162
163 for (j = 0; j < num_ss; ++j) {
164 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++);
165 flash_dev = qdev_new("n25q128");
166 if (dinfo) {
167 qdev_prop_set_drive_err(flash_dev, "drive",
168 blk_by_legacy_dinfo(dinfo),
169 &error_fatal);
170 }
171 qdev_prop_set_uint8(flash_dev, "cs", j);
172 qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);
173
174 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
175 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
176 }
177 }
178
179 return unit;
180 }
181
zynq_set_boot_mode(Object * obj,const char * str,Error ** errp)182 static void zynq_set_boot_mode(Object *obj, const char *str,
183 Error **errp)
184 {
185 ZynqMachineState *m = ZYNQ_MACHINE(obj);
186 uint8_t mode = 0;
187
188 if (!strncasecmp(str, "qspi", 4)) {
189 mode = 1;
190 } else if (!strncasecmp(str, "sd", 2)) {
191 mode = 5;
192 } else if (!strncasecmp(str, "nor", 3)) {
193 mode = 2;
194 } else if (!strncasecmp(str, "jtag", 4)) {
195 mode = 0;
196 } else {
197 error_setg(errp, "%s boot mode not supported", str);
198 return;
199 }
200 m->boot_mode = mode;
201 }
202
zynq_init(MachineState * machine)203 static void zynq_init(MachineState *machine)
204 {
205 ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
206 MemoryRegion *address_space_mem = get_system_memory();
207 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
208 DeviceState *dev, *slcr;
209 SysBusDevice *busdev;
210 qemu_irq pic[64];
211 int n;
212 unsigned int smp_cpus = machine->smp.cpus;
213
214 /* max 2GB ram */
215 if (machine->ram_size > 2 * GiB) {
216 error_report("RAM size more than 2 GiB is not supported");
217 exit(EXIT_FAILURE);
218 }
219
220 for (n = 0; n < smp_cpus; n++) {
221 Object *cpuobj = object_new(machine->cpu_type);
222
223 object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR,
224 &error_fatal);
225 object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
226 &error_fatal);
227
228 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
229
230 zynq_machine->cpu[n] = ARM_CPU(cpuobj);
231 }
232
233 /* DDR remapped to address zero. */
234 memory_region_add_subregion(address_space_mem, 0, machine->ram);
235
236 /* 256K of on-chip memory */
237 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
238 &error_fatal);
239 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
240
241 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
242
243 /* AMD */
244 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
245 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
246 FLASH_SECTOR_SIZE, 1,
247 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
248 0);
249
250 /* Create the main clock source, and feed slcr with it */
251 zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
252 object_property_add_child(OBJECT(zynq_machine), "ps_clk",
253 OBJECT(zynq_machine->ps_clk));
254 object_unref(OBJECT(zynq_machine->ps_clk));
255 clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
256
257 /* Create slcr, keep a pointer to connect clocks */
258 slcr = qdev_new("xilinx-zynq_slcr");
259 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
260 qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode);
261 sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
262 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
263
264 dev = qdev_new(TYPE_A9MPCORE_PRIV);
265 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
266 busdev = SYS_BUS_DEVICE(dev);
267 sysbus_realize_and_unref(busdev, &error_fatal);
268 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
269 zynq_binfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100;
270 sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL);
271 for (n = 0; n < smp_cpus; n++) {
272 /* See "hw/intc/arm_gic.h" for the IRQ line association */
273 DeviceState *cpudev = DEVICE(zynq_machine->cpu[n]);
274 sysbus_connect_irq(busdev, n,
275 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
276 sysbus_connect_irq(busdev, smp_cpus + n,
277 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
278 }
279
280 for (n = 0; n < 64; n++) {
281 pic[n] = qdev_get_gpio_in(dev, n);
282 }
283
284 n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0);
285 n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n);
286 n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n);
287
288 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
289 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
290
291 dev = qdev_new(TYPE_CADENCE_UART);
292 busdev = SYS_BUS_DEVICE(dev);
293 qdev_prop_set_chr(dev, "chardev", serial_hd(0));
294 qdev_connect_clock_in(dev, "refclk",
295 qdev_get_clock_out(slcr, "uart0_ref_clk"));
296 sysbus_realize_and_unref(busdev, &error_fatal);
297 sysbus_mmio_map(busdev, 0, 0xE0000000);
298 sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
299 dev = qdev_new(TYPE_CADENCE_UART);
300 busdev = SYS_BUS_DEVICE(dev);
301 qdev_prop_set_chr(dev, "chardev", serial_hd(1));
302 qdev_connect_clock_in(dev, "refclk",
303 qdev_get_clock_out(slcr, "uart1_ref_clk"));
304 sysbus_realize_and_unref(busdev, &error_fatal);
305 sysbus_mmio_map(busdev, 0, 0xE0001000);
306 sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
307
308 sysbus_create_varargs("cadence_ttc", 0xF8001000,
309 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
310 sysbus_create_varargs("cadence_ttc", 0xF8002000,
311 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
312
313 gem_init(0xE000B000, pic[54 - IRQ_OFFSET]);
314 gem_init(0xE000C000, pic[77 - IRQ_OFFSET]);
315
316 for (n = 0; n < 2; n++) {
317 int hci_irq = n ? 79 : 56;
318 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
319 DriveInfo *di;
320 BlockBackend *blk;
321 DeviceState *carddev;
322
323 /* Compatible with:
324 * - SD Host Controller Specification Version 2.0 Part A2
325 * - SDIO Specification Version 2.0
326 * - MMC Specification Version 3.31
327 */
328 dev = qdev_new(TYPE_SYSBUS_SDHCI);
329 qdev_prop_set_uint8(dev, "sd-spec-version", 2);
330 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
331 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
332 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
333 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
334
335 di = drive_get(IF_SD, 0, n);
336 blk = di ? blk_by_legacy_dinfo(di) : NULL;
337 carddev = qdev_new(TYPE_SD_CARD);
338 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
339 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
340 &error_fatal);
341 }
342
343 dev = qdev_new(TYPE_ZYNQ_XADC);
344 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
345 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
346 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
347
348 dev = qdev_new("pl330");
349 object_property_set_link(OBJECT(dev), "memory",
350 OBJECT(address_space_mem),
351 &error_fatal);
352 qdev_prop_set_uint8(dev, "num_chnls", 8);
353 qdev_prop_set_uint8(dev, "num_periph_req", 4);
354 qdev_prop_set_uint8(dev, "num_events", 16);
355
356 qdev_prop_set_uint8(dev, "data_width", 64);
357 qdev_prop_set_uint8(dev, "wr_cap", 8);
358 qdev_prop_set_uint8(dev, "wr_q_dep", 16);
359 qdev_prop_set_uint8(dev, "rd_cap", 8);
360 qdev_prop_set_uint8(dev, "rd_q_dep", 16);
361 qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
362
363 busdev = SYS_BUS_DEVICE(dev);
364 sysbus_realize_and_unref(busdev, &error_fatal);
365 sysbus_mmio_map(busdev, 0, 0xF8003000);
366 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
367 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
368 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
369 }
370
371 dev = qdev_new("xlnx.ps7-dev-cfg");
372 busdev = SYS_BUS_DEVICE(dev);
373 sysbus_realize_and_unref(busdev, &error_fatal);
374 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
375 sysbus_mmio_map(busdev, 0, 0xF8007000);
376
377 /*
378 * Refer to the ug585-Zynq-7000-TRM manual B.3 (Module Summary) and
379 * the zynq-7000.dtsi. Add placeholders for unimplemented devices.
380 */
381 create_unimplemented_device("zynq.i2c0", 0xE0004000, 4 * KiB);
382 create_unimplemented_device("zynq.i2c1", 0xE0005000, 4 * KiB);
383 create_unimplemented_device("zynq.can0", 0xE0008000, 4 * KiB);
384 create_unimplemented_device("zynq.can1", 0xE0009000, 4 * KiB);
385 create_unimplemented_device("zynq.gpio", 0xE000A000, 4 * KiB);
386 create_unimplemented_device("zynq.smcc", 0xE000E000, 4 * KiB);
387
388 /* Direct Memory Access Controller, PL330, Non-Secure Mode */
389 create_unimplemented_device("zynq.dma_ns", 0xF8004000, 4 * KiB);
390
391 /* System Watchdog Timer Registers */
392 create_unimplemented_device("zynq.swdt", 0xF8005000, 4 * KiB);
393
394 /* DDR memory controller */
395 create_unimplemented_device("zynq.ddrc", 0xF8006000, 4 * KiB);
396
397 /* AXI_HP Interface (AFI) */
398 create_unimplemented_device("zynq.axi_hp0", 0xF8008000, 0x28);
399 create_unimplemented_device("zynq.axi_hp1", 0xF8009000, 0x28);
400 create_unimplemented_device("zynq.axi_hp2", 0xF800A000, 0x28);
401 create_unimplemented_device("zynq.axi_hp3", 0xF800B000, 0x28);
402
403 create_unimplemented_device("zynq.efuse", 0xF800d000, 0x20);
404
405 /* Embedded Trace Buffer */
406 create_unimplemented_device("zynq.etb", 0xF8801000, 4 * KiB);
407
408 /* Cross Trigger Interface, ETB and TPIU */
409 create_unimplemented_device("zynq.cti_etb_tpiu", 0xF8802000, 4 * KiB);
410
411 /* Trace Port Interface Unit */
412 create_unimplemented_device("zynq.tpiu", 0xF8803000, 4 * KiB);
413
414 /* CoreSight Trace Funnel */
415 create_unimplemented_device("zynq.funnel", 0xF8804000, 4 * KiB);
416
417 /* Instrumentation Trace Macrocell */
418 create_unimplemented_device("zynq.itm", 0xF8805000, 4 * KiB);
419
420 /* Cross Trigger Interface, FTM */
421 create_unimplemented_device("zynq.cti_ftm", 0xF8809000, 4 * KiB);
422
423 /* Fabric Trace Macrocell */
424 create_unimplemented_device("zynq.ftm", 0xF880B000, 4 * KiB);
425
426 /* Cortex A9 Performance Monitoring Unit, CPU */
427 create_unimplemented_device("cortex-a9.pmu0", 0xF8891000, 4 * KiB);
428 create_unimplemented_device("cortex-a9.pmu1", 0xF8893000, 4 * KiB);
429
430 /* Cross Trigger Interface, CPU */
431 create_unimplemented_device("zynq.cpu_cti0", 0xF8898000, 4 * KiB);
432 create_unimplemented_device("zynq.cpu_cti1", 0xF8899000, 4 * KiB);
433
434 /* CoreSight PTM-A9, CPU */
435 create_unimplemented_device("cortex-a9.ptm0", 0xF889c000, 4 * KiB);
436 create_unimplemented_device("cortex-a9.ptm1", 0xF889d000, 4 * KiB);
437
438 /* AMBA NIC301 TrustZone */
439 create_unimplemented_device("zynq.trustZone", 0xF8900000, 0x20);
440
441 /* AMBA Network Interconnect Advanced Quality of Service (QoS-301) */
442 create_unimplemented_device("zynq.qos301_cpu", 0xF8946000, 0x130);
443 create_unimplemented_device("zynq.qos301_dmac", 0xF8947000, 0x130);
444 create_unimplemented_device("zynq.qos301_iou", 0xF8948000, 0x130);
445
446 zynq_binfo.ram_size = machine->ram_size;
447 zynq_binfo.board_id = 0xd32;
448 zynq_binfo.loader_start = 0;
449 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
450 zynq_binfo.write_board_setup = zynq_write_board_setup;
451
452 arm_load_kernel(zynq_machine->cpu[0], machine, &zynq_binfo);
453 }
454
zynq_machine_class_init(ObjectClass * oc,void * data)455 static void zynq_machine_class_init(ObjectClass *oc, void *data)
456 {
457 static const char * const valid_cpu_types[] = {
458 ARM_CPU_TYPE_NAME("cortex-a9"),
459 NULL
460 };
461 MachineClass *mc = MACHINE_CLASS(oc);
462 ObjectProperty *prop;
463 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
464 mc->init = zynq_init;
465 mc->max_cpus = ZYNQ_MAX_CPUS;
466 mc->no_sdcard = 1;
467 mc->ignore_memory_transaction_failures = true;
468 mc->valid_cpu_types = valid_cpu_types;
469 mc->default_ram_id = "zynq.ext_ram";
470 prop = object_class_property_add_str(oc, "boot-mode", NULL,
471 zynq_set_boot_mode);
472 object_class_property_set_description(oc, "boot-mode",
473 "Supported boot modes:"
474 " jtag qspi sd nor");
475 object_property_set_default_str(prop, "qspi");
476 }
477
478 static const TypeInfo zynq_machine_type = {
479 .name = TYPE_ZYNQ_MACHINE,
480 .parent = TYPE_MACHINE,
481 .class_init = zynq_machine_class_init,
482 .instance_size = sizeof(ZynqMachineState),
483 };
484
zynq_machine_register_types(void)485 static void zynq_machine_register_types(void)
486 {
487 type_register_static(&zynq_machine_type);
488 }
489
490 type_init(zynq_machine_register_types)
491