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Searched defs:TX1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dvector_internals.h181 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ argument
209 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ argument
H A Dvector_helper.c1890 #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ argument
1936 #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ argument
2141 #define OPIVV2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ argument
2269 #define OPIVX2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ argument
3061 #define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ in RVVCALL() argument
3107 #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ argument
3342 #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ in RVVCALL() argument
3374 #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ in RVVCALL() argument