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Searched defs:TSR_WIS (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/hw/ppc/
H A Dppc_booke.c71 #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */ macro
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_booke.h557 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ macro
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h417 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ macro