1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2012 - 2014 Allwinner Tech
4 * Pan Nan <pannan@allwinnertech.com>
5 *
6 * Copyright (C) 2014 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18
19 #include <linux/spi/spi.h>
20
21 #define SUN4I_FIFO_DEPTH 64
22
23 #define SUN4I_RXDATA_REG 0x00
24
25 #define SUN4I_TXDATA_REG 0x04
26
27 #define SUN4I_CTL_REG 0x08
28 #define SUN4I_CTL_ENABLE BIT(0)
29 #define SUN4I_CTL_MASTER BIT(1)
30 #define SUN4I_CTL_CPHA BIT(2)
31 #define SUN4I_CTL_CPOL BIT(3)
32 #define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
33 #define SUN4I_CTL_LMTF BIT(6)
34 #define SUN4I_CTL_TF_RST BIT(8)
35 #define SUN4I_CTL_RF_RST BIT(9)
36 #define SUN4I_CTL_XCH BIT(10)
37 #define SUN4I_CTL_CS_MASK 0x3000
38 #define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
39 #define SUN4I_CTL_DHB BIT(15)
40 #define SUN4I_CTL_CS_MANUAL BIT(16)
41 #define SUN4I_CTL_CS_LEVEL BIT(17)
42 #define SUN4I_CTL_TP BIT(18)
43
44 #define SUN4I_INT_CTL_REG 0x0c
45 #define SUN4I_INT_CTL_RF_F34 BIT(4)
46 #define SUN4I_INT_CTL_TF_E34 BIT(12)
47 #define SUN4I_INT_CTL_TC BIT(16)
48
49 #define SUN4I_INT_STA_REG 0x10
50
51 #define SUN4I_DMA_CTL_REG 0x14
52
53 #define SUN4I_WAIT_REG 0x18
54
55 #define SUN4I_CLK_CTL_REG 0x1c
56 #define SUN4I_CLK_CTL_CDR2_MASK 0xff
57 #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
58 #define SUN4I_CLK_CTL_CDR1_MASK 0xf
59 #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
60 #define SUN4I_CLK_CTL_DRS BIT(12)
61
62 #define SUN4I_MAX_XFER_SIZE 0xffffff
63
64 #define SUN4I_BURST_CNT_REG 0x20
65 #define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
66
67 #define SUN4I_XMIT_CNT_REG 0x24
68 #define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
69
70
71 #define SUN4I_FIFO_STA_REG 0x28
72 #define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
73 #define SUN4I_FIFO_STA_RF_CNT_BITS 0
74 #define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
75 #define SUN4I_FIFO_STA_TF_CNT_BITS 16
76
77 struct sun4i_spi {
78 struct spi_master *master;
79 void __iomem *base_addr;
80 struct clk *hclk;
81 struct clk *mclk;
82
83 struct completion done;
84
85 const u8 *tx_buf;
86 u8 *rx_buf;
87 int len;
88 };
89
sun4i_spi_read(struct sun4i_spi * sspi,u32 reg)90 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
91 {
92 return readl(sspi->base_addr + reg);
93 }
94
sun4i_spi_write(struct sun4i_spi * sspi,u32 reg,u32 value)95 static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
96 {
97 writel(value, sspi->base_addr + reg);
98 }
99
sun4i_spi_get_tx_fifo_count(struct sun4i_spi * sspi)100 static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
101 {
102 u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
103
104 reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
105
106 return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
107 }
108
sun4i_spi_enable_interrupt(struct sun4i_spi * sspi,u32 mask)109 static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
110 {
111 u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
112
113 reg |= mask;
114 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
115 }
116
sun4i_spi_disable_interrupt(struct sun4i_spi * sspi,u32 mask)117 static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
118 {
119 u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
120
121 reg &= ~mask;
122 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
123 }
124
sun4i_spi_drain_fifo(struct sun4i_spi * sspi,int len)125 static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
126 {
127 u32 reg, cnt;
128 u8 byte;
129
130 /* See how much data is available */
131 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
132 reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
133 cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
134
135 if (len > cnt)
136 len = cnt;
137
138 while (len--) {
139 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
140 if (sspi->rx_buf)
141 *sspi->rx_buf++ = byte;
142 }
143 }
144
sun4i_spi_fill_fifo(struct sun4i_spi * sspi,int len)145 static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
146 {
147 u32 cnt;
148 u8 byte;
149
150 /* See how much data we can fit */
151 cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
152
153 len = min3(len, (int)cnt, sspi->len);
154
155 while (len--) {
156 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
157 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
158 sspi->len--;
159 }
160 }
161
sun4i_spi_set_cs(struct spi_device * spi,bool enable)162 static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
163 {
164 struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
165 u32 reg;
166
167 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
168
169 reg &= ~SUN4I_CTL_CS_MASK;
170 reg |= SUN4I_CTL_CS(spi_get_chipselect(spi, 0));
171
172 /* We want to control the chip select manually */
173 reg |= SUN4I_CTL_CS_MANUAL;
174
175 if (enable)
176 reg |= SUN4I_CTL_CS_LEVEL;
177 else
178 reg &= ~SUN4I_CTL_CS_LEVEL;
179
180 /*
181 * Even though this looks irrelevant since we are supposed to
182 * be controlling the chip select manually, this bit also
183 * controls the levels of the chip select for inactive
184 * devices.
185 *
186 * If we don't set it, the chip select level will go low by
187 * default when the device is idle, which is not really
188 * expected in the common case where the chip select is active
189 * low.
190 */
191 if (spi->mode & SPI_CS_HIGH)
192 reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
193 else
194 reg |= SUN4I_CTL_CS_ACTIVE_LOW;
195
196 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
197 }
198
sun4i_spi_max_transfer_size(struct spi_device * spi)199 static size_t sun4i_spi_max_transfer_size(struct spi_device *spi)
200 {
201 return SUN4I_MAX_XFER_SIZE - 1;
202 }
203
sun4i_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)204 static int sun4i_spi_transfer_one(struct spi_master *master,
205 struct spi_device *spi,
206 struct spi_transfer *tfr)
207 {
208 struct sun4i_spi *sspi = spi_master_get_devdata(master);
209 unsigned int mclk_rate, div, timeout;
210 unsigned int start, end, tx_time;
211 unsigned int tx_len = 0;
212 int ret = 0;
213 u32 reg;
214
215 /* We don't support transfer larger than the FIFO */
216 if (tfr->len > SUN4I_MAX_XFER_SIZE)
217 return -EMSGSIZE;
218
219 if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE)
220 return -EMSGSIZE;
221
222 reinit_completion(&sspi->done);
223 sspi->tx_buf = tfr->tx_buf;
224 sspi->rx_buf = tfr->rx_buf;
225 sspi->len = tfr->len;
226
227 /* Clear pending interrupts */
228 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
229
230
231 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
232
233 /* Reset FIFOs */
234 sun4i_spi_write(sspi, SUN4I_CTL_REG,
235 reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
236
237 /*
238 * Setup the transfer control register: Chip Select,
239 * polarities, etc.
240 */
241 if (spi->mode & SPI_CPOL)
242 reg |= SUN4I_CTL_CPOL;
243 else
244 reg &= ~SUN4I_CTL_CPOL;
245
246 if (spi->mode & SPI_CPHA)
247 reg |= SUN4I_CTL_CPHA;
248 else
249 reg &= ~SUN4I_CTL_CPHA;
250
251 if (spi->mode & SPI_LSB_FIRST)
252 reg |= SUN4I_CTL_LMTF;
253 else
254 reg &= ~SUN4I_CTL_LMTF;
255
256
257 /*
258 * If it's a TX only transfer, we don't want to fill the RX
259 * FIFO with bogus data
260 */
261 if (sspi->rx_buf)
262 reg &= ~SUN4I_CTL_DHB;
263 else
264 reg |= SUN4I_CTL_DHB;
265
266 /* Now that the settings are correct, enable the interface */
267 reg |= SUN4I_CTL_ENABLE;
268
269 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
270
271 /* Ensure that we have a parent clock fast enough */
272 mclk_rate = clk_get_rate(sspi->mclk);
273 if (mclk_rate < (2 * tfr->speed_hz)) {
274 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
275 mclk_rate = clk_get_rate(sspi->mclk);
276 }
277
278 /*
279 * Setup clock divider.
280 *
281 * We have two choices there. Either we can use the clock
282 * divide rate 1, which is calculated thanks to this formula:
283 * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
284 * Or we can use CDR2, which is calculated with the formula:
285 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
286 * Whether we use the former or the latter is set through the
287 * DRS bit.
288 *
289 * First try CDR2, and if we can't reach the expected
290 * frequency, fall back to CDR1.
291 */
292 div = mclk_rate / (2 * tfr->speed_hz);
293 if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
294 if (div > 0)
295 div--;
296
297 reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
298 } else {
299 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
300 reg = SUN4I_CLK_CTL_CDR1(div);
301 }
302
303 sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
304
305 /* Setup the transfer now... */
306 if (sspi->tx_buf)
307 tx_len = tfr->len;
308
309 /* Setup the counters */
310 sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
311 sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
312
313 /*
314 * Fill the TX FIFO
315 * Filling the FIFO fully causes timeout for some reason
316 * at least on spi2 on A10s
317 */
318 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
319
320 /* Enable the interrupts */
321 sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
322 SUN4I_INT_CTL_RF_F34);
323 /* Only enable Tx FIFO interrupt if we really need it */
324 if (tx_len > SUN4I_FIFO_DEPTH)
325 sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
326
327 /* Start the transfer */
328 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
329 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
330
331 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
332 start = jiffies;
333 timeout = wait_for_completion_timeout(&sspi->done,
334 msecs_to_jiffies(tx_time));
335 end = jiffies;
336 if (!timeout) {
337 dev_warn(&master->dev,
338 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
339 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
340 jiffies_to_msecs(end - start), tx_time);
341 ret = -ETIMEDOUT;
342 goto out;
343 }
344
345
346 out:
347 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
348
349 return ret;
350 }
351
sun4i_spi_handler(int irq,void * dev_id)352 static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
353 {
354 struct sun4i_spi *sspi = dev_id;
355 u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
356
357 /* Transfer complete */
358 if (status & SUN4I_INT_CTL_TC) {
359 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
360 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
361 complete(&sspi->done);
362 return IRQ_HANDLED;
363 }
364
365 /* Receive FIFO 3/4 full */
366 if (status & SUN4I_INT_CTL_RF_F34) {
367 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
368 /* Only clear the interrupt _after_ draining the FIFO */
369 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
370 return IRQ_HANDLED;
371 }
372
373 /* Transmit FIFO 3/4 empty */
374 if (status & SUN4I_INT_CTL_TF_E34) {
375 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
376
377 if (!sspi->len)
378 /* nothing left to transmit */
379 sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
380
381 /* Only clear the interrupt _after_ re-seeding the FIFO */
382 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
383
384 return IRQ_HANDLED;
385 }
386
387 return IRQ_NONE;
388 }
389
sun4i_spi_runtime_resume(struct device * dev)390 static int sun4i_spi_runtime_resume(struct device *dev)
391 {
392 struct spi_master *master = dev_get_drvdata(dev);
393 struct sun4i_spi *sspi = spi_master_get_devdata(master);
394 int ret;
395
396 ret = clk_prepare_enable(sspi->hclk);
397 if (ret) {
398 dev_err(dev, "Couldn't enable AHB clock\n");
399 goto out;
400 }
401
402 ret = clk_prepare_enable(sspi->mclk);
403 if (ret) {
404 dev_err(dev, "Couldn't enable module clock\n");
405 goto err;
406 }
407
408 sun4i_spi_write(sspi, SUN4I_CTL_REG,
409 SUN4I_CTL_MASTER | SUN4I_CTL_TP);
410
411 return 0;
412
413 err:
414 clk_disable_unprepare(sspi->hclk);
415 out:
416 return ret;
417 }
418
sun4i_spi_runtime_suspend(struct device * dev)419 static int sun4i_spi_runtime_suspend(struct device *dev)
420 {
421 struct spi_master *master = dev_get_drvdata(dev);
422 struct sun4i_spi *sspi = spi_master_get_devdata(master);
423
424 clk_disable_unprepare(sspi->mclk);
425 clk_disable_unprepare(sspi->hclk);
426
427 return 0;
428 }
429
sun4i_spi_probe(struct platform_device * pdev)430 static int sun4i_spi_probe(struct platform_device *pdev)
431 {
432 struct spi_master *master;
433 struct sun4i_spi *sspi;
434 int ret = 0, irq;
435
436 master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
437 if (!master) {
438 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
439 return -ENOMEM;
440 }
441
442 platform_set_drvdata(pdev, master);
443 sspi = spi_master_get_devdata(master);
444
445 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
446 if (IS_ERR(sspi->base_addr)) {
447 ret = PTR_ERR(sspi->base_addr);
448 goto err_free_master;
449 }
450
451 irq = platform_get_irq(pdev, 0);
452 if (irq < 0) {
453 ret = -ENXIO;
454 goto err_free_master;
455 }
456
457 ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
458 0, "sun4i-spi", sspi);
459 if (ret) {
460 dev_err(&pdev->dev, "Cannot request IRQ\n");
461 goto err_free_master;
462 }
463
464 sspi->master = master;
465 master->max_speed_hz = 100 * 1000 * 1000;
466 master->min_speed_hz = 3 * 1000;
467 master->set_cs = sun4i_spi_set_cs;
468 master->transfer_one = sun4i_spi_transfer_one;
469 master->num_chipselect = 4;
470 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
471 master->bits_per_word_mask = SPI_BPW_MASK(8);
472 master->dev.of_node = pdev->dev.of_node;
473 master->auto_runtime_pm = true;
474 master->max_transfer_size = sun4i_spi_max_transfer_size;
475
476 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
477 if (IS_ERR(sspi->hclk)) {
478 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
479 ret = PTR_ERR(sspi->hclk);
480 goto err_free_master;
481 }
482
483 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
484 if (IS_ERR(sspi->mclk)) {
485 dev_err(&pdev->dev, "Unable to acquire module clock\n");
486 ret = PTR_ERR(sspi->mclk);
487 goto err_free_master;
488 }
489
490 init_completion(&sspi->done);
491
492 /*
493 * This wake-up/shutdown pattern is to be able to have the
494 * device woken up, even if runtime_pm is disabled
495 */
496 ret = sun4i_spi_runtime_resume(&pdev->dev);
497 if (ret) {
498 dev_err(&pdev->dev, "Couldn't resume the device\n");
499 goto err_free_master;
500 }
501
502 pm_runtime_set_active(&pdev->dev);
503 pm_runtime_enable(&pdev->dev);
504 pm_runtime_idle(&pdev->dev);
505
506 ret = devm_spi_register_master(&pdev->dev, master);
507 if (ret) {
508 dev_err(&pdev->dev, "cannot register SPI master\n");
509 goto err_pm_disable;
510 }
511
512 return 0;
513
514 err_pm_disable:
515 pm_runtime_disable(&pdev->dev);
516 sun4i_spi_runtime_suspend(&pdev->dev);
517 err_free_master:
518 spi_master_put(master);
519 return ret;
520 }
521
sun4i_spi_remove(struct platform_device * pdev)522 static void sun4i_spi_remove(struct platform_device *pdev)
523 {
524 pm_runtime_force_suspend(&pdev->dev);
525 }
526
527 static const struct of_device_id sun4i_spi_match[] = {
528 { .compatible = "allwinner,sun4i-a10-spi", },
529 {}
530 };
531 MODULE_DEVICE_TABLE(of, sun4i_spi_match);
532
533 static const struct dev_pm_ops sun4i_spi_pm_ops = {
534 .runtime_resume = sun4i_spi_runtime_resume,
535 .runtime_suspend = sun4i_spi_runtime_suspend,
536 };
537
538 static struct platform_driver sun4i_spi_driver = {
539 .probe = sun4i_spi_probe,
540 .remove_new = sun4i_spi_remove,
541 .driver = {
542 .name = "sun4i-spi",
543 .of_match_table = sun4i_spi_match,
544 .pm = &sun4i_spi_pm_ops,
545 },
546 };
547 module_platform_driver(sun4i_spi_driver);
548
549 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
550 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
551 MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
552 MODULE_LICENSE("GPL");
553