1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef LINUX_SSB_CHIPCO_H_ 3 #define LINUX_SSB_CHIPCO_H_ 4 5 /* SonicsSiliconBackplane CHIPCOMMON core hardware definitions 6 * 7 * The chipcommon core provides chip identification, SB control, 8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer, 9 * gpio interface, extbus, and support for serial and parallel flashes. 10 * 11 * Copyright 2005, Broadcom Corporation 12 * Copyright 2006, Michael Buesch <m@bues.ch> 13 */ 14 15 /** ChipCommon core registers. **/ 16 17 #define SSB_CHIPCO_CHIPID 0x0000 18 #define SSB_CHIPCO_IDMASK 0x0000FFFF 19 #define SSB_CHIPCO_REVMASK 0x000F0000 20 #define SSB_CHIPCO_REVSHIFT 16 21 #define SSB_CHIPCO_PACKMASK 0x00F00000 22 #define SSB_CHIPCO_PACKSHIFT 20 23 #define SSB_CHIPCO_NRCORESMASK 0x0F000000 24 #define SSB_CHIPCO_NRCORESSHIFT 24 25 #define SSB_CHIPCO_CAP 0x0004 /* Capabilities */ 26 #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */ 27 #define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */ 28 #define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */ 29 #define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */ 30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */ 31 #define SSB_CHIPCO_CAP_EXTBUS 0x000000C0 /* External buses present */ 32 #define SSB_CHIPCO_CAP_FLASHT 0x00000700 /* Flash Type */ 33 #define SSB_CHIPCO_FLASHT_NONE 0x00000000 /* No flash */ 34 #define SSB_CHIPCO_FLASHT_STSER 0x00000100 /* ST serial flash */ 35 #define SSB_CHIPCO_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ 36 #define SSB_CHIPCO_FLASHT_PARA 0x00000700 /* Parallel flash */ 37 #define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */ 38 #define SSB_PLLTYPE_NONE 0x00000000 39 #define SSB_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */ 40 #define SSB_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */ 41 #define SSB_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */ 42 #define SSB_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */ 43 #define SSB_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */ 44 #define SSB_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */ 45 #define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */ 46 #define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */ 47 #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */ 48 #define SSB_CHIPCO_CAP_OTPS_SHIFT 19 49 #define SSB_CHIPCO_CAP_OTPS_BASE 5 50 #define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */ 51 #define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */ 52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ 53 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ 54 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ 55 #define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */ 56 #define SSB_CHIPCO_CORECTL 0x0008 57 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ 58 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ 59 #define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */ 60 #define SSB_CHIPCO_BIST 0x000C 61 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */ 62 #define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000 63 #define SSB_CHIPCO_OTPS_PROTECT 0x00000007 64 #define SSB_CHIPCO_OTPS_HW_PROTECT 0x00000001 65 #define SSB_CHIPCO_OTPS_SW_PROTECT 0x00000002 66 #define SSB_CHIPCO_OTPS_CID_PROTECT 0x00000004 67 #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */ 68 #define SSB_CHIPCO_OTPC_RECWAIT 0xFF000000 69 #define SSB_CHIPCO_OTPC_PROGWAIT 0x00FFFF00 70 #define SSB_CHIPCO_OTPC_PRW_SHIFT 8 71 #define SSB_CHIPCO_OTPC_MAXFAIL 0x00000038 72 #define SSB_CHIPCO_OTPC_VSEL 0x00000006 73 #define SSB_CHIPCO_OTPC_SELVL 0x00000001 74 #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */ 75 #define SSB_CHIPCO_OTPP_COL 0x000000FF 76 #define SSB_CHIPCO_OTPP_ROW 0x0000FF00 77 #define SSB_CHIPCO_OTPP_ROW_SHIFT 8 78 #define SSB_CHIPCO_OTPP_READERR 0x10000000 79 #define SSB_CHIPCO_OTPP_VALUE 0x20000000 80 #define SSB_CHIPCO_OTPP_READ 0x40000000 81 #define SSB_CHIPCO_OTPP_START 0x80000000 82 #define SSB_CHIPCO_OTPP_BUSY 0x80000000 83 #define SSB_CHIPCO_IRQSTAT 0x0020 84 #define SSB_CHIPCO_IRQMASK 0x0024 85 #define SSB_CHIPCO_IRQ_GPIO 0x00000001 /* gpio intr */ 86 #define SSB_CHIPCO_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */ 87 #define SSB_CHIPCO_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ 88 #define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */ 89 #define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */ 90 #define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */ 91 #define SSB_CHIPCO_JCMD_START 0x80000000 92 #define SSB_CHIPCO_JCMD_BUSY 0x80000000 93 #define SSB_CHIPCO_JCMD_PAUSE 0x40000000 94 #define SSB_CHIPCO_JCMD0_ACC_MASK 0x0000F000 95 #define SSB_CHIPCO_JCMD0_ACC_IRDR 0x00000000 96 #define SSB_CHIPCO_JCMD0_ACC_DR 0x00001000 97 #define SSB_CHIPCO_JCMD0_ACC_IR 0x00002000 98 #define SSB_CHIPCO_JCMD0_ACC_RESET 0x00003000 99 #define SSB_CHIPCO_JCMD0_ACC_IRPDR 0x00004000 100 #define SSB_CHIPCO_JCMD0_ACC_PDR 0x00005000 101 #define SSB_CHIPCO_JCMD0_IRW_MASK 0x00000F00 102 #define SSB_CHIPCO_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */ 103 #define SSB_CHIPCO_JCMD_ACC_IRDR 0x00000000 104 #define SSB_CHIPCO_JCMD_ACC_DR 0x00010000 105 #define SSB_CHIPCO_JCMD_ACC_IR 0x00020000 106 #define SSB_CHIPCO_JCMD_ACC_RESET 0x00030000 107 #define SSB_CHIPCO_JCMD_ACC_IRPDR 0x00040000 108 #define SSB_CHIPCO_JCMD_ACC_PDR 0x00050000 109 #define SSB_CHIPCO_JCMD_IRW_MASK 0x00001F00 110 #define SSB_CHIPCO_JCMD_IRW_SHIFT 8 111 #define SSB_CHIPCO_JCMD_DRW_MASK 0x0000003F 112 #define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */ 113 #define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */ 114 #define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */ 115 #define SSB_CHIPCO_JCTL_FORCE_CLK 4 /* Force clock */ 116 #define SSB_CHIPCO_JCTL_EXT_EN 2 /* Enable external targets */ 117 #define SSB_CHIPCO_JCTL_EN 1 /* Enable Jtag master */ 118 #define SSB_CHIPCO_FLASHCTL 0x0040 119 #define SSB_CHIPCO_FLASHCTL_START 0x80000000 120 #define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START 121 #define SSB_CHIPCO_FLASHADDR 0x0044 122 #define SSB_CHIPCO_FLASHDATA 0x0048 123 #define SSB_CHIPCO_BCAST_ADDR 0x0050 124 #define SSB_CHIPCO_BCAST_DATA 0x0054 125 #define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */ 126 #define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */ 127 #define SSB_CHIPCO_GPIOIN 0x0060 128 #define SSB_CHIPCO_GPIOOUT 0x0064 129 #define SSB_CHIPCO_GPIOOUTEN 0x0068 130 #define SSB_CHIPCO_GPIOCTL 0x006C 131 #define SSB_CHIPCO_GPIOPOL 0x0070 132 #define SSB_CHIPCO_GPIOIRQ 0x0074 133 #define SSB_CHIPCO_WATCHDOG 0x0080 134 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ 135 #define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF 136 #define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0 137 #define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000 138 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16 139 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ 140 #define SSB_CHIPCO_CLOCK_N 0x0090 141 #define SSB_CHIPCO_CLOCK_SB 0x0094 142 #define SSB_CHIPCO_CLOCK_PCI 0x0098 143 #define SSB_CHIPCO_CLOCK_M2 0x009C 144 #define SSB_CHIPCO_CLOCK_MIPS 0x00A0 145 #define SSB_CHIPCO_CLKDIV 0x00A4 /* Rev >= 3 only */ 146 #define SSB_CHIPCO_CLKDIV_SFLASH 0x0F000000 147 #define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT 24 148 #define SSB_CHIPCO_CLKDIV_OTP 0x000F0000 149 #define SSB_CHIPCO_CLKDIV_OTP_SHIFT 16 150 #define SSB_CHIPCO_CLKDIV_JTAG 0x00000F00 151 #define SSB_CHIPCO_CLKDIV_JTAG_SHIFT 8 152 #define SSB_CHIPCO_CLKDIV_UART 0x000000FF 153 #define SSB_CHIPCO_PLLONDELAY 0x00B0 /* Rev >= 4 only */ 154 #define SSB_CHIPCO_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ 155 #define SSB_CHIPCO_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */ 156 #define SSB_CHIPCO_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */ 157 #define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */ 158 #define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */ 159 #define SSB_CHIPCO_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */ 160 #define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ 161 #define SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ 162 #define SSB_CHIPCO_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ 163 #define SSB_CHIPCO_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */ 164 #define SSB_CHIPCO_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */ 165 #define SSB_CHIPCO_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ 166 #define SSB_CHIPCO_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ 167 #define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT 16 168 #define SSB_CHIPCO_SYSCLKCTL 0x00C0 /* Rev >= 3 only */ 169 #define SSB_CHIPCO_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */ 170 #define SSB_CHIPCO_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */ 171 #define SSB_CHIPCO_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */ 172 #define SSB_CHIPCO_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */ 173 #define SSB_CHIPCO_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */ 174 #define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */ 175 #define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT 16 176 #define SSB_CHIPCO_CLKSTSTR 0x00C4 /* Rev >= 3 only */ 177 #define SSB_CHIPCO_PCMCIA_CFG 0x0100 178 #define SSB_CHIPCO_PCMCIA_MEMWAIT 0x0104 179 #define SSB_CHIPCO_PCMCIA_ATTRWAIT 0x0108 180 #define SSB_CHIPCO_PCMCIA_IOWAIT 0x010C 181 #define SSB_CHIPCO_IDE_CFG 0x0110 182 #define SSB_CHIPCO_IDE_MEMWAIT 0x0114 183 #define SSB_CHIPCO_IDE_ATTRWAIT 0x0118 184 #define SSB_CHIPCO_IDE_IOWAIT 0x011C 185 #define SSB_CHIPCO_PROG_CFG 0x0120 186 #define SSB_CHIPCO_PROG_WAITCNT 0x0124 187 #define SSB_CHIPCO_FLASH_CFG 0x0128 188 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C 189 #define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */ 190 #define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */ 191 #define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */ 192 #define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */ 193 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */ 194 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ 195 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ 196 #define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */ 197 #define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */ 198 #define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */ 199 #define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */ 200 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ 201 #define SSB_CHIPCO_UART0_DATA 0x0300 202 #define SSB_CHIPCO_UART0_IMR 0x0304 203 #define SSB_CHIPCO_UART0_FCR 0x0308 204 #define SSB_CHIPCO_UART0_LCR 0x030C 205 #define SSB_CHIPCO_UART0_MCR 0x0310 206 #define SSB_CHIPCO_UART0_LSR 0x0314 207 #define SSB_CHIPCO_UART0_MSR 0x0318 208 #define SSB_CHIPCO_UART0_SCRATCH 0x031C 209 #define SSB_CHIPCO_UART1_DATA 0x0400 210 #define SSB_CHIPCO_UART1_IMR 0x0404 211 #define SSB_CHIPCO_UART1_FCR 0x0408 212 #define SSB_CHIPCO_UART1_LCR 0x040C 213 #define SSB_CHIPCO_UART1_MCR 0x0410 214 #define SSB_CHIPCO_UART1_LSR 0x0414 215 #define SSB_CHIPCO_UART1_MSR 0x0418 216 #define SSB_CHIPCO_UART1_SCRATCH 0x041C 217 /* PMU registers (rev >= 20) */ 218 #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */ 219 #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ 220 #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16 221 #define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400 222 #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ 223 #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ 224 #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ 225 #define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */ 226 #define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2 227 #define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */ 228 #define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */ 229 #define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */ 230 #define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */ 231 #define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */ 232 #define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */ 233 #define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */ 234 #define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */ 235 #define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */ 236 #define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */ 237 #define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */ 238 #define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */ 239 #define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */ 240 #define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */ 241 #define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */ 242 #define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */ 243 #define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */ 244 #define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */ 245 #define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */ 246 #define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */ 247 #define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */ 248 #define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */ 249 #define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */ 250 #define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */ 251 #define SSB_CHIPCO_CHIPCTL_ADDR 0x0650 252 #define SSB_CHIPCO_CHIPCTL_DATA 0x0654 253 #define SSB_CHIPCO_REGCTL_ADDR 0x0658 254 #define SSB_CHIPCO_REGCTL_DATA 0x065C 255 #define SSB_CHIPCO_PLLCTL_ADDR 0x0660 256 #define SSB_CHIPCO_PLLCTL_DATA 0x0664 257 258 259 260 /** PMU PLL registers */ 261 262 /* PMU rev 0 PLL registers */ 263 #define SSB_PMU0_PLLCTL0 0 264 #define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001 265 #define SSB_PMU0_PLLCTL0_PDIV_FREQ 25000 /* kHz */ 266 #define SSB_PMU0_PLLCTL1 1 267 #define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */ 268 #define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT 28 269 #define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */ 270 #define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT 8 271 #define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */ 272 #define SSB_PMU0_PLLCTL2 2 273 #define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */ 274 #define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0 275 276 /* PMU rev 1 PLL registers */ 277 #define SSB_PMU1_PLLCTL0 0 278 #define SSB_PMU1_PLLCTL0_P1DIV 0x00F00000 /* P1 div */ 279 #define SSB_PMU1_PLLCTL0_P1DIV_SHIFT 20 280 #define SSB_PMU1_PLLCTL0_P2DIV 0x0F000000 /* P2 div */ 281 #define SSB_PMU1_PLLCTL0_P2DIV_SHIFT 24 282 #define SSB_PMU1_PLLCTL1 1 283 #define SSB_PMU1_PLLCTL1_M1DIV 0x000000FF /* M1 div */ 284 #define SSB_PMU1_PLLCTL1_M1DIV_SHIFT 0 285 #define SSB_PMU1_PLLCTL1_M2DIV 0x0000FF00 /* M2 div */ 286 #define SSB_PMU1_PLLCTL1_M2DIV_SHIFT 8 287 #define SSB_PMU1_PLLCTL1_M3DIV 0x00FF0000 /* M3 div */ 288 #define SSB_PMU1_PLLCTL1_M3DIV_SHIFT 16 289 #define SSB_PMU1_PLLCTL1_M4DIV 0xFF000000 /* M4 div */ 290 #define SSB_PMU1_PLLCTL1_M4DIV_SHIFT 24 291 #define SSB_PMU1_PLLCTL2 2 292 #define SSB_PMU1_PLLCTL2_M5DIV 0x000000FF /* M5 div */ 293 #define SSB_PMU1_PLLCTL2_M5DIV_SHIFT 0 294 #define SSB_PMU1_PLLCTL2_M6DIV 0x0000FF00 /* M6 div */ 295 #define SSB_PMU1_PLLCTL2_M6DIV_SHIFT 8 296 #define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */ 297 #define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT 17 298 #define SSB_PMU1_PLLCTL2_NDIVINT 0x1FF00000 /* NDIV int */ 299 #define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT 20 300 #define SSB_PMU1_PLLCTL3 3 301 #define SSB_PMU1_PLLCTL3_NDIVFRAC 0x00FFFFFF /* NDIV frac */ 302 #define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT 0 303 #define SSB_PMU1_PLLCTL4 4 304 #define SSB_PMU1_PLLCTL5 5 305 #define SSB_PMU1_PLLCTL5_CLKDRV 0xFFFFFF00 /* clk drv */ 306 #define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT 8 307 308 /* BCM4312 PLL resource numbers. */ 309 #define SSB_PMURES_4312_SWITCHER_BURST 0 310 #define SSB_PMURES_4312_SWITCHER_PWM 1 311 #define SSB_PMURES_4312_PA_REF_LDO 2 312 #define SSB_PMURES_4312_CORE_LDO_BURST 3 313 #define SSB_PMURES_4312_CORE_LDO_PWM 4 314 #define SSB_PMURES_4312_RADIO_LDO 5 315 #define SSB_PMURES_4312_ILP_REQUEST 6 316 #define SSB_PMURES_4312_BG_FILTBYP 7 317 #define SSB_PMURES_4312_TX_FILTBYP 8 318 #define SSB_PMURES_4312_RX_FILTBYP 9 319 #define SSB_PMURES_4312_XTAL_PU 10 320 #define SSB_PMURES_4312_ALP_AVAIL 11 321 #define SSB_PMURES_4312_BB_PLL_FILTBYP 12 322 #define SSB_PMURES_4312_RF_PLL_FILTBYP 13 323 #define SSB_PMURES_4312_HT_AVAIL 14 324 325 /* BCM4325 PLL resource numbers. */ 326 #define SSB_PMURES_4325_BUCK_BOOST_BURST 0 327 #define SSB_PMURES_4325_CBUCK_BURST 1 328 #define SSB_PMURES_4325_CBUCK_PWM 2 329 #define SSB_PMURES_4325_CLDO_CBUCK_BURST 3 330 #define SSB_PMURES_4325_CLDO_CBUCK_PWM 4 331 #define SSB_PMURES_4325_BUCK_BOOST_PWM 5 332 #define SSB_PMURES_4325_ILP_REQUEST 6 333 #define SSB_PMURES_4325_ABUCK_BURST 7 334 #define SSB_PMURES_4325_ABUCK_PWM 8 335 #define SSB_PMURES_4325_LNLDO1_PU 9 336 #define SSB_PMURES_4325_LNLDO2_PU 10 337 #define SSB_PMURES_4325_LNLDO3_PU 11 338 #define SSB_PMURES_4325_LNLDO4_PU 12 339 #define SSB_PMURES_4325_XTAL_PU 13 340 #define SSB_PMURES_4325_ALP_AVAIL 14 341 #define SSB_PMURES_4325_RX_PWRSW_PU 15 342 #define SSB_PMURES_4325_TX_PWRSW_PU 16 343 #define SSB_PMURES_4325_RFPLL_PWRSW_PU 17 344 #define SSB_PMURES_4325_LOGEN_PWRSW_PU 18 345 #define SSB_PMURES_4325_AFE_PWRSW_PU 19 346 #define SSB_PMURES_4325_BBPLL_PWRSW_PU 20 347 #define SSB_PMURES_4325_HT_AVAIL 21 348 349 /* BCM4328 PLL resource numbers. */ 350 #define SSB_PMURES_4328_EXT_SWITCHER_PWM 0 351 #define SSB_PMURES_4328_BB_SWITCHER_PWM 1 352 #define SSB_PMURES_4328_BB_SWITCHER_BURST 2 353 #define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST 3 354 #define SSB_PMURES_4328_ILP_REQUEST 4 355 #define SSB_PMURES_4328_RADIO_SWITCHER_PWM 5 356 #define SSB_PMURES_4328_RADIO_SWITCHER_BURST 6 357 #define SSB_PMURES_4328_ROM_SWITCH 7 358 #define SSB_PMURES_4328_PA_REF_LDO 8 359 #define SSB_PMURES_4328_RADIO_LDO 9 360 #define SSB_PMURES_4328_AFE_LDO 10 361 #define SSB_PMURES_4328_PLL_LDO 11 362 #define SSB_PMURES_4328_BG_FILTBYP 12 363 #define SSB_PMURES_4328_TX_FILTBYP 13 364 #define SSB_PMURES_4328_RX_FILTBYP 14 365 #define SSB_PMURES_4328_XTAL_PU 15 366 #define SSB_PMURES_4328_XTAL_EN 16 367 #define SSB_PMURES_4328_BB_PLL_FILTBYP 17 368 #define SSB_PMURES_4328_RF_PLL_FILTBYP 18 369 #define SSB_PMURES_4328_BB_PLL_PU 19 370 371 /* BCM5354 PLL resource numbers. */ 372 #define SSB_PMURES_5354_EXT_SWITCHER_PWM 0 373 #define SSB_PMURES_5354_BB_SWITCHER_PWM 1 374 #define SSB_PMURES_5354_BB_SWITCHER_BURST 2 375 #define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST 3 376 #define SSB_PMURES_5354_ILP_REQUEST 4 377 #define SSB_PMURES_5354_RADIO_SWITCHER_PWM 5 378 #define SSB_PMURES_5354_RADIO_SWITCHER_BURST 6 379 #define SSB_PMURES_5354_ROM_SWITCH 7 380 #define SSB_PMURES_5354_PA_REF_LDO 8 381 #define SSB_PMURES_5354_RADIO_LDO 9 382 #define SSB_PMURES_5354_AFE_LDO 10 383 #define SSB_PMURES_5354_PLL_LDO 11 384 #define SSB_PMURES_5354_BG_FILTBYP 12 385 #define SSB_PMURES_5354_TX_FILTBYP 13 386 #define SSB_PMURES_5354_RX_FILTBYP 14 387 #define SSB_PMURES_5354_XTAL_PU 15 388 #define SSB_PMURES_5354_XTAL_EN 16 389 #define SSB_PMURES_5354_BB_PLL_FILTBYP 17 390 #define SSB_PMURES_5354_RF_PLL_FILTBYP 18 391 #define SSB_PMURES_5354_BB_PLL_PU 19 392 393 394 395 /** Chip specific Chip-Status register contents. */ 396 #define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */ 397 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003 398 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 399 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 400 #define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */ 401 #define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ 402 #define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE 0x00000004 403 #define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT 2 404 #define SSB_CHIPCO_CHST_4325_RCAL_VALID 0x00000008 405 #define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT 3 406 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE 0x000001F0 407 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4 408 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */ 409 410 /** Macros to determine SPROM presence based on Chip-Status register. */ 411 #define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \ 412 ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ 413 SSB_CHIPCO_CHST_4325_OTP_SEL) 414 #define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \ 415 (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS) 416 #define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \ 417 (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ 418 SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \ 419 ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ 420 SSB_CHIPCO_CHST_4325_OTP_SEL)) 421 422 423 424 /** Clockcontrol masks and values **/ 425 426 /* SSB_CHIPCO_CLOCK_N */ 427 #define SSB_CHIPCO_CLK_N1 0x0000003F /* n1 control */ 428 #define SSB_CHIPCO_CLK_N2 0x00003F00 /* n2 control */ 429 #define SSB_CHIPCO_CLK_N2_SHIFT 8 430 #define SSB_CHIPCO_CLK_PLLC 0x000F0000 /* pll control */ 431 #define SSB_CHIPCO_CLK_PLLC_SHIFT 16 432 433 /* SSB_CHIPCO_CLOCK_SB/PCI/UART */ 434 #define SSB_CHIPCO_CLK_M1 0x0000003F /* m1 control */ 435 #define SSB_CHIPCO_CLK_M2 0x00003F00 /* m2 control */ 436 #define SSB_CHIPCO_CLK_M2_SHIFT 8 437 #define SSB_CHIPCO_CLK_M3 0x003F0000 /* m3 control */ 438 #define SSB_CHIPCO_CLK_M3_SHIFT 16 439 #define SSB_CHIPCO_CLK_MC 0x1F000000 /* mux control */ 440 #define SSB_CHIPCO_CLK_MC_SHIFT 24 441 442 /* N3M Clock control magic field values */ 443 #define SSB_CHIPCO_CLK_F6_2 0x02 /* A factor of 2 in */ 444 #define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */ 445 #define SSB_CHIPCO_CLK_F6_4 0x05 /* N1, M1 or M3 */ 446 #define SSB_CHIPCO_CLK_F6_5 0x09 447 #define SSB_CHIPCO_CLK_F6_6 0x11 448 #define SSB_CHIPCO_CLK_F6_7 0x21 449 450 #define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */ 451 452 #define SSB_CHIPCO_CLK_MC_BYPASS 0x08 453 #define SSB_CHIPCO_CLK_MC_M1 0x04 454 #define SSB_CHIPCO_CLK_MC_M1M2 0x02 455 #define SSB_CHIPCO_CLK_MC_M1M2M3 0x01 456 #define SSB_CHIPCO_CLK_MC_M1M3 0x11 457 458 /* Type 2 Clock control magic field values */ 459 #define SSB_CHIPCO_CLK_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ 460 #define SSB_CHIPCO_CLK_T2M2_BIAS 3 /* m2 bias */ 461 462 #define SSB_CHIPCO_CLK_T2MC_M1BYP 1 463 #define SSB_CHIPCO_CLK_T2MC_M2BYP 2 464 #define SSB_CHIPCO_CLK_T2MC_M3BYP 4 465 466 /* Type 6 Clock control magic field values */ 467 #define SSB_CHIPCO_CLK_T6_MMASK 1 /* bits of interest in m */ 468 #define SSB_CHIPCO_CLK_T6_M0 120000000 /* sb clock for m = 0 */ 469 #define SSB_CHIPCO_CLK_T6_M1 100000000 /* sb clock for m = 1 */ 470 #define SSB_CHIPCO_CLK_SB2MIPS_T6(sb) (2 * (sb)) 471 472 /* Common clock base */ 473 #define SSB_CHIPCO_CLK_BASE1 24000000 /* Half the clock freq */ 474 #define SSB_CHIPCO_CLK_BASE2 12500000 /* Alternate crystal on some PLL's */ 475 476 /* Clock control values for 200Mhz in 5350 */ 477 #define SSB_CHIPCO_CLK_5350_N 0x0311 478 #define SSB_CHIPCO_CLK_5350_M 0x04020009 479 480 481 /** Bits in the config registers **/ 482 483 #define SSB_CHIPCO_CFG_EN 0x0001 /* Enable */ 484 #define SSB_CHIPCO_CFG_EXTM 0x000E /* Extif Mode */ 485 #define SSB_CHIPCO_CFG_EXTM_ASYNC 0x0002 /* Async/Parallel flash */ 486 #define SSB_CHIPCO_CFG_EXTM_SYNC 0x0004 /* Synchronous */ 487 #define SSB_CHIPCO_CFG_EXTM_PCMCIA 0x0008 /* PCMCIA */ 488 #define SSB_CHIPCO_CFG_EXTM_IDE 0x000A /* IDE */ 489 #define SSB_CHIPCO_CFG_DS16 0x0010 /* Data size, 0=8bit, 1=16bit */ 490 #define SSB_CHIPCO_CFG_CLKDIV 0x0060 /* Sync: Clock divisor */ 491 #define SSB_CHIPCO_CFG_CLKEN 0x0080 /* Sync: Clock enable */ 492 #define SSB_CHIPCO_CFG_BSTRO 0x0100 /* Sync: Size/Bytestrobe */ 493 494 495 /** Flash-specific control/status values */ 496 497 /* flashcontrol opcodes for ST flashes */ 498 #define SSB_CHIPCO_FLASHCTL_ST_WREN 0x0006 /* Write Enable */ 499 #define SSB_CHIPCO_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */ 500 #define SSB_CHIPCO_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */ 501 #define SSB_CHIPCO_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */ 502 #define SSB_CHIPCO_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */ 503 #define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */ 504 #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */ 505 #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */ 506 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */ 507 #define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */ 508 #define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */ 509 #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */ 510 511 /* Status register bits for ST flashes */ 512 #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */ 513 #define SSB_CHIPCO_FLASHSTA_ST_WEL 0x02 /* Write Enable Latch */ 514 #define SSB_CHIPCO_FLASHSTA_ST_BP 0x1C /* Block Protect */ 515 #define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT 2 516 #define SSB_CHIPCO_FLASHSTA_ST_SRWD 0x80 /* Status Register Write Disable */ 517 518 /* flashcontrol opcodes for Atmel flashes */ 519 #define SSB_CHIPCO_FLASHCTL_AT_READ 0x07E8 520 #define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ 0x07D2 521 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ /* FIXME */ 522 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ /* FIXME */ 523 #define SSB_CHIPCO_FLASHCTL_AT_STATUS 0x01D7 524 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE 0x0384 525 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE 0x0387 526 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM 0x0283 /* Erase program */ 527 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM 0x0286 /* Erase program */ 528 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM 0x0288 529 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM 0x0289 530 #define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE 0x0281 531 #define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE 0x0250 532 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM 0x0382 /* Write erase program */ 533 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM 0x0385 /* Write erase program */ 534 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD 0x0253 535 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD 0x0255 536 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE 0x0260 537 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE 0x0261 538 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM 0x0258 539 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM 0x0259 540 541 /* Status register bits for Atmel flashes */ 542 #define SSB_CHIPCO_FLASHSTA_AT_READY 0x80 543 #define SSB_CHIPCO_FLASHSTA_AT_MISMATCH 0x40 544 #define SSB_CHIPCO_FLASHSTA_AT_ID 0x38 545 #define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT 3 546 547 548 /** OTP **/ 549 550 /* OTP regions */ 551 #define SSB_CHIPCO_OTP_HW_REGION SSB_CHIPCO_OTPS_HW_PROTECT 552 #define SSB_CHIPCO_OTP_SW_REGION SSB_CHIPCO_OTPS_SW_PROTECT 553 #define SSB_CHIPCO_OTP_CID_REGION SSB_CHIPCO_OTPS_CID_PROTECT 554 555 /* OTP regions (Byte offsets from otp size) */ 556 #define SSB_CHIPCO_OTP_SWLIM_OFF (-8) 557 #define SSB_CHIPCO_OTP_CIDBASE_OFF 0 558 #define SSB_CHIPCO_OTP_CIDLIM_OFF 8 559 560 /* Predefined OTP words (Word offset from otp size) */ 561 #define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4) 562 #define SSB_CHIPCO_OTP_HWSIGN_OFF (-3) 563 #define SSB_CHIPCO_OTP_SWSIGN_OFF (-2) 564 #define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1) 565 566 #define SSB_CHIPCO_OTP_CID_OFF 0 567 #define SSB_CHIPCO_OTP_PKG_OFF 1 568 #define SSB_CHIPCO_OTP_FID_OFF 2 569 #define SSB_CHIPCO_OTP_RSV_OFF 3 570 #define SSB_CHIPCO_OTP_LIM_OFF 4 571 572 #define SSB_CHIPCO_OTP_SIGNATURE 0x578A 573 #define SSB_CHIPCO_OTP_MAGIC 0x4E56 574 575 576 struct ssb_device; 577 struct ssb_serial_port; 578 579 /* Data for the PMU, if available. 580 * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU) 581 */ 582 struct ssb_chipcommon_pmu { 583 u8 rev; /* PMU revision */ 584 u32 crystalfreq; /* The active crystal frequency (in kHz) */ 585 }; 586 587 struct ssb_chipcommon { 588 struct ssb_device *dev; 589 u32 capabilities; 590 u32 status; 591 /* Fast Powerup Delay constant */ 592 u16 fast_pwrup_delay; 593 spinlock_t gpio_lock; 594 struct ssb_chipcommon_pmu pmu; 595 u32 ticks_per_ms; 596 u32 max_timer_ms; 597 }; 598 ssb_chipco_available(struct ssb_chipcommon * cc)599 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) 600 { 601 return (cc->dev != NULL); 602 } 603 604 /* Register access */ 605 #define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset) 606 #define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val) 607 608 #define chipco_mask32(cc, offset, mask) \ 609 chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask)) 610 #define chipco_set32(cc, offset, set) \ 611 chipco_write32(cc, offset, chipco_read32(cc, offset) | (set)) 612 #define chipco_maskset32(cc, offset, mask, set) \ 613 chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set)) 614 615 extern void ssb_chipcommon_init(struct ssb_chipcommon *cc); 616 617 extern void ssb_chipco_suspend(struct ssb_chipcommon *cc); 618 extern void ssb_chipco_resume(struct ssb_chipcommon *cc); 619 620 extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, 621 u32 *plltype, u32 *n, u32 *m); 622 extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, 623 u32 *plltype, u32 *n, u32 *m); 624 extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc, 625 unsigned long ns_per_cycle); 626 627 enum ssb_clkmode { 628 SSB_CLKMODE_SLOW, 629 SSB_CLKMODE_FAST, 630 SSB_CLKMODE_DYNAMIC, 631 }; 632 633 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, 634 enum ssb_clkmode mode); 635 636 extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks); 637 638 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); 639 640 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask); 641 642 /* Chipcommon GPIO pin access. */ 643 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask); 644 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value); 645 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value); 646 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); 647 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); 648 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); 649 u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value); 650 u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value); 651 652 #ifdef CONFIG_SSB_SERIAL 653 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, 654 struct ssb_serial_port *ports); 655 #endif /* CONFIG_SSB_SERIAL */ 656 657 /* PMU support */ 658 extern void ssb_pmu_init(struct ssb_chipcommon *cc); 659 660 enum ssb_pmu_ldo_volt_id { 661 LDO_PAREF = 0, 662 LDO_VOLT1, 663 LDO_VOLT2, 664 LDO_VOLT3, 665 }; 666 667 void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, 668 enum ssb_pmu_ldo_volt_id id, u32 voltage); 669 void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on); 670 void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid); 671 672 #endif /* LINUX_SSB_CHIPCO_H_ */ 673