1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7 #include <linux/atomic.h>
8 #include <linux/auxiliary_bus.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/i2c.h>
16 #include <linux/iopoll.h>
17 #include <linux/module.h>
18 #include <linux/of_graph.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/pwm.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <asm/unaligned.h>
25
26 #include <drm/display/drm_dp_aux_bus.h>
27 #include <drm/display/drm_dp_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_bridge.h>
31 #include <drm/drm_bridge_connector.h>
32 #include <drm/drm_edid.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_of.h>
35 #include <drm/drm_panel.h>
36 #include <drm/drm_print.h>
37 #include <drm/drm_probe_helper.h>
38
39 #define SN_DEVICE_REV_REG 0x08
40 #define SN_DPPLL_SRC_REG 0x0A
41 #define DPPLL_CLK_SRC_DSICLK BIT(0)
42 #define REFCLK_FREQ_MASK GENMASK(3, 1)
43 #define REFCLK_FREQ(x) ((x) << 1)
44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
45 #define SN_PLL_ENABLE_REG 0x0D
46 #define SN_DSI_LANES_REG 0x10
47 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
48 #define CHA_DSI_LANES(x) ((x) << 3)
49 #define SN_DSIA_CLK_FREQ_REG 0x12
50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
54 #define CHA_HSYNC_POLARITY BIT(7)
55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
57 #define CHA_VSYNC_POLARITY BIT(7)
58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
62 #define SN_LN_ASSIGN_REG 0x59
63 #define LN_ASSIGN_WIDTH 2
64 #define SN_ENH_FRAME_REG 0x5A
65 #define VSTREAM_ENABLE BIT(3)
66 #define LN_POLRS_OFFSET 4
67 #define LN_POLRS_MASK 0xf0
68 #define SN_DATA_FORMAT_REG 0x5B
69 #define BPP_18_RGB BIT(0)
70 #define SN_HPD_DISABLE_REG 0x5C
71 #define HPD_DISABLE BIT(0)
72 #define HPD_DEBOUNCED_STATE BIT(4)
73 #define SN_GPIO_IO_REG 0x5E
74 #define SN_GPIO_INPUT_SHIFT 4
75 #define SN_GPIO_OUTPUT_SHIFT 0
76 #define SN_GPIO_CTRL_REG 0x5F
77 #define SN_GPIO_MUX_INPUT 0
78 #define SN_GPIO_MUX_OUTPUT 1
79 #define SN_GPIO_MUX_SPECIAL 2
80 #define SN_GPIO_MUX_MASK 0x3
81 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
82 #define SN_AUX_ADDR_19_16_REG 0x74
83 #define SN_AUX_ADDR_15_8_REG 0x75
84 #define SN_AUX_ADDR_7_0_REG 0x76
85 #define SN_AUX_ADDR_MASK GENMASK(19, 0)
86 #define SN_AUX_LENGTH_REG 0x77
87 #define SN_AUX_CMD_REG 0x78
88 #define AUX_CMD_SEND BIT(0)
89 #define AUX_CMD_REQ(x) ((x) << 4)
90 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
91 #define SN_SSC_CONFIG_REG 0x93
92 #define DP_NUM_LANES_MASK GENMASK(5, 4)
93 #define DP_NUM_LANES(x) ((x) << 4)
94 #define SN_DATARATE_CONFIG_REG 0x94
95 #define DP_DATARATE_MASK GENMASK(7, 5)
96 #define DP_DATARATE(x) ((x) << 5)
97 #define SN_TRAINING_SETTING_REG 0x95
98 #define SCRAMBLE_DISABLE BIT(4)
99 #define SN_ML_TX_MODE_REG 0x96
100 #define ML_TX_MAIN_LINK_OFF 0
101 #define ML_TX_NORMAL_MODE BIT(0)
102 #define SN_PWM_PRE_DIV_REG 0xA0
103 #define SN_BACKLIGHT_SCALE_REG 0xA1
104 #define BACKLIGHT_SCALE_MAX 0xFFFF
105 #define SN_BACKLIGHT_REG 0xA3
106 #define SN_PWM_EN_INV_REG 0xA5
107 #define SN_PWM_INV_MASK BIT(0)
108 #define SN_PWM_EN_MASK BIT(1)
109 #define SN_AUX_CMD_STATUS_REG 0xF4
110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
113
114 #define MIN_DSI_CLK_FREQ_MHZ 40
115
116 /* fudge factor required to account for 8b/10b encoding */
117 #define DP_CLK_FUDGE_NUM 10
118 #define DP_CLK_FUDGE_DEN 8
119
120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
121 #define SN_AUX_MAX_PAYLOAD_BYTES 16
122
123 #define SN_REGULATOR_SUPPLY_NUM 4
124
125 #define SN_MAX_DP_LANES 4
126 #define SN_NUM_GPIOS 4
127 #define SN_GPIO_PHYSICAL_OFFSET 1
128
129 #define SN_LINK_TRAINING_TRIES 10
130
131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */
132
133 /**
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
139 *
140 * @dev: Pointer to the top level (i2c) device.
141 * @regmap: Regmap for accessing i2c.
142 * @aux: Our aux channel.
143 * @bridge: Our bridge.
144 * @connector: Our connector.
145 * @host_node: Remote DSI node.
146 * @dsi: Our MIPI DSI source.
147 * @refclk: Our reference clock.
148 * @next_bridge: The bridge on the eDP side.
149 * @enable_gpio: The GPIO we toggle to enable the bridge.
150 * @supplies: Data for bulk enabling/disabling our regulators.
151 * @dp_lanes: Count of dp_lanes we're using.
152 * @ln_assign: Value to program to the LN_ASSIGN register.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
154 * @comms_enabled: If true then communication over the aux channel is enabled.
155 * @comms_mutex: Protects modification of comms_enabled.
156 *
157 * @gchip: If we expose our GPIOs, this is used.
158 * @gchip_output: A cache of whether we've set GPIOs to output. This
159 * serves double-duty of keeping track of the direction and
160 * also keeping track of whether we've incremented the
161 * pm_runtime reference count for this pin, which we do
162 * whenever a pin is configured as an output. This is a
163 * bitmap so we can do atomic ops on it without an extra
164 * lock so concurrent users of our 4 GPIOs don't stomp on
165 * each other's read-modify-write.
166 *
167 * @pchip: pwm_chip if the PWM is exposed.
168 * @pwm_enabled: Used to track if the PWM signal is currently enabled.
169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
171 */
172 struct ti_sn65dsi86 {
173 struct auxiliary_device *bridge_aux;
174 struct auxiliary_device *gpio_aux;
175 struct auxiliary_device *aux_aux;
176 struct auxiliary_device *pwm_aux;
177
178 struct device *dev;
179 struct regmap *regmap;
180 struct drm_dp_aux aux;
181 struct drm_bridge bridge;
182 struct drm_connector *connector;
183 struct device_node *host_node;
184 struct mipi_dsi_device *dsi;
185 struct clk *refclk;
186 struct drm_bridge *next_bridge;
187 struct gpio_desc *enable_gpio;
188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
189 int dp_lanes;
190 u8 ln_assign;
191 u8 ln_polrs;
192 bool comms_enabled;
193 struct mutex comms_mutex;
194
195 #if defined(CONFIG_OF_GPIO)
196 struct gpio_chip gchip;
197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
198 #endif
199 #if defined(CONFIG_PWM)
200 struct pwm_chip pchip;
201 bool pwm_enabled;
202 atomic_t pwm_pin_busy;
203 #endif
204 unsigned int pwm_refclk_freq;
205 };
206
207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
208 { .range_min = 0, .range_max = 0xFF },
209 };
210
211 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
212 .yes_ranges = ti_sn65dsi86_volatile_ranges,
213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
214 };
215
216 static const struct regmap_config ti_sn65dsi86_regmap_config = {
217 .reg_bits = 8,
218 .val_bits = 8,
219 .volatile_table = &ti_sn_bridge_volatile_table,
220 .cache_type = REGCACHE_NONE,
221 .max_register = 0xFF,
222 };
223
ti_sn65dsi86_read_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 * val)224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
225 unsigned int reg, u16 *val)
226 {
227 u8 buf[2];
228 int ret;
229
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
231 if (ret)
232 return ret;
233
234 *val = buf[0] | (buf[1] << 8);
235
236 return 0;
237 }
238
ti_sn65dsi86_write_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 val)239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
240 unsigned int reg, u16 val)
241 {
242 u8 buf[2] = { val & 0xff, val >> 8 };
243
244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
245 }
246
ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 * pdata)247 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
248 {
249 u32 bit_rate_khz, clk_freq_khz;
250 struct drm_display_mode *mode =
251 &pdata->bridge.encoder->crtc->state->adjusted_mode;
252
253 bit_rate_khz = mode->clock *
254 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
256
257 return clk_freq_khz;
258 }
259
260 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
261 static const u32 ti_sn_bridge_refclk_lut[] = {
262 12000000,
263 19200000,
264 26000000,
265 27000000,
266 38400000,
267 };
268
269 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
270 static const u32 ti_sn_bridge_dsiclk_lut[] = {
271 468000000,
272 384000000,
273 416000000,
274 486000000,
275 460800000,
276 };
277
ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 * pdata)278 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
279 {
280 int i;
281 u32 refclk_rate;
282 const u32 *refclk_lut;
283 size_t refclk_lut_size;
284
285 if (pdata->refclk) {
286 refclk_rate = clk_get_rate(pdata->refclk);
287 refclk_lut = ti_sn_bridge_refclk_lut;
288 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
289 clk_prepare_enable(pdata->refclk);
290 } else {
291 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
292 refclk_lut = ti_sn_bridge_dsiclk_lut;
293 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
294 }
295
296 /* for i equals to refclk_lut_size means default frequency */
297 for (i = 0; i < refclk_lut_size; i++)
298 if (refclk_lut[i] == refclk_rate)
299 break;
300
301 /* avoid buffer overflow and "1" is the default rate in the datasheet. */
302 if (i >= refclk_lut_size)
303 i = 1;
304
305 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
306 REFCLK_FREQ(i));
307
308 /*
309 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
310 * regardless of its actual sourcing.
311 */
312 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
313 }
314
ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 * pdata)315 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
316 {
317 mutex_lock(&pdata->comms_mutex);
318
319 /* configure bridge ref_clk */
320 ti_sn_bridge_set_refclk_freq(pdata);
321
322 /*
323 * HPD on this bridge chip is a bit useless. This is an eDP bridge
324 * so the HPD is an internal signal that's only there to signal that
325 * the panel is done powering up. ...but the bridge chip debounces
326 * this signal by between 100 ms and 400 ms (depending on process,
327 * voltage, and temperate--I measured it at about 200 ms). One
328 * particular panel asserted HPD 84 ms after it was powered on meaning
329 * that we saw HPD 284 ms after power on. ...but the same panel said
330 * that instead of looking at HPD you could just hardcode a delay of
331 * 200 ms. We'll assume that the panel driver will have the hardcoded
332 * delay in its prepare and always disable HPD.
333 *
334 * For DisplayPort bridge type, we need HPD. So we use the bridge type
335 * to conditionally disable HPD.
336 * NOTE: The bridge type is set in ti_sn_bridge_probe() but enable_comms()
337 * can be called before. So for DisplayPort, HPD will be enabled once
338 * bridge type is set. We are using bridge type instead of "no-hpd"
339 * property because it is not used properly in devicetree description
340 * and hence is unreliable.
341 */
342
343 if (pdata->bridge.type != DRM_MODE_CONNECTOR_DisplayPort)
344 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
345 HPD_DISABLE);
346
347 pdata->comms_enabled = true;
348
349 mutex_unlock(&pdata->comms_mutex);
350 }
351
ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 * pdata)352 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
353 {
354 mutex_lock(&pdata->comms_mutex);
355
356 pdata->comms_enabled = false;
357 clk_disable_unprepare(pdata->refclk);
358
359 mutex_unlock(&pdata->comms_mutex);
360 }
361
ti_sn65dsi86_resume(struct device * dev)362 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
363 {
364 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
365 int ret;
366
367 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
368 if (ret) {
369 DRM_ERROR("failed to enable supplies %d\n", ret);
370 return ret;
371 }
372
373 /* td2: min 100 us after regulators before enabling the GPIO */
374 usleep_range(100, 110);
375
376 gpiod_set_value_cansleep(pdata->enable_gpio, 1);
377
378 /*
379 * If we have a reference clock we can enable communication w/ the
380 * panel (including the aux channel) w/out any need for an input clock
381 * so we can do it in resume which lets us read the EDID before
382 * pre_enable(). Without a reference clock we need the MIPI reference
383 * clock so reading early doesn't work.
384 */
385 if (pdata->refclk)
386 ti_sn65dsi86_enable_comms(pdata);
387
388 return ret;
389 }
390
ti_sn65dsi86_suspend(struct device * dev)391 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
392 {
393 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
394 int ret;
395
396 if (pdata->refclk)
397 ti_sn65dsi86_disable_comms(pdata);
398
399 gpiod_set_value_cansleep(pdata->enable_gpio, 0);
400
401 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
402 if (ret)
403 DRM_ERROR("failed to disable supplies %d\n", ret);
404
405 return ret;
406 }
407
408 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
409 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
410 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
411 pm_runtime_force_resume)
412 };
413
status_show(struct seq_file * s,void * data)414 static int status_show(struct seq_file *s, void *data)
415 {
416 struct ti_sn65dsi86 *pdata = s->private;
417 unsigned int reg, val;
418
419 seq_puts(s, "STATUS REGISTERS:\n");
420
421 pm_runtime_get_sync(pdata->dev);
422
423 /* IRQ Status Registers, see Table 31 in datasheet */
424 for (reg = 0xf0; reg <= 0xf8; reg++) {
425 regmap_read(pdata->regmap, reg, &val);
426 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
427 }
428
429 pm_runtime_put_autosuspend(pdata->dev);
430
431 return 0;
432 }
433 DEFINE_SHOW_ATTRIBUTE(status);
434
435 /* -----------------------------------------------------------------------------
436 * Auxiliary Devices (*not* AUX)
437 */
438
ti_sn65dsi86_uninit_aux(void * data)439 static void ti_sn65dsi86_uninit_aux(void *data)
440 {
441 auxiliary_device_uninit(data);
442 }
443
ti_sn65dsi86_delete_aux(void * data)444 static void ti_sn65dsi86_delete_aux(void *data)
445 {
446 auxiliary_device_delete(data);
447 }
448
ti_sn65dsi86_aux_device_release(struct device * dev)449 static void ti_sn65dsi86_aux_device_release(struct device *dev)
450 {
451 struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev);
452
453 kfree(aux);
454 }
455
ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 * pdata,struct auxiliary_device ** aux_out,const char * name)456 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
457 struct auxiliary_device **aux_out,
458 const char *name)
459 {
460 struct device *dev = pdata->dev;
461 const struct i2c_client *client = to_i2c_client(dev);
462 struct auxiliary_device *aux;
463 int ret;
464
465 aux = kzalloc(sizeof(*aux), GFP_KERNEL);
466 if (!aux)
467 return -ENOMEM;
468
469 aux->name = name;
470 aux->id = (client->adapter->nr << 10) | client->addr;
471 aux->dev.parent = dev;
472 aux->dev.release = ti_sn65dsi86_aux_device_release;
473 device_set_of_node_from_dev(&aux->dev, dev);
474 ret = auxiliary_device_init(aux);
475 if (ret) {
476 kfree(aux);
477 return ret;
478 }
479 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
480 if (ret)
481 return ret;
482
483 ret = auxiliary_device_add(aux);
484 if (ret)
485 return ret;
486 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
487 if (!ret)
488 *aux_out = aux;
489
490 return ret;
491 }
492
493 /* -----------------------------------------------------------------------------
494 * AUX Adapter
495 */
496
aux_to_ti_sn65dsi86(struct drm_dp_aux * aux)497 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
498 {
499 return container_of(aux, struct ti_sn65dsi86, aux);
500 }
501
ti_sn_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)502 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
503 struct drm_dp_aux_msg *msg)
504 {
505 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
506 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
507 u32 request_val = AUX_CMD_REQ(msg->request);
508 u8 *buf = msg->buffer;
509 unsigned int len = msg->size;
510 unsigned int short_len;
511 unsigned int val;
512 int ret;
513 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
514
515 if (len > SN_AUX_MAX_PAYLOAD_BYTES)
516 return -EINVAL;
517
518 pm_runtime_get_sync(pdata->dev);
519 mutex_lock(&pdata->comms_mutex);
520
521 /*
522 * If someone tries to do a DDC over AUX transaction before pre_enable()
523 * on a device without a dedicated reference clock then we just can't
524 * do it. Fail right away. This prevents non-refclk users from reading
525 * the EDID before enabling the panel but such is life.
526 */
527 if (!pdata->comms_enabled) {
528 ret = -EIO;
529 goto exit;
530 }
531
532 switch (request) {
533 case DP_AUX_NATIVE_WRITE:
534 case DP_AUX_I2C_WRITE:
535 case DP_AUX_NATIVE_READ:
536 case DP_AUX_I2C_READ:
537 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
538 /* Assume it's good */
539 msg->reply = 0;
540 break;
541 default:
542 ret = -EINVAL;
543 goto exit;
544 }
545
546 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
547 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
548 addr_len);
549 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
550 ARRAY_SIZE(addr_len));
551
552 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
553 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
554
555 /* Clear old status bits before start so we don't get confused */
556 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
557 AUX_IRQ_STATUS_NAT_I2C_FAIL |
558 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
559 AUX_IRQ_STATUS_AUX_SHORT);
560
561 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
562
563 /* Zero delay loop because i2c transactions are slow already */
564 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
565 !(val & AUX_CMD_SEND), 0, 50 * 1000);
566 if (ret)
567 goto exit;
568
569 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
570 if (ret)
571 goto exit;
572
573 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
574 /*
575 * The hardware tried the message seven times per the DP spec
576 * but it hit a timeout. We ignore defers here because they're
577 * handled in hardware.
578 */
579 ret = -ETIMEDOUT;
580 goto exit;
581 }
582
583 if (val & AUX_IRQ_STATUS_AUX_SHORT) {
584 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len);
585 len = min(len, short_len);
586 if (ret)
587 goto exit;
588 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
589 switch (request) {
590 case DP_AUX_I2C_WRITE:
591 case DP_AUX_I2C_READ:
592 msg->reply |= DP_AUX_I2C_REPLY_NACK;
593 break;
594 case DP_AUX_NATIVE_READ:
595 case DP_AUX_NATIVE_WRITE:
596 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
597 break;
598 }
599 len = 0;
600 goto exit;
601 }
602
603 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
604 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
605
606 exit:
607 mutex_unlock(&pdata->comms_mutex);
608 pm_runtime_mark_last_busy(pdata->dev);
609 pm_runtime_put_autosuspend(pdata->dev);
610
611 if (ret)
612 return ret;
613 return len;
614 }
615
ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux * aux,unsigned long wait_us)616 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
617 {
618 /*
619 * The HPD in this chip is a bit useless (See comment in
620 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
621 * for HPD, we just assume it's asserted after the wait_us delay.
622 *
623 * In case we are asked to wait forever (wait_us=0) take conservative
624 * 500ms delay.
625 */
626 if (wait_us == 0)
627 wait_us = 500000;
628
629 usleep_range(wait_us, wait_us + 1000);
630
631 return 0;
632 }
633
ti_sn_aux_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)634 static int ti_sn_aux_probe(struct auxiliary_device *adev,
635 const struct auxiliary_device_id *id)
636 {
637 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
638 int ret;
639
640 pdata->aux.name = "ti-sn65dsi86-aux";
641 pdata->aux.dev = &adev->dev;
642 pdata->aux.transfer = ti_sn_aux_transfer;
643 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
644 drm_dp_aux_init(&pdata->aux);
645
646 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
647 if (ret)
648 return ret;
649
650 /*
651 * The eDP to MIPI bridge parts don't work until the AUX channel is
652 * setup so we don't add it in the main driver probe, we add it now.
653 */
654 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
655 }
656
657 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
658 { .name = "ti_sn65dsi86.aux", },
659 {},
660 };
661
662 static struct auxiliary_driver ti_sn_aux_driver = {
663 .name = "aux",
664 .probe = ti_sn_aux_probe,
665 .id_table = ti_sn_aux_id_table,
666 };
667
668 /*------------------------------------------------------------------------------
669 * DRM Bridge
670 */
671
bridge_to_ti_sn65dsi86(struct drm_bridge * bridge)672 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
673 {
674 return container_of(bridge, struct ti_sn65dsi86, bridge);
675 }
676
ti_sn_attach_host(struct auxiliary_device * adev,struct ti_sn65dsi86 * pdata)677 static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata)
678 {
679 int val;
680 struct mipi_dsi_host *host;
681 struct mipi_dsi_device *dsi;
682 struct device *dev = pdata->dev;
683 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
684 .channel = 0,
685 .node = NULL,
686 };
687
688 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
689 if (!host)
690 return -EPROBE_DEFER;
691
692 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info);
693 if (IS_ERR(dsi))
694 return PTR_ERR(dsi);
695
696 /* TODO: setting to 4 MIPI lanes always for now */
697 dsi->lanes = 4;
698 dsi->format = MIPI_DSI_FMT_RGB888;
699 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
700
701 /* check if continuous dsi clock is required or not */
702 pm_runtime_get_sync(dev);
703 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
704 pm_runtime_put_autosuspend(dev);
705 if (!(val & DPPLL_CLK_SRC_DSICLK))
706 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
707
708 pdata->dsi = dsi;
709
710 return devm_mipi_dsi_attach(&adev->dev, dsi);
711 }
712
ti_sn_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)713 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
714 enum drm_bridge_attach_flags flags)
715 {
716 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
717 int ret;
718
719 pdata->aux.drm_dev = bridge->dev;
720 ret = drm_dp_aux_register(&pdata->aux);
721 if (ret < 0) {
722 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
723 return ret;
724 }
725
726 /*
727 * Attach the next bridge.
728 * We never want the next bridge to *also* create a connector.
729 */
730 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
731 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
732 if (ret < 0)
733 goto err_initted_aux;
734
735 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
736 return 0;
737
738 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
739 pdata->bridge.encoder);
740 if (IS_ERR(pdata->connector)) {
741 ret = PTR_ERR(pdata->connector);
742 goto err_initted_aux;
743 }
744
745 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
746
747 return 0;
748
749 err_initted_aux:
750 drm_dp_aux_unregister(&pdata->aux);
751 return ret;
752 }
753
ti_sn_bridge_detach(struct drm_bridge * bridge)754 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
755 {
756 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
757 }
758
759 static enum drm_mode_status
ti_sn_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)760 ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
761 const struct drm_display_info *info,
762 const struct drm_display_mode *mode)
763 {
764 /* maximum supported resolution is 4K at 60 fps */
765 if (mode->clock > 594000)
766 return MODE_CLOCK_HIGH;
767
768 /*
769 * The front and back porch registers are 8 bits, and pulse width
770 * registers are 15 bits, so reject any modes with larger periods.
771 */
772
773 if ((mode->hsync_start - mode->hdisplay) > 0xff)
774 return MODE_HBLANK_WIDE;
775
776 if ((mode->vsync_start - mode->vdisplay) > 0xff)
777 return MODE_VBLANK_WIDE;
778
779 if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
780 return MODE_HSYNC_WIDE;
781
782 if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
783 return MODE_VSYNC_WIDE;
784
785 if ((mode->htotal - mode->hsync_end) > 0xff)
786 return MODE_HBLANK_WIDE;
787
788 if ((mode->vtotal - mode->vsync_end) > 0xff)
789 return MODE_VBLANK_WIDE;
790
791 return MODE_OK;
792 }
793
ti_sn_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)794 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
795 struct drm_bridge_state *old_bridge_state)
796 {
797 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
798
799 /* disable video stream */
800 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
801 }
802
ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 * pdata)803 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
804 {
805 unsigned int bit_rate_mhz, clk_freq_mhz;
806 unsigned int val;
807 struct drm_display_mode *mode =
808 &pdata->bridge.encoder->crtc->state->adjusted_mode;
809
810 /* set DSIA clk frequency */
811 bit_rate_mhz = (mode->clock / 1000) *
812 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
813 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
814
815 /* for each increment in val, frequency increases by 5MHz */
816 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
817 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
818 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
819 }
820
ti_sn_bridge_get_bpp(struct drm_connector * connector)821 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
822 {
823 if (connector->display_info.bpc <= 6)
824 return 18;
825 else
826 return 24;
827 }
828
829 /*
830 * LUT index corresponds to register value and
831 * LUT values corresponds to dp data rate supported
832 * by the bridge in Mbps unit.
833 */
834 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
835 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
836 };
837
ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 * pdata,unsigned int bpp)838 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, unsigned int bpp)
839 {
840 unsigned int bit_rate_khz, dp_rate_mhz;
841 unsigned int i;
842 struct drm_display_mode *mode =
843 &pdata->bridge.encoder->crtc->state->adjusted_mode;
844
845 /* Calculate minimum bit rate based on our pixel clock. */
846 bit_rate_khz = mode->clock * bpp;
847
848 /* Calculate minimum DP data rate, taking 80% as per DP spec */
849 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
850 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
851
852 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
853 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
854 break;
855
856 return i;
857 }
858
ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 * pdata)859 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
860 {
861 unsigned int valid_rates = 0;
862 unsigned int rate_per_200khz;
863 unsigned int rate_mhz;
864 u8 dpcd_val;
865 int ret;
866 int i, j;
867
868 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
869 if (ret != 1) {
870 DRM_DEV_ERROR(pdata->dev,
871 "Can't read eDP rev (%d), assuming 1.1\n", ret);
872 dpcd_val = DP_EDP_11;
873 }
874
875 if (dpcd_val >= DP_EDP_14) {
876 /* eDP 1.4 devices must provide a custom table */
877 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
878
879 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
880 sink_rates, sizeof(sink_rates));
881
882 if (ret != sizeof(sink_rates)) {
883 DRM_DEV_ERROR(pdata->dev,
884 "Can't read supported rate table (%d)\n", ret);
885
886 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
887 memset(sink_rates, 0, sizeof(sink_rates));
888 }
889
890 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
891 rate_per_200khz = le16_to_cpu(sink_rates[i]);
892
893 if (!rate_per_200khz)
894 break;
895
896 rate_mhz = rate_per_200khz * 200 / 1000;
897 for (j = 0;
898 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
899 j++) {
900 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
901 valid_rates |= BIT(j);
902 }
903 }
904
905 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
906 if (valid_rates & BIT(i))
907 return valid_rates;
908 }
909 DRM_DEV_ERROR(pdata->dev,
910 "No matching eDP rates in table; falling back\n");
911 }
912
913 /* On older versions best we can do is use DP_MAX_LINK_RATE */
914 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
915 if (ret != 1) {
916 DRM_DEV_ERROR(pdata->dev,
917 "Can't read max rate (%d); assuming 5.4 GHz\n",
918 ret);
919 dpcd_val = DP_LINK_BW_5_4;
920 }
921
922 switch (dpcd_val) {
923 default:
924 DRM_DEV_ERROR(pdata->dev,
925 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
926 (int)dpcd_val);
927 fallthrough;
928 case DP_LINK_BW_5_4:
929 valid_rates |= BIT(7);
930 fallthrough;
931 case DP_LINK_BW_2_7:
932 valid_rates |= BIT(4);
933 fallthrough;
934 case DP_LINK_BW_1_62:
935 valid_rates |= BIT(1);
936 break;
937 }
938
939 return valid_rates;
940 }
941
ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 * pdata)942 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
943 {
944 struct drm_display_mode *mode =
945 &pdata->bridge.encoder->crtc->state->adjusted_mode;
946 u8 hsync_polarity = 0, vsync_polarity = 0;
947
948 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
949 hsync_polarity = CHA_HSYNC_POLARITY;
950 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
951 vsync_polarity = CHA_VSYNC_POLARITY;
952
953 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
954 mode->hdisplay);
955 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
956 mode->vdisplay);
957 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
958 (mode->hsync_end - mode->hsync_start) & 0xFF);
959 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
960 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
961 hsync_polarity);
962 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
963 (mode->vsync_end - mode->vsync_start) & 0xFF);
964 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
965 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
966 vsync_polarity);
967
968 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
969 (mode->htotal - mode->hsync_end) & 0xFF);
970 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
971 (mode->vtotal - mode->vsync_end) & 0xFF);
972
973 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
974 (mode->hsync_start - mode->hdisplay) & 0xFF);
975 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
976 (mode->vsync_start - mode->vdisplay) & 0xFF);
977
978 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
979 }
980
ti_sn_get_max_lanes(struct ti_sn65dsi86 * pdata)981 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
982 {
983 u8 data;
984 int ret;
985
986 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
987 if (ret != 1) {
988 DRM_DEV_ERROR(pdata->dev,
989 "Can't read lane count (%d); assuming 4\n", ret);
990 return 4;
991 }
992
993 return data & DP_LANE_COUNT_MASK;
994 }
995
ti_sn_link_training(struct ti_sn65dsi86 * pdata,int dp_rate_idx,const char ** last_err_str)996 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
997 const char **last_err_str)
998 {
999 unsigned int val;
1000 int ret;
1001 int i;
1002
1003 /* set dp clk frequency value */
1004 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1005 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1006
1007 /* enable DP PLL */
1008 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1009
1010 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1011 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1012 50 * 1000);
1013 if (ret) {
1014 *last_err_str = "DP_PLL_LOCK polling failed";
1015 goto exit;
1016 }
1017
1018 /*
1019 * We'll try to link train several times. As part of link training
1020 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
1021 * the panel isn't ready quite it might respond NAK here which means
1022 * we need to try again.
1023 */
1024 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1025 /* Semi auto link training mode */
1026 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1027 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1028 val == ML_TX_MAIN_LINK_OFF ||
1029 val == ML_TX_NORMAL_MODE, 1000,
1030 500 * 1000);
1031 if (ret) {
1032 *last_err_str = "Training complete polling failed";
1033 } else if (val == ML_TX_MAIN_LINK_OFF) {
1034 *last_err_str = "Link training failed, link is off";
1035 ret = -EIO;
1036 continue;
1037 }
1038
1039 break;
1040 }
1041
1042 /* If we saw quite a few retries, add a note about it */
1043 if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1044 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1045
1046 exit:
1047 /* Disable the PLL if we failed */
1048 if (ret)
1049 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1050
1051 return ret;
1052 }
1053
ti_sn_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1054 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
1055 struct drm_bridge_state *old_bridge_state)
1056 {
1057 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1058 struct drm_connector *connector;
1059 const char *last_err_str = "No supported DP rate";
1060 unsigned int valid_rates;
1061 int dp_rate_idx;
1062 unsigned int val;
1063 int ret = -EINVAL;
1064 int max_dp_lanes;
1065 unsigned int bpp;
1066
1067 connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state,
1068 bridge->encoder);
1069 if (!connector) {
1070 dev_err_ratelimited(pdata->dev, "Could not get the connector\n");
1071 return;
1072 }
1073
1074 max_dp_lanes = ti_sn_get_max_lanes(pdata);
1075 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1076
1077 /* DSI_A lane config */
1078 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1079 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1080 CHA_DSI_LANES_MASK, val);
1081
1082 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1083 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1084 pdata->ln_polrs << LN_POLRS_OFFSET);
1085
1086 /* set dsi clk frequency value */
1087 ti_sn_bridge_set_dsi_rate(pdata);
1088
1089 /*
1090 * The SN65DSI86 only supports ASSR Display Authentication method and
1091 * this method is enabled for eDP panels. An eDP panel must support this
1092 * authentication method. We need to enable this method in the eDP panel
1093 * at DisplayPort address 0x0010A prior to link training.
1094 *
1095 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays
1096 * we need to disable the scrambler.
1097 */
1098 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
1099 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1100 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1101
1102 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1103 SCRAMBLE_DISABLE, 0);
1104 } else {
1105 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1106 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);
1107 }
1108
1109 bpp = ti_sn_bridge_get_bpp(connector);
1110 /* Set the DP output format (18 bpp or 24 bpp) */
1111 val = bpp == 18 ? BPP_18_RGB : 0;
1112 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1113
1114 /* DP lane config */
1115 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1116 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1117 val);
1118
1119 valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1120
1121 /* Train until we run out of rates */
1122 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp);
1123 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1124 dp_rate_idx++) {
1125 if (!(valid_rates & BIT(dp_rate_idx)))
1126 continue;
1127
1128 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1129 if (!ret)
1130 break;
1131 }
1132 if (ret) {
1133 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1134 return;
1135 }
1136
1137 /* config video parameters */
1138 ti_sn_bridge_set_video_timings(pdata);
1139
1140 /* enable video stream */
1141 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1142 VSTREAM_ENABLE);
1143 }
1144
ti_sn_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1145 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1146 struct drm_bridge_state *old_bridge_state)
1147 {
1148 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1149
1150 pm_runtime_get_sync(pdata->dev);
1151
1152 if (!pdata->refclk)
1153 ti_sn65dsi86_enable_comms(pdata);
1154
1155 /* td7: min 100 us after enable before DSI data */
1156 usleep_range(100, 110);
1157 }
1158
ti_sn_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1159 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
1160 struct drm_bridge_state *old_bridge_state)
1161 {
1162 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1163
1164 /* semi auto link training mode OFF */
1165 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1166 /* Num lanes to 0 as per power sequencing in data sheet */
1167 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1168 /* disable DP PLL */
1169 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1170
1171 if (!pdata->refclk)
1172 ti_sn65dsi86_disable_comms(pdata);
1173
1174 pm_runtime_put_sync(pdata->dev);
1175 }
1176
ti_sn_bridge_detect(struct drm_bridge * bridge)1177 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge)
1178 {
1179 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1180 int val = 0;
1181
1182 /*
1183 * Runtime reference is grabbed in ti_sn_bridge_hpd_enable()
1184 * as the chip won't report HPD just after being powered on.
1185 * HPD_DEBOUNCED_STATE reflects correct state only after the
1186 * debounce time (~100-400 ms).
1187 */
1188
1189 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val);
1190
1191 return val & HPD_DEBOUNCED_STATE ? connector_status_connected
1192 : connector_status_disconnected;
1193 }
1194
ti_sn_bridge_get_edid(struct drm_bridge * bridge,struct drm_connector * connector)1195 static struct edid *ti_sn_bridge_get_edid(struct drm_bridge *bridge,
1196 struct drm_connector *connector)
1197 {
1198 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1199
1200 return drm_get_edid(connector, &pdata->aux.ddc);
1201 }
1202
ti_sn65dsi86_debugfs_init(struct drm_bridge * bridge,struct dentry * root)1203 static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
1204 {
1205 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1206 struct dentry *debugfs;
1207
1208 debugfs = debugfs_create_dir(dev_name(pdata->dev), root);
1209 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
1210 }
1211
ti_sn_bridge_hpd_enable(struct drm_bridge * bridge)1212 static void ti_sn_bridge_hpd_enable(struct drm_bridge *bridge)
1213 {
1214 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1215
1216 /*
1217 * Device needs to be powered on before reading the HPD state
1218 * for reliable hpd detection in ti_sn_bridge_detect() due to
1219 * the high debounce time.
1220 */
1221
1222 pm_runtime_get_sync(pdata->dev);
1223 }
1224
ti_sn_bridge_hpd_disable(struct drm_bridge * bridge)1225 static void ti_sn_bridge_hpd_disable(struct drm_bridge *bridge)
1226 {
1227 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1228
1229 pm_runtime_put_autosuspend(pdata->dev);
1230 }
1231
1232 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1233 .attach = ti_sn_bridge_attach,
1234 .detach = ti_sn_bridge_detach,
1235 .mode_valid = ti_sn_bridge_mode_valid,
1236 .get_edid = ti_sn_bridge_get_edid,
1237 .detect = ti_sn_bridge_detect,
1238 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
1239 .atomic_enable = ti_sn_bridge_atomic_enable,
1240 .atomic_disable = ti_sn_bridge_atomic_disable,
1241 .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
1242 .atomic_reset = drm_atomic_helper_bridge_reset,
1243 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1244 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1245 .debugfs_init = ti_sn65dsi86_debugfs_init,
1246 .hpd_enable = ti_sn_bridge_hpd_enable,
1247 .hpd_disable = ti_sn_bridge_hpd_disable,
1248 };
1249
ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 * pdata,struct device_node * np)1250 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1251 struct device_node *np)
1252 {
1253 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1254 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1255 struct device_node *endpoint;
1256 u8 ln_assign = 0;
1257 u8 ln_polrs = 0;
1258 int dp_lanes;
1259 int i;
1260
1261 /*
1262 * Read config from the device tree about lane remapping and lane
1263 * polarities. These are optional and we assume identity map and
1264 * normal polarity if nothing is specified. It's OK to specify just
1265 * data-lanes but not lane-polarities but not vice versa.
1266 *
1267 * Error checking is light (we just make sure we don't crash or
1268 * buffer overrun) and we assume dts is well formed and specifying
1269 * mappings that the hardware supports.
1270 */
1271 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1272 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES);
1273 if (dp_lanes > 0) {
1274 of_property_read_u32_array(endpoint, "data-lanes",
1275 lane_assignments, dp_lanes);
1276 of_property_read_u32_array(endpoint, "lane-polarities",
1277 lane_polarities, dp_lanes);
1278 } else {
1279 dp_lanes = SN_MAX_DP_LANES;
1280 }
1281 of_node_put(endpoint);
1282
1283 /*
1284 * Convert into register format. Loop over all lanes even if
1285 * data-lanes had fewer elements so that we nicely initialize
1286 * the LN_ASSIGN register.
1287 */
1288 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1289 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1290 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1291 }
1292
1293 /* Stash in our struct for when we power on */
1294 pdata->dp_lanes = dp_lanes;
1295 pdata->ln_assign = ln_assign;
1296 pdata->ln_polrs = ln_polrs;
1297 }
1298
ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 * pdata)1299 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1300 {
1301 struct device_node *np = pdata->dev->of_node;
1302
1303 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1304
1305 if (!pdata->host_node) {
1306 DRM_ERROR("remote dsi host node not found\n");
1307 return -ENODEV;
1308 }
1309
1310 return 0;
1311 }
1312
ti_sn_bridge_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1313 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1314 const struct auxiliary_device_id *id)
1315 {
1316 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1317 struct device_node *np = pdata->dev->of_node;
1318 int ret;
1319
1320 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0);
1321 if (IS_ERR(pdata->next_bridge))
1322 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge),
1323 "failed to create panel bridge\n");
1324
1325 ti_sn_bridge_parse_lanes(pdata, np);
1326
1327 ret = ti_sn_bridge_parse_dsi_host(pdata);
1328 if (ret)
1329 return ret;
1330
1331 pdata->bridge.funcs = &ti_sn_bridge_funcs;
1332 pdata->bridge.of_node = np;
1333 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
1334 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
1335
1336 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) {
1337 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT |
1338 DRM_BRIDGE_OP_HPD;
1339 /*
1340 * If comms were already enabled they would have been enabled
1341 * with the wrong value of HPD_DISABLE. Update it now. Comms
1342 * could be enabled if anyone is holding a pm_runtime reference
1343 * (like if a GPIO is in use). Note that in most cases nobody
1344 * is doing AUX channel xfers before the bridge is added so
1345 * HPD doesn't _really_ matter then. The only exception is in
1346 * the eDP case where the panel wants to read the EDID before
1347 * the bridge is added. We always consistently have HPD disabled
1348 * for eDP.
1349 */
1350 mutex_lock(&pdata->comms_mutex);
1351 if (pdata->comms_enabled)
1352 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
1353 HPD_DISABLE, 0);
1354 mutex_unlock(&pdata->comms_mutex);
1355 };
1356
1357 drm_bridge_add(&pdata->bridge);
1358
1359 ret = ti_sn_attach_host(adev, pdata);
1360 if (ret) {
1361 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n");
1362 goto err_remove_bridge;
1363 }
1364
1365 return 0;
1366
1367 err_remove_bridge:
1368 drm_bridge_remove(&pdata->bridge);
1369 return ret;
1370 }
1371
ti_sn_bridge_remove(struct auxiliary_device * adev)1372 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1373 {
1374 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1375
1376 if (!pdata)
1377 return;
1378
1379 drm_bridge_remove(&pdata->bridge);
1380
1381 of_node_put(pdata->host_node);
1382 }
1383
1384 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1385 { .name = "ti_sn65dsi86.bridge", },
1386 {},
1387 };
1388
1389 static struct auxiliary_driver ti_sn_bridge_driver = {
1390 .name = "bridge",
1391 .probe = ti_sn_bridge_probe,
1392 .remove = ti_sn_bridge_remove,
1393 .id_table = ti_sn_bridge_id_table,
1394 };
1395
1396 /* -----------------------------------------------------------------------------
1397 * PWM Controller
1398 */
1399 #if defined(CONFIG_PWM)
ti_sn_pwm_pin_request(struct ti_sn65dsi86 * pdata)1400 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1401 {
1402 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1403 }
1404
ti_sn_pwm_pin_release(struct ti_sn65dsi86 * pdata)1405 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1406 {
1407 atomic_set(&pdata->pwm_pin_busy, 0);
1408 }
1409
pwm_chip_to_ti_sn_bridge(struct pwm_chip * chip)1410 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1411 {
1412 return container_of(chip, struct ti_sn65dsi86, pchip);
1413 }
1414
ti_sn_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)1415 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1416 {
1417 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1418
1419 return ti_sn_pwm_pin_request(pdata);
1420 }
1421
ti_sn_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)1422 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1423 {
1424 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1425
1426 ti_sn_pwm_pin_release(pdata);
1427 }
1428
1429 /*
1430 * Limitations:
1431 * - The PWM signal is not driven when the chip is powered down, or in its
1432 * reset state and the driver does not implement the "suspend state"
1433 * described in the documentation. In order to save power, state->enabled is
1434 * interpreted as denoting if the signal is expected to be valid, and is used
1435 * to determine if the chip needs to be kept powered.
1436 * - Changing both period and duty_cycle is not done atomically, neither is the
1437 * multi-byte register updates, so the output might briefly be undefined
1438 * during update.
1439 */
ti_sn_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)1440 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1441 const struct pwm_state *state)
1442 {
1443 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1444 unsigned int pwm_en_inv;
1445 unsigned int backlight;
1446 unsigned int pre_div;
1447 unsigned int scale;
1448 u64 period_max;
1449 u64 period;
1450 int ret;
1451
1452 if (!pdata->pwm_enabled) {
1453 ret = pm_runtime_get_sync(pdata->dev);
1454 if (ret < 0) {
1455 pm_runtime_put_sync(pdata->dev);
1456 return ret;
1457 }
1458 }
1459
1460 if (state->enabled) {
1461 if (!pdata->pwm_enabled) {
1462 /*
1463 * The chip might have been powered down while we
1464 * didn't hold a PM runtime reference, so mux in the
1465 * PWM function on the GPIO pin again.
1466 */
1467 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1468 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1469 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1470 if (ret) {
1471 dev_err(pdata->dev, "failed to mux in PWM function\n");
1472 goto out;
1473 }
1474 }
1475
1476 /*
1477 * Per the datasheet the PWM frequency is given by:
1478 *
1479 * REFCLK_FREQ
1480 * PWM_FREQ = -----------------------------------
1481 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1482 *
1483 * However, after careful review the author is convinced that
1484 * the documentation has lost some parenthesis around
1485 * "BACKLIGHT_SCALE + 1".
1486 *
1487 * With the period T_pwm = 1/PWM_FREQ this can be written:
1488 *
1489 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1490 *
1491 * In order to keep BACKLIGHT_SCALE within its 16 bits,
1492 * PWM_PRE_DIV must be:
1493 *
1494 * T_pwm * REFCLK_FREQ
1495 * PWM_PRE_DIV >= -------------------------
1496 * BACKLIGHT_SCALE_MAX + 1
1497 *
1498 * To simplify the search and to favour higher resolution of
1499 * the duty cycle over accuracy of the period, the lowest
1500 * possible PWM_PRE_DIV is used. Finally the scale is
1501 * calculated as:
1502 *
1503 * T_pwm * REFCLK_FREQ
1504 * BACKLIGHT_SCALE = ---------------------- - 1
1505 * PWM_PRE_DIV
1506 *
1507 * Here T_pwm is represented in seconds, so appropriate scaling
1508 * to nanoseconds is necessary.
1509 */
1510
1511 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1512 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1513 ret = -EINVAL;
1514 goto out;
1515 }
1516
1517 /*
1518 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1519 * Limit period to this to avoid overflows
1520 */
1521 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1522 pdata->pwm_refclk_freq);
1523 period = min(state->period, period_max);
1524
1525 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1526 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1527 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1528
1529 /*
1530 * The documentation has the duty ratio given as:
1531 *
1532 * duty BACKLIGHT
1533 * ------- = ---------------------
1534 * period BACKLIGHT_SCALE + 1
1535 *
1536 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1537 * to definition above and adjusting for nanosecond
1538 * representation of duty cycle gives us:
1539 */
1540 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1541 (u64)NSEC_PER_SEC * pre_div);
1542 if (backlight > scale)
1543 backlight = scale;
1544
1545 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1546 if (ret) {
1547 dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n");
1548 goto out;
1549 }
1550
1551 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1552 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1553 }
1554
1555 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1556 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1557 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1558 if (ret) {
1559 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n");
1560 goto out;
1561 }
1562
1563 pdata->pwm_enabled = state->enabled;
1564 out:
1565
1566 if (!pdata->pwm_enabled)
1567 pm_runtime_put_sync(pdata->dev);
1568
1569 return ret;
1570 }
1571
ti_sn_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)1572 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1573 struct pwm_state *state)
1574 {
1575 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1576 unsigned int pwm_en_inv;
1577 unsigned int pre_div;
1578 u16 backlight;
1579 u16 scale;
1580 int ret;
1581
1582 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1583 if (ret)
1584 return ret;
1585
1586 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1587 if (ret)
1588 return ret;
1589
1590 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1591 if (ret)
1592 return ret;
1593
1594 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1595 if (ret)
1596 return ret;
1597
1598 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1599 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1600 state->polarity = PWM_POLARITY_INVERSED;
1601 else
1602 state->polarity = PWM_POLARITY_NORMAL;
1603
1604 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1605 pdata->pwm_refclk_freq);
1606 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1607 pdata->pwm_refclk_freq);
1608
1609 if (state->duty_cycle > state->period)
1610 state->duty_cycle = state->period;
1611
1612 return 0;
1613 }
1614
1615 static const struct pwm_ops ti_sn_pwm_ops = {
1616 .request = ti_sn_pwm_request,
1617 .free = ti_sn_pwm_free,
1618 .apply = ti_sn_pwm_apply,
1619 .get_state = ti_sn_pwm_get_state,
1620 .owner = THIS_MODULE,
1621 };
1622
ti_sn_pwm_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1623 static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1624 const struct auxiliary_device_id *id)
1625 {
1626 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1627
1628 pdata->pchip.dev = pdata->dev;
1629 pdata->pchip.ops = &ti_sn_pwm_ops;
1630 pdata->pchip.npwm = 1;
1631 pdata->pchip.of_xlate = of_pwm_single_xlate;
1632 pdata->pchip.of_pwm_n_cells = 1;
1633
1634 return pwmchip_add(&pdata->pchip);
1635 }
1636
ti_sn_pwm_remove(struct auxiliary_device * adev)1637 static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1638 {
1639 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1640
1641 pwmchip_remove(&pdata->pchip);
1642
1643 if (pdata->pwm_enabled)
1644 pm_runtime_put_sync(pdata->dev);
1645 }
1646
1647 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1648 { .name = "ti_sn65dsi86.pwm", },
1649 {},
1650 };
1651
1652 static struct auxiliary_driver ti_sn_pwm_driver = {
1653 .name = "pwm",
1654 .probe = ti_sn_pwm_probe,
1655 .remove = ti_sn_pwm_remove,
1656 .id_table = ti_sn_pwm_id_table,
1657 };
1658
ti_sn_pwm_register(void)1659 static int __init ti_sn_pwm_register(void)
1660 {
1661 return auxiliary_driver_register(&ti_sn_pwm_driver);
1662 }
1663
ti_sn_pwm_unregister(void)1664 static void ti_sn_pwm_unregister(void)
1665 {
1666 auxiliary_driver_unregister(&ti_sn_pwm_driver);
1667 }
1668
1669 #else
ti_sn_pwm_pin_request(struct ti_sn65dsi86 * pdata)1670 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
ti_sn_pwm_pin_release(struct ti_sn65dsi86 * pdata)1671 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1672
ti_sn_pwm_register(void)1673 static inline int ti_sn_pwm_register(void) { return 0; }
ti_sn_pwm_unregister(void)1674 static inline void ti_sn_pwm_unregister(void) {}
1675 #endif
1676
1677 /* -----------------------------------------------------------------------------
1678 * GPIO Controller
1679 */
1680 #if defined(CONFIG_OF_GPIO)
1681
tn_sn_bridge_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpiospec,u32 * flags)1682 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1683 const struct of_phandle_args *gpiospec,
1684 u32 *flags)
1685 {
1686 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1687 return -EINVAL;
1688
1689 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1690 return -EINVAL;
1691
1692 if (flags)
1693 *flags = gpiospec->args[1];
1694
1695 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1696 }
1697
ti_sn_bridge_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1698 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1699 unsigned int offset)
1700 {
1701 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1702
1703 /*
1704 * We already have to keep track of the direction because we use
1705 * that to figure out whether we've powered the device. We can
1706 * just return that rather than (maybe) powering up the device
1707 * to ask its direction.
1708 */
1709 return test_bit(offset, pdata->gchip_output) ?
1710 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1711 }
1712
ti_sn_bridge_gpio_get(struct gpio_chip * chip,unsigned int offset)1713 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1714 {
1715 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1716 unsigned int val;
1717 int ret;
1718
1719 /*
1720 * When the pin is an input we don't forcibly keep the bridge
1721 * powered--we just power it on to read the pin. NOTE: part of
1722 * the reason this works is that the bridge defaults (when
1723 * powered back on) to all 4 GPIOs being configured as GPIO input.
1724 * Also note that if something else is keeping the chip powered the
1725 * pm_runtime functions are lightweight increments of a refcount.
1726 */
1727 pm_runtime_get_sync(pdata->dev);
1728 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1729 pm_runtime_put_autosuspend(pdata->dev);
1730
1731 if (ret)
1732 return ret;
1733
1734 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1735 }
1736
ti_sn_bridge_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1737 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1738 int val)
1739 {
1740 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1741 int ret;
1742
1743 if (!test_bit(offset, pdata->gchip_output)) {
1744 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1745 return;
1746 }
1747
1748 val &= 1;
1749 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1750 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1751 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1752 if (ret)
1753 dev_warn(pdata->dev,
1754 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1755 }
1756
ti_sn_bridge_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1757 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1758 unsigned int offset)
1759 {
1760 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1761 int shift = offset * 2;
1762 int ret;
1763
1764 if (!test_and_clear_bit(offset, pdata->gchip_output))
1765 return 0;
1766
1767 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1768 SN_GPIO_MUX_MASK << shift,
1769 SN_GPIO_MUX_INPUT << shift);
1770 if (ret) {
1771 set_bit(offset, pdata->gchip_output);
1772 return ret;
1773 }
1774
1775 /*
1776 * NOTE: if nobody else is powering the device this may fully power
1777 * it off and when it comes back it will have lost all state, but
1778 * that's OK because the default is input and we're now an input.
1779 */
1780 pm_runtime_put_autosuspend(pdata->dev);
1781
1782 return 0;
1783 }
1784
ti_sn_bridge_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)1785 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1786 unsigned int offset, int val)
1787 {
1788 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1789 int shift = offset * 2;
1790 int ret;
1791
1792 if (test_and_set_bit(offset, pdata->gchip_output))
1793 return 0;
1794
1795 pm_runtime_get_sync(pdata->dev);
1796
1797 /* Set value first to avoid glitching */
1798 ti_sn_bridge_gpio_set(chip, offset, val);
1799
1800 /* Set direction */
1801 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1802 SN_GPIO_MUX_MASK << shift,
1803 SN_GPIO_MUX_OUTPUT << shift);
1804 if (ret) {
1805 clear_bit(offset, pdata->gchip_output);
1806 pm_runtime_put_autosuspend(pdata->dev);
1807 }
1808
1809 return ret;
1810 }
1811
ti_sn_bridge_gpio_request(struct gpio_chip * chip,unsigned int offset)1812 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1813 {
1814 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1815
1816 if (offset == SN_PWM_GPIO_IDX)
1817 return ti_sn_pwm_pin_request(pdata);
1818
1819 return 0;
1820 }
1821
ti_sn_bridge_gpio_free(struct gpio_chip * chip,unsigned int offset)1822 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1823 {
1824 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1825
1826 /* We won't keep pm_runtime if we're input, so switch there on free */
1827 ti_sn_bridge_gpio_direction_input(chip, offset);
1828
1829 if (offset == SN_PWM_GPIO_IDX)
1830 ti_sn_pwm_pin_release(pdata);
1831 }
1832
1833 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1834 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1835 };
1836
ti_sn_gpio_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1837 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1838 const struct auxiliary_device_id *id)
1839 {
1840 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1841 int ret;
1842
1843 /* Only init if someone is going to use us as a GPIO controller */
1844 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1845 return 0;
1846
1847 pdata->gchip.label = dev_name(pdata->dev);
1848 pdata->gchip.parent = pdata->dev;
1849 pdata->gchip.owner = THIS_MODULE;
1850 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1851 pdata->gchip.of_gpio_n_cells = 2;
1852 pdata->gchip.request = ti_sn_bridge_gpio_request;
1853 pdata->gchip.free = ti_sn_bridge_gpio_free;
1854 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1855 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1856 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1857 pdata->gchip.get = ti_sn_bridge_gpio_get;
1858 pdata->gchip.set = ti_sn_bridge_gpio_set;
1859 pdata->gchip.can_sleep = true;
1860 pdata->gchip.names = ti_sn_bridge_gpio_names;
1861 pdata->gchip.ngpio = SN_NUM_GPIOS;
1862 pdata->gchip.base = -1;
1863 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1864 if (ret)
1865 dev_err(pdata->dev, "can't add gpio chip\n");
1866
1867 return ret;
1868 }
1869
1870 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1871 { .name = "ti_sn65dsi86.gpio", },
1872 {},
1873 };
1874
1875 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1876
1877 static struct auxiliary_driver ti_sn_gpio_driver = {
1878 .name = "gpio",
1879 .probe = ti_sn_gpio_probe,
1880 .id_table = ti_sn_gpio_id_table,
1881 };
1882
ti_sn_gpio_register(void)1883 static int __init ti_sn_gpio_register(void)
1884 {
1885 return auxiliary_driver_register(&ti_sn_gpio_driver);
1886 }
1887
ti_sn_gpio_unregister(void)1888 static void ti_sn_gpio_unregister(void)
1889 {
1890 auxiliary_driver_unregister(&ti_sn_gpio_driver);
1891 }
1892
1893 #else
1894
ti_sn_gpio_register(void)1895 static inline int ti_sn_gpio_register(void) { return 0; }
ti_sn_gpio_unregister(void)1896 static inline void ti_sn_gpio_unregister(void) {}
1897
1898 #endif
1899
1900 /* -----------------------------------------------------------------------------
1901 * Probe & Remove
1902 */
1903
ti_sn65dsi86_runtime_disable(void * data)1904 static void ti_sn65dsi86_runtime_disable(void *data)
1905 {
1906 pm_runtime_dont_use_autosuspend(data);
1907 pm_runtime_disable(data);
1908 }
1909
ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 * pdata)1910 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1911 {
1912 unsigned int i;
1913 const char * const ti_sn_bridge_supply_names[] = {
1914 "vcca", "vcc", "vccio", "vpll",
1915 };
1916
1917 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1918 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1919
1920 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1921 pdata->supplies);
1922 }
1923
ti_sn65dsi86_probe(struct i2c_client * client)1924 static int ti_sn65dsi86_probe(struct i2c_client *client)
1925 {
1926 struct device *dev = &client->dev;
1927 struct ti_sn65dsi86 *pdata;
1928 int ret;
1929
1930 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1931 DRM_ERROR("device doesn't support I2C\n");
1932 return -ENODEV;
1933 }
1934
1935 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1936 if (!pdata)
1937 return -ENOMEM;
1938 dev_set_drvdata(dev, pdata);
1939 pdata->dev = dev;
1940
1941 mutex_init(&pdata->comms_mutex);
1942
1943 pdata->regmap = devm_regmap_init_i2c(client,
1944 &ti_sn65dsi86_regmap_config);
1945 if (IS_ERR(pdata->regmap))
1946 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1947 "regmap i2c init failed\n");
1948
1949 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1950 GPIOD_OUT_LOW);
1951 if (IS_ERR(pdata->enable_gpio))
1952 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1953 "failed to get enable gpio from DT\n");
1954
1955 ret = ti_sn65dsi86_parse_regulators(pdata);
1956 if (ret)
1957 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1958
1959 pdata->refclk = devm_clk_get_optional(dev, "refclk");
1960 if (IS_ERR(pdata->refclk))
1961 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1962 "failed to get reference clock\n");
1963
1964 pm_runtime_enable(dev);
1965 pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1966 pm_runtime_use_autosuspend(pdata->dev);
1967 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1968 if (ret)
1969 return ret;
1970
1971 /*
1972 * Break ourselves up into a collection of aux devices. The only real
1973 * motiviation here is to solve the chicken-and-egg problem of probe
1974 * ordering. The bridge wants the panel to be there when it probes.
1975 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1976 * when it probes. The panel and maybe backlight might want the DDC
1977 * bus or the pwm_chip. Having sub-devices allows the some sub devices
1978 * to finish probing even if others return -EPROBE_DEFER and gets us
1979 * around the problems.
1980 */
1981
1982 if (IS_ENABLED(CONFIG_OF_GPIO)) {
1983 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1984 if (ret)
1985 return ret;
1986 }
1987
1988 if (IS_ENABLED(CONFIG_PWM)) {
1989 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
1990 if (ret)
1991 return ret;
1992 }
1993
1994 /*
1995 * NOTE: At the end of the AUX channel probe we'll add the aux device
1996 * for the bridge. This is because the bridge can't be used until the
1997 * AUX channel is there and this is a very simple solution to the
1998 * dependency problem.
1999 */
2000 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
2001 }
2002
2003 static struct i2c_device_id ti_sn65dsi86_id[] = {
2004 { "ti,sn65dsi86", 0},
2005 {},
2006 };
2007 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
2008
2009 static const struct of_device_id ti_sn65dsi86_match_table[] = {
2010 {.compatible = "ti,sn65dsi86"},
2011 {},
2012 };
2013 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
2014
2015 static struct i2c_driver ti_sn65dsi86_driver = {
2016 .driver = {
2017 .name = "ti_sn65dsi86",
2018 .of_match_table = ti_sn65dsi86_match_table,
2019 .pm = &ti_sn65dsi86_pm_ops,
2020 },
2021 .probe = ti_sn65dsi86_probe,
2022 .id_table = ti_sn65dsi86_id,
2023 };
2024
ti_sn65dsi86_init(void)2025 static int __init ti_sn65dsi86_init(void)
2026 {
2027 int ret;
2028
2029 ret = i2c_add_driver(&ti_sn65dsi86_driver);
2030 if (ret)
2031 return ret;
2032
2033 ret = ti_sn_gpio_register();
2034 if (ret)
2035 goto err_main_was_registered;
2036
2037 ret = ti_sn_pwm_register();
2038 if (ret)
2039 goto err_gpio_was_registered;
2040
2041 ret = auxiliary_driver_register(&ti_sn_aux_driver);
2042 if (ret)
2043 goto err_pwm_was_registered;
2044
2045 ret = auxiliary_driver_register(&ti_sn_bridge_driver);
2046 if (ret)
2047 goto err_aux_was_registered;
2048
2049 return 0;
2050
2051 err_aux_was_registered:
2052 auxiliary_driver_unregister(&ti_sn_aux_driver);
2053 err_pwm_was_registered:
2054 ti_sn_pwm_unregister();
2055 err_gpio_was_registered:
2056 ti_sn_gpio_unregister();
2057 err_main_was_registered:
2058 i2c_del_driver(&ti_sn65dsi86_driver);
2059
2060 return ret;
2061 }
2062 module_init(ti_sn65dsi86_init);
2063
ti_sn65dsi86_exit(void)2064 static void __exit ti_sn65dsi86_exit(void)
2065 {
2066 auxiliary_driver_unregister(&ti_sn_bridge_driver);
2067 auxiliary_driver_unregister(&ti_sn_aux_driver);
2068 ti_sn_pwm_unregister();
2069 ti_sn_gpio_unregister();
2070 i2c_del_driver(&ti_sn65dsi86_driver);
2071 }
2072 module_exit(ti_sn65dsi86_exit);
2073
2074 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
2075 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
2076 MODULE_LICENSE("GPL v2");
2077