xref: /openbmc/linux/drivers/staging/qlge/qlge.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1  /* SPDX-License-Identifier: GPL-2.0-only */
2  /*
3   * QLogic QLA41xx NIC HBA Driver
4   * Copyright (c)  2003-2006 QLogic Corporation
5   */
6  #ifndef _QLGE_H_
7  #define _QLGE_H_
8  
9  #include <linux/interrupt.h>
10  #include <linux/pci.h>
11  #include <linux/netdevice.h>
12  #include <linux/rtnetlink.h>
13  #include <linux/if_vlan.h>
14  
15  /*
16   * General definitions...
17   */
18  #define DRV_NAME	"qlge"
19  #define DRV_STRING	"QLogic 10 Gigabit PCI-E Ethernet Driver "
20  #define DRV_VERSION	"1.00.00.35"
21  
22  #define WQ_ADDR_ALIGN	0x3	/* 4 byte alignment */
23  
24  #define QLGE_VENDOR_ID    0x1077
25  #define QLGE_DEVICE_ID_8012	0x8012
26  #define QLGE_DEVICE_ID_8000	0x8000
27  #define QLGE_MEZZ_SSYS_ID_068	0x0068
28  #define QLGE_MEZZ_SSYS_ID_180	0x0180
29  #define MAX_CPUS 8
30  #define MAX_TX_RINGS MAX_CPUS
31  #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
32  
33  #define NUM_TX_RING_ENTRIES	256
34  #define NUM_RX_RING_ENTRIES	256
35  
36  /* Use the same len for sbq and lbq. Note that it seems like the device might
37   * support different sizes.
38   */
39  #define QLGE_BQ_SHIFT 9
40  #define QLGE_BQ_LEN BIT(QLGE_BQ_SHIFT)
41  #define QLGE_BQ_SIZE (QLGE_BQ_LEN * sizeof(__le64))
42  
43  #define DB_PAGE_SIZE 4096
44  
45  /* Calculate the number of (4k) pages required to
46   * contain a buffer queue of the given length.
47   */
48  #define MAX_DB_PAGES_PER_BQ(x) \
49  		(((x * sizeof(u64)) / DB_PAGE_SIZE) + \
50  		(((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
51  
52  #define RX_RING_SHADOW_SPACE	(sizeof(u64) + \
53  		MAX_DB_PAGES_PER_BQ(QLGE_BQ_LEN) * sizeof(u64) + \
54  		MAX_DB_PAGES_PER_BQ(QLGE_BQ_LEN) * sizeof(u64))
55  #define LARGE_BUFFER_MAX_SIZE 8192
56  #define LARGE_BUFFER_MIN_SIZE 2048
57  
58  #define MAX_CQ 128
59  #define DFLT_COALESCE_WAIT 100	/* 100 usec wait for coalescing */
60  #define MAX_INTER_FRAME_WAIT 10	/* 10 usec max interframe-wait for coalescing */
61  #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT / 2)
62  #define UDELAY_COUNT 3
63  #define UDELAY_DELAY 100
64  
65  #define TX_DESC_PER_IOCB 8
66  
67  #if ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2) > 0
68  #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
69  #else /* all other page sizes */
70  #define TX_DESC_PER_OAL 0
71  #endif
72  
73  /* Word shifting for converting 64-bit
74   * address to a series of 16-bit words.
75   * This is used for some MPI firmware
76   * mailbox commands.
77   */
78  #define LSW(x)  ((u16)(x))
79  #define MSW(x)  ((u16)((u32)(x) >> 16))
80  #define LSD(x)  ((u32)((u64)(x)))
81  #define MSD(x)  ((u32)((((u64)(x)) >> 32)))
82  
83  /* In some cases, the device interprets a value of 0x0000 as 65536. These
84   * cases are marked using the following macro.
85   */
86  #define QLGE_FIT16(value) ((u16)(value))
87  
88  /* MPI test register definitions. This register
89   * is used for determining alternate NIC function's
90   * PCI->func number.
91   */
92  enum {
93  	MPI_TEST_FUNC_PORT_CFG = 0x1002,
94  	MPI_TEST_FUNC_PRB_CTL = 0x100e,
95  		MPI_TEST_FUNC_PRB_EN = 0x18a20000,
96  	MPI_TEST_FUNC_RST_STS = 0x100a,
97  		MPI_TEST_FUNC_RST_FRC = 0x00000003,
98  	MPI_TEST_NIC_FUNC_MASK = 0x00000007,
99  	MPI_TEST_NIC1_FUNCTION_ENABLE = (1 << 0),
100  	MPI_TEST_NIC1_FUNCTION_MASK = 0x0000000e,
101  	MPI_TEST_NIC1_FUNC_SHIFT = 1,
102  	MPI_TEST_NIC2_FUNCTION_ENABLE = (1 << 4),
103  	MPI_TEST_NIC2_FUNCTION_MASK = 0x000000e0,
104  	MPI_TEST_NIC2_FUNC_SHIFT = 5,
105  	MPI_TEST_FC1_FUNCTION_ENABLE = (1 << 8),
106  	MPI_TEST_FC1_FUNCTION_MASK	= 0x00000e00,
107  	MPI_TEST_FC1_FUNCTION_SHIFT = 9,
108  	MPI_TEST_FC2_FUNCTION_ENABLE = (1 << 12),
109  	MPI_TEST_FC2_FUNCTION_MASK = 0x0000e000,
110  	MPI_TEST_FC2_FUNCTION_SHIFT = 13,
111  
112  	MPI_NIC_READ = 0x00000000,
113  	MPI_NIC_REG_BLOCK = 0x00020000,
114  	MPI_NIC_FUNCTION_SHIFT = 6,
115  };
116  
117  /*
118   * Processor Address Register (PROC_ADDR) bit definitions.
119   */
120  enum {
121  	/* Misc. stuff */
122  	MAILBOX_COUNT = 16,
123  	MAILBOX_TIMEOUT = 5,
124  
125  	PROC_ADDR_RDY = (1 << 31),
126  	PROC_ADDR_R = (1 << 30),
127  	PROC_ADDR_ERR = (1 << 29),
128  	PROC_ADDR_DA = (1 << 28),
129  	PROC_ADDR_FUNC0_MBI = 0x00001180,
130  	PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
131  	PROC_ADDR_FUNC0_CTL = 0x000011a1,
132  	PROC_ADDR_FUNC2_MBI = 0x00001280,
133  	PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
134  	PROC_ADDR_FUNC2_CTL = 0x000012a1,
135  	PROC_ADDR_MPI_RISC = 0x00000000,
136  	PROC_ADDR_MDE = 0x00010000,
137  	PROC_ADDR_REGBLOCK = 0x00020000,
138  	PROC_ADDR_RISC_REG = 0x00030000,
139  };
140  
141  /*
142   * System Register (SYS) bit definitions.
143   */
144  enum {
145  	SYS_EFE = (1 << 0),
146  	SYS_FAE = (1 << 1),
147  	SYS_MDC = (1 << 2),
148  	SYS_DST = (1 << 3),
149  	SYS_DWC = (1 << 4),
150  	SYS_EVW = (1 << 5),
151  	SYS_OMP_DLY_MASK = 0x3f000000,
152  	/*
153  	 * There are no values defined as of edit #15.
154  	 */
155  	SYS_ODI = (1 << 14),
156  };
157  
158  /*
159   *  Reset/Failover Register (RST_FO) bit definitions.
160   */
161  enum {
162  	RST_FO_TFO = (1 << 0),
163  	RST_FO_RR_MASK = 0x00060000,
164  	RST_FO_RR_CQ_CAM = 0x00000000,
165  	RST_FO_RR_DROP = 0x00000002,
166  	RST_FO_RR_DQ = 0x00000004,
167  	RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
168  	RST_FO_FRB = (1 << 12),
169  	RST_FO_MOP = (1 << 13),
170  	RST_FO_REG = (1 << 14),
171  	RST_FO_FR = (1 << 15),
172  };
173  
174  /*
175   * Function Specific Control Register (FSC) bit definitions.
176   */
177  enum {
178  	FSC_DBRST_MASK = 0x00070000,
179  	FSC_DBRST_256 = 0x00000000,
180  	FSC_DBRST_512 = 0x00000001,
181  	FSC_DBRST_768 = 0x00000002,
182  	FSC_DBRST_1024 = 0x00000003,
183  	FSC_DBL_MASK = 0x00180000,
184  	FSC_DBL_DBRST = 0x00000000,
185  	FSC_DBL_MAX_PLD = 0x00000008,
186  	FSC_DBL_MAX_BRST = 0x00000010,
187  	FSC_DBL_128_BYTES = 0x00000018,
188  	FSC_EC = (1 << 5),
189  	FSC_EPC_MASK = 0x00c00000,
190  	FSC_EPC_INBOUND = (1 << 6),
191  	FSC_EPC_OUTBOUND = (1 << 7),
192  	FSC_VM_PAGESIZE_MASK = 0x07000000,
193  	FSC_VM_PAGE_2K = 0x00000100,
194  	FSC_VM_PAGE_4K = 0x00000200,
195  	FSC_VM_PAGE_8K = 0x00000300,
196  	FSC_VM_PAGE_64K = 0x00000600,
197  	FSC_SH = (1 << 11),
198  	FSC_DSB = (1 << 12),
199  	FSC_STE = (1 << 13),
200  	FSC_FE = (1 << 15),
201  };
202  
203  /*
204   *  Host Command Status Register (CSR) bit definitions.
205   */
206  enum {
207  	CSR_ERR_STS_MASK = 0x0000003f,
208  	/*
209  	 * There are no valued defined as of edit #15.
210  	 */
211  	CSR_RR = (1 << 8),
212  	CSR_HRI = (1 << 9),
213  	CSR_RP = (1 << 10),
214  	CSR_CMD_PARM_SHIFT = 22,
215  	CSR_CMD_NOP = 0x00000000,
216  	CSR_CMD_SET_RST = 0x10000000,
217  	CSR_CMD_CLR_RST = 0x20000000,
218  	CSR_CMD_SET_PAUSE = 0x30000000,
219  	CSR_CMD_CLR_PAUSE = 0x40000000,
220  	CSR_CMD_SET_H2R_INT = 0x50000000,
221  	CSR_CMD_CLR_H2R_INT = 0x60000000,
222  	CSR_CMD_PAR_EN = 0x70000000,
223  	CSR_CMD_SET_BAD_PAR = 0x80000000,
224  	CSR_CMD_CLR_BAD_PAR = 0x90000000,
225  	CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
226  };
227  
228  /*
229   *  Configuration Register (CFG) bit definitions.
230   */
231  enum {
232  	CFG_LRQ = (1 << 0),
233  	CFG_DRQ = (1 << 1),
234  	CFG_LR = (1 << 2),
235  	CFG_DR = (1 << 3),
236  	CFG_LE = (1 << 5),
237  	CFG_LCQ = (1 << 6),
238  	CFG_DCQ = (1 << 7),
239  	CFG_Q_SHIFT = 8,
240  	CFG_Q_MASK = 0x7f000000,
241  };
242  
243  /*
244   *  Status Register (STS) bit definitions.
245   */
246  enum {
247  	STS_FE = (1 << 0),
248  	STS_PI = (1 << 1),
249  	STS_PL0 = (1 << 2),
250  	STS_PL1 = (1 << 3),
251  	STS_PI0 = (1 << 4),
252  	STS_PI1 = (1 << 5),
253  	STS_FUNC_ID_MASK = 0x000000c0,
254  	STS_FUNC_ID_SHIFT = 6,
255  	STS_F0E = (1 << 8),
256  	STS_F1E = (1 << 9),
257  	STS_F2E = (1 << 10),
258  	STS_F3E = (1 << 11),
259  	STS_NFE = (1 << 12),
260  };
261  
262  /*
263   * Interrupt Enable Register (INTR_EN) bit definitions.
264   */
265  enum {
266  	INTR_EN_INTR_MASK = 0x007f0000,
267  	INTR_EN_TYPE_MASK = 0x03000000,
268  	INTR_EN_TYPE_ENABLE = 0x00000100,
269  	INTR_EN_TYPE_DISABLE = 0x00000200,
270  	INTR_EN_TYPE_READ = 0x00000300,
271  	INTR_EN_IHD = (1 << 13),
272  	INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
273  	INTR_EN_EI = (1 << 14),
274  	INTR_EN_EN = (1 << 15),
275  };
276  
277  /*
278   * Interrupt Mask Register (INTR_MASK) bit definitions.
279   */
280  enum {
281  	INTR_MASK_PI = (1 << 0),
282  	INTR_MASK_HL0 = (1 << 1),
283  	INTR_MASK_LH0 = (1 << 2),
284  	INTR_MASK_HL1 = (1 << 3),
285  	INTR_MASK_LH1 = (1 << 4),
286  	INTR_MASK_SE = (1 << 5),
287  	INTR_MASK_LSC = (1 << 6),
288  	INTR_MASK_MC = (1 << 7),
289  	INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
290  };
291  
292  /*
293   *  Register (REV_ID) bit definitions.
294   */
295  enum {
296  	REV_ID_MASK = 0x0000000f,
297  	REV_ID_NICROLL_SHIFT = 0,
298  	REV_ID_NICREV_SHIFT = 4,
299  	REV_ID_XGROLL_SHIFT = 8,
300  	REV_ID_XGREV_SHIFT = 12,
301  	REV_ID_CHIPREV_SHIFT = 28,
302  };
303  
304  /*
305   *  Force ECC Error Register (FRC_ECC_ERR) bit definitions.
306   */
307  enum {
308  	FRC_ECC_ERR_VW = (1 << 12),
309  	FRC_ECC_ERR_VB = (1 << 13),
310  	FRC_ECC_ERR_NI = (1 << 14),
311  	FRC_ECC_ERR_NO = (1 << 15),
312  	FRC_ECC_PFE_SHIFT = 16,
313  	FRC_ECC_ERR_DO = (1 << 18),
314  	FRC_ECC_P14 = (1 << 19),
315  };
316  
317  /*
318   *  Error Status Register (ERR_STS) bit definitions.
319   */
320  enum {
321  	ERR_STS_NOF = (1 << 0),
322  	ERR_STS_NIF = (1 << 1),
323  	ERR_STS_DRP = (1 << 2),
324  	ERR_STS_XGP = (1 << 3),
325  	ERR_STS_FOU = (1 << 4),
326  	ERR_STS_FOC = (1 << 5),
327  	ERR_STS_FOF = (1 << 6),
328  	ERR_STS_FIU = (1 << 7),
329  	ERR_STS_FIC = (1 << 8),
330  	ERR_STS_FIF = (1 << 9),
331  	ERR_STS_MOF = (1 << 10),
332  	ERR_STS_TA = (1 << 11),
333  	ERR_STS_MA = (1 << 12),
334  	ERR_STS_MPE = (1 << 13),
335  	ERR_STS_SCE = (1 << 14),
336  	ERR_STS_STE = (1 << 15),
337  	ERR_STS_FOW = (1 << 16),
338  	ERR_STS_UE = (1 << 17),
339  	ERR_STS_MCH = (1 << 26),
340  	ERR_STS_LOC_SHIFT = 27,
341  };
342  
343  /*
344   *  RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
345   */
346  enum {
347  	RAM_DBG_ADDR_FW = (1 << 30),
348  	RAM_DBG_ADDR_FR = (1 << 31),
349  };
350  
351  /*
352   * Semaphore Register (SEM) bit definitions.
353   */
354  enum {
355  	/*
356  	 * Example:
357  	 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
358  	 */
359  	SEM_CLEAR = 0,
360  	SEM_SET = 1,
361  	SEM_FORCE = 3,
362  	SEM_XGMAC0_SHIFT = 0,
363  	SEM_XGMAC1_SHIFT = 2,
364  	SEM_ICB_SHIFT = 4,
365  	SEM_MAC_ADDR_SHIFT = 6,
366  	SEM_FLASH_SHIFT = 8,
367  	SEM_PROBE_SHIFT = 10,
368  	SEM_RT_IDX_SHIFT = 12,
369  	SEM_PROC_REG_SHIFT = 14,
370  	SEM_XGMAC0_MASK = 0x00030000,
371  	SEM_XGMAC1_MASK = 0x000c0000,
372  	SEM_ICB_MASK = 0x00300000,
373  	SEM_MAC_ADDR_MASK = 0x00c00000,
374  	SEM_FLASH_MASK = 0x03000000,
375  	SEM_PROBE_MASK = 0x0c000000,
376  	SEM_RT_IDX_MASK = 0x30000000,
377  	SEM_PROC_REG_MASK = 0xc0000000,
378  };
379  
380  /*
381   *  10G MAC Address  Register (XGMAC_ADDR) bit definitions.
382   */
383  enum {
384  	XGMAC_ADDR_RDY = (1 << 31),
385  	XGMAC_ADDR_R = (1 << 30),
386  	XGMAC_ADDR_XME = (1 << 29),
387  
388  	/* XGMAC control registers */
389  	PAUSE_SRC_LO = 0x00000100,
390  	PAUSE_SRC_HI = 0x00000104,
391  	GLOBAL_CFG = 0x00000108,
392  	GLOBAL_CFG_RESET = (1 << 0),
393  	GLOBAL_CFG_JUMBO = (1 << 6),
394  	GLOBAL_CFG_TX_STAT_EN = (1 << 10),
395  	GLOBAL_CFG_RX_STAT_EN = (1 << 11),
396  	TX_CFG = 0x0000010c,
397  	TX_CFG_RESET = (1 << 0),
398  	TX_CFG_EN = (1 << 1),
399  	TX_CFG_PREAM = (1 << 2),
400  	RX_CFG = 0x00000110,
401  	RX_CFG_RESET = (1 << 0),
402  	RX_CFG_EN = (1 << 1),
403  	RX_CFG_PREAM = (1 << 2),
404  	FLOW_CTL = 0x0000011c,
405  	PAUSE_OPCODE = 0x00000120,
406  	PAUSE_TIMER = 0x00000124,
407  	PAUSE_FRM_DEST_LO = 0x00000128,
408  	PAUSE_FRM_DEST_HI = 0x0000012c,
409  	MAC_TX_PARAMS = 0x00000134,
410  	MAC_TX_PARAMS_JUMBO = (1 << 31),
411  	MAC_TX_PARAMS_SIZE_SHIFT = 16,
412  	MAC_RX_PARAMS = 0x00000138,
413  	MAC_SYS_INT = 0x00000144,
414  	MAC_SYS_INT_MASK = 0x00000148,
415  	MAC_MGMT_INT = 0x0000014c,
416  	MAC_MGMT_IN_MASK = 0x00000150,
417  	EXT_ARB_MODE = 0x000001fc,
418  
419  	/* XGMAC TX statistics  registers */
420  	TX_PKTS = 0x00000200,
421  	TX_BYTES = 0x00000208,
422  	TX_MCAST_PKTS = 0x00000210,
423  	TX_BCAST_PKTS = 0x00000218,
424  	TX_UCAST_PKTS = 0x00000220,
425  	TX_CTL_PKTS = 0x00000228,
426  	TX_PAUSE_PKTS = 0x00000230,
427  	TX_64_PKT = 0x00000238,
428  	TX_65_TO_127_PKT = 0x00000240,
429  	TX_128_TO_255_PKT = 0x00000248,
430  	TX_256_511_PKT = 0x00000250,
431  	TX_512_TO_1023_PKT = 0x00000258,
432  	TX_1024_TO_1518_PKT = 0x00000260,
433  	TX_1519_TO_MAX_PKT = 0x00000268,
434  	TX_UNDERSIZE_PKT = 0x00000270,
435  	TX_OVERSIZE_PKT = 0x00000278,
436  
437  	/* XGMAC statistics control registers */
438  	RX_HALF_FULL_DET = 0x000002a0,
439  	TX_HALF_FULL_DET = 0x000002a4,
440  	RX_OVERFLOW_DET = 0x000002a8,
441  	TX_OVERFLOW_DET = 0x000002ac,
442  	RX_HALF_FULL_MASK = 0x000002b0,
443  	TX_HALF_FULL_MASK = 0x000002b4,
444  	RX_OVERFLOW_MASK = 0x000002b8,
445  	TX_OVERFLOW_MASK = 0x000002bc,
446  	STAT_CNT_CTL = 0x000002c0,
447  	STAT_CNT_CTL_CLEAR_TX = (1 << 0),
448  	STAT_CNT_CTL_CLEAR_RX = (1 << 1),
449  	AUX_RX_HALF_FULL_DET = 0x000002d0,
450  	AUX_TX_HALF_FULL_DET = 0x000002d4,
451  	AUX_RX_OVERFLOW_DET = 0x000002d8,
452  	AUX_TX_OVERFLOW_DET = 0x000002dc,
453  	AUX_RX_HALF_FULL_MASK = 0x000002f0,
454  	AUX_TX_HALF_FULL_MASK = 0x000002f4,
455  	AUX_RX_OVERFLOW_MASK = 0x000002f8,
456  	AUX_TX_OVERFLOW_MASK = 0x000002fc,
457  
458  	/* XGMAC RX statistics  registers */
459  	RX_BYTES = 0x00000300,
460  	RX_BYTES_OK = 0x00000308,
461  	RX_PKTS = 0x00000310,
462  	RX_PKTS_OK = 0x00000318,
463  	RX_BCAST_PKTS = 0x00000320,
464  	RX_MCAST_PKTS = 0x00000328,
465  	RX_UCAST_PKTS = 0x00000330,
466  	RX_UNDERSIZE_PKTS = 0x00000338,
467  	RX_OVERSIZE_PKTS = 0x00000340,
468  	RX_JABBER_PKTS = 0x00000348,
469  	RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
470  	RX_DROP_EVENTS = 0x00000358,
471  	RX_FCERR_PKTS = 0x00000360,
472  	RX_ALIGN_ERR = 0x00000368,
473  	RX_SYMBOL_ERR = 0x00000370,
474  	RX_MAC_ERR = 0x00000378,
475  	RX_CTL_PKTS = 0x00000380,
476  	RX_PAUSE_PKTS = 0x00000388,
477  	RX_64_PKTS = 0x00000390,
478  	RX_65_TO_127_PKTS = 0x00000398,
479  	RX_128_255_PKTS = 0x000003a0,
480  	RX_256_511_PKTS = 0x000003a8,
481  	RX_512_TO_1023_PKTS = 0x000003b0,
482  	RX_1024_TO_1518_PKTS = 0x000003b8,
483  	RX_1519_TO_MAX_PKTS = 0x000003c0,
484  	RX_LEN_ERR_PKTS = 0x000003c8,
485  
486  	/* XGMAC MDIO control registers */
487  	MDIO_TX_DATA = 0x00000400,
488  	MDIO_RX_DATA = 0x00000410,
489  	MDIO_CMD = 0x00000420,
490  	MDIO_PHY_ADDR = 0x00000430,
491  	MDIO_PORT = 0x00000440,
492  	MDIO_STATUS = 0x00000450,
493  
494  	XGMAC_REGISTER_END = 0x00000740,
495  };
496  
497  /*
498   *  Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
499   */
500  enum {
501  	ETS_QUEUE_SHIFT = 29,
502  	ETS_REF = (1 << 26),
503  	ETS_RS = (1 << 27),
504  	ETS_P = (1 << 28),
505  	ETS_FC_COS_SHIFT = 23,
506  };
507  
508  /*
509   *  Flash Address Register (FLASH_ADDR) bit definitions.
510   */
511  enum {
512  	FLASH_ADDR_RDY = (1 << 31),
513  	FLASH_ADDR_R = (1 << 30),
514  	FLASH_ADDR_ERR = (1 << 29),
515  };
516  
517  /*
518   *  Stop CQ Processing Register (CQ_STOP) bit definitions.
519   */
520  enum {
521  	CQ_STOP_QUEUE_MASK = (0x007f0000),
522  	CQ_STOP_TYPE_MASK = (0x03000000),
523  	CQ_STOP_TYPE_START = 0x00000100,
524  	CQ_STOP_TYPE_STOP = 0x00000200,
525  	CQ_STOP_TYPE_READ = 0x00000300,
526  	CQ_STOP_EN = (1 << 15),
527  };
528  
529  /*
530   *  MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
531   */
532  enum {
533  	MAC_ADDR_IDX_SHIFT = 4,
534  	MAC_ADDR_TYPE_SHIFT = 16,
535  	MAC_ADDR_TYPE_COUNT = 10,
536  	MAC_ADDR_TYPE_MASK = 0x000f0000,
537  	MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
538  	MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
539  	MAC_ADDR_TYPE_VLAN = 0x00020000,
540  	MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
541  	MAC_ADDR_TYPE_FC_MAC = 0x00040000,
542  	MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
543  	MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
544  	MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
545  	MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
546  	MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
547  	MAC_ADDR_ADR = (1 << 25),
548  	MAC_ADDR_RS = (1 << 26),
549  	MAC_ADDR_E = (1 << 27),
550  	MAC_ADDR_MR = (1 << 30),
551  	MAC_ADDR_MW = (1 << 31),
552  	MAX_MULTICAST_ENTRIES = 32,
553  
554  	/* Entry count and words per entry
555  	 * for each address type in the filter.
556  	 */
557  	MAC_ADDR_MAX_CAM_ENTRIES = 512,
558  	MAC_ADDR_MAX_CAM_WCOUNT = 3,
559  	MAC_ADDR_MAX_MULTICAST_ENTRIES = 32,
560  	MAC_ADDR_MAX_MULTICAST_WCOUNT = 2,
561  	MAC_ADDR_MAX_VLAN_ENTRIES = 4096,
562  	MAC_ADDR_MAX_VLAN_WCOUNT = 1,
563  	MAC_ADDR_MAX_MCAST_FLTR_ENTRIES = 4096,
564  	MAC_ADDR_MAX_MCAST_FLTR_WCOUNT = 1,
565  	MAC_ADDR_MAX_FC_MAC_ENTRIES = 4,
566  	MAC_ADDR_MAX_FC_MAC_WCOUNT = 2,
567  	MAC_ADDR_MAX_MGMT_MAC_ENTRIES = 8,
568  	MAC_ADDR_MAX_MGMT_MAC_WCOUNT = 2,
569  	MAC_ADDR_MAX_MGMT_VLAN_ENTRIES = 16,
570  	MAC_ADDR_MAX_MGMT_VLAN_WCOUNT = 1,
571  	MAC_ADDR_MAX_MGMT_V4_ENTRIES = 4,
572  	MAC_ADDR_MAX_MGMT_V4_WCOUNT = 1,
573  	MAC_ADDR_MAX_MGMT_V6_ENTRIES = 4,
574  	MAC_ADDR_MAX_MGMT_V6_WCOUNT = 4,
575  	MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES = 4,
576  	MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT = 1,
577  };
578  
579  /*
580   *  MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
581   */
582  enum {
583  	SPLT_HDR_EP = (1 << 31),
584  };
585  
586  /*
587   *  FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
588   */
589  enum {
590  	FC_RCV_CFG_ECT = (1 << 15),
591  	FC_RCV_CFG_DFH = (1 << 20),
592  	FC_RCV_CFG_DVF = (1 << 21),
593  	FC_RCV_CFG_RCE = (1 << 27),
594  	FC_RCV_CFG_RFE = (1 << 28),
595  	FC_RCV_CFG_TEE = (1 << 29),
596  	FC_RCV_CFG_TCE = (1 << 30),
597  	FC_RCV_CFG_TFE = (1 << 31),
598  };
599  
600  /*
601   *  NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
602   */
603  enum {
604  	NIC_RCV_CFG_PPE = (1 << 0),
605  	NIC_RCV_CFG_VLAN_MASK = 0x00060000,
606  	NIC_RCV_CFG_VLAN_ALL = 0x00000000,
607  	NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
608  	NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
609  	NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
610  	NIC_RCV_CFG_RV = (1 << 3),
611  	NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
612  	NIC_RCV_CFG_DFQ_SHIFT = 8,
613  	NIC_RCV_CFG_DFQ = 0,	/* HARDCODE default queue to 0. */
614  };
615  
616  /*
617   *   Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
618   */
619  enum {
620  	MGMT_RCV_CFG_ARP = (1 << 0),
621  	MGMT_RCV_CFG_DHC = (1 << 1),
622  	MGMT_RCV_CFG_DHS = (1 << 2),
623  	MGMT_RCV_CFG_NP = (1 << 3),
624  	MGMT_RCV_CFG_I6N = (1 << 4),
625  	MGMT_RCV_CFG_I6R = (1 << 5),
626  	MGMT_RCV_CFG_DH6 = (1 << 6),
627  	MGMT_RCV_CFG_UD1 = (1 << 7),
628  	MGMT_RCV_CFG_UD0 = (1 << 8),
629  	MGMT_RCV_CFG_BCT = (1 << 9),
630  	MGMT_RCV_CFG_MCT = (1 << 10),
631  	MGMT_RCV_CFG_DM = (1 << 11),
632  	MGMT_RCV_CFG_RM = (1 << 12),
633  	MGMT_RCV_CFG_STL = (1 << 13),
634  	MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
635  	MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
636  	MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
637  	MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
638  	MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
639  };
640  
641  /*
642   *  Routing Index Register (RT_IDX) bit definitions.
643   */
644  enum {
645  	RT_IDX_IDX_SHIFT = 8,
646  	RT_IDX_TYPE_MASK = 0x000f0000,
647  	RT_IDX_TYPE_SHIFT = 16,
648  	RT_IDX_TYPE_RT = 0x00000000,
649  	RT_IDX_TYPE_RT_INV = 0x00010000,
650  	RT_IDX_TYPE_NICQ = 0x00020000,
651  	RT_IDX_TYPE_NICQ_INV = 0x00030000,
652  	RT_IDX_DST_MASK = 0x00700000,
653  	RT_IDX_DST_RSS = 0x00000000,
654  	RT_IDX_DST_CAM_Q = 0x00100000,
655  	RT_IDX_DST_COS_Q = 0x00200000,
656  	RT_IDX_DST_DFLT_Q = 0x00300000,
657  	RT_IDX_DST_DEST_Q = 0x00400000,
658  	RT_IDX_RS = (1 << 26),
659  	RT_IDX_E = (1 << 27),
660  	RT_IDX_MR = (1 << 30),
661  	RT_IDX_MW = (1 << 31),
662  
663  	/* Nic Queue format - type 2 bits */
664  	RT_IDX_BCAST = (1 << 0),
665  	RT_IDX_MCAST = (1 << 1),
666  	RT_IDX_MCAST_MATCH = (1 << 2),
667  	RT_IDX_MCAST_REG_MATCH = (1 << 3),
668  	RT_IDX_MCAST_HASH_MATCH = (1 << 4),
669  	RT_IDX_FC_MACH = (1 << 5),
670  	RT_IDX_ETH_FCOE = (1 << 6),
671  	RT_IDX_CAM_HIT = (1 << 7),
672  	RT_IDX_CAM_BIT0 = (1 << 8),
673  	RT_IDX_CAM_BIT1 = (1 << 9),
674  	RT_IDX_VLAN_TAG = (1 << 10),
675  	RT_IDX_VLAN_MATCH = (1 << 11),
676  	RT_IDX_VLAN_FILTER = (1 << 12),
677  	RT_IDX_ETH_SKIP1 = (1 << 13),
678  	RT_IDX_ETH_SKIP2 = (1 << 14),
679  	RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
680  	RT_IDX_802_3 = (1 << 16),
681  	RT_IDX_LLDP = (1 << 17),
682  	RT_IDX_UNUSED018 = (1 << 18),
683  	RT_IDX_UNUSED019 = (1 << 19),
684  	RT_IDX_UNUSED20 = (1 << 20),
685  	RT_IDX_UNUSED21 = (1 << 21),
686  	RT_IDX_ERR = (1 << 22),
687  	RT_IDX_VALID = (1 << 23),
688  	RT_IDX_TU_CSUM_ERR = (1 << 24),
689  	RT_IDX_IP_CSUM_ERR = (1 << 25),
690  	RT_IDX_MAC_ERR = (1 << 26),
691  	RT_IDX_RSS_TCP6 = (1 << 27),
692  	RT_IDX_RSS_TCP4 = (1 << 28),
693  	RT_IDX_RSS_IPV6 = (1 << 29),
694  	RT_IDX_RSS_IPV4 = (1 << 30),
695  	RT_IDX_RSS_MATCH = (1 << 31),
696  
697  	/* Hierarchy for the NIC Queue Mask */
698  	RT_IDX_ALL_ERR_SLOT = 0,
699  	RT_IDX_MAC_ERR_SLOT = 0,
700  	RT_IDX_IP_CSUM_ERR_SLOT = 1,
701  	RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
702  	RT_IDX_BCAST_SLOT = 3,
703  	RT_IDX_MCAST_MATCH_SLOT = 4,
704  	RT_IDX_ALLMULTI_SLOT = 5,
705  	RT_IDX_UNUSED6_SLOT = 6,
706  	RT_IDX_UNUSED7_SLOT = 7,
707  	RT_IDX_RSS_MATCH_SLOT = 8,
708  	RT_IDX_RSS_IPV4_SLOT = 8,
709  	RT_IDX_RSS_IPV6_SLOT = 9,
710  	RT_IDX_RSS_TCP4_SLOT = 10,
711  	RT_IDX_RSS_TCP6_SLOT = 11,
712  	RT_IDX_CAM_HIT_SLOT = 12,
713  	RT_IDX_UNUSED013 = 13,
714  	RT_IDX_UNUSED014 = 14,
715  	RT_IDX_PROMISCUOUS_SLOT = 15,
716  	RT_IDX_MAX_RT_SLOTS = 8,
717  	RT_IDX_MAX_NIC_SLOTS = 16,
718  };
719  
720  /*
721   * Serdes Address Register (XG_SERDES_ADDR) bit definitions.
722   */
723  enum {
724  	XG_SERDES_ADDR_RDY = (1 << 31),
725  	XG_SERDES_ADDR_R = (1 << 30),
726  
727  	XG_SERDES_ADDR_STS = 0x00001E06,
728  	XG_SERDES_ADDR_XFI1_PWR_UP = 0x00000005,
729  	XG_SERDES_ADDR_XFI2_PWR_UP = 0x0000000a,
730  	XG_SERDES_ADDR_XAUI_PWR_DOWN = 0x00000001,
731  
732  	/* Serdes coredump definitions. */
733  	XG_SERDES_XAUI_AN_START = 0x00000000,
734  	XG_SERDES_XAUI_AN_END = 0x00000034,
735  	XG_SERDES_XAUI_HSS_PCS_START = 0x00000800,
736  	XG_SERDES_XAUI_HSS_PCS_END = 0x0000880,
737  	XG_SERDES_XFI_AN_START = 0x00001000,
738  	XG_SERDES_XFI_AN_END = 0x00001034,
739  	XG_SERDES_XFI_TRAIN_START = 0x10001050,
740  	XG_SERDES_XFI_TRAIN_END = 0x1000107C,
741  	XG_SERDES_XFI_HSS_PCS_START = 0x00001800,
742  	XG_SERDES_XFI_HSS_PCS_END = 0x00001838,
743  	XG_SERDES_XFI_HSS_TX_START = 0x00001c00,
744  	XG_SERDES_XFI_HSS_TX_END = 0x00001c1f,
745  	XG_SERDES_XFI_HSS_RX_START = 0x00001c40,
746  	XG_SERDES_XFI_HSS_RX_END = 0x00001c5f,
747  	XG_SERDES_XFI_HSS_PLL_START = 0x00001e00,
748  	XG_SERDES_XFI_HSS_PLL_END = 0x00001e1f,
749  };
750  
751  /*
752   *  NIC Probe Mux Address Register (PRB_MX_ADDR) bit definitions.
753   */
754  enum {
755  	PRB_MX_ADDR_ARE = (1 << 16),
756  	PRB_MX_ADDR_UP = (1 << 15),
757  	PRB_MX_ADDR_SWP = (1 << 14),
758  
759  	/* Module select values. */
760  	PRB_MX_ADDR_MAX_MODS = 21,
761  	PRB_MX_ADDR_MOD_SEL_SHIFT = 9,
762  	PRB_MX_ADDR_MOD_SEL_TBD = 0,
763  	PRB_MX_ADDR_MOD_SEL_IDE1 = 1,
764  	PRB_MX_ADDR_MOD_SEL_IDE2 = 2,
765  	PRB_MX_ADDR_MOD_SEL_FRB = 3,
766  	PRB_MX_ADDR_MOD_SEL_ODE1 = 4,
767  	PRB_MX_ADDR_MOD_SEL_ODE2 = 5,
768  	PRB_MX_ADDR_MOD_SEL_DA1 = 6,
769  	PRB_MX_ADDR_MOD_SEL_DA2 = 7,
770  	PRB_MX_ADDR_MOD_SEL_IMP1 = 8,
771  	PRB_MX_ADDR_MOD_SEL_IMP2 = 9,
772  	PRB_MX_ADDR_MOD_SEL_OMP1 = 10,
773  	PRB_MX_ADDR_MOD_SEL_OMP2 = 11,
774  	PRB_MX_ADDR_MOD_SEL_ORS1 = 12,
775  	PRB_MX_ADDR_MOD_SEL_ORS2 = 13,
776  	PRB_MX_ADDR_MOD_SEL_REG = 14,
777  	PRB_MX_ADDR_MOD_SEL_MAC1 = 16,
778  	PRB_MX_ADDR_MOD_SEL_MAC2 = 17,
779  	PRB_MX_ADDR_MOD_SEL_VQM1 = 18,
780  	PRB_MX_ADDR_MOD_SEL_VQM2 = 19,
781  	PRB_MX_ADDR_MOD_SEL_MOP = 20,
782  	/* Bit fields indicating which modules
783  	 * are valid for each clock domain.
784  	 */
785  	PRB_MX_ADDR_VALID_SYS_MOD = 0x000f7ff7,
786  	PRB_MX_ADDR_VALID_PCI_MOD = 0x000040c1,
787  	PRB_MX_ADDR_VALID_XGM_MOD = 0x00037309,
788  	PRB_MX_ADDR_VALID_FC_MOD = 0x00003001,
789  	PRB_MX_ADDR_VALID_TOTAL = 34,
790  
791  	/* Clock domain values. */
792  	PRB_MX_ADDR_CLOCK_SHIFT = 6,
793  	PRB_MX_ADDR_SYS_CLOCK = 0,
794  	PRB_MX_ADDR_PCI_CLOCK = 2,
795  	PRB_MX_ADDR_FC_CLOCK = 5,
796  	PRB_MX_ADDR_XGM_CLOCK = 6,
797  
798  	PRB_MX_ADDR_MAX_MUX = 64,
799  };
800  
801  /*
802   * Control Register Set Map
803   */
804  enum {
805  	PROC_ADDR = 0,		/* Use semaphore */
806  	PROC_DATA = 0x04,	/* Use semaphore */
807  	SYS = 0x08,
808  	RST_FO = 0x0c,
809  	FSC = 0x10,
810  	CSR = 0x14,
811  	LED = 0x18,
812  	ICB_RID = 0x1c,		/* Use semaphore */
813  	ICB_L = 0x20,		/* Use semaphore */
814  	ICB_H = 0x24,		/* Use semaphore */
815  	CFG = 0x28,
816  	BIOS_ADDR = 0x2c,
817  	STS = 0x30,
818  	INTR_EN = 0x34,
819  	INTR_MASK = 0x38,
820  	ISR1 = 0x3c,
821  	ISR2 = 0x40,
822  	ISR3 = 0x44,
823  	ISR4 = 0x48,
824  	REV_ID = 0x4c,
825  	FRC_ECC_ERR = 0x50,
826  	ERR_STS = 0x54,
827  	RAM_DBG_ADDR = 0x58,
828  	RAM_DBG_DATA = 0x5c,
829  	ECC_ERR_CNT = 0x60,
830  	SEM = 0x64,
831  	GPIO_1 = 0x68,		/* Use semaphore */
832  	GPIO_2 = 0x6c,		/* Use semaphore */
833  	GPIO_3 = 0x70,		/* Use semaphore */
834  	RSVD2 = 0x74,
835  	XGMAC_ADDR = 0x78,	/* Use semaphore */
836  	XGMAC_DATA = 0x7c,	/* Use semaphore */
837  	NIC_ETS = 0x80,
838  	CNA_ETS = 0x84,
839  	FLASH_ADDR = 0x88,	/* Use semaphore */
840  	FLASH_DATA = 0x8c,	/* Use semaphore */
841  	CQ_STOP = 0x90,
842  	PAGE_TBL_RID = 0x94,
843  	WQ_PAGE_TBL_LO = 0x98,
844  	WQ_PAGE_TBL_HI = 0x9c,
845  	CQ_PAGE_TBL_LO = 0xa0,
846  	CQ_PAGE_TBL_HI = 0xa4,
847  	MAC_ADDR_IDX = 0xa8,	/* Use semaphore */
848  	MAC_ADDR_DATA = 0xac,	/* Use semaphore */
849  	COS_DFLT_CQ1 = 0xb0,
850  	COS_DFLT_CQ2 = 0xb4,
851  	ETYPE_SKIP1 = 0xb8,
852  	ETYPE_SKIP2 = 0xbc,
853  	SPLT_HDR = 0xc0,
854  	FC_PAUSE_THRES = 0xc4,
855  	NIC_PAUSE_THRES = 0xc8,
856  	FC_ETHERTYPE = 0xcc,
857  	FC_RCV_CFG = 0xd0,
858  	NIC_RCV_CFG = 0xd4,
859  	FC_COS_TAGS = 0xd8,
860  	NIC_COS_TAGS = 0xdc,
861  	MGMT_RCV_CFG = 0xe0,
862  	RT_IDX = 0xe4,
863  	RT_DATA = 0xe8,
864  	RSVD7 = 0xec,
865  	XG_SERDES_ADDR = 0xf0,
866  	XG_SERDES_DATA = 0xf4,
867  	PRB_MX_ADDR = 0xf8,	/* Use semaphore */
868  	PRB_MX_DATA = 0xfc,	/* Use semaphore */
869  };
870  
871  #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
872  #define SMALL_BUFFER_SIZE 256
873  #define SMALL_BUF_MAP_SIZE SMALL_BUFFER_SIZE
874  #define SPLT_SETTING  FSC_DBRST_1024
875  #define SPLT_LEN 0
876  #define QLGE_SB_PAD 0
877  #else
878  #define SMALL_BUFFER_SIZE 512
879  #define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)
880  #define SPLT_SETTING  FSC_SH
881  #define SPLT_LEN (SPLT_HDR_EP | \
882  	min(SMALL_BUF_MAP_SIZE, 1023))
883  #define QLGE_SB_PAD 32
884  #endif
885  
886  /*
887   * CAM output format.
888   */
889  enum {
890  	CAM_OUT_ROUTE_FC = 0,
891  	CAM_OUT_ROUTE_NIC = 1,
892  	CAM_OUT_FUNC_SHIFT = 2,
893  	CAM_OUT_RV = (1 << 4),
894  	CAM_OUT_SH = (1 << 15),
895  	CAM_OUT_CQ_ID_SHIFT = 5,
896  };
897  
898  /*
899   * Mailbox  definitions
900   */
901  enum {
902  	/* Asynchronous Event Notifications */
903  	AEN_SYS_ERR = 0x00008002,
904  	AEN_LINK_UP = 0x00008011,
905  	AEN_LINK_DOWN = 0x00008012,
906  	AEN_IDC_CMPLT = 0x00008100,
907  	AEN_IDC_REQ = 0x00008101,
908  	AEN_IDC_EXT = 0x00008102,
909  	AEN_DCBX_CHG = 0x00008110,
910  	AEN_AEN_LOST = 0x00008120,
911  	AEN_AEN_SFP_IN = 0x00008130,
912  	AEN_AEN_SFP_OUT = 0x00008131,
913  	AEN_FW_INIT_DONE = 0x00008400,
914  	AEN_FW_INIT_FAIL = 0x00008401,
915  
916  	/* Mailbox Command Opcodes. */
917  	MB_CMD_NOP = 0x00000000,
918  	MB_CMD_EX_FW = 0x00000002,
919  	MB_CMD_MB_TEST = 0x00000006,
920  	MB_CMD_CSUM_TEST = 0x00000007,	/* Verify Checksum */
921  	MB_CMD_ABOUT_FW = 0x00000008,
922  	MB_CMD_COPY_RISC_RAM = 0x0000000a,
923  	MB_CMD_LOAD_RISC_RAM = 0x0000000b,
924  	MB_CMD_DUMP_RISC_RAM = 0x0000000c,
925  	MB_CMD_WRITE_RAM = 0x0000000d,
926  	MB_CMD_INIT_RISC_RAM = 0x0000000e,
927  	MB_CMD_READ_RAM = 0x0000000f,
928  	MB_CMD_STOP_FW = 0x00000014,
929  	MB_CMD_MAKE_SYS_ERR = 0x0000002a,
930  	MB_CMD_WRITE_SFP = 0x00000030,
931  	MB_CMD_READ_SFP = 0x00000031,
932  	MB_CMD_INIT_FW = 0x00000060,
933  	MB_CMD_GET_IFCB = 0x00000061,
934  	MB_CMD_GET_FW_STATE = 0x00000069,
935  	MB_CMD_IDC_REQ = 0x00000100,	/* Inter-Driver Communication */
936  	MB_CMD_IDC_ACK = 0x00000101,	/* Inter-Driver Communication */
937  	MB_CMD_SET_WOL_MODE = 0x00000110,	/* Wake On Lan */
938  	MB_WOL_DISABLE = 0,
939  	MB_WOL_MAGIC_PKT = (1 << 1),
940  	MB_WOL_FLTR = (1 << 2),
941  	MB_WOL_UCAST = (1 << 3),
942  	MB_WOL_MCAST = (1 << 4),
943  	MB_WOL_BCAST = (1 << 5),
944  	MB_WOL_LINK_UP = (1 << 6),
945  	MB_WOL_LINK_DOWN = (1 << 7),
946  	MB_WOL_MODE_ON = (1 << 16),		/* Wake on Lan Mode on */
947  	MB_CMD_SET_WOL_FLTR = 0x00000111,	/* Wake On Lan Filter */
948  	MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
949  	MB_CMD_SET_WOL_MAGIC = 0x00000113,	/* Wake On Lan Magic Packet */
950  	MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
951  	MB_CMD_SET_WOL_IMMED = 0x00000115,
952  	MB_CMD_PORT_RESET = 0x00000120,
953  	MB_CMD_SET_PORT_CFG = 0x00000122,
954  	MB_CMD_GET_PORT_CFG = 0x00000123,
955  	MB_CMD_GET_LINK_STS = 0x00000124,
956  	MB_CMD_SET_LED_CFG = 0x00000125, /* Set LED Configuration Register */
957  		QL_LED_BLINK = 0x03e803e8,
958  	MB_CMD_GET_LED_CFG = 0x00000126, /* Get LED Configuration Register */
959  	MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, /* Set Mgmnt Traffic Control */
960  	MB_SET_MPI_TFK_STOP = (1 << 0),
961  	MB_SET_MPI_TFK_RESUME = (1 << 1),
962  	MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, /* Get Mgmnt Traffic Control */
963  	MB_GET_MPI_TFK_STOPPED = (1 << 0),
964  	MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
965  	/* Sub-commands for IDC request.
966  	 * This describes the reason for the
967  	 * IDC request.
968  	 */
969  	MB_CMD_IOP_NONE = 0x0000,
970  	MB_CMD_IOP_PREP_UPDATE_MPI	= 0x0001,
971  	MB_CMD_IOP_COMP_UPDATE_MPI	= 0x0002,
972  	MB_CMD_IOP_PREP_LINK_DOWN	= 0x0010,
973  	MB_CMD_IOP_DVR_START	 = 0x0100,
974  	MB_CMD_IOP_FLASH_ACC	 = 0x0101,
975  	MB_CMD_IOP_RESTART_MPI	= 0x0102,
976  	MB_CMD_IOP_CORE_DUMP_MPI	= 0x0103,
977  
978  	/* Mailbox Command Status. */
979  	MB_CMD_STS_GOOD = 0x00004000,	/* Success. */
980  	MB_CMD_STS_INTRMDT = 0x00001000,	/* Intermediate Complete. */
981  	MB_CMD_STS_INVLD_CMD = 0x00004001,	/* Invalid. */
982  	MB_CMD_STS_XFC_ERR = 0x00004002,	/* Interface Error. */
983  	MB_CMD_STS_CSUM_ERR = 0x00004003,	/* Csum Error. */
984  	MB_CMD_STS_ERR = 0x00004005,	/* System Error. */
985  	MB_CMD_STS_PARAM_ERR = 0x00004006,	/* Parameter Error. */
986  };
987  
988  struct mbox_params {
989  	u32 mbox_in[MAILBOX_COUNT];
990  	u32 mbox_out[MAILBOX_COUNT];
991  	int in_count;
992  	int out_count;
993  };
994  
995  struct flash_params_8012 {
996  	u8 dev_id_str[4];
997  	__le16 size;
998  	__le16 csum;
999  	__le16 ver;
1000  	__le16 sub_dev_id;
1001  	u8 mac_addr[6];
1002  	__le16 res;
1003  };
1004  
1005  /* 8000 device's flash is a different structure
1006   * at a different offset in flash.
1007   */
1008  #define FUNC0_FLASH_OFFSET 0x140200
1009  #define FUNC1_FLASH_OFFSET 0x140600
1010  
1011  /* Flash related data structures. */
1012  struct flash_params_8000 {
1013  	u8 dev_id_str[4];	/* "8000" */
1014  	__le16 ver;
1015  	__le16 size;
1016  	__le16 csum;
1017  	__le16 reserved0;
1018  	__le16 total_size;
1019  	__le16 entry_count;
1020  	u8 data_type0;
1021  	u8 data_size0;
1022  	u8 mac_addr[6];
1023  	u8 data_type1;
1024  	u8 data_size1;
1025  	u8 mac_addr1[6];
1026  	u8 data_type2;
1027  	u8 data_size2;
1028  	__le16 vlan_id;
1029  	u8 data_type3;
1030  	u8 data_size3;
1031  	__le16 last;
1032  	u8 reserved1[464];
1033  	__le16	subsys_ven_id;
1034  	__le16	subsys_dev_id;
1035  	u8 reserved2[4];
1036  };
1037  
1038  union flash_params {
1039  	struct flash_params_8012 flash_params_8012;
1040  	struct flash_params_8000 flash_params_8000;
1041  };
1042  
1043  /*
1044   * doorbell space for the rx ring context
1045   */
1046  struct rx_doorbell_context {
1047  	u32 cnsmr_idx;		/* 0x00 */
1048  	u32 valid;		/* 0x04 */
1049  	u32 reserved[4];	/* 0x08-0x14 */
1050  	u32 lbq_prod_idx;	/* 0x18 */
1051  	u32 sbq_prod_idx;	/* 0x1c */
1052  };
1053  
1054  /*
1055   * doorbell space for the tx ring context
1056   */
1057  struct tx_doorbell_context {
1058  	u32 prod_idx;		/* 0x00 */
1059  	u32 valid;		/* 0x04 */
1060  	u32 reserved[4];	/* 0x08-0x14 */
1061  	u32 lbq_prod_idx;	/* 0x18 */
1062  	u32 sbq_prod_idx;	/* 0x1c */
1063  };
1064  
1065  /* DATA STRUCTURES SHARED WITH HARDWARE. */
1066  struct tx_buf_desc {
1067  	__le64 addr;
1068  	__le32 len;
1069  #define TX_DESC_LEN_MASK	0x000fffff
1070  #define TX_DESC_C	0x40000000
1071  #define TX_DESC_E	0x80000000
1072  } __packed;
1073  
1074  /*
1075   * IOCB Definitions...
1076   */
1077  
1078  #define OPCODE_OB_MAC_IOCB		0x01
1079  #define OPCODE_OB_MAC_TSO_IOCB		0x02
1080  #define OPCODE_IB_MAC_IOCB		0x20
1081  #define OPCODE_IB_MPI_IOCB		0x21
1082  #define OPCODE_IB_AE_IOCB		0x3f
1083  
1084  struct qlge_ob_mac_iocb_req {
1085  	u8 opcode;
1086  	u8 flags1;
1087  #define OB_MAC_IOCB_REQ_OI	0x01
1088  #define OB_MAC_IOCB_REQ_I	0x02
1089  #define OB_MAC_IOCB_REQ_D	0x08
1090  #define OB_MAC_IOCB_REQ_F	0x10
1091  	u8 flags2;
1092  	u8 flags3;
1093  #define OB_MAC_IOCB_DFP	0x02
1094  #define OB_MAC_IOCB_V	0x04
1095  	__le32 reserved1[2];
1096  	__le16 frame_len;
1097  #define OB_MAC_IOCB_LEN_MASK 0x3ffff
1098  	__le16 reserved2;
1099  	u32 tid;
1100  	u32 txq_idx;
1101  	__le32 reserved3;
1102  	__le16 vlan_tci;
1103  	__le16 reserved4;
1104  	struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1105  } __packed;
1106  
1107  struct qlge_ob_mac_iocb_rsp {
1108  	u8 opcode;		/* */
1109  	u8 flags1;		/* */
1110  #define OB_MAC_IOCB_RSP_OI	0x01	/* */
1111  #define OB_MAC_IOCB_RSP_I	0x02	/* */
1112  #define OB_MAC_IOCB_RSP_E	0x08	/* */
1113  #define OB_MAC_IOCB_RSP_S	0x10	/* too Short */
1114  #define OB_MAC_IOCB_RSP_L	0x20	/* too Large */
1115  #define OB_MAC_IOCB_RSP_P	0x40	/* Padded */
1116  	u8 flags2;		/* */
1117  	u8 flags3;		/* */
1118  #define OB_MAC_IOCB_RSP_B	0x80	/* */
1119  	u32 tid;
1120  	u32 txq_idx;
1121  	__le32 reserved[13];
1122  } __packed;
1123  
1124  struct qlge_ob_mac_tso_iocb_req {
1125  	u8 opcode;
1126  	u8 flags1;
1127  #define OB_MAC_TSO_IOCB_OI	0x01
1128  #define OB_MAC_TSO_IOCB_I	0x02
1129  #define OB_MAC_TSO_IOCB_D	0x08
1130  #define OB_MAC_TSO_IOCB_IP4	0x40
1131  #define OB_MAC_TSO_IOCB_IP6	0x80
1132  	u8 flags2;
1133  #define OB_MAC_TSO_IOCB_LSO	0x20
1134  #define OB_MAC_TSO_IOCB_UC	0x40
1135  #define OB_MAC_TSO_IOCB_TC	0x80
1136  	u8 flags3;
1137  #define OB_MAC_TSO_IOCB_IC	0x01
1138  #define OB_MAC_TSO_IOCB_DFP	0x02
1139  #define OB_MAC_TSO_IOCB_V	0x04
1140  	__le32 reserved1[2];
1141  	__le32 frame_len;
1142  	u32 tid;
1143  	u32 txq_idx;
1144  	__le16 total_hdrs_len;
1145  	__le16 net_trans_offset;
1146  #define OB_MAC_TRANSPORT_HDR_SHIFT 6
1147  	__le16 vlan_tci;
1148  	__le16 mss;
1149  	struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1150  } __packed;
1151  
1152  struct qlge_ob_mac_tso_iocb_rsp {
1153  	u8 opcode;
1154  	u8 flags1;
1155  #define OB_MAC_TSO_IOCB_RSP_OI	0x01
1156  #define OB_MAC_TSO_IOCB_RSP_I	0x02
1157  #define OB_MAC_TSO_IOCB_RSP_E	0x08
1158  #define OB_MAC_TSO_IOCB_RSP_S	0x10
1159  #define OB_MAC_TSO_IOCB_RSP_L	0x20
1160  #define OB_MAC_TSO_IOCB_RSP_P	0x40
1161  	u8 flags2;		/* */
1162  	u8 flags3;		/* */
1163  #define OB_MAC_TSO_IOCB_RSP_B	0x8000
1164  	u32 tid;
1165  	u32 txq_idx;
1166  	__le32 reserved2[13];
1167  } __packed;
1168  
1169  struct qlge_ib_mac_iocb_rsp {
1170  	u8 opcode;		/* 0x20 */
1171  	u8 flags1;
1172  #define IB_MAC_IOCB_RSP_OI	0x01	/* Override intr delay */
1173  #define IB_MAC_IOCB_RSP_I	0x02	/* Disable Intr Generation */
1174  #define IB_MAC_CSUM_ERR_MASK	0x1c	/* A mask to use for csum errs */
1175  #define IB_MAC_IOCB_RSP_TE	0x04	/* Checksum error */
1176  #define IB_MAC_IOCB_RSP_NU	0x08	/* No checksum rcvd */
1177  #define IB_MAC_IOCB_RSP_IE	0x10	/* IPv4 checksum error */
1178  #define IB_MAC_IOCB_RSP_M_MASK	0x60	/* Multicast info */
1179  #define IB_MAC_IOCB_RSP_M_NONE	0x00	/* Not mcast frame */
1180  #define IB_MAC_IOCB_RSP_M_HASH	0x20	/* HASH mcast frame */
1181  #define IB_MAC_IOCB_RSP_M_REG	0x40	/* Registered mcast frame */
1182  #define IB_MAC_IOCB_RSP_M_PROM	0x60	/* Promiscuous mcast frame */
1183  #define IB_MAC_IOCB_RSP_B	0x80	/* Broadcast frame */
1184  	u8 flags2;
1185  #define IB_MAC_IOCB_RSP_P	0x01	/* Promiscuous frame */
1186  #define IB_MAC_IOCB_RSP_V	0x02	/* Vlan tag present */
1187  #define IB_MAC_IOCB_RSP_ERR_MASK	0x1c	/*  */
1188  #define IB_MAC_IOCB_RSP_ERR_CODE_ERR	0x04
1189  #define IB_MAC_IOCB_RSP_ERR_OVERSIZE	0x08
1190  #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE	0x10
1191  #define IB_MAC_IOCB_RSP_ERR_PREAMBLE	0x14
1192  #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN	0x18
1193  #define IB_MAC_IOCB_RSP_ERR_CRC		0x1c
1194  #define IB_MAC_IOCB_RSP_U	0x20	/* UDP packet */
1195  #define IB_MAC_IOCB_RSP_T	0x40	/* TCP packet */
1196  #define IB_MAC_IOCB_RSP_FO	0x80	/* Failover port */
1197  	u8 flags3;
1198  #define IB_MAC_IOCB_RSP_RSS_MASK	0x07	/* RSS mask */
1199  #define IB_MAC_IOCB_RSP_M_NONE		0x00	/* No RSS match */
1200  #define IB_MAC_IOCB_RSP_M_IPV4		0x04	/* IPv4 RSS match */
1201  #define IB_MAC_IOCB_RSP_M_IPV6		0x02	/* IPv6 RSS match */
1202  #define IB_MAC_IOCB_RSP_M_TCP_V4	0x05	/* TCP with IPv4 */
1203  #define IB_MAC_IOCB_RSP_M_TCP_V6	0x03	/* TCP with IPv6 */
1204  #define IB_MAC_IOCB_RSP_V4		0x08	/* IPV4 */
1205  #define IB_MAC_IOCB_RSP_V6		0x10	/* IPV6 */
1206  #define IB_MAC_IOCB_RSP_IH		0x20	/* Split after IP header */
1207  #define IB_MAC_IOCB_RSP_DS		0x40	/* data is in small buffer */
1208  #define IB_MAC_IOCB_RSP_DL		0x80	/* data is in large buffer */
1209  	__le32 data_len;	/* */
1210  	__le64 data_addr;	/* */
1211  	__le32 rss;		/* */
1212  	__le16 vlan_id;		/* 12 bits */
1213  #define IB_MAC_IOCB_RSP_C	0x1000	/* VLAN CFI bit */
1214  #define IB_MAC_IOCB_RSP_COS_SHIFT	12	/* class of service value */
1215  #define IB_MAC_IOCB_RSP_VLAN_MASK	0x0ffff
1216  
1217  	__le16 reserved1;
1218  	__le32 reserved2[6];
1219  	u8 reserved3[3];
1220  	u8 flags4;
1221  #define IB_MAC_IOCB_RSP_HV	0x20
1222  #define IB_MAC_IOCB_RSP_HS	0x40
1223  #define IB_MAC_IOCB_RSP_HL	0x80
1224  	__le32 hdr_len;		/* */
1225  	__le64 hdr_addr;	/* */
1226  } __packed;
1227  
1228  struct qlge_ib_ae_iocb_rsp {
1229  	u8 opcode;
1230  	u8 flags1;
1231  #define IB_AE_IOCB_RSP_OI		0x01
1232  #define IB_AE_IOCB_RSP_I		0x02
1233  	u8 event;
1234  #define LINK_UP_EVENT			0x00
1235  #define LINK_DOWN_EVENT			0x01
1236  #define CAM_LOOKUP_ERR_EVENT		0x06
1237  #define SOFT_ECC_ERROR_EVENT		0x07
1238  #define MGMT_ERR_EVENT			0x08
1239  #define TEN_GIG_MAC_EVENT		0x09
1240  #define GPI0_H2L_EVENT			0x10
1241  #define GPI0_L2H_EVENT			0x20
1242  #define GPI1_H2L_EVENT			0x11
1243  #define GPI1_L2H_EVENT			0x21
1244  #define PCI_ERR_ANON_BUF_RD		0x40
1245  	u8 q_id;
1246  	__le32 reserved[15];
1247  } __packed;
1248  
1249  /*
1250   * These three structures are for generic
1251   * handling of ib and ob iocbs.
1252   */
1253  struct qlge_net_rsp_iocb {
1254  	u8 opcode;
1255  	u8 flags0;
1256  	__le16 length;
1257  	__le32 tid;
1258  	__le32 reserved[14];
1259  } __packed;
1260  
1261  struct qlge_net_req_iocb {
1262  	u8 opcode;
1263  	u8 flags0;
1264  	__le16 flags1;
1265  	__le32 tid;
1266  	__le32 reserved1[30];
1267  } __packed;
1268  
1269  /*
1270   * tx ring initialization control block for chip.
1271   * It is defined as:
1272   * "Work Queue Initialization Control Block"
1273   */
1274  struct wqicb {
1275  	__le16 len;
1276  #define Q_LEN_V		(1 << 4)
1277  #define Q_LEN_CPP_CONT	0x0000
1278  #define Q_LEN_CPP_16	0x0001
1279  #define Q_LEN_CPP_32	0x0002
1280  #define Q_LEN_CPP_64	0x0003
1281  #define Q_LEN_CPP_512	0x0006
1282  	__le16 flags;
1283  #define Q_PRI_SHIFT	1
1284  #define Q_FLAGS_LC	0x1000
1285  #define Q_FLAGS_LB	0x2000
1286  #define Q_FLAGS_LI	0x4000
1287  #define Q_FLAGS_LO	0x8000
1288  	__le16 cq_id_rss;
1289  #define Q_CQ_ID_RSS_RV 0x8000
1290  	__le16 rid;
1291  	__le64 addr;
1292  	__le64 cnsmr_idx_addr;
1293  } __packed;
1294  
1295  /*
1296   * rx ring initialization control block for chip.
1297   * It is defined as:
1298   * "Completion Queue Initialization Control Block"
1299   */
1300  struct cqicb {
1301  	u8 msix_vect;
1302  	u8 reserved1;
1303  	u8 reserved2;
1304  	u8 flags;
1305  #define FLAGS_LV	0x08
1306  #define FLAGS_LS	0x10
1307  #define FLAGS_LL	0x20
1308  #define FLAGS_LI	0x40
1309  #define FLAGS_LC	0x80
1310  	__le16 len;
1311  #define LEN_V		(1 << 4)
1312  #define LEN_CPP_CONT	0x0000
1313  #define LEN_CPP_32	0x0001
1314  #define LEN_CPP_64	0x0002
1315  #define LEN_CPP_128	0x0003
1316  	__le16 rid;
1317  	__le64 addr;
1318  	__le64 prod_idx_addr;
1319  	__le16 pkt_delay;
1320  	__le16 irq_delay;
1321  	__le64 lbq_addr;
1322  	__le16 lbq_buf_size;
1323  	__le16 lbq_len;		/* entry count */
1324  	__le64 sbq_addr;
1325  	__le16 sbq_buf_size;
1326  	__le16 sbq_len;		/* entry count */
1327  } __packed;
1328  
1329  struct ricb {
1330  	u8 base_cq;
1331  #define RSS_L4K 0x80
1332  	u8 flags;
1333  #define RSS_L6K 0x01
1334  #define RSS_LI  0x02
1335  #define RSS_LB  0x04
1336  #define RSS_LM  0x08
1337  #define RSS_RI4 0x10
1338  #define RSS_RT4 0x20
1339  #define RSS_RI6 0x40
1340  #define RSS_RT6 0x80
1341  	__le16 mask;
1342  	u8 hash_cq_id[1024];
1343  	__le32 ipv6_hash_key[10];
1344  	__le32 ipv4_hash_key[4];
1345  } __packed;
1346  
1347  /* SOFTWARE/DRIVER DATA STRUCTURES. */
1348  
1349  struct qlge_oal {
1350  	struct tx_buf_desc oal[TX_DESC_PER_OAL];
1351  };
1352  
1353  struct map_list {
1354  	DEFINE_DMA_UNMAP_ADDR(mapaddr);
1355  	DEFINE_DMA_UNMAP_LEN(maplen);
1356  };
1357  
1358  struct tx_ring_desc {
1359  	struct sk_buff *skb;
1360  	struct qlge_ob_mac_iocb_req *queue_entry;
1361  	u32 index;
1362  	struct qlge_oal oal;
1363  	struct map_list map[MAX_SKB_FRAGS + 2];
1364  	int map_cnt;
1365  	struct tx_ring_desc *next;
1366  };
1367  
1368  #define QL_TXQ_IDX(qdev, skb) (smp_processor_id() % (qdev->tx_ring_count))
1369  
1370  struct tx_ring {
1371  	/*
1372  	 * queue info.
1373  	 */
1374  	struct wqicb wqicb;	/* structure used to inform chip of new queue */
1375  	void *wq_base;		/* pci_alloc:virtual addr for tx */
1376  	dma_addr_t wq_base_dma;	/* pci_alloc:dma addr for tx */
1377  	__le32 *cnsmr_idx_sh_reg;	/* shadow copy of consumer idx */
1378  	dma_addr_t cnsmr_idx_sh_reg_dma;	/* dma-shadow copy of consumer */
1379  	u32 wq_size;		/* size in bytes of queue area */
1380  	u32 wq_len;		/* number of entries in queue */
1381  	void __iomem *prod_idx_db_reg;	/* doorbell area index reg at offset 0x00 */
1382  	void __iomem *valid_db_reg;	/* doorbell area valid reg at offset 0x04 */
1383  	u16 prod_idx;		/* current value for prod idx */
1384  	u16 cq_id;		/* completion (rx) queue for tx completions */
1385  	u8 wq_id;		/* queue id for this entry */
1386  	u8 reserved1[3];
1387  	struct tx_ring_desc *q;	/* descriptor list for the queue */
1388  	spinlock_t lock;
1389  	atomic_t tx_count;	/* counts down for every outstanding IO */
1390  	struct delayed_work tx_work;
1391  	struct qlge_adapter *qdev;
1392  	u64 tx_packets;
1393  	u64 tx_bytes;
1394  	u64 tx_errors;
1395  };
1396  
1397  struct qlge_page_chunk {
1398  	struct page *page;
1399  	void *va; /* virt addr including offset */
1400  	unsigned int offset;
1401  };
1402  
1403  struct qlge_bq_desc {
1404  	union {
1405  		/* for large buffers */
1406  		struct qlge_page_chunk pg_chunk;
1407  		/* for small buffers */
1408  		struct sk_buff *skb;
1409  	} p;
1410  	dma_addr_t dma_addr;
1411  	/* address in ring where the buffer address is written for the device */
1412  	__le64 *buf_ptr;
1413  	u32 index;
1414  };
1415  
1416  /* buffer queue */
1417  struct qlge_bq {
1418  	__le64 *base;
1419  	dma_addr_t base_dma;
1420  	__le64 *base_indirect;
1421  	dma_addr_t base_indirect_dma;
1422  	struct qlge_bq_desc *queue;
1423  	/* prod_idx is the index of the first buffer that may NOT be used by
1424  	 * hw, ie. one after the last. Advanced by sw.
1425  	 */
1426  	void __iomem *prod_idx_db_reg;
1427  	/* next index where sw should refill a buffer for hw */
1428  	u16 next_to_use;
1429  	/* next index where sw expects to find a buffer filled by hw */
1430  	u16 next_to_clean;
1431  	enum {
1432  		QLGE_SB,		/* small buffer */
1433  		QLGE_LB,		/* large buffer */
1434  	} type;
1435  };
1436  
1437  #define QLGE_BQ_CONTAINER(bq) \
1438  ({ \
1439  	typeof(bq) _bq = bq; \
1440  	(struct rx_ring *)((char *)_bq - (_bq->type == QLGE_SB ? \
1441  					  offsetof(struct rx_ring, sbq) : \
1442  					  offsetof(struct rx_ring, lbq))); \
1443  })
1444  
1445  /* Experience shows that the device ignores the low 4 bits of the tail index.
1446   * Refill up to a x16 multiple.
1447   */
1448  #define QLGE_BQ_ALIGN(index) ALIGN_DOWN(index, 16)
1449  
1450  #define QLGE_BQ_WRAP(index) ((index) & (QLGE_BQ_LEN - 1))
1451  
1452  #define QLGE_BQ_HW_OWNED(bq) \
1453  ({ \
1454  	typeof(bq) _bq = bq; \
1455  	QLGE_BQ_WRAP(QLGE_BQ_ALIGN((_bq)->next_to_use) - \
1456  		     (_bq)->next_to_clean); \
1457  })
1458  
1459  struct rx_ring {
1460  	struct cqicb cqicb;	/* The chip's completion queue init control block. */
1461  
1462  	/* Completion queue elements. */
1463  	void *cq_base;
1464  	dma_addr_t cq_base_dma;
1465  	u32 cq_size;
1466  	u32 cq_len;
1467  	u16 cq_id;
1468  	__le32 *prod_idx_sh_reg;	/* Shadowed producer register. */
1469  	dma_addr_t prod_idx_sh_reg_dma;
1470  	void __iomem *cnsmr_idx_db_reg;	/* PCI doorbell mem area + 0 */
1471  	u32 cnsmr_idx;		/* current sw idx */
1472  	struct qlge_net_rsp_iocb *curr_entry;	/* next entry on queue */
1473  	void __iomem *valid_db_reg;	/* PCI doorbell mem area + 0x04 */
1474  
1475  	/* Large buffer queue elements. */
1476  	struct qlge_bq lbq;
1477  	struct qlge_page_chunk master_chunk;
1478  	dma_addr_t chunk_dma_addr;
1479  
1480  	/* Small buffer queue elements. */
1481  	struct qlge_bq sbq;
1482  
1483  	/* Misc. handler elements. */
1484  	u32 irq;		/* Which vector this ring is assigned. */
1485  	u32 cpu;		/* Which CPU this should run on. */
1486  	struct delayed_work refill_work;
1487  	char name[IFNAMSIZ + 5];
1488  	struct napi_struct napi;
1489  	u8 reserved;
1490  	struct qlge_adapter *qdev;
1491  	u64 rx_packets;
1492  	u64 rx_multicast;
1493  	u64 rx_bytes;
1494  	u64 rx_dropped;
1495  	u64 rx_errors;
1496  };
1497  
1498  /*
1499   * RSS Initialization Control Block
1500   */
1501  struct hash_id {
1502  	u8 value[4];
1503  };
1504  
1505  struct nic_stats {
1506  	/*
1507  	 * These stats come from offset 200h to 278h
1508  	 * in the XGMAC register.
1509  	 */
1510  	u64 tx_pkts;
1511  	u64 tx_bytes;
1512  	u64 tx_mcast_pkts;
1513  	u64 tx_bcast_pkts;
1514  	u64 tx_ucast_pkts;
1515  	u64 tx_ctl_pkts;
1516  	u64 tx_pause_pkts;
1517  	u64 tx_64_pkt;
1518  	u64 tx_65_to_127_pkt;
1519  	u64 tx_128_to_255_pkt;
1520  	u64 tx_256_511_pkt;
1521  	u64 tx_512_to_1023_pkt;
1522  	u64 tx_1024_to_1518_pkt;
1523  	u64 tx_1519_to_max_pkt;
1524  	u64 tx_undersize_pkt;
1525  	u64 tx_oversize_pkt;
1526  
1527  	/*
1528  	 * These stats come from offset 300h to 3C8h
1529  	 * in the XGMAC register.
1530  	 */
1531  	u64 rx_bytes;
1532  	u64 rx_bytes_ok;
1533  	u64 rx_pkts;
1534  	u64 rx_pkts_ok;
1535  	u64 rx_bcast_pkts;
1536  	u64 rx_mcast_pkts;
1537  	u64 rx_ucast_pkts;
1538  	u64 rx_undersize_pkts;
1539  	u64 rx_oversize_pkts;
1540  	u64 rx_jabber_pkts;
1541  	u64 rx_undersize_fcerr_pkts;
1542  	u64 rx_drop_events;
1543  	u64 rx_fcerr_pkts;
1544  	u64 rx_align_err;
1545  	u64 rx_symbol_err;
1546  	u64 rx_mac_err;
1547  	u64 rx_ctl_pkts;
1548  	u64 rx_pause_pkts;
1549  	u64 rx_64_pkts;
1550  	u64 rx_65_to_127_pkts;
1551  	u64 rx_128_255_pkts;
1552  	u64 rx_256_511_pkts;
1553  	u64 rx_512_to_1023_pkts;
1554  	u64 rx_1024_to_1518_pkts;
1555  	u64 rx_1519_to_max_pkts;
1556  	u64 rx_len_err_pkts;
1557  	/* Receive Mac Err stats */
1558  	u64 rx_code_err;
1559  	u64 rx_oversize_err;
1560  	u64 rx_undersize_err;
1561  	u64 rx_preamble_err;
1562  	u64 rx_frame_len_err;
1563  	u64 rx_crc_err;
1564  	u64 rx_err_count;
1565  	/*
1566  	 * These stats come from offset 500h to 5C8h
1567  	 * in the XGMAC register.
1568  	 */
1569  	u64 tx_cbfc_pause_frames0;
1570  	u64 tx_cbfc_pause_frames1;
1571  	u64 tx_cbfc_pause_frames2;
1572  	u64 tx_cbfc_pause_frames3;
1573  	u64 tx_cbfc_pause_frames4;
1574  	u64 tx_cbfc_pause_frames5;
1575  	u64 tx_cbfc_pause_frames6;
1576  	u64 tx_cbfc_pause_frames7;
1577  	u64 rx_cbfc_pause_frames0;
1578  	u64 rx_cbfc_pause_frames1;
1579  	u64 rx_cbfc_pause_frames2;
1580  	u64 rx_cbfc_pause_frames3;
1581  	u64 rx_cbfc_pause_frames4;
1582  	u64 rx_cbfc_pause_frames5;
1583  	u64 rx_cbfc_pause_frames6;
1584  	u64 rx_cbfc_pause_frames7;
1585  	u64 rx_nic_fifo_drop;
1586  };
1587  
1588  /* Firmware coredump internal register address/length pairs. */
1589  enum {
1590  	MPI_CORE_REGS_ADDR = 0x00030000,
1591  	MPI_CORE_REGS_CNT = 127,
1592  	MPI_CORE_SH_REGS_CNT = 16,
1593  	TEST_REGS_ADDR = 0x00001000,
1594  	TEST_REGS_CNT = 23,
1595  	RMII_REGS_ADDR = 0x00001040,
1596  	RMII_REGS_CNT = 64,
1597  	FCMAC1_REGS_ADDR = 0x00001080,
1598  	FCMAC2_REGS_ADDR = 0x000010c0,
1599  	FCMAC_REGS_CNT = 64,
1600  	FC1_MBX_REGS_ADDR = 0x00001100,
1601  	FC2_MBX_REGS_ADDR = 0x00001240,
1602  	FC_MBX_REGS_CNT = 64,
1603  	IDE_REGS_ADDR = 0x00001140,
1604  	IDE_REGS_CNT = 64,
1605  	NIC1_MBX_REGS_ADDR = 0x00001180,
1606  	NIC2_MBX_REGS_ADDR = 0x00001280,
1607  	NIC_MBX_REGS_CNT = 64,
1608  	SMBUS_REGS_ADDR = 0x00001200,
1609  	SMBUS_REGS_CNT = 64,
1610  	I2C_REGS_ADDR = 0x00001fc0,
1611  	I2C_REGS_CNT = 64,
1612  	MEMC_REGS_ADDR = 0x00003000,
1613  	MEMC_REGS_CNT = 256,
1614  	PBUS_REGS_ADDR = 0x00007c00,
1615  	PBUS_REGS_CNT = 256,
1616  	MDE_REGS_ADDR = 0x00010000,
1617  	MDE_REGS_CNT = 6,
1618  	CODE_RAM_ADDR = 0x00020000,
1619  	CODE_RAM_CNT = 0x2000,
1620  	MEMC_RAM_ADDR = 0x00100000,
1621  	MEMC_RAM_CNT = 0x2000,
1622  };
1623  
1624  #define MPI_COREDUMP_COOKIE 0x5555aaaa
1625  struct mpi_coredump_global_header {
1626  	u32	cookie;
1627  	u8	id_string[16];
1628  	u32	time_lo;
1629  	u32	time_hi;
1630  	u32	image_size;
1631  	u32	header_size;
1632  	u8	info[220];
1633  };
1634  
1635  struct mpi_coredump_segment_header {
1636  	u32	cookie;
1637  	u32	seg_num;
1638  	u32	seg_size;
1639  	u32	extra;
1640  	u8	description[16];
1641  };
1642  
1643  /* Firmware coredump header segment numbers. */
1644  enum {
1645  	CORE_SEG_NUM = 1,
1646  	TEST_LOGIC_SEG_NUM = 2,
1647  	RMII_SEG_NUM = 3,
1648  	FCMAC1_SEG_NUM = 4,
1649  	FCMAC2_SEG_NUM = 5,
1650  	FC1_MBOX_SEG_NUM = 6,
1651  	IDE_SEG_NUM = 7,
1652  	NIC1_MBOX_SEG_NUM = 8,
1653  	SMBUS_SEG_NUM = 9,
1654  	FC2_MBOX_SEG_NUM = 10,
1655  	NIC2_MBOX_SEG_NUM = 11,
1656  	I2C_SEG_NUM = 12,
1657  	MEMC_SEG_NUM = 13,
1658  	PBUS_SEG_NUM = 14,
1659  	MDE_SEG_NUM = 15,
1660  	NIC1_CONTROL_SEG_NUM = 16,
1661  	NIC2_CONTROL_SEG_NUM = 17,
1662  	NIC1_XGMAC_SEG_NUM = 18,
1663  	NIC2_XGMAC_SEG_NUM = 19,
1664  	WCS_RAM_SEG_NUM = 20,
1665  	MEMC_RAM_SEG_NUM = 21,
1666  	XAUI_AN_SEG_NUM = 22,
1667  	XAUI_HSS_PCS_SEG_NUM = 23,
1668  	XFI_AN_SEG_NUM = 24,
1669  	XFI_TRAIN_SEG_NUM = 25,
1670  	XFI_HSS_PCS_SEG_NUM = 26,
1671  	XFI_HSS_TX_SEG_NUM = 27,
1672  	XFI_HSS_RX_SEG_NUM = 28,
1673  	XFI_HSS_PLL_SEG_NUM = 29,
1674  	MISC_NIC_INFO_SEG_NUM = 30,
1675  	INTR_STATES_SEG_NUM = 31,
1676  	CAM_ENTRIES_SEG_NUM = 32,
1677  	ROUTING_WORDS_SEG_NUM = 33,
1678  	ETS_SEG_NUM = 34,
1679  	PROBE_DUMP_SEG_NUM = 35,
1680  	ROUTING_INDEX_SEG_NUM = 36,
1681  	MAC_PROTOCOL_SEG_NUM = 37,
1682  	XAUI2_AN_SEG_NUM = 38,
1683  	XAUI2_HSS_PCS_SEG_NUM = 39,
1684  	XFI2_AN_SEG_NUM = 40,
1685  	XFI2_TRAIN_SEG_NUM = 41,
1686  	XFI2_HSS_PCS_SEG_NUM = 42,
1687  	XFI2_HSS_TX_SEG_NUM = 43,
1688  	XFI2_HSS_RX_SEG_NUM = 44,
1689  	XFI2_HSS_PLL_SEG_NUM = 45,
1690  	SEM_REGS_SEG_NUM = 50
1691  
1692  };
1693  
1694  /* There are 64 generic NIC registers. */
1695  #define NIC_REGS_DUMP_WORD_COUNT		64
1696  /* XGMAC word count. */
1697  #define XGMAC_DUMP_WORD_COUNT		(XGMAC_REGISTER_END / 4)
1698  /* Word counts for the SERDES blocks. */
1699  #define XG_SERDES_XAUI_AN_COUNT		14
1700  #define XG_SERDES_XAUI_HSS_PCS_COUNT	33
1701  #define XG_SERDES_XFI_AN_COUNT		14
1702  #define XG_SERDES_XFI_TRAIN_COUNT		12
1703  #define XG_SERDES_XFI_HSS_PCS_COUNT	15
1704  #define XG_SERDES_XFI_HSS_TX_COUNT		32
1705  #define XG_SERDES_XFI_HSS_RX_COUNT		32
1706  #define XG_SERDES_XFI_HSS_PLL_COUNT	32
1707  
1708  /* There are 2 CNA ETS and 8 NIC ETS registers. */
1709  #define ETS_REGS_DUMP_WORD_COUNT		10
1710  
1711  /* Each probe mux entry stores the probe type plus 64 entries
1712   * that are each 64-bits in length. There are a total of
1713   * 34 (PRB_MX_ADDR_VALID_TOTAL) valid probes.
1714   */
1715  #define PRB_MX_ADDR_PRB_WORD_COUNT		(1 + (PRB_MX_ADDR_MAX_MUX * 2))
1716  #define PRB_MX_DUMP_TOT_COUNT		(PRB_MX_ADDR_PRB_WORD_COUNT * \
1717  							PRB_MX_ADDR_VALID_TOTAL)
1718  /* Each routing entry consists of 4 32-bit words.
1719   * They are route type, index, index word, and result.
1720   * There are 2 route blocks with 8 entries each and
1721   *  2 NIC blocks with 16 entries each.
1722   * The totol entries is 48 with 4 words each.
1723   */
1724  #define RT_IDX_DUMP_ENTRIES			48
1725  #define RT_IDX_DUMP_WORDS_PER_ENTRY	4
1726  #define RT_IDX_DUMP_TOT_WORDS		(RT_IDX_DUMP_ENTRIES * \
1727  						RT_IDX_DUMP_WORDS_PER_ENTRY)
1728  /* There are 10 address blocks in filter, each with
1729   * different entry counts and different word-count-per-entry.
1730   */
1731  #define MAC_ADDR_DUMP_ENTRIES \
1732  	((MAC_ADDR_MAX_CAM_ENTRIES * MAC_ADDR_MAX_CAM_WCOUNT) + \
1733  	(MAC_ADDR_MAX_MULTICAST_ENTRIES * MAC_ADDR_MAX_MULTICAST_WCOUNT) + \
1734  	(MAC_ADDR_MAX_VLAN_ENTRIES * MAC_ADDR_MAX_VLAN_WCOUNT) + \
1735  	(MAC_ADDR_MAX_MCAST_FLTR_ENTRIES * MAC_ADDR_MAX_MCAST_FLTR_WCOUNT) + \
1736  	(MAC_ADDR_MAX_FC_MAC_ENTRIES * MAC_ADDR_MAX_FC_MAC_WCOUNT) + \
1737  	(MAC_ADDR_MAX_MGMT_MAC_ENTRIES * MAC_ADDR_MAX_MGMT_MAC_WCOUNT) + \
1738  	(MAC_ADDR_MAX_MGMT_VLAN_ENTRIES * MAC_ADDR_MAX_MGMT_VLAN_WCOUNT) + \
1739  	(MAC_ADDR_MAX_MGMT_V4_ENTRIES * MAC_ADDR_MAX_MGMT_V4_WCOUNT) + \
1740  	(MAC_ADDR_MAX_MGMT_V6_ENTRIES * MAC_ADDR_MAX_MGMT_V6_WCOUNT) + \
1741  	(MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES * MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT))
1742  #define MAC_ADDR_DUMP_WORDS_PER_ENTRY	2
1743  #define MAC_ADDR_DUMP_TOT_WORDS		(MAC_ADDR_DUMP_ENTRIES * \
1744  						MAC_ADDR_DUMP_WORDS_PER_ENTRY)
1745  /* Maximum of 4 functions whose semaphore registeres are
1746   * in the coredump.
1747   */
1748  #define MAX_SEMAPHORE_FUNCTIONS		4
1749  /* Defines for access the MPI shadow registers. */
1750  #define RISC_124		0x0003007c
1751  #define RISC_127		0x0003007f
1752  #define SHADOW_OFFSET	0xb0000000
1753  #define SHADOW_REG_SHIFT	20
1754  
1755  struct qlge_nic_misc {
1756  	u32 rx_ring_count;
1757  	u32 tx_ring_count;
1758  	u32 intr_count;
1759  	u32 function;
1760  };
1761  
1762  struct qlge_reg_dump {
1763  	/* segment 0 */
1764  	struct mpi_coredump_global_header mpi_global_header;
1765  
1766  	/* segment 16 */
1767  	struct mpi_coredump_segment_header nic_regs_seg_hdr;
1768  	u32 nic_regs[64];
1769  
1770  	/* segment 30 */
1771  	struct mpi_coredump_segment_header misc_nic_seg_hdr;
1772  	struct qlge_nic_misc misc_nic_info;
1773  
1774  	/* segment 31 */
1775  	/* one interrupt state for each CQ */
1776  	struct mpi_coredump_segment_header intr_states_seg_hdr;
1777  	u32 intr_states[MAX_CPUS];
1778  
1779  	/* segment 32 */
1780  	/* 3 cam words each for 16 unicast,
1781  	 * 2 cam words for each of 32 multicast.
1782  	 */
1783  	struct mpi_coredump_segment_header cam_entries_seg_hdr;
1784  	u32 cam_entries[(16 * 3) + (32 * 3)];
1785  
1786  	/* segment 33 */
1787  	struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1788  	u32 nic_routing_words[16];
1789  
1790  	/* segment 34 */
1791  	struct mpi_coredump_segment_header ets_seg_hdr;
1792  	u32 ets[8 + 2];
1793  };
1794  
1795  struct qlge_mpi_coredump {
1796  	/* segment 0 */
1797  	struct mpi_coredump_global_header mpi_global_header;
1798  
1799  	/* segment 1 */
1800  	struct mpi_coredump_segment_header core_regs_seg_hdr;
1801  	u32 mpi_core_regs[MPI_CORE_REGS_CNT];
1802  	u32 mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT];
1803  
1804  	/* segment 2 */
1805  	struct mpi_coredump_segment_header test_logic_regs_seg_hdr;
1806  	u32 test_logic_regs[TEST_REGS_CNT];
1807  
1808  	/* segment 3 */
1809  	struct mpi_coredump_segment_header rmii_regs_seg_hdr;
1810  	u32 rmii_regs[RMII_REGS_CNT];
1811  
1812  	/* segment 4 */
1813  	struct mpi_coredump_segment_header fcmac1_regs_seg_hdr;
1814  	u32 fcmac1_regs[FCMAC_REGS_CNT];
1815  
1816  	/* segment 5 */
1817  	struct mpi_coredump_segment_header fcmac2_regs_seg_hdr;
1818  	u32 fcmac2_regs[FCMAC_REGS_CNT];
1819  
1820  	/* segment 6 */
1821  	struct mpi_coredump_segment_header fc1_mbx_regs_seg_hdr;
1822  	u32 fc1_mbx_regs[FC_MBX_REGS_CNT];
1823  
1824  	/* segment 7 */
1825  	struct mpi_coredump_segment_header ide_regs_seg_hdr;
1826  	u32 ide_regs[IDE_REGS_CNT];
1827  
1828  	/* segment 8 */
1829  	struct mpi_coredump_segment_header nic1_mbx_regs_seg_hdr;
1830  	u32 nic1_mbx_regs[NIC_MBX_REGS_CNT];
1831  
1832  	/* segment 9 */
1833  	struct mpi_coredump_segment_header smbus_regs_seg_hdr;
1834  	u32 smbus_regs[SMBUS_REGS_CNT];
1835  
1836  	/* segment 10 */
1837  	struct mpi_coredump_segment_header fc2_mbx_regs_seg_hdr;
1838  	u32 fc2_mbx_regs[FC_MBX_REGS_CNT];
1839  
1840  	/* segment 11 */
1841  	struct mpi_coredump_segment_header nic2_mbx_regs_seg_hdr;
1842  	u32 nic2_mbx_regs[NIC_MBX_REGS_CNT];
1843  
1844  	/* segment 12 */
1845  	struct mpi_coredump_segment_header i2c_regs_seg_hdr;
1846  	u32 i2c_regs[I2C_REGS_CNT];
1847  	/* segment 13 */
1848  	struct mpi_coredump_segment_header memc_regs_seg_hdr;
1849  	u32 memc_regs[MEMC_REGS_CNT];
1850  
1851  	/* segment 14 */
1852  	struct mpi_coredump_segment_header pbus_regs_seg_hdr;
1853  	u32 pbus_regs[PBUS_REGS_CNT];
1854  
1855  	/* segment 15 */
1856  	struct mpi_coredump_segment_header mde_regs_seg_hdr;
1857  	u32 mde_regs[MDE_REGS_CNT];
1858  
1859  	/* segment 16 */
1860  	struct mpi_coredump_segment_header nic_regs_seg_hdr;
1861  	u32 nic_regs[NIC_REGS_DUMP_WORD_COUNT];
1862  
1863  	/* segment 17 */
1864  	struct mpi_coredump_segment_header nic2_regs_seg_hdr;
1865  	u32 nic2_regs[NIC_REGS_DUMP_WORD_COUNT];
1866  
1867  	/* segment 18 */
1868  	struct mpi_coredump_segment_header xgmac1_seg_hdr;
1869  	u32 xgmac1[XGMAC_DUMP_WORD_COUNT];
1870  
1871  	/* segment 19 */
1872  	struct mpi_coredump_segment_header xgmac2_seg_hdr;
1873  	u32 xgmac2[XGMAC_DUMP_WORD_COUNT];
1874  
1875  	/* segment 20 */
1876  	struct mpi_coredump_segment_header code_ram_seg_hdr;
1877  	u32 code_ram[CODE_RAM_CNT];
1878  
1879  	/* segment 21 */
1880  	struct mpi_coredump_segment_header memc_ram_seg_hdr;
1881  	u32 memc_ram[MEMC_RAM_CNT];
1882  
1883  	/* segment 22 */
1884  	struct mpi_coredump_segment_header xaui_an_hdr;
1885  	u32 serdes_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1886  
1887  	/* segment 23 */
1888  	struct mpi_coredump_segment_header xaui_hss_pcs_hdr;
1889  	u32 serdes_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1890  
1891  	/* segment 24 */
1892  	struct mpi_coredump_segment_header xfi_an_hdr;
1893  	u32 serdes_xfi_an[XG_SERDES_XFI_AN_COUNT];
1894  
1895  	/* segment 25 */
1896  	struct mpi_coredump_segment_header xfi_train_hdr;
1897  	u32 serdes_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1898  
1899  	/* segment 26 */
1900  	struct mpi_coredump_segment_header xfi_hss_pcs_hdr;
1901  	u32 serdes_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1902  
1903  	/* segment 27 */
1904  	struct mpi_coredump_segment_header xfi_hss_tx_hdr;
1905  	u32 serdes_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1906  
1907  	/* segment 28 */
1908  	struct mpi_coredump_segment_header xfi_hss_rx_hdr;
1909  	u32 serdes_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1910  
1911  	/* segment 29 */
1912  	struct mpi_coredump_segment_header xfi_hss_pll_hdr;
1913  	u32 serdes_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1914  
1915  	/* segment 30 */
1916  	struct mpi_coredump_segment_header misc_nic_seg_hdr;
1917  	struct qlge_nic_misc misc_nic_info;
1918  
1919  	/* segment 31 */
1920  	/* one interrupt state for each CQ */
1921  	struct mpi_coredump_segment_header intr_states_seg_hdr;
1922  	u32 intr_states[MAX_RX_RINGS];
1923  
1924  	/* segment 32 */
1925  	/* 3 cam words each for 16 unicast,
1926  	 * 2 cam words for each of 32 multicast.
1927  	 */
1928  	struct mpi_coredump_segment_header cam_entries_seg_hdr;
1929  	u32 cam_entries[(16 * 3) + (32 * 3)];
1930  
1931  	/* segment 33 */
1932  	struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1933  	u32 nic_routing_words[16];
1934  	/* segment 34 */
1935  	struct mpi_coredump_segment_header ets_seg_hdr;
1936  	u32 ets[ETS_REGS_DUMP_WORD_COUNT];
1937  
1938  	/* segment 35 */
1939  	struct mpi_coredump_segment_header probe_dump_seg_hdr;
1940  	u32 probe_dump[PRB_MX_DUMP_TOT_COUNT];
1941  
1942  	/* segment 36 */
1943  	struct mpi_coredump_segment_header routing_reg_seg_hdr;
1944  	u32 routing_regs[RT_IDX_DUMP_TOT_WORDS];
1945  
1946  	/* segment 37 */
1947  	struct mpi_coredump_segment_header mac_prot_reg_seg_hdr;
1948  	u32 mac_prot_regs[MAC_ADDR_DUMP_TOT_WORDS];
1949  
1950  	/* segment 38 */
1951  	struct mpi_coredump_segment_header xaui2_an_hdr;
1952  	u32 serdes2_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1953  
1954  	/* segment 39 */
1955  	struct mpi_coredump_segment_header xaui2_hss_pcs_hdr;
1956  	u32 serdes2_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1957  
1958  	/* segment 40 */
1959  	struct mpi_coredump_segment_header xfi2_an_hdr;
1960  	u32 serdes2_xfi_an[XG_SERDES_XFI_AN_COUNT];
1961  
1962  	/* segment 41 */
1963  	struct mpi_coredump_segment_header xfi2_train_hdr;
1964  	u32 serdes2_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1965  
1966  	/* segment 42 */
1967  	struct mpi_coredump_segment_header xfi2_hss_pcs_hdr;
1968  	u32 serdes2_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1969  
1970  	/* segment 43 */
1971  	struct mpi_coredump_segment_header xfi2_hss_tx_hdr;
1972  	u32 serdes2_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1973  
1974  	/* segment 44 */
1975  	struct mpi_coredump_segment_header xfi2_hss_rx_hdr;
1976  	u32 serdes2_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1977  
1978  	/* segment 45 */
1979  	struct mpi_coredump_segment_header xfi2_hss_pll_hdr;
1980  	u32 serdes2_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1981  
1982  	/* segment 50 */
1983  	/* semaphore register for all 5 functions */
1984  	struct mpi_coredump_segment_header sem_regs_seg_hdr;
1985  	u32 sem_regs[MAX_SEMAPHORE_FUNCTIONS];
1986  };
1987  
1988  /*
1989   * intr_context structure is used during initialization
1990   * to hook the interrupts.  It is also used in a single
1991   * irq environment as a context to the ISR.
1992   */
1993  struct intr_context {
1994  	struct qlge_adapter *qdev;
1995  	u32 intr;
1996  	u32 irq_mask;		/* Mask of which rings the vector services. */
1997  	u32 hooked;
1998  	u32 intr_en_mask;	/* value/mask used to enable this intr */
1999  	u32 intr_dis_mask;	/* value/mask used to disable this intr */
2000  	u32 intr_read_mask;	/* value/mask used to read this intr */
2001  	char name[IFNAMSIZ * 2];
2002  	irq_handler_t handler;
2003  };
2004  
2005  /* adapter flags definitions. */
2006  enum {
2007  	QL_ADAPTER_UP = 0,	/* Adapter has been brought up. */
2008  	QL_LEGACY_ENABLED = 1,
2009  	QL_MSI_ENABLED = 2,
2010  	QL_MSIX_ENABLED = 3,
2011  	QL_DMA64 = 4,
2012  	QL_PROMISCUOUS = 5,
2013  	QL_ALLMULTI = 6,
2014  	QL_PORT_CFG = 7,
2015  	QL_CAM_RT_SET = 8,
2016  	QL_SELFTEST = 9,
2017  	QL_LB_LINK_UP = 10,
2018  	QL_FRC_COREDUMP = 11,
2019  	QL_EEH_FATAL = 12,
2020  	QL_ASIC_RECOVERY = 14, /* We are in ascic recovery. */
2021  };
2022  
2023  /* link_status bit definitions */
2024  enum {
2025  	STS_LOOPBACK_MASK = 0x00000700,
2026  	STS_LOOPBACK_PCS = 0x00000100,
2027  	STS_LOOPBACK_HSS = 0x00000200,
2028  	STS_LOOPBACK_EXT = 0x00000300,
2029  	STS_PAUSE_MASK = 0x000000c0,
2030  	STS_PAUSE_STD = 0x00000040,
2031  	STS_PAUSE_PRI = 0x00000080,
2032  	STS_SPEED_MASK = 0x00000038,
2033  	STS_SPEED_100Mb = 0x00000000,
2034  	STS_SPEED_1Gb = 0x00000008,
2035  	STS_SPEED_10Gb = 0x00000010,
2036  	STS_LINK_TYPE_MASK = 0x00000007,
2037  	STS_LINK_TYPE_XFI = 0x00000001,
2038  	STS_LINK_TYPE_XAUI = 0x00000002,
2039  	STS_LINK_TYPE_XFI_BP = 0x00000003,
2040  	STS_LINK_TYPE_XAUI_BP = 0x00000004,
2041  	STS_LINK_TYPE_10GBASET = 0x00000005,
2042  };
2043  
2044  /* link_config bit definitions */
2045  enum {
2046  	CFG_JUMBO_FRAME_SIZE = 0x00010000,
2047  	CFG_PAUSE_MASK = 0x00000060,
2048  	CFG_PAUSE_STD = 0x00000020,
2049  	CFG_PAUSE_PRI = 0x00000040,
2050  	CFG_DCBX = 0x00000010,
2051  	CFG_LOOPBACK_MASK = 0x00000007,
2052  	CFG_LOOPBACK_PCS = 0x00000002,
2053  	CFG_LOOPBACK_HSS = 0x00000004,
2054  	CFG_LOOPBACK_EXT = 0x00000006,
2055  	CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
2056  };
2057  
2058  struct nic_operations {
2059  	int (*get_flash)(struct qlge_adapter *qdev);
2060  	int (*port_initialize)(struct qlge_adapter *qdev);
2061  };
2062  
2063  struct qlge_netdev_priv {
2064  	struct qlge_adapter *qdev;
2065  	struct net_device *ndev;
2066  };
2067  
2068  static inline
netdev_to_qdev(struct net_device * ndev)2069  struct qlge_adapter *netdev_to_qdev(struct net_device *ndev)
2070  {
2071  	struct qlge_netdev_priv *ndev_priv = netdev_priv(ndev);
2072  
2073  	return ndev_priv->qdev;
2074  }
2075  
2076  /*
2077   * The main Adapter structure definition.
2078   * This structure has all fields relevant to the hardware.
2079   */
2080  struct qlge_adapter {
2081  	struct ricb ricb;
2082  	unsigned long flags;
2083  	u32 wol;
2084  
2085  	struct nic_stats nic_stats;
2086  
2087  	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
2088  
2089  	/* PCI Configuration information for this device */
2090  	struct pci_dev *pdev;
2091  	struct net_device *ndev;	/* Parent NET device */
2092  
2093  	struct devlink_health_reporter *reporter;
2094  	/* Hardware information */
2095  	u32 chip_rev_id;
2096  	u32 fw_rev_id;
2097  	u32 func;		/* PCI function for this adapter */
2098  	u32 alt_func;		/* PCI function for alternate adapter */
2099  	u32 port;		/* Port number this adapter */
2100  
2101  	spinlock_t adapter_lock;
2102  	spinlock_t stats_lock;
2103  
2104  	/* PCI Bus Relative Register Addresses */
2105  	void __iomem *reg_base;
2106  	void __iomem *doorbell_area;
2107  	u32 doorbell_area_size;
2108  
2109  	u32 msg_enable;
2110  
2111  	/* Page for Shadow Registers */
2112  	void *rx_ring_shadow_reg_area;
2113  	dma_addr_t rx_ring_shadow_reg_dma;
2114  	void *tx_ring_shadow_reg_area;
2115  	dma_addr_t tx_ring_shadow_reg_dma;
2116  
2117  	u32 mailbox_in;
2118  	u32 mailbox_out;
2119  	struct mbox_params idc_mbc;
2120  	struct mutex	mpi_mutex;
2121  
2122  	int tx_ring_size;
2123  	int rx_ring_size;
2124  	u32 intr_count;
2125  	struct msix_entry *msi_x_entry;
2126  	struct intr_context intr_context[MAX_RX_RINGS];
2127  
2128  	int tx_ring_count;	/* One per online CPU. */
2129  	u32 rss_ring_count;	/* One per irq vector.  */
2130  	/*
2131  	 * rx_ring_count =
2132  	 *  (CPU count * outbound completion rx_ring) +
2133  	 *  (irq_vector_cnt * inbound (RSS) completion rx_ring)
2134  	 */
2135  	int rx_ring_count;
2136  	int ring_mem_size;
2137  	void *ring_mem;
2138  
2139  	struct rx_ring rx_ring[MAX_RX_RINGS];
2140  	struct tx_ring tx_ring[MAX_TX_RINGS];
2141  	unsigned int lbq_buf_order;
2142  	u32 lbq_buf_size;
2143  
2144  	int rx_csum;
2145  	u32 default_rx_queue;
2146  
2147  	u16 rx_coalesce_usecs;	/* cqicb->int_delay */
2148  	u16 rx_max_coalesced_frames;	/* cqicb->pkt_int_delay */
2149  	u16 tx_coalesce_usecs;	/* cqicb->int_delay */
2150  	u16 tx_max_coalesced_frames;	/* cqicb->pkt_int_delay */
2151  
2152  	u32 xg_sem_mask;
2153  	u32 port_link_up;
2154  	u32 port_init;
2155  	u32 link_status;
2156  	struct qlge_mpi_coredump *mpi_coredump;
2157  	u32 link_config;
2158  	u32 led_config;
2159  	u32 max_frame_size;
2160  
2161  	union flash_params flash;
2162  
2163  	struct workqueue_struct *workqueue;
2164  	struct delayed_work asic_reset_work;
2165  	struct delayed_work mpi_reset_work;
2166  	struct delayed_work mpi_work;
2167  	struct delayed_work mpi_port_cfg_work;
2168  	struct delayed_work mpi_idc_work;
2169  	struct completion ide_completion;
2170  	const struct nic_operations *nic_ops;
2171  	u16 device_id;
2172  	struct timer_list timer;
2173  	atomic_t lb_count;
2174  	/* Keep local copy of current mac address. */
2175  	char current_mac_addr[ETH_ALEN];
2176  };
2177  
2178  /*
2179   * Typical Register accessor for memory mapped device.
2180   */
qlge_read32(const struct qlge_adapter * qdev,int reg)2181  static inline u32 qlge_read32(const struct qlge_adapter *qdev, int reg)
2182  {
2183  	return readl(qdev->reg_base + reg);
2184  }
2185  
2186  /*
2187   * Typical Register accessor for memory mapped device.
2188   */
qlge_write32(const struct qlge_adapter * qdev,int reg,u32 val)2189  static inline void qlge_write32(const struct qlge_adapter *qdev, int reg, u32 val)
2190  {
2191  	writel(val, qdev->reg_base + reg);
2192  }
2193  
2194  /*
2195   * Doorbell Registers:
2196   * Doorbell registers are virtual registers in the PCI memory space.
2197   * The space is allocated by the chip during PCI initialization.  The
2198   * device driver finds the doorbell address in BAR 3 in PCI config space.
2199   * The registers are used to control outbound and inbound queues. For
2200   * example, the producer index for an outbound queue.  Each queue uses
2201   * 1 4k chunk of memory.  The lower half of the space is for outbound
2202   * queues. The upper half is for inbound queues.
2203   */
qlge_write_db_reg(u32 val,void __iomem * addr)2204  static inline void qlge_write_db_reg(u32 val, void __iomem *addr)
2205  {
2206  	writel(val, addr);
2207  }
2208  
2209  /*
2210   * Doorbell Registers:
2211   * Doorbell registers are virtual registers in the PCI memory space.
2212   * The space is allocated by the chip during PCI initialization.  The
2213   * device driver finds the doorbell address in BAR 3 in PCI config space.
2214   * The registers are used to control outbound and inbound queues. For
2215   * example, the producer index for an outbound queue.  Each queue uses
2216   * 1 4k chunk of memory.  The lower half of the space is for outbound
2217   * queues. The upper half is for inbound queues.
2218   * Caller has to guarantee ordering.
2219   */
qlge_write_db_reg_relaxed(u32 val,void __iomem * addr)2220  static inline void qlge_write_db_reg_relaxed(u32 val, void __iomem *addr)
2221  {
2222  	writel_relaxed(val, addr);
2223  }
2224  
2225  /*
2226   * Shadow Registers:
2227   * Outbound queues have a consumer index that is maintained by the chip.
2228   * Inbound queues have a producer index that is maintained by the chip.
2229   * For lower overhead, these registers are "shadowed" to host memory
2230   * which allows the device driver to track the queue progress without
2231   * PCI reads. When an entry is placed on an inbound queue, the chip will
2232   * update the relevant index register and then copy the value to the
2233   * shadow register in host memory.
2234   */
qlge_read_sh_reg(__le32 * addr)2235  static inline u32 qlge_read_sh_reg(__le32  *addr)
2236  {
2237  	u32 reg;
2238  
2239  	reg =  le32_to_cpu(*addr);
2240  	rmb();
2241  	return reg;
2242  }
2243  
2244  extern char qlge_driver_name[];
2245  extern const char qlge_driver_version[];
2246  extern const struct ethtool_ops qlge_ethtool_ops;
2247  
2248  int qlge_sem_spinlock(struct qlge_adapter *qdev, u32 sem_mask);
2249  void qlge_sem_unlock(struct qlge_adapter *qdev, u32 sem_mask);
2250  int qlge_read_xgmac_reg(struct qlge_adapter *qdev, u32 reg, u32 *data);
2251  int qlge_get_mac_addr_reg(struct qlge_adapter *qdev, u32 type, u16 index,
2252  			  u32 *value);
2253  int qlge_get_routing_reg(struct qlge_adapter *qdev, u32 index, u32 *value);
2254  int qlge_write_cfg(struct qlge_adapter *qdev, void *ptr, int size, u32 bit,
2255  		   u16 q_id);
2256  void qlge_queue_fw_error(struct qlge_adapter *qdev);
2257  void qlge_mpi_work(struct work_struct *work);
2258  void qlge_mpi_reset_work(struct work_struct *work);
2259  int qlge_wait_reg_rdy(struct qlge_adapter *qdev, u32 reg, u32 bit, u32 ebit);
2260  void qlge_queue_asic_error(struct qlge_adapter *qdev);
2261  void qlge_set_ethtool_ops(struct net_device *ndev);
2262  int qlge_read_xgmac_reg64(struct qlge_adapter *qdev, u32 reg, u64 *data);
2263  void qlge_mpi_idc_work(struct work_struct *work);
2264  void qlge_mpi_port_cfg_work(struct work_struct *work);
2265  int qlge_mb_get_fw_state(struct qlge_adapter *qdev);
2266  int qlge_cam_route_initialize(struct qlge_adapter *qdev);
2267  int qlge_read_mpi_reg(struct qlge_adapter *qdev, u32 reg, u32 *data);
2268  int qlge_write_mpi_reg(struct qlge_adapter *qdev, u32 reg, u32 data);
2269  int qlge_unpause_mpi_risc(struct qlge_adapter *qdev);
2270  int qlge_pause_mpi_risc(struct qlge_adapter *qdev);
2271  int qlge_hard_reset_mpi_risc(struct qlge_adapter *qdev);
2272  int qlge_soft_reset_mpi_risc(struct qlge_adapter *qdev);
2273  int qlge_dump_risc_ram_area(struct qlge_adapter *qdev, void *buf, u32 ram_addr,
2274  			    int word_count);
2275  int qlge_core_dump(struct qlge_adapter *qdev, struct qlge_mpi_coredump *mpi_coredump);
2276  int qlge_mb_about_fw(struct qlge_adapter *qdev);
2277  int qlge_mb_wol_set_magic(struct qlge_adapter *qdev, u32 enable_wol);
2278  int qlge_mb_wol_mode(struct qlge_adapter *qdev, u32 wol);
2279  int qlge_mb_set_led_cfg(struct qlge_adapter *qdev, u32 led_config);
2280  int qlge_mb_get_led_cfg(struct qlge_adapter *qdev);
2281  void qlge_link_on(struct qlge_adapter *qdev);
2282  void qlge_link_off(struct qlge_adapter *qdev);
2283  int qlge_mb_set_mgmnt_traffic_ctl(struct qlge_adapter *qdev, u32 control);
2284  int qlge_mb_get_port_cfg(struct qlge_adapter *qdev);
2285  int qlge_mb_set_port_cfg(struct qlge_adapter *qdev);
2286  int qlge_wait_fifo_empty(struct qlge_adapter *qdev);
2287  void qlge_get_dump(struct qlge_adapter *qdev, void *buff);
2288  netdev_tx_t qlge_lb_send(struct sk_buff *skb, struct net_device *ndev);
2289  void qlge_check_lb_frame(struct qlge_adapter *qdev, struct sk_buff *skb);
2290  int qlge_own_firmware(struct qlge_adapter *qdev);
2291  int qlge_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget);
2292  
2293  #endif /* _QLGE_H_ */
2294