1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip Successive Approximation Register (SAR) A/D Converter
4 * Copyright (C) 2014 ROCKCHIP, Inc.
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/module.h>
9 #include <linux/mutex.h>
10 #include <linux/platform_device.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/of.h>
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/reset.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23
24 #define SARADC_DATA 0x00
25
26 #define SARADC_STAS 0x04
27 #define SARADC_STAS_BUSY BIT(0)
28
29 #define SARADC_CTRL 0x08
30 #define SARADC_CTRL_IRQ_STATUS BIT(6)
31 #define SARADC_CTRL_IRQ_ENABLE BIT(5)
32 #define SARADC_CTRL_POWER_CTRL BIT(3)
33 #define SARADC_CTRL_CHN_MASK 0x7
34
35 #define SARADC_DLY_PU_SOC 0x0c
36 #define SARADC_DLY_PU_SOC_MASK 0x3f
37
38 #define SARADC_TIMEOUT msecs_to_jiffies(100)
39 #define SARADC_MAX_CHANNELS 8
40
41 /* v2 registers */
42 #define SARADC2_CONV_CON 0x000
43 #define SARADC_T_PD_SOC 0x004
44 #define SARADC_T_DAS_SOC 0x00c
45 #define SARADC2_END_INT_EN 0x104
46 #define SARADC2_ST_CON 0x108
47 #define SARADC2_STATUS 0x10c
48 #define SARADC2_END_INT_ST 0x110
49 #define SARADC2_DATA_BASE 0x120
50
51 #define SARADC2_EN_END_INT BIT(0)
52 #define SARADC2_START BIT(4)
53 #define SARADC2_SINGLE_MODE BIT(5)
54
55 #define SARADC2_CONV_CHANNELS GENMASK(3, 0)
56
57 struct rockchip_saradc;
58
59 struct rockchip_saradc_data {
60 const struct iio_chan_spec *channels;
61 int num_channels;
62 unsigned long clk_rate;
63 void (*start)(struct rockchip_saradc *info, int chn);
64 int (*read)(struct rockchip_saradc *info);
65 void (*power_down)(struct rockchip_saradc *info);
66 };
67
68 struct rockchip_saradc {
69 void __iomem *regs;
70 struct clk *pclk;
71 struct clk *clk;
72 struct completion completion;
73 struct regulator *vref;
74 /* lock to protect against multiple access to the device */
75 struct mutex lock;
76 int uv_vref;
77 struct reset_control *reset;
78 const struct rockchip_saradc_data *data;
79 u16 last_val;
80 const struct iio_chan_spec *last_chan;
81 struct notifier_block nb;
82 };
83
84 static void rockchip_saradc_reset_controller(struct reset_control *reset);
85
rockchip_saradc_start_v1(struct rockchip_saradc * info,int chn)86 static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
87 {
88 /* 8 clock periods as delay between power up and start cmd */
89 writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
90 /* Select the channel to be used and trigger conversion */
91 writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
92 SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
93 }
94
rockchip_saradc_start_v2(struct rockchip_saradc * info,int chn)95 static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
96 {
97 int val;
98
99 if (info->reset)
100 rockchip_saradc_reset_controller(info->reset);
101
102 writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
103 writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
104 val = FIELD_PREP(SARADC2_EN_END_INT, 1);
105 val |= SARADC2_EN_END_INT << 16;
106 writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
107 val = FIELD_PREP(SARADC2_START, 1) |
108 FIELD_PREP(SARADC2_SINGLE_MODE, 1) |
109 FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
110 val |= (SARADC2_START | SARADC2_SINGLE_MODE | SARADC2_CONV_CHANNELS) << 16;
111 writel(val, info->regs + SARADC2_CONV_CON);
112 }
113
rockchip_saradc_start(struct rockchip_saradc * info,int chn)114 static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
115 {
116 info->data->start(info, chn);
117 }
118
rockchip_saradc_read_v1(struct rockchip_saradc * info)119 static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
120 {
121 return readl_relaxed(info->regs + SARADC_DATA);
122 }
123
rockchip_saradc_read_v2(struct rockchip_saradc * info)124 static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
125 {
126 int offset;
127
128 /* Clear irq */
129 writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
130
131 offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
132
133 return readl_relaxed(info->regs + offset);
134 }
135
rockchip_saradc_read(struct rockchip_saradc * info)136 static int rockchip_saradc_read(struct rockchip_saradc *info)
137 {
138 return info->data->read(info);
139 }
140
rockchip_saradc_power_down_v1(struct rockchip_saradc * info)141 static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
142 {
143 writel_relaxed(0, info->regs + SARADC_CTRL);
144 }
145
rockchip_saradc_power_down(struct rockchip_saradc * info)146 static void rockchip_saradc_power_down(struct rockchip_saradc *info)
147 {
148 if (info->data->power_down)
149 info->data->power_down(info);
150 }
151
rockchip_saradc_conversion(struct rockchip_saradc * info,struct iio_chan_spec const * chan)152 static int rockchip_saradc_conversion(struct rockchip_saradc *info,
153 struct iio_chan_spec const *chan)
154 {
155 reinit_completion(&info->completion);
156
157 info->last_chan = chan;
158 rockchip_saradc_start(info, chan->channel);
159
160 if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
161 return -ETIMEDOUT;
162
163 return 0;
164 }
165
rockchip_saradc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)166 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
167 struct iio_chan_spec const *chan,
168 int *val, int *val2, long mask)
169 {
170 struct rockchip_saradc *info = iio_priv(indio_dev);
171 int ret;
172
173 switch (mask) {
174 case IIO_CHAN_INFO_RAW:
175 mutex_lock(&info->lock);
176
177 ret = rockchip_saradc_conversion(info, chan);
178 if (ret) {
179 rockchip_saradc_power_down(info);
180 mutex_unlock(&info->lock);
181 return ret;
182 }
183
184 *val = info->last_val;
185 mutex_unlock(&info->lock);
186 return IIO_VAL_INT;
187 case IIO_CHAN_INFO_SCALE:
188 *val = info->uv_vref / 1000;
189 *val2 = chan->scan_type.realbits;
190 return IIO_VAL_FRACTIONAL_LOG2;
191 default:
192 return -EINVAL;
193 }
194 }
195
rockchip_saradc_isr(int irq,void * dev_id)196 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
197 {
198 struct rockchip_saradc *info = dev_id;
199
200 /* Read value */
201 info->last_val = rockchip_saradc_read(info);
202 info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
203
204 rockchip_saradc_power_down(info);
205
206 complete(&info->completion);
207
208 return IRQ_HANDLED;
209 }
210
211 static const struct iio_info rockchip_saradc_iio_info = {
212 .read_raw = rockchip_saradc_read_raw,
213 };
214
215 #define SARADC_CHANNEL(_index, _id, _res) { \
216 .type = IIO_VOLTAGE, \
217 .indexed = 1, \
218 .channel = _index, \
219 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
220 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
221 .datasheet_name = _id, \
222 .scan_index = _index, \
223 .scan_type = { \
224 .sign = 'u', \
225 .realbits = _res, \
226 .storagebits = 16, \
227 .endianness = IIO_CPU, \
228 }, \
229 }
230
231 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
232 SARADC_CHANNEL(0, "adc0", 10),
233 SARADC_CHANNEL(1, "adc1", 10),
234 SARADC_CHANNEL(2, "adc2", 10),
235 };
236
237 static const struct rockchip_saradc_data saradc_data = {
238 .channels = rockchip_saradc_iio_channels,
239 .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
240 .clk_rate = 1000000,
241 .start = rockchip_saradc_start_v1,
242 .read = rockchip_saradc_read_v1,
243 .power_down = rockchip_saradc_power_down_v1,
244 };
245
246 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
247 SARADC_CHANNEL(0, "adc0", 12),
248 SARADC_CHANNEL(1, "adc1", 12),
249 };
250
251 static const struct rockchip_saradc_data rk3066_tsadc_data = {
252 .channels = rockchip_rk3066_tsadc_iio_channels,
253 .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
254 .clk_rate = 50000,
255 .start = rockchip_saradc_start_v1,
256 .read = rockchip_saradc_read_v1,
257 .power_down = rockchip_saradc_power_down_v1,
258 };
259
260 static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
261 SARADC_CHANNEL(0, "adc0", 10),
262 SARADC_CHANNEL(1, "adc1", 10),
263 SARADC_CHANNEL(2, "adc2", 10),
264 SARADC_CHANNEL(3, "adc3", 10),
265 SARADC_CHANNEL(4, "adc4", 10),
266 SARADC_CHANNEL(5, "adc5", 10),
267 };
268
269 static const struct rockchip_saradc_data rk3399_saradc_data = {
270 .channels = rockchip_rk3399_saradc_iio_channels,
271 .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
272 .clk_rate = 1000000,
273 .start = rockchip_saradc_start_v1,
274 .read = rockchip_saradc_read_v1,
275 .power_down = rockchip_saradc_power_down_v1,
276 };
277
278 static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
279 SARADC_CHANNEL(0, "adc0", 10),
280 SARADC_CHANNEL(1, "adc1", 10),
281 SARADC_CHANNEL(2, "adc2", 10),
282 SARADC_CHANNEL(3, "adc3", 10),
283 SARADC_CHANNEL(4, "adc4", 10),
284 SARADC_CHANNEL(5, "adc5", 10),
285 SARADC_CHANNEL(6, "adc6", 10),
286 SARADC_CHANNEL(7, "adc7", 10),
287 };
288
289 static const struct rockchip_saradc_data rk3568_saradc_data = {
290 .channels = rockchip_rk3568_saradc_iio_channels,
291 .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
292 .clk_rate = 1000000,
293 .start = rockchip_saradc_start_v1,
294 .read = rockchip_saradc_read_v1,
295 .power_down = rockchip_saradc_power_down_v1,
296 };
297
298 static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
299 SARADC_CHANNEL(0, "adc0", 12),
300 SARADC_CHANNEL(1, "adc1", 12),
301 SARADC_CHANNEL(2, "adc2", 12),
302 SARADC_CHANNEL(3, "adc3", 12),
303 SARADC_CHANNEL(4, "adc4", 12),
304 SARADC_CHANNEL(5, "adc5", 12),
305 SARADC_CHANNEL(6, "adc6", 12),
306 SARADC_CHANNEL(7, "adc7", 12),
307 };
308
309 static const struct rockchip_saradc_data rk3588_saradc_data = {
310 .channels = rockchip_rk3588_saradc_iio_channels,
311 .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
312 .clk_rate = 1000000,
313 .start = rockchip_saradc_start_v2,
314 .read = rockchip_saradc_read_v2,
315 };
316
317 static const struct of_device_id rockchip_saradc_match[] = {
318 {
319 .compatible = "rockchip,saradc",
320 .data = &saradc_data,
321 }, {
322 .compatible = "rockchip,rk3066-tsadc",
323 .data = &rk3066_tsadc_data,
324 }, {
325 .compatible = "rockchip,rk3399-saradc",
326 .data = &rk3399_saradc_data,
327 }, {
328 .compatible = "rockchip,rk3568-saradc",
329 .data = &rk3568_saradc_data,
330 }, {
331 .compatible = "rockchip,rk3588-saradc",
332 .data = &rk3588_saradc_data,
333 },
334 {},
335 };
336 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
337
338 /*
339 * Reset SARADC Controller.
340 */
rockchip_saradc_reset_controller(struct reset_control * reset)341 static void rockchip_saradc_reset_controller(struct reset_control *reset)
342 {
343 reset_control_assert(reset);
344 usleep_range(10, 20);
345 reset_control_deassert(reset);
346 }
347
rockchip_saradc_regulator_disable(void * data)348 static void rockchip_saradc_regulator_disable(void *data)
349 {
350 struct rockchip_saradc *info = data;
351
352 regulator_disable(info->vref);
353 }
354
rockchip_saradc_trigger_handler(int irq,void * p)355 static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
356 {
357 struct iio_poll_func *pf = p;
358 struct iio_dev *i_dev = pf->indio_dev;
359 struct rockchip_saradc *info = iio_priv(i_dev);
360 /*
361 * @values: each channel takes an u16 value
362 * @timestamp: will be 8-byte aligned automatically
363 */
364 struct {
365 u16 values[SARADC_MAX_CHANNELS];
366 int64_t timestamp;
367 } data;
368 int ret;
369 int i, j = 0;
370
371 memset(&data, 0, sizeof(data));
372
373 mutex_lock(&info->lock);
374
375 for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
376 const struct iio_chan_spec *chan = &i_dev->channels[i];
377
378 ret = rockchip_saradc_conversion(info, chan);
379 if (ret) {
380 rockchip_saradc_power_down(info);
381 goto out;
382 }
383
384 data.values[j] = info->last_val;
385 j++;
386 }
387
388 iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
389 out:
390 mutex_unlock(&info->lock);
391
392 iio_trigger_notify_done(i_dev->trig);
393
394 return IRQ_HANDLED;
395 }
396
rockchip_saradc_volt_notify(struct notifier_block * nb,unsigned long event,void * data)397 static int rockchip_saradc_volt_notify(struct notifier_block *nb,
398 unsigned long event, void *data)
399 {
400 struct rockchip_saradc *info =
401 container_of(nb, struct rockchip_saradc, nb);
402
403 if (event & REGULATOR_EVENT_VOLTAGE_CHANGE)
404 info->uv_vref = (unsigned long)data;
405
406 return NOTIFY_OK;
407 }
408
rockchip_saradc_regulator_unreg_notifier(void * data)409 static void rockchip_saradc_regulator_unreg_notifier(void *data)
410 {
411 struct rockchip_saradc *info = data;
412
413 regulator_unregister_notifier(info->vref, &info->nb);
414 }
415
rockchip_saradc_probe(struct platform_device * pdev)416 static int rockchip_saradc_probe(struct platform_device *pdev)
417 {
418 const struct rockchip_saradc_data *match_data;
419 struct rockchip_saradc *info = NULL;
420 struct device_node *np = pdev->dev.of_node;
421 struct iio_dev *indio_dev = NULL;
422 int ret;
423 int irq;
424
425 if (!np)
426 return -ENODEV;
427
428 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
429 if (!indio_dev)
430 return dev_err_probe(&pdev->dev, -ENOMEM,
431 "failed allocating iio device\n");
432
433 info = iio_priv(indio_dev);
434
435 match_data = of_device_get_match_data(&pdev->dev);
436 if (!match_data)
437 return dev_err_probe(&pdev->dev, -ENODEV,
438 "failed to match device\n");
439
440 info->data = match_data;
441
442 /* Sanity check for possible later IP variants with more channels */
443 if (info->data->num_channels > SARADC_MAX_CHANNELS)
444 return dev_err_probe(&pdev->dev, -EINVAL,
445 "max channels exceeded");
446
447 info->regs = devm_platform_ioremap_resource(pdev, 0);
448 if (IS_ERR(info->regs))
449 return PTR_ERR(info->regs);
450
451 /*
452 * The reset should be an optional property, as it should work
453 * with old devicetrees as well
454 */
455 info->reset = devm_reset_control_get_exclusive(&pdev->dev,
456 "saradc-apb");
457 if (IS_ERR(info->reset)) {
458 ret = PTR_ERR(info->reset);
459 if (ret != -ENOENT)
460 return dev_err_probe(&pdev->dev, ret,
461 "failed to get saradc-apb\n");
462
463 dev_dbg(&pdev->dev, "no reset control found\n");
464 info->reset = NULL;
465 }
466
467 init_completion(&info->completion);
468
469 irq = platform_get_irq(pdev, 0);
470 if (irq < 0)
471 return irq;
472
473 ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
474 0, dev_name(&pdev->dev), info);
475 if (ret < 0) {
476 dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
477 return ret;
478 }
479
480 info->vref = devm_regulator_get(&pdev->dev, "vref");
481 if (IS_ERR(info->vref))
482 return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
483 "failed to get regulator\n");
484
485 if (info->reset)
486 rockchip_saradc_reset_controller(info->reset);
487
488 /*
489 * Use a default value for the converter clock.
490 * This may become user-configurable in the future.
491 */
492 ret = clk_set_rate(info->clk, info->data->clk_rate);
493 if (ret < 0)
494 return dev_err_probe(&pdev->dev, ret,
495 "failed to set adc clk rate\n");
496
497 ret = regulator_enable(info->vref);
498 if (ret < 0)
499 return dev_err_probe(&pdev->dev, ret,
500 "failed to enable vref regulator\n");
501
502 ret = devm_add_action_or_reset(&pdev->dev,
503 rockchip_saradc_regulator_disable, info);
504 if (ret)
505 return dev_err_probe(&pdev->dev, ret,
506 "failed to register devm action\n");
507
508 ret = regulator_get_voltage(info->vref);
509 if (ret < 0)
510 return ret;
511
512 info->uv_vref = ret;
513
514 info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
515 if (IS_ERR(info->pclk))
516 return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
517 "failed to get pclk\n");
518
519 info->clk = devm_clk_get_enabled(&pdev->dev, "saradc");
520 if (IS_ERR(info->clk))
521 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
522 "failed to get adc clock\n");
523
524 platform_set_drvdata(pdev, indio_dev);
525
526 indio_dev->name = dev_name(&pdev->dev);
527 indio_dev->info = &rockchip_saradc_iio_info;
528 indio_dev->modes = INDIO_DIRECT_MODE;
529
530 indio_dev->channels = info->data->channels;
531 indio_dev->num_channels = info->data->num_channels;
532 ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
533 rockchip_saradc_trigger_handler,
534 NULL);
535 if (ret)
536 return ret;
537
538 info->nb.notifier_call = rockchip_saradc_volt_notify;
539 ret = regulator_register_notifier(info->vref, &info->nb);
540 if (ret)
541 return ret;
542
543 ret = devm_add_action_or_reset(&pdev->dev,
544 rockchip_saradc_regulator_unreg_notifier,
545 info);
546 if (ret)
547 return ret;
548
549 mutex_init(&info->lock);
550
551 return devm_iio_device_register(&pdev->dev, indio_dev);
552 }
553
rockchip_saradc_suspend(struct device * dev)554 static int rockchip_saradc_suspend(struct device *dev)
555 {
556 struct iio_dev *indio_dev = dev_get_drvdata(dev);
557 struct rockchip_saradc *info = iio_priv(indio_dev);
558
559 clk_disable_unprepare(info->clk);
560 clk_disable_unprepare(info->pclk);
561 regulator_disable(info->vref);
562
563 return 0;
564 }
565
rockchip_saradc_resume(struct device * dev)566 static int rockchip_saradc_resume(struct device *dev)
567 {
568 struct iio_dev *indio_dev = dev_get_drvdata(dev);
569 struct rockchip_saradc *info = iio_priv(indio_dev);
570 int ret;
571
572 ret = regulator_enable(info->vref);
573 if (ret)
574 return ret;
575
576 ret = clk_prepare_enable(info->pclk);
577 if (ret)
578 return ret;
579
580 ret = clk_prepare_enable(info->clk);
581 if (ret)
582 clk_disable_unprepare(info->pclk);
583
584 return ret;
585 }
586
587 static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
588 rockchip_saradc_suspend,
589 rockchip_saradc_resume);
590
591 static struct platform_driver rockchip_saradc_driver = {
592 .probe = rockchip_saradc_probe,
593 .driver = {
594 .name = "rockchip-saradc",
595 .of_match_table = rockchip_saradc_match,
596 .pm = pm_sleep_ptr(&rockchip_saradc_pm_ops),
597 },
598 };
599
600 module_platform_driver(rockchip_saradc_driver);
601
602 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
603 MODULE_DESCRIPTION("Rockchip SARADC driver");
604 MODULE_LICENSE("GPL v2");
605