1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2014, Sony Mobile Communications AB.
5 *
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/atomic.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dmapool.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/interconnect.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/scatterlist.h>
25
26 /* QUP Registers */
27 #define QUP_CONFIG 0x000
28 #define QUP_STATE 0x004
29 #define QUP_IO_MODE 0x008
30 #define QUP_SW_RESET 0x00c
31 #define QUP_OPERATIONAL 0x018
32 #define QUP_ERROR_FLAGS 0x01c
33 #define QUP_ERROR_FLAGS_EN 0x020
34 #define QUP_OPERATIONAL_MASK 0x028
35 #define QUP_HW_VERSION 0x030
36 #define QUP_MX_OUTPUT_CNT 0x100
37 #define QUP_OUT_FIFO_BASE 0x110
38 #define QUP_MX_WRITE_CNT 0x150
39 #define QUP_MX_INPUT_CNT 0x200
40 #define QUP_MX_READ_CNT 0x208
41 #define QUP_IN_FIFO_BASE 0x218
42 #define QUP_I2C_CLK_CTL 0x400
43 #define QUP_I2C_STATUS 0x404
44 #define QUP_I2C_MASTER_GEN 0x408
45
46 /* QUP States and reset values */
47 #define QUP_RESET_STATE 0
48 #define QUP_RUN_STATE 1
49 #define QUP_PAUSE_STATE 3
50 #define QUP_STATE_MASK 3
51
52 #define QUP_STATE_VALID BIT(2)
53 #define QUP_I2C_MAST_GEN BIT(4)
54 #define QUP_I2C_FLUSH BIT(6)
55
56 #define QUP_OPERATIONAL_RESET 0x000ff0
57 #define QUP_I2C_STATUS_RESET 0xfffffc
58
59 /* QUP OPERATIONAL FLAGS */
60 #define QUP_I2C_NACK_FLAG BIT(3)
61 #define QUP_OUT_NOT_EMPTY BIT(4)
62 #define QUP_IN_NOT_EMPTY BIT(5)
63 #define QUP_OUT_FULL BIT(6)
64 #define QUP_OUT_SVC_FLAG BIT(8)
65 #define QUP_IN_SVC_FLAG BIT(9)
66 #define QUP_MX_OUTPUT_DONE BIT(10)
67 #define QUP_MX_INPUT_DONE BIT(11)
68 #define OUT_BLOCK_WRITE_REQ BIT(12)
69 #define IN_BLOCK_READ_REQ BIT(13)
70
71 /* I2C mini core related values */
72 #define QUP_NO_INPUT BIT(7)
73 #define QUP_CLOCK_AUTO_GATE BIT(13)
74 #define I2C_MINI_CORE (2 << 8)
75 #define I2C_N_VAL 15
76 #define I2C_N_VAL_V2 7
77
78 /* Most significant word offset in FIFO port */
79 #define QUP_MSW_SHIFT (I2C_N_VAL + 1)
80
81 /* Packing/Unpacking words in FIFOs, and IO modes */
82 #define QUP_OUTPUT_BLK_MODE (1 << 10)
83 #define QUP_OUTPUT_BAM_MODE (3 << 10)
84 #define QUP_INPUT_BLK_MODE (1 << 12)
85 #define QUP_INPUT_BAM_MODE (3 << 12)
86 #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
87 #define QUP_UNPACK_EN BIT(14)
88 #define QUP_PACK_EN BIT(15)
89
90 #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
91 #define QUP_V2_TAGS_EN 1
92
93 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
94 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
95 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
96 #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
97
98 /* QUP tags */
99 #define QUP_TAG_START (1 << 8)
100 #define QUP_TAG_DATA (2 << 8)
101 #define QUP_TAG_STOP (3 << 8)
102 #define QUP_TAG_REC (4 << 8)
103 #define QUP_BAM_INPUT_EOT 0x93
104 #define QUP_BAM_FLUSH_STOP 0x96
105
106 /* QUP v2 tags */
107 #define QUP_TAG_V2_START 0x81
108 #define QUP_TAG_V2_DATAWR 0x82
109 #define QUP_TAG_V2_DATAWR_STOP 0x83
110 #define QUP_TAG_V2_DATARD 0x85
111 #define QUP_TAG_V2_DATARD_NACK 0x86
112 #define QUP_TAG_V2_DATARD_STOP 0x87
113
114 /* Status, Error flags */
115 #define I2C_STATUS_WR_BUFFER_FULL BIT(0)
116 #define I2C_STATUS_BUS_ACTIVE BIT(8)
117 #define I2C_STATUS_ERROR_MASK 0x38000fc
118 #define QUP_STATUS_ERROR_FLAGS 0x7c
119
120 #define QUP_READ_LIMIT 256
121 #define SET_BIT 0x1
122 #define RESET_BIT 0x0
123 #define ONE_BYTE 0x1
124 #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
125
126 /* Maximum transfer length for single DMA descriptor */
127 #define MX_TX_RX_LEN SZ_64K
128 #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
129 /* Maximum transfer length for all DMA descriptors */
130 #define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN)
131 #define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT)
132
133 /*
134 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
135 * the top of maximum transfer time calculated from i2c bus speed to compensate
136 * the overheads.
137 */
138 #define TOUT_MIN 2
139
140 /* Default values. Use these if FW query fails */
141 #define DEFAULT_CLK_FREQ I2C_MAX_STANDARD_MODE_FREQ
142 #define DEFAULT_SRC_CLK 20000000
143
144 /*
145 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
146 * data transfer
147 */
148 #define QUP_MAX_TAGS_LEN 4
149 /* Max data length for each DATARD tags */
150 #define RECV_MAX_DATA_LEN 254
151 /* TAG length for DATA READ in RX FIFO */
152 #define READ_RX_TAGS_LEN 2
153
154 #define QUP_BUS_WIDTH 8
155
156 static unsigned int scl_freq;
157 module_param_named(scl_freq, scl_freq, uint, 0444);
158 MODULE_PARM_DESC(scl_freq, "SCL frequency override");
159
160 /*
161 * count: no of blocks
162 * pos: current block number
163 * tx_tag_len: tx tag length for current block
164 * rx_tag_len: rx tag length for current block
165 * data_len: remaining data length for current message
166 * cur_blk_len: data length for current block
167 * total_tx_len: total tx length including tag bytes for current QUP transfer
168 * total_rx_len: total rx length including tag bytes for current QUP transfer
169 * tx_fifo_data_pos: current byte number in TX FIFO word
170 * tx_fifo_free: number of free bytes in current QUP block write.
171 * rx_fifo_data_pos: current byte number in RX FIFO word
172 * fifo_available: number of available bytes in RX FIFO for current
173 * QUP block read
174 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
175 * to TX FIFO will be appended in this data and will be written to
176 * TX FIFO when all the 4 bytes are available.
177 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
178 * contains the 4 bytes of RX data.
179 * cur_data: pointer to tell cur data position for current message
180 * cur_tx_tags: pointer to tell cur position in tags
181 * tx_tags_sent: all tx tag bytes have been written in FIFO word
182 * send_last_word: for tx FIFO, last word send is pending in current block
183 * rx_bytes_read: if all the bytes have been read from rx FIFO.
184 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word
185 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
186 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
187 * tags: contains tx tag bytes for current QUP transfer
188 */
189 struct qup_i2c_block {
190 int count;
191 int pos;
192 int tx_tag_len;
193 int rx_tag_len;
194 int data_len;
195 int cur_blk_len;
196 int total_tx_len;
197 int total_rx_len;
198 int tx_fifo_data_pos;
199 int tx_fifo_free;
200 int rx_fifo_data_pos;
201 int fifo_available;
202 u32 tx_fifo_data;
203 u32 rx_fifo_data;
204 u8 *cur_data;
205 u8 *cur_tx_tags;
206 bool tx_tags_sent;
207 bool send_last_word;
208 bool rx_tags_fetched;
209 bool rx_bytes_read;
210 bool is_tx_blk_mode;
211 bool is_rx_blk_mode;
212 u8 tags[6];
213 };
214
215 struct qup_i2c_tag {
216 u8 *start;
217 dma_addr_t addr;
218 };
219
220 struct qup_i2c_bam {
221 struct qup_i2c_tag tag;
222 struct dma_chan *dma;
223 struct scatterlist *sg;
224 unsigned int sg_cnt;
225 };
226
227 struct qup_i2c_dev {
228 struct device *dev;
229 void __iomem *base;
230 int irq;
231 struct clk *clk;
232 struct clk *pclk;
233 struct icc_path *icc_path;
234 struct i2c_adapter adap;
235
236 int clk_ctl;
237 int out_fifo_sz;
238 int in_fifo_sz;
239 int out_blk_sz;
240 int in_blk_sz;
241
242 int blk_xfer_limit;
243 unsigned long one_byte_t;
244 unsigned long xfer_timeout;
245 struct qup_i2c_block blk;
246
247 struct i2c_msg *msg;
248 /* Current posion in user message buffer */
249 int pos;
250 /* I2C protocol errors */
251 u32 bus_err;
252 /* QUP core errors */
253 u32 qup_err;
254
255 /* To check if this is the last msg */
256 bool is_last;
257 bool is_smbus_read;
258
259 /* To configure when bus is in run state */
260 u32 config_run;
261
262 /* bandwidth votes */
263 u32 src_clk_freq;
264 u32 cur_bw_clk_freq;
265
266 /* dma parameters */
267 bool is_dma;
268 /* To check if the current transfer is using DMA */
269 bool use_dma;
270 unsigned int max_xfer_sg_len;
271 unsigned int tag_buf_pos;
272 /* The threshold length above which block mode will be used */
273 unsigned int blk_mode_threshold;
274 struct dma_pool *dpool;
275 struct qup_i2c_tag start_tag;
276 struct qup_i2c_bam brx;
277 struct qup_i2c_bam btx;
278
279 struct completion xfer;
280 /* function to write data in tx fifo */
281 void (*write_tx_fifo)(struct qup_i2c_dev *qup);
282 /* function to read data from rx fifo */
283 void (*read_rx_fifo)(struct qup_i2c_dev *qup);
284 /* function to write tags in tx fifo for i2c read transfer */
285 void (*write_rx_tags)(struct qup_i2c_dev *qup);
286 };
287
qup_i2c_interrupt(int irq,void * dev)288 static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
289 {
290 struct qup_i2c_dev *qup = dev;
291 struct qup_i2c_block *blk = &qup->blk;
292 u32 bus_err;
293 u32 qup_err;
294 u32 opflags;
295
296 bus_err = readl(qup->base + QUP_I2C_STATUS);
297 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
298 opflags = readl(qup->base + QUP_OPERATIONAL);
299
300 if (!qup->msg) {
301 /* Clear Error interrupt */
302 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
303 return IRQ_HANDLED;
304 }
305
306 bus_err &= I2C_STATUS_ERROR_MASK;
307 qup_err &= QUP_STATUS_ERROR_FLAGS;
308
309 /* Clear the error bits in QUP_ERROR_FLAGS */
310 if (qup_err)
311 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
312
313 /* Clear the error bits in QUP_I2C_STATUS */
314 if (bus_err)
315 writel(bus_err, qup->base + QUP_I2C_STATUS);
316
317 /*
318 * Check for BAM mode and returns if already error has come for current
319 * transfer. In Error case, sometimes, QUP generates more than one
320 * interrupt.
321 */
322 if (qup->use_dma && (qup->qup_err || qup->bus_err))
323 return IRQ_HANDLED;
324
325 /* Reset the QUP State in case of error */
326 if (qup_err || bus_err) {
327 /*
328 * Don’t reset the QUP state in case of BAM mode. The BAM
329 * flush operation needs to be scheduled in transfer function
330 * which will clear the remaining schedule descriptors in BAM
331 * HW FIFO and generates the BAM interrupt.
332 */
333 if (!qup->use_dma)
334 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
335 goto done;
336 }
337
338 if (opflags & QUP_OUT_SVC_FLAG) {
339 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
340
341 if (opflags & OUT_BLOCK_WRITE_REQ) {
342 blk->tx_fifo_free += qup->out_blk_sz;
343 if (qup->msg->flags & I2C_M_RD)
344 qup->write_rx_tags(qup);
345 else
346 qup->write_tx_fifo(qup);
347 }
348 }
349
350 if (opflags & QUP_IN_SVC_FLAG) {
351 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
352
353 if (!blk->is_rx_blk_mode) {
354 blk->fifo_available += qup->in_fifo_sz;
355 qup->read_rx_fifo(qup);
356 } else if (opflags & IN_BLOCK_READ_REQ) {
357 blk->fifo_available += qup->in_blk_sz;
358 qup->read_rx_fifo(qup);
359 }
360 }
361
362 if (qup->msg->flags & I2C_M_RD) {
363 if (!blk->rx_bytes_read)
364 return IRQ_HANDLED;
365 } else {
366 /*
367 * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
368 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
369 * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
370 * of interrupt for write message in FIFO mode is
371 * QUP_MAX_OUTPUT_DONE_FLAG condition.
372 */
373 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
374 return IRQ_HANDLED;
375 }
376
377 done:
378 qup->qup_err = qup_err;
379 qup->bus_err = bus_err;
380 complete(&qup->xfer);
381 return IRQ_HANDLED;
382 }
383
qup_i2c_poll_state_mask(struct qup_i2c_dev * qup,u32 req_state,u32 req_mask)384 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
385 u32 req_state, u32 req_mask)
386 {
387 int retries = 1;
388 u32 state;
389
390 /*
391 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
392 * cycles. So retry once after a 1uS delay.
393 */
394 do {
395 state = readl(qup->base + QUP_STATE);
396
397 if (state & QUP_STATE_VALID &&
398 (state & req_mask) == req_state)
399 return 0;
400
401 udelay(1);
402 } while (retries--);
403
404 return -ETIMEDOUT;
405 }
406
qup_i2c_poll_state(struct qup_i2c_dev * qup,u32 req_state)407 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
408 {
409 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
410 }
411
qup_i2c_flush(struct qup_i2c_dev * qup)412 static void qup_i2c_flush(struct qup_i2c_dev *qup)
413 {
414 u32 val = readl(qup->base + QUP_STATE);
415
416 val |= QUP_I2C_FLUSH;
417 writel(val, qup->base + QUP_STATE);
418 }
419
qup_i2c_poll_state_valid(struct qup_i2c_dev * qup)420 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
421 {
422 return qup_i2c_poll_state_mask(qup, 0, 0);
423 }
424
qup_i2c_poll_state_i2c_master(struct qup_i2c_dev * qup)425 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
426 {
427 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
428 }
429
qup_i2c_change_state(struct qup_i2c_dev * qup,u32 state)430 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
431 {
432 if (qup_i2c_poll_state_valid(qup) != 0)
433 return -EIO;
434
435 writel(state, qup->base + QUP_STATE);
436
437 if (qup_i2c_poll_state(qup, state) != 0)
438 return -EIO;
439 return 0;
440 }
441
442 /* Check if I2C bus returns to IDLE state */
qup_i2c_bus_active(struct qup_i2c_dev * qup,int len)443 static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
444 {
445 unsigned long timeout;
446 u32 status;
447 int ret = 0;
448
449 timeout = jiffies + len * 4;
450 for (;;) {
451 status = readl(qup->base + QUP_I2C_STATUS);
452 if (!(status & I2C_STATUS_BUS_ACTIVE))
453 break;
454
455 if (time_after(jiffies, timeout)) {
456 ret = -ETIMEDOUT;
457 break;
458 }
459
460 usleep_range(len, len * 2);
461 }
462
463 return ret;
464 }
465
qup_i2c_vote_bw(struct qup_i2c_dev * qup,u32 clk_freq)466 static int qup_i2c_vote_bw(struct qup_i2c_dev *qup, u32 clk_freq)
467 {
468 u32 needed_peak_bw;
469 int ret;
470
471 if (qup->cur_bw_clk_freq == clk_freq)
472 return 0;
473
474 needed_peak_bw = Bps_to_icc(clk_freq * QUP_BUS_WIDTH);
475 ret = icc_set_bw(qup->icc_path, 0, needed_peak_bw);
476 if (ret)
477 return ret;
478
479 qup->cur_bw_clk_freq = clk_freq;
480 return 0;
481 }
482
qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev * qup)483 static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
484 {
485 struct qup_i2c_block *blk = &qup->blk;
486 struct i2c_msg *msg = qup->msg;
487 u32 addr = i2c_8bit_addr_from_msg(msg);
488 u32 qup_tag;
489 int idx;
490 u32 val;
491
492 if (qup->pos == 0) {
493 val = QUP_TAG_START | addr;
494 idx = 1;
495 blk->tx_fifo_free--;
496 } else {
497 val = 0;
498 idx = 0;
499 }
500
501 while (blk->tx_fifo_free && qup->pos < msg->len) {
502 if (qup->pos == msg->len - 1)
503 qup_tag = QUP_TAG_STOP;
504 else
505 qup_tag = QUP_TAG_DATA;
506
507 if (idx & 1)
508 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
509 else
510 val = qup_tag | msg->buf[qup->pos];
511
512 /* Write out the pair and the last odd value */
513 if (idx & 1 || qup->pos == msg->len - 1)
514 writel(val, qup->base + QUP_OUT_FIFO_BASE);
515
516 qup->pos++;
517 idx++;
518 blk->tx_fifo_free--;
519 }
520 }
521
qup_i2c_set_blk_data(struct qup_i2c_dev * qup,struct i2c_msg * msg)522 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
523 struct i2c_msg *msg)
524 {
525 qup->blk.pos = 0;
526 qup->blk.data_len = msg->len;
527 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit);
528 }
529
qup_i2c_get_data_len(struct qup_i2c_dev * qup)530 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
531 {
532 int data_len;
533
534 if (qup->blk.data_len > qup->blk_xfer_limit)
535 data_len = qup->blk_xfer_limit;
536 else
537 data_len = qup->blk.data_len;
538
539 return data_len;
540 }
541
qup_i2c_check_msg_len(struct i2c_msg * msg)542 static bool qup_i2c_check_msg_len(struct i2c_msg *msg)
543 {
544 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN));
545 }
546
qup_i2c_set_tags_smb(u16 addr,u8 * tags,struct qup_i2c_dev * qup,struct i2c_msg * msg)547 static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup,
548 struct i2c_msg *msg)
549 {
550 int len = 0;
551
552 if (qup->is_smbus_read) {
553 tags[len++] = QUP_TAG_V2_DATARD_STOP;
554 tags[len++] = qup_i2c_get_data_len(qup);
555 } else {
556 tags[len++] = QUP_TAG_V2_START;
557 tags[len++] = addr & 0xff;
558
559 if (msg->flags & I2C_M_TEN)
560 tags[len++] = addr >> 8;
561
562 tags[len++] = QUP_TAG_V2_DATARD;
563 /* Read 1 byte indicating the length of the SMBus message */
564 tags[len++] = 1;
565 }
566 return len;
567 }
568
qup_i2c_set_tags(u8 * tags,struct qup_i2c_dev * qup,struct i2c_msg * msg)569 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
570 struct i2c_msg *msg)
571 {
572 u16 addr = i2c_8bit_addr_from_msg(msg);
573 int len = 0;
574 int data_len;
575
576 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
577
578 /* Handle tags for SMBus block read */
579 if (qup_i2c_check_msg_len(msg))
580 return qup_i2c_set_tags_smb(addr, tags, qup, msg);
581
582 if (qup->blk.pos == 0) {
583 tags[len++] = QUP_TAG_V2_START;
584 tags[len++] = addr & 0xff;
585
586 if (msg->flags & I2C_M_TEN)
587 tags[len++] = addr >> 8;
588 }
589
590 /* Send _STOP commands for the last block */
591 if (last) {
592 if (msg->flags & I2C_M_RD)
593 tags[len++] = QUP_TAG_V2_DATARD_STOP;
594 else
595 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
596 } else {
597 if (msg->flags & I2C_M_RD)
598 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ?
599 QUP_TAG_V2_DATARD_NACK :
600 QUP_TAG_V2_DATARD;
601 else
602 tags[len++] = QUP_TAG_V2_DATAWR;
603 }
604
605 data_len = qup_i2c_get_data_len(qup);
606
607 /* 0 implies 256 bytes */
608 if (data_len == QUP_READ_LIMIT)
609 tags[len++] = 0;
610 else
611 tags[len++] = data_len;
612
613 return len;
614 }
615
616
qup_i2c_bam_cb(void * data)617 static void qup_i2c_bam_cb(void *data)
618 {
619 struct qup_i2c_dev *qup = data;
620
621 complete(&qup->xfer);
622 }
623
qup_sg_set_buf(struct scatterlist * sg,void * buf,unsigned int buflen,struct qup_i2c_dev * qup,int dir)624 static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
625 unsigned int buflen, struct qup_i2c_dev *qup,
626 int dir)
627 {
628 int ret;
629
630 sg_set_buf(sg, buf, buflen);
631 ret = dma_map_sg(qup->dev, sg, 1, dir);
632 if (!ret)
633 return -EINVAL;
634
635 return 0;
636 }
637
qup_i2c_rel_dma(struct qup_i2c_dev * qup)638 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
639 {
640 if (qup->btx.dma)
641 dma_release_channel(qup->btx.dma);
642 if (qup->brx.dma)
643 dma_release_channel(qup->brx.dma);
644 qup->btx.dma = NULL;
645 qup->brx.dma = NULL;
646 }
647
qup_i2c_req_dma(struct qup_i2c_dev * qup)648 static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
649 {
650 int err;
651
652 if (!qup->btx.dma) {
653 qup->btx.dma = dma_request_chan(qup->dev, "tx");
654 if (IS_ERR(qup->btx.dma)) {
655 err = PTR_ERR(qup->btx.dma);
656 qup->btx.dma = NULL;
657 dev_err(qup->dev, "\n tx channel not available");
658 return err;
659 }
660 }
661
662 if (!qup->brx.dma) {
663 qup->brx.dma = dma_request_chan(qup->dev, "rx");
664 if (IS_ERR(qup->brx.dma)) {
665 dev_err(qup->dev, "\n rx channel not available");
666 err = PTR_ERR(qup->brx.dma);
667 qup->brx.dma = NULL;
668 qup_i2c_rel_dma(qup);
669 return err;
670 }
671 }
672 return 0;
673 }
674
qup_i2c_bam_make_desc(struct qup_i2c_dev * qup,struct i2c_msg * msg)675 static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)
676 {
677 int ret = 0, limit = QUP_READ_LIMIT;
678 u32 len = 0, blocks, rem;
679 u32 i = 0, tlen, tx_len = 0;
680 u8 *tags;
681
682 qup->blk_xfer_limit = QUP_READ_LIMIT;
683 qup_i2c_set_blk_data(qup, msg);
684
685 blocks = qup->blk.count;
686 rem = msg->len - (blocks - 1) * limit;
687
688 if (msg->flags & I2C_M_RD) {
689 while (qup->blk.pos < blocks) {
690 tlen = (i == (blocks - 1)) ? rem : limit;
691 tags = &qup->start_tag.start[qup->tag_buf_pos + len];
692 len += qup_i2c_set_tags(tags, qup, msg);
693 qup->blk.data_len -= tlen;
694
695 /* scratch buf to read the start and len tags */
696 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
697 &qup->brx.tag.start[0],
698 2, qup, DMA_FROM_DEVICE);
699
700 if (ret)
701 return ret;
702
703 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
704 &msg->buf[limit * i],
705 tlen, qup,
706 DMA_FROM_DEVICE);
707 if (ret)
708 return ret;
709
710 i++;
711 qup->blk.pos = i;
712 }
713 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
714 &qup->start_tag.start[qup->tag_buf_pos],
715 len, qup, DMA_TO_DEVICE);
716 if (ret)
717 return ret;
718
719 qup->tag_buf_pos += len;
720 } else {
721 while (qup->blk.pos < blocks) {
722 tlen = (i == (blocks - 1)) ? rem : limit;
723 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len];
724 len = qup_i2c_set_tags(tags, qup, msg);
725 qup->blk.data_len -= tlen;
726
727 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
728 tags, len,
729 qup, DMA_TO_DEVICE);
730 if (ret)
731 return ret;
732
733 tx_len += len;
734 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
735 &msg->buf[limit * i],
736 tlen, qup, DMA_TO_DEVICE);
737 if (ret)
738 return ret;
739 i++;
740 qup->blk.pos = i;
741 }
742
743 qup->tag_buf_pos += tx_len;
744 }
745
746 return 0;
747 }
748
qup_i2c_bam_schedule_desc(struct qup_i2c_dev * qup)749 static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup)
750 {
751 struct dma_async_tx_descriptor *txd, *rxd = NULL;
752 int ret = 0;
753 dma_cookie_t cookie_rx, cookie_tx;
754 u32 len = 0;
755 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt;
756
757 /* schedule the EOT and FLUSH I2C tags */
758 len = 1;
759 if (rx_cnt) {
760 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT;
761 len++;
762
763 /* scratch buf to read the BAM EOT FLUSH tags */
764 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
765 &qup->brx.tag.start[0],
766 1, qup, DMA_FROM_DEVICE);
767 if (ret)
768 return ret;
769 }
770
771 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP;
772 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0],
773 len, qup, DMA_TO_DEVICE);
774 if (ret)
775 return ret;
776
777 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
778 DMA_MEM_TO_DEV,
779 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
780 if (!txd) {
781 dev_err(qup->dev, "failed to get tx desc\n");
782 ret = -EINVAL;
783 goto desc_err;
784 }
785
786 if (!rx_cnt) {
787 txd->callback = qup_i2c_bam_cb;
788 txd->callback_param = qup;
789 }
790
791 cookie_tx = dmaengine_submit(txd);
792 if (dma_submit_error(cookie_tx)) {
793 ret = -EINVAL;
794 goto desc_err;
795 }
796
797 dma_async_issue_pending(qup->btx.dma);
798
799 if (rx_cnt) {
800 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
801 rx_cnt, DMA_DEV_TO_MEM,
802 DMA_PREP_INTERRUPT);
803 if (!rxd) {
804 dev_err(qup->dev, "failed to get rx desc\n");
805 ret = -EINVAL;
806
807 /* abort TX descriptors */
808 dmaengine_terminate_sync(qup->btx.dma);
809 goto desc_err;
810 }
811
812 rxd->callback = qup_i2c_bam_cb;
813 rxd->callback_param = qup;
814 cookie_rx = dmaengine_submit(rxd);
815 if (dma_submit_error(cookie_rx)) {
816 ret = -EINVAL;
817 goto desc_err;
818 }
819
820 dma_async_issue_pending(qup->brx.dma);
821 }
822
823 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) {
824 dev_err(qup->dev, "normal trans timed out\n");
825 ret = -ETIMEDOUT;
826 }
827
828 if (ret || qup->bus_err || qup->qup_err) {
829 reinit_completion(&qup->xfer);
830
831 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
832 if (ret) {
833 dev_err(qup->dev, "change to run state timed out");
834 goto desc_err;
835 }
836
837 qup_i2c_flush(qup);
838
839 /* wait for remaining interrupts to occur */
840 if (!wait_for_completion_timeout(&qup->xfer, HZ))
841 dev_err(qup->dev, "flush timed out\n");
842
843 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
844 }
845
846 desc_err:
847 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE);
848
849 if (rx_cnt)
850 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt,
851 DMA_FROM_DEVICE);
852
853 return ret;
854 }
855
qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev * qup)856 static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup)
857 {
858 qup->btx.sg_cnt = 0;
859 qup->brx.sg_cnt = 0;
860 qup->tag_buf_pos = 0;
861 }
862
qup_i2c_bam_xfer(struct i2c_adapter * adap,struct i2c_msg * msg,int num)863 static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
864 int num)
865 {
866 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
867 int ret = 0;
868 int idx = 0;
869
870 ret = qup_i2c_vote_bw(qup, qup->src_clk_freq);
871 if (ret)
872 return ret;
873
874 enable_irq(qup->irq);
875 ret = qup_i2c_req_dma(qup);
876
877 if (ret)
878 goto out;
879
880 writel(0, qup->base + QUP_MX_INPUT_CNT);
881 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
882
883 /* set BAM mode */
884 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
885
886 /* mask fifo irqs */
887 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
888
889 /* set RUN STATE */
890 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
891 if (ret)
892 goto out;
893
894 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
895 qup_i2c_bam_clear_tag_buffers(qup);
896
897 for (idx = 0; idx < num; idx++) {
898 qup->msg = msg + idx;
899 qup->is_last = idx == (num - 1);
900
901 ret = qup_i2c_bam_make_desc(qup, qup->msg);
902 if (ret)
903 break;
904
905 /*
906 * Make DMA descriptor and schedule the BAM transfer if its
907 * already crossed the maximum length. Since the memory for all
908 * tags buffers have been taken for 2 maximum possible
909 * transfers length so it will never cross the buffer actual
910 * length.
911 */
912 if (qup->btx.sg_cnt > qup->max_xfer_sg_len ||
913 qup->brx.sg_cnt > qup->max_xfer_sg_len ||
914 qup->is_last) {
915 ret = qup_i2c_bam_schedule_desc(qup);
916 if (ret)
917 break;
918
919 qup_i2c_bam_clear_tag_buffers(qup);
920 }
921 }
922
923 out:
924 disable_irq(qup->irq);
925
926 qup->msg = NULL;
927 return ret;
928 }
929
qup_i2c_wait_for_complete(struct qup_i2c_dev * qup,struct i2c_msg * msg)930 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
931 struct i2c_msg *msg)
932 {
933 unsigned long left;
934 int ret = 0;
935
936 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout);
937 if (!left) {
938 writel(1, qup->base + QUP_SW_RESET);
939 ret = -ETIMEDOUT;
940 }
941
942 if (qup->bus_err || qup->qup_err)
943 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
944
945 return ret;
946 }
947
qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev * qup)948 static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
949 {
950 struct qup_i2c_block *blk = &qup->blk;
951 struct i2c_msg *msg = qup->msg;
952 u32 val = 0;
953 int idx = 0;
954
955 while (blk->fifo_available && qup->pos < msg->len) {
956 if ((idx & 1) == 0) {
957 /* Reading 2 words at time */
958 val = readl(qup->base + QUP_IN_FIFO_BASE);
959 msg->buf[qup->pos++] = val & 0xFF;
960 } else {
961 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
962 }
963 idx++;
964 blk->fifo_available--;
965 }
966
967 if (qup->pos == msg->len)
968 blk->rx_bytes_read = true;
969 }
970
qup_i2c_write_rx_tags_v1(struct qup_i2c_dev * qup)971 static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
972 {
973 struct i2c_msg *msg = qup->msg;
974 u32 addr, len, val;
975
976 addr = i2c_8bit_addr_from_msg(msg);
977
978 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
979 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
980
981 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
982 writel(val, qup->base + QUP_OUT_FIFO_BASE);
983 }
984
qup_i2c_conf_v1(struct qup_i2c_dev * qup)985 static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
986 {
987 struct qup_i2c_block *blk = &qup->blk;
988 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
989 u32 io_mode = QUP_REPACK_EN;
990
991 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz;
992 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz;
993
994 if (blk->is_tx_blk_mode) {
995 io_mode |= QUP_OUTPUT_BLK_MODE;
996 writel(0, qup->base + QUP_MX_WRITE_CNT);
997 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
998 } else {
999 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
1000 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
1001 }
1002
1003 if (blk->total_rx_len) {
1004 if (blk->is_rx_blk_mode) {
1005 io_mode |= QUP_INPUT_BLK_MODE;
1006 writel(0, qup->base + QUP_MX_READ_CNT);
1007 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
1008 } else {
1009 writel(0, qup->base + QUP_MX_INPUT_CNT);
1010 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
1011 }
1012 } else {
1013 qup_config |= QUP_NO_INPUT;
1014 }
1015
1016 writel(qup_config, qup->base + QUP_CONFIG);
1017 writel(io_mode, qup->base + QUP_IO_MODE);
1018 }
1019
qup_i2c_clear_blk_v1(struct qup_i2c_block * blk)1020 static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
1021 {
1022 blk->tx_fifo_free = 0;
1023 blk->fifo_available = 0;
1024 blk->rx_bytes_read = false;
1025 }
1026
qup_i2c_conf_xfer_v1(struct qup_i2c_dev * qup,bool is_rx)1027 static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
1028 {
1029 struct qup_i2c_block *blk = &qup->blk;
1030 int ret;
1031
1032 qup_i2c_clear_blk_v1(blk);
1033 qup_i2c_conf_v1(qup);
1034 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1035 if (ret)
1036 return ret;
1037
1038 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1039
1040 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1041 if (ret)
1042 return ret;
1043
1044 reinit_completion(&qup->xfer);
1045 enable_irq(qup->irq);
1046 if (!blk->is_tx_blk_mode) {
1047 blk->tx_fifo_free = qup->out_fifo_sz;
1048
1049 if (is_rx)
1050 qup_i2c_write_rx_tags_v1(qup);
1051 else
1052 qup_i2c_write_tx_fifo_v1(qup);
1053 }
1054
1055 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1056 if (ret)
1057 goto err;
1058
1059 ret = qup_i2c_wait_for_complete(qup, qup->msg);
1060 if (ret)
1061 goto err;
1062
1063 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1064
1065 err:
1066 disable_irq(qup->irq);
1067 return ret;
1068 }
1069
qup_i2c_write_one(struct qup_i2c_dev * qup)1070 static int qup_i2c_write_one(struct qup_i2c_dev *qup)
1071 {
1072 struct i2c_msg *msg = qup->msg;
1073 struct qup_i2c_block *blk = &qup->blk;
1074
1075 qup->pos = 0;
1076 blk->total_tx_len = msg->len + 1;
1077 blk->total_rx_len = 0;
1078
1079 return qup_i2c_conf_xfer_v1(qup, false);
1080 }
1081
qup_i2c_read_one(struct qup_i2c_dev * qup)1082 static int qup_i2c_read_one(struct qup_i2c_dev *qup)
1083 {
1084 struct qup_i2c_block *blk = &qup->blk;
1085
1086 qup->pos = 0;
1087 blk->total_tx_len = 2;
1088 blk->total_rx_len = qup->msg->len;
1089
1090 return qup_i2c_conf_xfer_v1(qup, true);
1091 }
1092
qup_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1093 static int qup_i2c_xfer(struct i2c_adapter *adap,
1094 struct i2c_msg msgs[],
1095 int num)
1096 {
1097 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1098 int ret, idx;
1099
1100 ret = pm_runtime_get_sync(qup->dev);
1101 if (ret < 0)
1102 goto out;
1103
1104 qup->bus_err = 0;
1105 qup->qup_err = 0;
1106
1107 writel(1, qup->base + QUP_SW_RESET);
1108 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1109 if (ret)
1110 goto out;
1111
1112 /* Configure QUP as I2C mini core */
1113 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1114
1115 for (idx = 0; idx < num; idx++) {
1116 if (qup_i2c_poll_state_i2c_master(qup)) {
1117 ret = -EIO;
1118 goto out;
1119 }
1120
1121 if (qup_i2c_check_msg_len(&msgs[idx])) {
1122 ret = -EINVAL;
1123 goto out;
1124 }
1125
1126 qup->msg = &msgs[idx];
1127 if (msgs[idx].flags & I2C_M_RD)
1128 ret = qup_i2c_read_one(qup);
1129 else
1130 ret = qup_i2c_write_one(qup);
1131
1132 if (ret)
1133 break;
1134
1135 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1136 if (ret)
1137 break;
1138 }
1139
1140 if (ret == 0)
1141 ret = num;
1142 out:
1143
1144 pm_runtime_mark_last_busy(qup->dev);
1145 pm_runtime_put_autosuspend(qup->dev);
1146
1147 return ret;
1148 }
1149
1150 /*
1151 * Configure registers related with reconfiguration during run and call it
1152 * before each i2c sub transfer.
1153 */
qup_i2c_conf_count_v2(struct qup_i2c_dev * qup)1154 static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup)
1155 {
1156 struct qup_i2c_block *blk = &qup->blk;
1157 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2;
1158
1159 if (blk->is_tx_blk_mode)
1160 writel(qup->config_run | blk->total_tx_len,
1161 qup->base + QUP_MX_OUTPUT_CNT);
1162 else
1163 writel(qup->config_run | blk->total_tx_len,
1164 qup->base + QUP_MX_WRITE_CNT);
1165
1166 if (blk->total_rx_len) {
1167 if (blk->is_rx_blk_mode)
1168 writel(qup->config_run | blk->total_rx_len,
1169 qup->base + QUP_MX_INPUT_CNT);
1170 else
1171 writel(qup->config_run | blk->total_rx_len,
1172 qup->base + QUP_MX_READ_CNT);
1173 } else {
1174 qup_config |= QUP_NO_INPUT;
1175 }
1176
1177 writel(qup_config, qup->base + QUP_CONFIG);
1178 }
1179
1180 /*
1181 * Configure registers related with transfer mode (FIFO/Block)
1182 * before starting of i2c transfer. It will be called only once in
1183 * QUP RESET state.
1184 */
qup_i2c_conf_mode_v2(struct qup_i2c_dev * qup)1185 static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup)
1186 {
1187 struct qup_i2c_block *blk = &qup->blk;
1188 u32 io_mode = QUP_REPACK_EN;
1189
1190 if (blk->is_tx_blk_mode) {
1191 io_mode |= QUP_OUTPUT_BLK_MODE;
1192 writel(0, qup->base + QUP_MX_WRITE_CNT);
1193 } else {
1194 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
1195 }
1196
1197 if (blk->is_rx_blk_mode) {
1198 io_mode |= QUP_INPUT_BLK_MODE;
1199 writel(0, qup->base + QUP_MX_READ_CNT);
1200 } else {
1201 writel(0, qup->base + QUP_MX_INPUT_CNT);
1202 }
1203
1204 writel(io_mode, qup->base + QUP_IO_MODE);
1205 }
1206
1207 /* Clear required variables before starting of any QUP v2 sub transfer. */
qup_i2c_clear_blk_v2(struct qup_i2c_block * blk)1208 static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk)
1209 {
1210 blk->send_last_word = false;
1211 blk->tx_tags_sent = false;
1212 blk->tx_fifo_data = 0;
1213 blk->tx_fifo_data_pos = 0;
1214 blk->tx_fifo_free = 0;
1215
1216 blk->rx_tags_fetched = false;
1217 blk->rx_bytes_read = false;
1218 blk->rx_fifo_data = 0;
1219 blk->rx_fifo_data_pos = 0;
1220 blk->fifo_available = 0;
1221 }
1222
1223 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
qup_i2c_recv_data(struct qup_i2c_dev * qup)1224 static void qup_i2c_recv_data(struct qup_i2c_dev *qup)
1225 {
1226 struct qup_i2c_block *blk = &qup->blk;
1227 int j;
1228
1229 for (j = blk->rx_fifo_data_pos;
1230 blk->cur_blk_len && blk->fifo_available;
1231 blk->cur_blk_len--, blk->fifo_available--) {
1232 if (j == 0)
1233 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1234
1235 *(blk->cur_data++) = blk->rx_fifo_data;
1236 blk->rx_fifo_data >>= 8;
1237
1238 if (j == 3)
1239 j = 0;
1240 else
1241 j++;
1242 }
1243
1244 blk->rx_fifo_data_pos = j;
1245 }
1246
1247 /* Receive tags for read message in QUP v2 i2c transfer. */
qup_i2c_recv_tags(struct qup_i2c_dev * qup)1248 static void qup_i2c_recv_tags(struct qup_i2c_dev *qup)
1249 {
1250 struct qup_i2c_block *blk = &qup->blk;
1251
1252 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1253 blk->rx_fifo_data >>= blk->rx_tag_len * 8;
1254 blk->rx_fifo_data_pos = blk->rx_tag_len;
1255 blk->fifo_available -= blk->rx_tag_len;
1256 }
1257
1258 /*
1259 * Read the data and tags from RX FIFO. Since in read case, the tags will be
1260 * preceded by received data bytes so
1261 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
1262 * all tag bytes and discard that.
1263 * 2. Read the data from RX FIFO. When all the data bytes have been read then
1264 * set rx_bytes_read to true.
1265 */
qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev * qup)1266 static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup)
1267 {
1268 struct qup_i2c_block *blk = &qup->blk;
1269
1270 if (!blk->rx_tags_fetched) {
1271 qup_i2c_recv_tags(qup);
1272 blk->rx_tags_fetched = true;
1273 }
1274
1275 qup_i2c_recv_data(qup);
1276 if (!blk->cur_blk_len)
1277 blk->rx_bytes_read = true;
1278 }
1279
1280 /*
1281 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1282 * write works on word basis (4 bytes). Append new data byte write for TX FIFO
1283 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present.
1284 */
1285 static void
qup_i2c_write_blk_data(struct qup_i2c_dev * qup,u8 ** data,unsigned int * len)1286 qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len)
1287 {
1288 struct qup_i2c_block *blk = &qup->blk;
1289 unsigned int j;
1290
1291 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free;
1292 (*len)--, blk->tx_fifo_free--) {
1293 blk->tx_fifo_data |= *(*data)++ << (j * 8);
1294 if (j == 3) {
1295 writel(blk->tx_fifo_data,
1296 qup->base + QUP_OUT_FIFO_BASE);
1297 blk->tx_fifo_data = 0x0;
1298 j = 0;
1299 } else {
1300 j++;
1301 }
1302 }
1303
1304 blk->tx_fifo_data_pos = j;
1305 }
1306
1307 /* Transfer tags for read message in QUP v2 i2c transfer. */
qup_i2c_write_rx_tags_v2(struct qup_i2c_dev * qup)1308 static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup)
1309 {
1310 struct qup_i2c_block *blk = &qup->blk;
1311
1312 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len);
1313 if (blk->tx_fifo_data_pos)
1314 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1315 }
1316
1317 /*
1318 * Write the data and tags in TX FIFO. Since in write case, both tags and data
1319 * need to be written and QUP write tags can have maximum 256 data length, so
1320 *
1321 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
1322 * tags to TX FIFO and set tx_tags_sent to true.
1323 * 2. Check if send_last_word is true. It will be set when last few data bytes
1324 * (less than 4 bytes) are remaining to be written in FIFO because of no FIFO
1325 * space. All this data bytes are available in tx_fifo_data so write this
1326 * in FIFO.
1327 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero
1328 * then more data is pending otherwise following 3 cases can be possible
1329 * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block
1330 * have been written in TX FIFO so nothing else is required.
1331 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data
1332 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write
1333 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free
1334 * will be always greater than or equal to 4 bytes.
1335 * c. tx_fifo_free is zero. In this case, last few bytes (less than 4
1336 * bytes) are copied to tx_fifo_data but couldn't be sent because of
1337 * FIFO full so make send_last_word true.
1338 */
qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev * qup)1339 static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup)
1340 {
1341 struct qup_i2c_block *blk = &qup->blk;
1342
1343 if (!blk->tx_tags_sent) {
1344 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags,
1345 &blk->tx_tag_len);
1346 blk->tx_tags_sent = true;
1347 }
1348
1349 if (blk->send_last_word)
1350 goto send_last_word;
1351
1352 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len);
1353 if (!blk->cur_blk_len) {
1354 if (!blk->tx_fifo_data_pos)
1355 return;
1356
1357 if (blk->tx_fifo_free)
1358 goto send_last_word;
1359
1360 blk->send_last_word = true;
1361 }
1362
1363 return;
1364
1365 send_last_word:
1366 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1367 }
1368
1369 /*
1370 * Main transfer function which read or write i2c data.
1371 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1372 * transfers can be scheduled.
1373 */
1374 static int
qup_i2c_conf_xfer_v2(struct qup_i2c_dev * qup,bool is_rx,bool is_first,bool change_pause_state)1375 qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first,
1376 bool change_pause_state)
1377 {
1378 struct qup_i2c_block *blk = &qup->blk;
1379 struct i2c_msg *msg = qup->msg;
1380 int ret;
1381
1382 /*
1383 * Check if its SMBus Block read for which the top level read will be
1384 * done into 2 QUP reads. One with message length 1 while other one is
1385 * with actual length.
1386 */
1387 if (qup_i2c_check_msg_len(msg)) {
1388 if (qup->is_smbus_read) {
1389 /*
1390 * If the message length is already read in
1391 * the first byte of the buffer, account for
1392 * that by setting the offset
1393 */
1394 blk->cur_data += 1;
1395 is_first = false;
1396 } else {
1397 change_pause_state = false;
1398 }
1399 }
1400
1401 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
1402
1403 qup_i2c_clear_blk_v2(blk);
1404 qup_i2c_conf_count_v2(qup);
1405
1406 /* If it is first sub transfer, then configure i2c bus clocks */
1407 if (is_first) {
1408 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1409 if (ret)
1410 return ret;
1411
1412 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1413
1414 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1415 if (ret)
1416 return ret;
1417 }
1418
1419 reinit_completion(&qup->xfer);
1420 enable_irq(qup->irq);
1421 /*
1422 * In FIFO mode, tx FIFO can be written directly while in block mode the
1423 * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt
1424 */
1425 if (!blk->is_tx_blk_mode) {
1426 blk->tx_fifo_free = qup->out_fifo_sz;
1427
1428 if (is_rx)
1429 qup_i2c_write_rx_tags_v2(qup);
1430 else
1431 qup_i2c_write_tx_fifo_v2(qup);
1432 }
1433
1434 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1435 if (ret)
1436 goto err;
1437
1438 ret = qup_i2c_wait_for_complete(qup, msg);
1439 if (ret)
1440 goto err;
1441
1442 /* Move to pause state for all the transfers, except last one */
1443 if (change_pause_state) {
1444 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1445 if (ret)
1446 goto err;
1447 }
1448
1449 err:
1450 disable_irq(qup->irq);
1451 return ret;
1452 }
1453
1454 /*
1455 * Transfer one read/write message in i2c transfer. It splits the message into
1456 * multiple of blk_xfer_limit data length blocks and schedule each
1457 * QUP block individually.
1458 */
qup_i2c_xfer_v2_msg(struct qup_i2c_dev * qup,int msg_id,bool is_rx)1459 static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)
1460 {
1461 int ret = 0;
1462 unsigned int data_len, i;
1463 struct i2c_msg *msg = qup->msg;
1464 struct qup_i2c_block *blk = &qup->blk;
1465 u8 *msg_buf = msg->buf;
1466
1467 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT;
1468 qup_i2c_set_blk_data(qup, msg);
1469
1470 for (i = 0; i < blk->count; i++) {
1471 data_len = qup_i2c_get_data_len(qup);
1472 blk->pos = i;
1473 blk->cur_tx_tags = blk->tags;
1474 blk->cur_blk_len = data_len;
1475 blk->tx_tag_len =
1476 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg);
1477
1478 blk->cur_data = msg_buf;
1479
1480 if (is_rx) {
1481 blk->total_tx_len = blk->tx_tag_len;
1482 blk->rx_tag_len = 2;
1483 blk->total_rx_len = blk->rx_tag_len + data_len;
1484 } else {
1485 blk->total_tx_len = blk->tx_tag_len + data_len;
1486 blk->total_rx_len = 0;
1487 }
1488
1489 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i,
1490 !qup->is_last || i < blk->count - 1);
1491 if (ret)
1492 return ret;
1493
1494 /* Handle SMBus block read length */
1495 if (qup_i2c_check_msg_len(msg) && msg->len == 1 &&
1496 !qup->is_smbus_read) {
1497 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX)
1498 return -EPROTO;
1499
1500 msg->len = msg->buf[0];
1501 qup->is_smbus_read = true;
1502 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true);
1503 qup->is_smbus_read = false;
1504 if (ret)
1505 return ret;
1506
1507 msg->len += 1;
1508 }
1509
1510 msg_buf += data_len;
1511 blk->data_len -= qup->blk_xfer_limit;
1512 }
1513
1514 return ret;
1515 }
1516
1517 /*
1518 * QUP v2 supports 3 modes
1519 * Programmed IO using FIFO mode : Less than FIFO size
1520 * Programmed IO using Block mode : Greater than FIFO size
1521 * DMA using BAM : Appropriate for any transaction size but the address should
1522 * be DMA applicable
1523 *
1524 * This function determines the mode which will be used for this transfer. An
1525 * i2c transfer contains multiple message. Following are the rules to determine
1526 * the mode used.
1527 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1528 * 2. If complete transfer length is greater than fifo size then use the DMA
1529 * mode.
1530 * 3. In FIFO or block mode, tx and rx can operate in different mode so check
1531 * for maximum tx and rx length to determine mode.
1532 */
1533 static int
qup_i2c_determine_mode_v2(struct qup_i2c_dev * qup,struct i2c_msg msgs[],int num)1534 qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup,
1535 struct i2c_msg msgs[], int num)
1536 {
1537 int idx;
1538 bool no_dma = false;
1539 unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0;
1540
1541 /* All i2c_msgs should be transferred using either dma or cpu */
1542 for (idx = 0; idx < num; idx++) {
1543 if (msgs[idx].flags & I2C_M_RD)
1544 max_rx_len = max_t(unsigned int, max_rx_len,
1545 msgs[idx].len);
1546 else
1547 max_tx_len = max_t(unsigned int, max_tx_len,
1548 msgs[idx].len);
1549
1550 if (is_vmalloc_addr(msgs[idx].buf))
1551 no_dma = true;
1552
1553 total_len += msgs[idx].len;
1554 }
1555
1556 if (!no_dma && qup->is_dma &&
1557 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) {
1558 qup->use_dma = true;
1559 } else {
1560 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz -
1561 QUP_MAX_TAGS_LEN;
1562 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz -
1563 READ_RX_TAGS_LEN;
1564 }
1565
1566 return 0;
1567 }
1568
qup_i2c_xfer_v2(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1569 static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1570 struct i2c_msg msgs[],
1571 int num)
1572 {
1573 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1574 int ret, idx = 0;
1575
1576 qup->bus_err = 0;
1577 qup->qup_err = 0;
1578
1579 ret = pm_runtime_get_sync(qup->dev);
1580 if (ret < 0)
1581 goto out;
1582
1583 ret = qup_i2c_determine_mode_v2(qup, msgs, num);
1584 if (ret)
1585 goto out;
1586
1587 writel(1, qup->base + QUP_SW_RESET);
1588 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1589 if (ret)
1590 goto out;
1591
1592 /* Configure QUP as I2C mini core */
1593 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1594 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1595
1596 if (qup_i2c_poll_state_i2c_master(qup)) {
1597 ret = -EIO;
1598 goto out;
1599 }
1600
1601 if (qup->use_dma) {
1602 reinit_completion(&qup->xfer);
1603 ret = qup_i2c_bam_xfer(adap, &msgs[0], num);
1604 qup->use_dma = false;
1605 } else {
1606 qup_i2c_conf_mode_v2(qup);
1607
1608 for (idx = 0; idx < num; idx++) {
1609 qup->msg = &msgs[idx];
1610 qup->is_last = idx == (num - 1);
1611
1612 ret = qup_i2c_xfer_v2_msg(qup, idx,
1613 !!(msgs[idx].flags & I2C_M_RD));
1614 if (ret)
1615 break;
1616 }
1617 qup->msg = NULL;
1618 }
1619
1620 if (!ret)
1621 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1622
1623 if (!ret)
1624 qup_i2c_change_state(qup, QUP_RESET_STATE);
1625
1626 if (ret == 0)
1627 ret = num;
1628 out:
1629 pm_runtime_mark_last_busy(qup->dev);
1630 pm_runtime_put_autosuspend(qup->dev);
1631
1632 return ret;
1633 }
1634
qup_i2c_func(struct i2c_adapter * adap)1635 static u32 qup_i2c_func(struct i2c_adapter *adap)
1636 {
1637 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
1638 }
1639
1640 static const struct i2c_algorithm qup_i2c_algo = {
1641 .master_xfer = qup_i2c_xfer,
1642 .functionality = qup_i2c_func,
1643 };
1644
1645 static const struct i2c_algorithm qup_i2c_algo_v2 = {
1646 .master_xfer = qup_i2c_xfer_v2,
1647 .functionality = qup_i2c_func,
1648 };
1649
1650 /*
1651 * The QUP block will issue a NACK and STOP on the bus when reaching
1652 * the end of the read, the length of the read is specified as one byte
1653 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1654 */
1655 static const struct i2c_adapter_quirks qup_i2c_quirks = {
1656 .flags = I2C_AQ_NO_ZERO_LEN,
1657 .max_read_len = QUP_READ_LIMIT,
1658 };
1659
1660 static const struct i2c_adapter_quirks qup_i2c_quirks_v2 = {
1661 .flags = I2C_AQ_NO_ZERO_LEN,
1662 };
1663
qup_i2c_enable_clocks(struct qup_i2c_dev * qup)1664 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1665 {
1666 clk_prepare_enable(qup->clk);
1667 clk_prepare_enable(qup->pclk);
1668 }
1669
qup_i2c_disable_clocks(struct qup_i2c_dev * qup)1670 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1671 {
1672 u32 config;
1673
1674 qup_i2c_change_state(qup, QUP_RESET_STATE);
1675 clk_disable_unprepare(qup->clk);
1676 config = readl(qup->base + QUP_CONFIG);
1677 config |= QUP_CLOCK_AUTO_GATE;
1678 writel(config, qup->base + QUP_CONFIG);
1679 qup_i2c_vote_bw(qup, 0);
1680 clk_disable_unprepare(qup->pclk);
1681 }
1682
1683 static const struct acpi_device_id qup_i2c_acpi_match[] = {
1684 { "QCOM8010"},
1685 { },
1686 };
1687 MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match);
1688
qup_i2c_probe(struct platform_device * pdev)1689 static int qup_i2c_probe(struct platform_device *pdev)
1690 {
1691 static const int blk_sizes[] = {4, 16, 32};
1692 struct qup_i2c_dev *qup;
1693 unsigned long one_bit_t;
1694 u32 io_mode, hw_ver, size;
1695 int ret, fs_div, hs_div;
1696 u32 src_clk_freq = DEFAULT_SRC_CLK;
1697 u32 clk_freq = DEFAULT_CLK_FREQ;
1698 int blocks;
1699 bool is_qup_v1;
1700
1701 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1702 if (!qup)
1703 return -ENOMEM;
1704
1705 qup->dev = &pdev->dev;
1706 init_completion(&qup->xfer);
1707 platform_set_drvdata(pdev, qup);
1708
1709 if (scl_freq) {
1710 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq);
1711 clk_freq = scl_freq;
1712 } else {
1713 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
1714 if (ret) {
1715 dev_notice(qup->dev, "using default clock-frequency %d",
1716 DEFAULT_CLK_FREQ);
1717 }
1718 }
1719
1720 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1721 qup->adap.algo = &qup_i2c_algo;
1722 qup->adap.quirks = &qup_i2c_quirks;
1723 is_qup_v1 = true;
1724 } else {
1725 qup->adap.algo = &qup_i2c_algo_v2;
1726 qup->adap.quirks = &qup_i2c_quirks_v2;
1727 is_qup_v1 = false;
1728 if (acpi_match_device(qup_i2c_acpi_match, qup->dev))
1729 goto nodma;
1730 else
1731 ret = qup_i2c_req_dma(qup);
1732
1733 if (ret == -EPROBE_DEFER)
1734 goto fail_dma;
1735 else if (ret != 0)
1736 goto nodma;
1737
1738 qup->max_xfer_sg_len = (MX_BLOCKS << 1);
1739 blocks = (MX_DMA_BLOCKS << 1) + 1;
1740 qup->btx.sg = devm_kcalloc(&pdev->dev,
1741 blocks, sizeof(*qup->btx.sg),
1742 GFP_KERNEL);
1743 if (!qup->btx.sg) {
1744 ret = -ENOMEM;
1745 goto fail_dma;
1746 }
1747 sg_init_table(qup->btx.sg, blocks);
1748
1749 qup->brx.sg = devm_kcalloc(&pdev->dev,
1750 blocks, sizeof(*qup->brx.sg),
1751 GFP_KERNEL);
1752 if (!qup->brx.sg) {
1753 ret = -ENOMEM;
1754 goto fail_dma;
1755 }
1756 sg_init_table(qup->brx.sg, blocks);
1757
1758 /* 2 tag bytes for each block + 5 for start, stop tags */
1759 size = blocks * 2 + 5;
1760
1761 qup->start_tag.start = devm_kzalloc(&pdev->dev,
1762 size, GFP_KERNEL);
1763 if (!qup->start_tag.start) {
1764 ret = -ENOMEM;
1765 goto fail_dma;
1766 }
1767
1768 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1769 if (!qup->brx.tag.start) {
1770 ret = -ENOMEM;
1771 goto fail_dma;
1772 }
1773
1774 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1775 if (!qup->btx.tag.start) {
1776 ret = -ENOMEM;
1777 goto fail_dma;
1778 }
1779 qup->is_dma = true;
1780
1781 qup->icc_path = devm_of_icc_get(&pdev->dev, NULL);
1782 if (IS_ERR(qup->icc_path))
1783 return dev_err_probe(&pdev->dev, PTR_ERR(qup->icc_path),
1784 "failed to get interconnect path\n");
1785 }
1786
1787 nodma:
1788 /* We support frequencies up to FAST Mode Plus (1MHz) */
1789 if (!clk_freq || clk_freq > I2C_MAX_FAST_MODE_PLUS_FREQ) {
1790 dev_err(qup->dev, "clock frequency not supported %d\n",
1791 clk_freq);
1792 ret = -EINVAL;
1793 goto fail_dma;
1794 }
1795
1796 qup->base = devm_platform_ioremap_resource(pdev, 0);
1797 if (IS_ERR(qup->base)) {
1798 ret = PTR_ERR(qup->base);
1799 goto fail_dma;
1800 }
1801
1802 qup->irq = platform_get_irq(pdev, 0);
1803 if (qup->irq < 0) {
1804 ret = qup->irq;
1805 goto fail_dma;
1806 }
1807
1808 if (has_acpi_companion(qup->dev)) {
1809 ret = device_property_read_u32(qup->dev,
1810 "src-clock-hz", &src_clk_freq);
1811 if (ret) {
1812 dev_notice(qup->dev, "using default src-clock-hz %d",
1813 DEFAULT_SRC_CLK);
1814 }
1815 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
1816 } else {
1817 qup->clk = devm_clk_get(qup->dev, "core");
1818 if (IS_ERR(qup->clk)) {
1819 dev_err(qup->dev, "Could not get core clock\n");
1820 ret = PTR_ERR(qup->clk);
1821 goto fail_dma;
1822 }
1823
1824 qup->pclk = devm_clk_get(qup->dev, "iface");
1825 if (IS_ERR(qup->pclk)) {
1826 dev_err(qup->dev, "Could not get iface clock\n");
1827 ret = PTR_ERR(qup->pclk);
1828 goto fail_dma;
1829 }
1830 qup_i2c_enable_clocks(qup);
1831 src_clk_freq = clk_get_rate(qup->clk);
1832 }
1833 qup->src_clk_freq = src_clk_freq;
1834
1835 /*
1836 * Bootloaders might leave a pending interrupt on certain QUP's,
1837 * so we reset the core before registering for interrupts.
1838 */
1839 writel(1, qup->base + QUP_SW_RESET);
1840 ret = qup_i2c_poll_state_valid(qup);
1841 if (ret)
1842 goto fail;
1843
1844 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1845 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
1846 "i2c_qup", qup);
1847 if (ret) {
1848 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1849 goto fail;
1850 }
1851
1852 hw_ver = readl(qup->base + QUP_HW_VERSION);
1853 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1854
1855 io_mode = readl(qup->base + QUP_IO_MODE);
1856
1857 /*
1858 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1859 * associated with each byte written/received
1860 */
1861 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1862 if (size >= ARRAY_SIZE(blk_sizes)) {
1863 ret = -EIO;
1864 goto fail;
1865 }
1866 qup->out_blk_sz = blk_sizes[size];
1867
1868 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1869 if (size >= ARRAY_SIZE(blk_sizes)) {
1870 ret = -EIO;
1871 goto fail;
1872 }
1873 qup->in_blk_sz = blk_sizes[size];
1874
1875 if (is_qup_v1) {
1876 /*
1877 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a
1878 * single transfer but the block size is in bytes so divide the
1879 * in_blk_sz and out_blk_sz by 2
1880 */
1881 qup->in_blk_sz /= 2;
1882 qup->out_blk_sz /= 2;
1883 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
1884 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
1885 qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
1886 } else {
1887 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;
1888 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;
1889 qup->write_rx_tags = qup_i2c_write_rx_tags_v2;
1890 }
1891
1892 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1893 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1894
1895 size = QUP_INPUT_FIFO_SIZE(io_mode);
1896 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1897
1898 hs_div = 3;
1899 if (clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) {
1900 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1901 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1902 } else {
1903 /* 33%/66% duty cycle */
1904 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
1905 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
1906 }
1907
1908 /*
1909 * Time it takes for a byte to be clocked out on the bus.
1910 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1911 */
1912 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1913 qup->one_byte_t = one_bit_t * 9;
1914 qup->xfer_timeout = TOUT_MIN * HZ +
1915 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);
1916
1917 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1918 qup->in_blk_sz, qup->in_fifo_sz,
1919 qup->out_blk_sz, qup->out_fifo_sz);
1920
1921 i2c_set_adapdata(&qup->adap, qup);
1922 qup->adap.dev.parent = qup->dev;
1923 qup->adap.dev.of_node = pdev->dev.of_node;
1924 qup->is_last = true;
1925
1926 strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1927
1928 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1929 pm_runtime_use_autosuspend(qup->dev);
1930 pm_runtime_set_active(qup->dev);
1931 pm_runtime_enable(qup->dev);
1932
1933 ret = i2c_add_adapter(&qup->adap);
1934 if (ret)
1935 goto fail_runtime;
1936
1937 return 0;
1938
1939 fail_runtime:
1940 pm_runtime_disable(qup->dev);
1941 pm_runtime_set_suspended(qup->dev);
1942 fail:
1943 qup_i2c_disable_clocks(qup);
1944 fail_dma:
1945 if (qup->btx.dma)
1946 dma_release_channel(qup->btx.dma);
1947 if (qup->brx.dma)
1948 dma_release_channel(qup->brx.dma);
1949 return ret;
1950 }
1951
qup_i2c_remove(struct platform_device * pdev)1952 static void qup_i2c_remove(struct platform_device *pdev)
1953 {
1954 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1955
1956 if (qup->is_dma) {
1957 dma_release_channel(qup->btx.dma);
1958 dma_release_channel(qup->brx.dma);
1959 }
1960
1961 disable_irq(qup->irq);
1962 qup_i2c_disable_clocks(qup);
1963 i2c_del_adapter(&qup->adap);
1964 pm_runtime_disable(qup->dev);
1965 pm_runtime_set_suspended(qup->dev);
1966 }
1967
qup_i2c_pm_suspend_runtime(struct device * device)1968 static int qup_i2c_pm_suspend_runtime(struct device *device)
1969 {
1970 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1971
1972 dev_dbg(device, "pm_runtime: suspending...\n");
1973 qup_i2c_disable_clocks(qup);
1974 return 0;
1975 }
1976
qup_i2c_pm_resume_runtime(struct device * device)1977 static int qup_i2c_pm_resume_runtime(struct device *device)
1978 {
1979 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1980
1981 dev_dbg(device, "pm_runtime: resuming...\n");
1982 qup_i2c_enable_clocks(qup);
1983 return 0;
1984 }
1985
qup_i2c_suspend(struct device * device)1986 static int qup_i2c_suspend(struct device *device)
1987 {
1988 if (!pm_runtime_suspended(device))
1989 return qup_i2c_pm_suspend_runtime(device);
1990 return 0;
1991 }
1992
qup_i2c_resume(struct device * device)1993 static int qup_i2c_resume(struct device *device)
1994 {
1995 qup_i2c_pm_resume_runtime(device);
1996 pm_runtime_mark_last_busy(device);
1997 pm_request_autosuspend(device);
1998 return 0;
1999 }
2000
2001 static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
2002 SYSTEM_SLEEP_PM_OPS(qup_i2c_suspend, qup_i2c_resume)
2003 RUNTIME_PM_OPS(qup_i2c_pm_suspend_runtime,
2004 qup_i2c_pm_resume_runtime, NULL)
2005 };
2006
2007 static const struct of_device_id qup_i2c_dt_match[] = {
2008 { .compatible = "qcom,i2c-qup-v1.1.1" },
2009 { .compatible = "qcom,i2c-qup-v2.1.1" },
2010 { .compatible = "qcom,i2c-qup-v2.2.1" },
2011 {}
2012 };
2013 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
2014
2015 static struct platform_driver qup_i2c_driver = {
2016 .probe = qup_i2c_probe,
2017 .remove_new = qup_i2c_remove,
2018 .driver = {
2019 .name = "i2c_qup",
2020 .pm = pm_ptr(&qup_i2c_qup_pm_ops),
2021 .of_match_table = qup_i2c_dt_match,
2022 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match),
2023 },
2024 };
2025
2026 module_platform_driver(qup_i2c_driver);
2027
2028 MODULE_LICENSE("GPL v2");
2029 MODULE_ALIAS("platform:i2c_qup");
2030