1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3
4 #include "exec/memory.h"
5 #include "system/dma.h"
6 #include "system/host_iommu_device.h"
7
8 /* PCI includes legacy ISA access. */
9 #include "hw/isa/isa.h"
10
11 extern bool pci_available;
12
13 /* PCI bus */
14
15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
16 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
17 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
18 #define PCI_FUNC(devfn) ((devfn) & 0x07)
19 #define PCI_BUILD_BDF(bus, devfn) (((bus) << 8) | (devfn))
20 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff)
21 #define PCI_BUS_MAX 256
22 #define PCI_DEVFN_MAX 256
23 #define PCI_SLOT_MAX 32
24 #define PCI_FUNC_MAX 8
25
26 #define PCI_SBDF(seg, bus, dev, func) \
27 ((((uint32_t)(seg)) << 16) | \
28 (PCI_BUILD_BDF(bus, PCI_DEVFN(dev, func))))
29
30 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
31 #include "hw/pci/pci_ids.h"
32
33 /* QEMU-specific Vendor and Device ID definitions */
34
35 /* IBM (0x1014) */
36 #define PCI_DEVICE_ID_IBM_440GX 0x027f
37 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
38
39 /* Hitachi (0x1054) */
40 #define PCI_VENDOR_ID_HITACHI 0x1054
41 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
42
43 /* Apple (0x106b) */
44 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
45 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
46 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
47 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
48 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
49
50 /* Realtek (0x10ec) */
51 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
52
53 /* Xilinx (0x10ee) */
54 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
55
56 /* Marvell (0x11ab) */
57 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
58
59 /* QEMU/Bochs VGA (0x1234) */
60 #define PCI_VENDOR_ID_QEMU 0x1234
61 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
62 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112
63
64 /* VMWare (0x15ad) */
65 #define PCI_VENDOR_ID_VMWARE 0x15ad
66 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
67 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
68 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
69 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
70 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
71 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
72 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
73
74 /* Intel (0x8086) */
75 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
76 #define PCI_DEVICE_ID_INTEL_82557 0x1229
77 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
78
79 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
80 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
81 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
82 #define PCI_SUBDEVICE_ID_QEMU 0x1100
83
84 /* legacy virtio-pci devices */
85 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
86 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
87 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
88 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
89 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
90 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
91 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
92 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
93
94 /*
95 * modern virtio-pci devices get their id assigned automatically,
96 * there is no need to add #defines here. It gets calculated as
97 *
98 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE +
99 * virtio_bus_get_vdev_id(bus)
100 */
101 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040
102
103 #define PCI_VENDOR_ID_REDHAT 0x1b36
104 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
105 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
106 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
107 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
108 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
109 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
110 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
111 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
112 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009
113 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
114 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
115 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
116 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
117 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
118 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
119 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010
120 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
121 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012
122 #define PCI_DEVICE_ID_REDHAT_UFS 0x0013
123 #define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014
124 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
125
126 #define FMT_PCIBUS PRIx64
127
128 typedef uint64_t pcibus_t;
129
130 struct PCIHostDeviceAddress {
131 unsigned int domain;
132 unsigned int bus;
133 unsigned int slot;
134 unsigned int function;
135 };
136
137 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
138 uint32_t address, uint32_t data, int len);
139 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
140 uint32_t address, int len);
141 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
142 pcibus_t addr, pcibus_t size, int type);
143 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
144
145 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg);
146 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector);
147 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector);
148
149 typedef struct PCIIORegion {
150 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
151 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
152 pcibus_t size;
153 uint8_t type;
154 MemoryRegion *memory;
155 MemoryRegion *address_space;
156 } PCIIORegion;
157
158 #define PCI_ROM_SLOT 6
159 #define PCI_NUM_REGIONS 7
160
161 enum {
162 QEMU_PCI_VGA_MEM,
163 QEMU_PCI_VGA_IO_LO,
164 QEMU_PCI_VGA_IO_HI,
165 QEMU_PCI_VGA_NUM_REGIONS,
166 };
167
168 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
169 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
170 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
171 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
172 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
173 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
174
175 #include "hw/pci/pci_regs.h"
176
177 /* PCI HEADER_TYPE */
178 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
179
180 /* Size of the standard PCI config header */
181 #define PCI_CONFIG_HEADER_SIZE 0x40
182 /* Size of the standard PCI config space */
183 #define PCI_CONFIG_SPACE_SIZE 0x100
184 /* Size of the standard PCIe config space: 4KB */
185 #define PCIE_CONFIG_SPACE_SIZE 0x1000
186
187 #define PCI_NUM_PINS 4 /* A-D */
188
189 /* Bits in cap_present field. */
190 enum {
191 QEMU_PCI_CAP_MSI = 0x1,
192 QEMU_PCI_CAP_MSIX = 0x2,
193 QEMU_PCI_CAP_EXPRESS = 0x4,
194
195 /* multifunction capable device */
196 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
197 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
198
199 /* command register SERR bit enabled - unused since QEMU v5.0 */
200 #define QEMU_PCI_CAP_SERR_BITNR 4
201 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
202 /* Standard hot plug controller. */
203 #define QEMU_PCI_SHPC_BITNR 5
204 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
205 #define QEMU_PCI_SLOTID_BITNR 6
206 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
207 /* PCI Express capability - Power Controller Present */
208 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
209 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
210 /* Link active status in endpoint capability is always set */
211 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
212 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
213 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
214 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
215 #define QEMU_PCIE_CXL_BITNR 10
216 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
217 #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11
218 QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR),
219 #define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12
220 QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR),
221 #define QEMU_PCIE_EXT_TAG_BITNR 13
222 QEMU_PCIE_EXT_TAG = (1 << QEMU_PCIE_EXT_TAG_BITNR),
223 #define QEMU_PCI_CAP_PM_BITNR 14
224 QEMU_PCI_CAP_PM = (1 << QEMU_PCI_CAP_PM_BITNR),
225 };
226
227 typedef struct PCIINTxRoute {
228 enum {
229 PCI_INTX_ENABLED,
230 PCI_INTX_INVERTED,
231 PCI_INTX_DISABLED,
232 } mode;
233 int irq;
234 } PCIINTxRoute;
235
236 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
237 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
238 MSIMessage msg);
239 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
240 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
241 unsigned int vector_start,
242 unsigned int vector_end);
243
244 void pci_register_bar(PCIDevice *pci_dev, int region_num,
245 uint8_t attr, MemoryRegion *memory);
246 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
247 MemoryRegion *io_lo, MemoryRegion *io_hi);
248 void pci_unregister_vga(PCIDevice *pci_dev);
249 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
250
251 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
252 uint8_t offset, uint8_t size,
253 Error **errp);
254
255 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
256
257 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
258
259
260 uint32_t pci_default_read_config(PCIDevice *d,
261 uint32_t address, int len);
262 void pci_default_write_config(PCIDevice *d,
263 uint32_t address, uint32_t val, int len);
264 void pci_device_save(PCIDevice *s, QEMUFile *f);
265 int pci_device_load(PCIDevice *s, QEMUFile *f);
266 MemoryRegion *pci_address_space(PCIDevice *dev);
267 MemoryRegion *pci_address_space_io(PCIDevice *dev);
268
269 /*
270 * Should not normally be used by devices. For use by sPAPR target
271 * where QEMU emulates firmware.
272 */
273 int pci_bar(PCIDevice *d, int reg);
274
275 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
276 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
277 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
278
279 #define TYPE_PCI_BUS "PCI"
280 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
281 #define TYPE_PCIE_BUS "PCIE"
282 #define TYPE_CXL_BUS "CXL"
283
284 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque);
285 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque);
286 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque);
287
288 bool pci_bus_is_express(const PCIBus *bus);
289
290 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
291 const char *name,
292 MemoryRegion *mem, MemoryRegion *io,
293 uint8_t devfn_min, const char *typename);
294 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
295 MemoryRegion *mem, MemoryRegion *io,
296 uint8_t devfn_min, const char *typename);
297 void pci_root_bus_cleanup(PCIBus *bus);
298 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
299 void *irq_opaque, int nirq);
300 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq);
301 void pci_bus_irqs_cleanup(PCIBus *bus);
302 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
303 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus);
304 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask);
305 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask);
306 bool pci_bus_add_fw_cfg_extra_pci_roots(FWCfgState *fw_cfg,
307 PCIBus *bus,
308 Error **errp);
309 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
pci_swizzle(int slot,int pin)310 static inline int pci_swizzle(int slot, int pin)
311 {
312 return (slot + pin) % PCI_NUM_PINS;
313 }
314 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
315 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
316 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
317 void *irq_opaque,
318 MemoryRegion *mem, MemoryRegion *io,
319 uint8_t devfn_min, int nirq,
320 const char *typename);
321 void pci_unregister_root_bus(PCIBus *bus);
322 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
323 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
324 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
325 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
326 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
327 PCIINTxRoutingNotifier notifier);
328 void pci_device_reset(PCIDevice *dev);
329
330 void pci_init_nic_devices(PCIBus *bus, const char *default_model);
331 bool pci_init_nic_in_slot(PCIBus *rootbus, const char *default_model,
332 const char *alias, const char *devaddr);
333 PCIDevice *pci_vga_init(PCIBus *bus);
334
pci_get_bus(const PCIDevice * dev)335 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
336 {
337 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
338 }
339 int pci_bus_num(PCIBus *s);
340 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
pci_dev_bus_num(const PCIDevice * dev)341 static inline int pci_dev_bus_num(const PCIDevice *dev)
342 {
343 return pci_bus_num(pci_get_bus(dev));
344 }
345
346 int pci_bus_numa_node(PCIBus *bus);
347 void pci_for_each_device(PCIBus *bus, int bus_num,
348 pci_bus_dev_fn fn,
349 void *opaque);
350 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
351 pci_bus_dev_fn fn,
352 void *opaque);
353 void pci_for_each_device_under_bus(PCIBus *bus,
354 pci_bus_dev_fn fn, void *opaque);
355 void pci_for_each_device_under_bus_reverse(PCIBus *bus,
356 pci_bus_dev_fn fn,
357 void *opaque);
358 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin,
359 pci_bus_fn end, void *parent_state);
360 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
361
362 /* Use this wrapper when specific scan order is not required. */
363 static inline
pci_for_each_bus(PCIBus * bus,pci_bus_fn fn,void * opaque)364 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque)
365 {
366 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
367 }
368
369 PCIBus *pci_device_root_bus(const PCIDevice *d);
370 const char *pci_root_bus_path(PCIDevice *dev);
371 bool pci_bus_bypass_iommu(PCIBus *bus);
372 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
373 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
374 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
375
376 void pci_device_deassert_intx(PCIDevice *dev);
377
378
379 /**
380 * struct PCIIOMMUOps: callbacks structure for specific IOMMU handlers
381 * of a PCIBus
382 *
383 * Allows to modify the behavior of some IOMMU operations of the PCI
384 * framework for a set of devices on a PCI bus.
385 */
386 typedef struct PCIIOMMUOps {
387 /**
388 * @get_address_space: get the address space for a set of devices
389 * on a PCI bus.
390 *
391 * Mandatory callback which returns a pointer to an #AddressSpace
392 *
393 * @bus: the #PCIBus being accessed.
394 *
395 * @opaque: the data passed to pci_setup_iommu().
396 *
397 * @devfn: device and function number
398 */
399 AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int devfn);
400 /**
401 * @set_iommu_device: attach a HostIOMMUDevice to a vIOMMU
402 *
403 * Optional callback, if not implemented in vIOMMU, then vIOMMU can't
404 * retrieve host information from the associated HostIOMMUDevice.
405 *
406 * @bus: the #PCIBus of the PCI device.
407 *
408 * @opaque: the data passed to pci_setup_iommu().
409 *
410 * @devfn: device and function number of the PCI device.
411 *
412 * @dev: the #HostIOMMUDevice to attach.
413 *
414 * @errp: pass an Error out only when return false
415 *
416 * Returns: true if HostIOMMUDevice is attached or else false with errp set.
417 */
418 bool (*set_iommu_device)(PCIBus *bus, void *opaque, int devfn,
419 HostIOMMUDevice *dev, Error **errp);
420 /**
421 * @unset_iommu_device: detach a HostIOMMUDevice from a vIOMMU
422 *
423 * Optional callback.
424 *
425 * @bus: the #PCIBus of the PCI device.
426 *
427 * @opaque: the data passed to pci_setup_iommu().
428 *
429 * @devfn: device and function number of the PCI device.
430 */
431 void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn);
432 } PCIIOMMUOps;
433
434 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
435 bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod,
436 Error **errp);
437 void pci_device_unset_iommu_device(PCIDevice *dev);
438
439 /**
440 * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus
441 *
442 * Let PCI host bridges define specific operations.
443 *
444 * @bus: the #PCIBus being updated.
445 * @ops: the #PCIIOMMUOps
446 * @opaque: passed to callbacks of the @ops structure.
447 */
448 void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque);
449
450 pcibus_t pci_bar_address(PCIDevice *d,
451 int reg, uint8_t type, pcibus_t size);
452
453 static inline void
pci_set_byte(uint8_t * config,uint8_t val)454 pci_set_byte(uint8_t *config, uint8_t val)
455 {
456 *config = val;
457 }
458
459 static inline uint8_t
pci_get_byte(const uint8_t * config)460 pci_get_byte(const uint8_t *config)
461 {
462 return *config;
463 }
464
465 static inline void
pci_set_word(uint8_t * config,uint16_t val)466 pci_set_word(uint8_t *config, uint16_t val)
467 {
468 stw_le_p(config, val);
469 }
470
471 static inline uint16_t
pci_get_word(const uint8_t * config)472 pci_get_word(const uint8_t *config)
473 {
474 return lduw_le_p(config);
475 }
476
477 static inline void
pci_set_long(uint8_t * config,uint32_t val)478 pci_set_long(uint8_t *config, uint32_t val)
479 {
480 stl_le_p(config, val);
481 }
482
483 static inline uint32_t
pci_get_long(const uint8_t * config)484 pci_get_long(const uint8_t *config)
485 {
486 return ldl_le_p(config);
487 }
488
489 /*
490 * PCI capabilities and/or their fields
491 * are generally DWORD aligned only so
492 * mechanism used by pci_set/get_quad()
493 * must be tolerant to unaligned pointers
494 *
495 */
496 static inline void
pci_set_quad(uint8_t * config,uint64_t val)497 pci_set_quad(uint8_t *config, uint64_t val)
498 {
499 stq_le_p(config, val);
500 }
501
502 static inline uint64_t
pci_get_quad(const uint8_t * config)503 pci_get_quad(const uint8_t *config)
504 {
505 return ldq_le_p(config);
506 }
507
508 static inline void
pci_config_set_vendor_id(uint8_t * pci_config,uint16_t val)509 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
510 {
511 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
512 }
513
514 static inline void
pci_config_set_device_id(uint8_t * pci_config,uint16_t val)515 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
516 {
517 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
518 }
519
520 static inline void
pci_config_set_revision(uint8_t * pci_config,uint8_t val)521 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
522 {
523 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
524 }
525
526 static inline void
pci_config_set_class(uint8_t * pci_config,uint16_t val)527 pci_config_set_class(uint8_t *pci_config, uint16_t val)
528 {
529 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
530 }
531
532 static inline void
pci_config_set_prog_interface(uint8_t * pci_config,uint8_t val)533 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
534 {
535 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
536 }
537
538 static inline void
pci_config_set_interrupt_pin(uint8_t * pci_config,uint8_t val)539 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
540 {
541 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
542 }
543
544 /*
545 * helper functions to do bit mask operation on configuration space.
546 * Just to set bit, use test-and-set and discard returned value.
547 * Just to clear bit, use test-and-clear and discard returned value.
548 * NOTE: They aren't atomic.
549 */
550 static inline uint8_t
pci_byte_test_and_clear_mask(uint8_t * config,uint8_t mask)551 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
552 {
553 uint8_t val = pci_get_byte(config);
554 pci_set_byte(config, val & ~mask);
555 return val & mask;
556 }
557
558 static inline uint8_t
pci_byte_test_and_set_mask(uint8_t * config,uint8_t mask)559 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
560 {
561 uint8_t val = pci_get_byte(config);
562 pci_set_byte(config, val | mask);
563 return val & mask;
564 }
565
566 static inline uint16_t
pci_word_test_and_clear_mask(uint8_t * config,uint16_t mask)567 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
568 {
569 uint16_t val = pci_get_word(config);
570 pci_set_word(config, val & ~mask);
571 return val & mask;
572 }
573
574 static inline uint16_t
pci_word_test_and_set_mask(uint8_t * config,uint16_t mask)575 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
576 {
577 uint16_t val = pci_get_word(config);
578 pci_set_word(config, val | mask);
579 return val & mask;
580 }
581
582 static inline uint32_t
pci_long_test_and_clear_mask(uint8_t * config,uint32_t mask)583 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
584 {
585 uint32_t val = pci_get_long(config);
586 pci_set_long(config, val & ~mask);
587 return val & mask;
588 }
589
590 static inline uint32_t
pci_long_test_and_set_mask(uint8_t * config,uint32_t mask)591 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
592 {
593 uint32_t val = pci_get_long(config);
594 pci_set_long(config, val | mask);
595 return val & mask;
596 }
597
598 static inline uint64_t
pci_quad_test_and_clear_mask(uint8_t * config,uint64_t mask)599 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
600 {
601 uint64_t val = pci_get_quad(config);
602 pci_set_quad(config, val & ~mask);
603 return val & mask;
604 }
605
606 static inline uint64_t
pci_quad_test_and_set_mask(uint8_t * config,uint64_t mask)607 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
608 {
609 uint64_t val = pci_get_quad(config);
610 pci_set_quad(config, val | mask);
611 return val & mask;
612 }
613
614 /* Access a register specified by a mask */
615 static inline void
pci_set_byte_by_mask(uint8_t * config,uint8_t mask,uint8_t reg)616 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
617 {
618 uint8_t val = pci_get_byte(config);
619 uint8_t rval;
620
621 assert(mask);
622 rval = reg << ctz32(mask);
623 pci_set_byte(config, (~mask & val) | (mask & rval));
624 }
625
626 static inline void
pci_set_word_by_mask(uint8_t * config,uint16_t mask,uint16_t reg)627 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
628 {
629 uint16_t val = pci_get_word(config);
630 uint16_t rval;
631
632 assert(mask);
633 rval = reg << ctz32(mask);
634 pci_set_word(config, (~mask & val) | (mask & rval));
635 }
636
637 static inline void
pci_set_long_by_mask(uint8_t * config,uint32_t mask,uint32_t reg)638 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
639 {
640 uint32_t val = pci_get_long(config);
641 uint32_t rval;
642
643 assert(mask);
644 rval = reg << ctz32(mask);
645 pci_set_long(config, (~mask & val) | (mask & rval));
646 }
647
648 static inline void
pci_set_quad_by_mask(uint8_t * config,uint64_t mask,uint64_t reg)649 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
650 {
651 uint64_t val = pci_get_quad(config);
652 uint64_t rval;
653
654 assert(mask);
655 rval = reg << ctz32(mask);
656 pci_set_quad(config, (~mask & val) | (mask & rval));
657 }
658
659 PCIDevice *pci_new_multifunction(int devfn, const char *name);
660 PCIDevice *pci_new(int devfn, const char *name);
661 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
662
663 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
664 const char *name);
665 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
666
667 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
668
669 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
670 void pci_set_irq(PCIDevice *pci_dev, int level);
671
pci_irq_assert(PCIDevice * pci_dev)672 static inline void pci_irq_assert(PCIDevice *pci_dev)
673 {
674 pci_set_irq(pci_dev, 1);
675 }
676
pci_irq_deassert(PCIDevice * pci_dev)677 static inline void pci_irq_deassert(PCIDevice *pci_dev)
678 {
679 pci_set_irq(pci_dev, 0);
680 }
681
682 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
683 void pci_set_enabled(PCIDevice *pci_dev, bool state);
684 void pci_set_power(PCIDevice *pci_dev, bool state);
685 int pci_pm_init(PCIDevice *pci_dev, uint8_t offset, Error **errp);
686
687 #endif
688