1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/media/i2c/ccs-pll.c
4 *
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
6 *
7 * Copyright (C) 2020 Intel Corporation
8 * Copyright (C) 2011--2012 Nokia Corporation
9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
10 */
11
12 #include <linux/device.h>
13 #include <linux/gcd.h>
14 #include <linux/lcm.h>
15 #include <linux/module.h>
16
17 #include "ccs-pll.h"
18
19 /* Return an even number or one. */
clk_div_even(u32 a)20 static inline u32 clk_div_even(u32 a)
21 {
22 return max_t(u32, 1, a & ~1);
23 }
24
25 /* Return an even number or one. */
clk_div_even_up(u32 a)26 static inline u32 clk_div_even_up(u32 a)
27 {
28 if (a == 1)
29 return 1;
30 return (a + 1) & ~1;
31 }
32
is_one_or_even(u32 a)33 static inline u32 is_one_or_even(u32 a)
34 {
35 if (a == 1)
36 return 1;
37 if (a & 1)
38 return 0;
39
40 return 1;
41 }
42
one_or_more(u32 a)43 static inline u32 one_or_more(u32 a)
44 {
45 return a ?: 1;
46 }
47
bounds_check(struct device * dev,u32 val,u32 min,u32 max,const char * prefix,char * str)48 static int bounds_check(struct device *dev, u32 val,
49 u32 min, u32 max, const char *prefix,
50 char *str)
51 {
52 if (val >= min && val <= max)
53 return 0;
54
55 dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix,
56 str, val, min, max);
57
58 return -EINVAL;
59 }
60
61 #define PLL_OP 1
62 #define PLL_VT 2
63
pll_string(unsigned int which)64 static const char *pll_string(unsigned int which)
65 {
66 switch (which) {
67 case PLL_OP:
68 return "op";
69 case PLL_VT:
70 return "vt";
71 }
72
73 return NULL;
74 }
75
76 #define PLL_FL(f) CCS_PLL_FLAG_##f
77
print_pll(struct device * dev,struct ccs_pll * pll)78 static void print_pll(struct device *dev, struct ccs_pll *pll)
79 {
80 const struct {
81 struct ccs_pll_branch_fr *fr;
82 struct ccs_pll_branch_bk *bk;
83 unsigned int which;
84 } branches[] = {
85 { &pll->vt_fr, &pll->vt_bk, PLL_VT },
86 { &pll->op_fr, &pll->op_bk, PLL_OP }
87 }, *br;
88 unsigned int i;
89
90 dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz);
91
92 for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) {
93 const char *s = pll_string(br->which);
94
95 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL ||
96 br->which == PLL_VT) {
97 dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n", s,
98 br->fr->pre_pll_clk_div);
99 dev_dbg(dev, "%s_pll_multiplier\t\t%u\n", s,
100 br->fr->pll_multiplier);
101
102 dev_dbg(dev, "%s_pll_ip_clk_freq_hz\t%u\n", s,
103 br->fr->pll_ip_clk_freq_hz);
104 dev_dbg(dev, "%s_pll_op_clk_freq_hz\t%u\n", s,
105 br->fr->pll_op_clk_freq_hz);
106 }
107
108 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) ||
109 br->which == PLL_VT) {
110 dev_dbg(dev, "%s_sys_clk_div\t\t%u\n", s,
111 br->bk->sys_clk_div);
112 dev_dbg(dev, "%s_pix_clk_div\t\t%u\n", s,
113 br->bk->pix_clk_div);
114
115 dev_dbg(dev, "%s_sys_clk_freq_hz\t%u\n", s,
116 br->bk->sys_clk_freq_hz);
117 dev_dbg(dev, "%s_pix_clk_freq_hz\t%u\n", s,
118 br->bk->pix_clk_freq_hz);
119 }
120 }
121
122 dev_dbg(dev, "pixel rate in pixel array:\t%u\n",
123 pll->pixel_rate_pixel_array);
124 dev_dbg(dev, "pixel rate on CSI-2 bus:\t%u\n",
125 pll->pixel_rate_csi);
126
127 dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s\n",
128 pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
129 pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "",
130 pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
131 " ext-ip-pll-divider" : "",
132 pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ?
133 " flexible-op-pix-div" : "",
134 pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "",
135 pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "",
136 pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "",
137 pll->flags & PLL_FL(OP_SYS_DDR) ? " op-sys-ddr" : "",
138 pll->flags & PLL_FL(OP_PIX_DDR) ? " op-pix-ddr" : "");
139 }
140
op_sys_ddr(u32 flags)141 static u32 op_sys_ddr(u32 flags)
142 {
143 return flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0;
144 }
145
op_pix_ddr(u32 flags)146 static u32 op_pix_ddr(u32 flags)
147 {
148 return flags & CCS_PLL_FLAG_OP_PIX_DDR ? 1 : 0;
149 }
150
check_fr_bounds(struct device * dev,const struct ccs_pll_limits * lim,struct ccs_pll * pll,unsigned int which)151 static int check_fr_bounds(struct device *dev,
152 const struct ccs_pll_limits *lim,
153 struct ccs_pll *pll, unsigned int which)
154 {
155 const struct ccs_pll_branch_limits_fr *lim_fr;
156 struct ccs_pll_branch_fr *pll_fr;
157 const char *s = pll_string(which);
158 int rval;
159
160 if (which == PLL_OP) {
161 lim_fr = &lim->op_fr;
162 pll_fr = &pll->op_fr;
163 } else {
164 lim_fr = &lim->vt_fr;
165 pll_fr = &pll->vt_fr;
166 }
167
168 rval = bounds_check(dev, pll_fr->pre_pll_clk_div,
169 lim_fr->min_pre_pll_clk_div,
170 lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div");
171
172 if (!rval)
173 rval = bounds_check(dev, pll_fr->pll_ip_clk_freq_hz,
174 lim_fr->min_pll_ip_clk_freq_hz,
175 lim_fr->max_pll_ip_clk_freq_hz,
176 s, "pll_ip_clk_freq_hz");
177 if (!rval)
178 rval = bounds_check(dev, pll_fr->pll_multiplier,
179 lim_fr->min_pll_multiplier,
180 lim_fr->max_pll_multiplier,
181 s, "pll_multiplier");
182 if (!rval)
183 rval = bounds_check(dev, pll_fr->pll_op_clk_freq_hz,
184 lim_fr->min_pll_op_clk_freq_hz,
185 lim_fr->max_pll_op_clk_freq_hz,
186 s, "pll_op_clk_freq_hz");
187
188 return rval;
189 }
190
check_bk_bounds(struct device * dev,const struct ccs_pll_limits * lim,struct ccs_pll * pll,unsigned int which)191 static int check_bk_bounds(struct device *dev,
192 const struct ccs_pll_limits *lim,
193 struct ccs_pll *pll, unsigned int which)
194 {
195 const struct ccs_pll_branch_limits_bk *lim_bk;
196 struct ccs_pll_branch_bk *pll_bk;
197 const char *s = pll_string(which);
198 int rval;
199
200 if (which == PLL_OP) {
201 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
202 return 0;
203
204 lim_bk = &lim->op_bk;
205 pll_bk = &pll->op_bk;
206 } else {
207 lim_bk = &lim->vt_bk;
208 pll_bk = &pll->vt_bk;
209 }
210
211 rval = bounds_check(dev, pll_bk->sys_clk_div,
212 lim_bk->min_sys_clk_div,
213 lim_bk->max_sys_clk_div, s, "op_sys_clk_div");
214 if (!rval)
215 rval = bounds_check(dev, pll_bk->sys_clk_freq_hz,
216 lim_bk->min_sys_clk_freq_hz,
217 lim_bk->max_sys_clk_freq_hz,
218 s, "sys_clk_freq_hz");
219 if (!rval)
220 rval = bounds_check(dev, pll_bk->sys_clk_div,
221 lim_bk->min_sys_clk_div,
222 lim_bk->max_sys_clk_div,
223 s, "sys_clk_div");
224 if (!rval)
225 rval = bounds_check(dev, pll_bk->pix_clk_freq_hz,
226 lim_bk->min_pix_clk_freq_hz,
227 lim_bk->max_pix_clk_freq_hz,
228 s, "pix_clk_freq_hz");
229
230 return rval;
231 }
232
check_ext_bounds(struct device * dev,struct ccs_pll * pll)233 static int check_ext_bounds(struct device *dev, struct ccs_pll *pll)
234 {
235 if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) &&
236 pll->pixel_rate_pixel_array > pll->pixel_rate_csi) {
237 dev_dbg(dev, "device does not support derating\n");
238 return -EINVAL;
239 }
240
241 if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) &&
242 pll->pixel_rate_pixel_array < pll->pixel_rate_csi) {
243 dev_dbg(dev, "device does not support overrating\n");
244 return -EINVAL;
245 }
246
247 return 0;
248 }
249
250 static void
ccs_pll_find_vt_sys_div(struct device * dev,const struct ccs_pll_limits * lim,struct ccs_pll * pll,struct ccs_pll_branch_fr * pll_fr,u16 min_vt_div,u16 max_vt_div,u16 * min_sys_div,u16 * max_sys_div)251 ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim,
252 struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
253 u16 min_vt_div, u16 max_vt_div,
254 u16 *min_sys_div, u16 *max_sys_div)
255 {
256 /*
257 * Find limits for sys_clk_div. Not all values are possible with all
258 * values of pix_clk_div.
259 */
260 *min_sys_div = lim->vt_bk.min_sys_clk_div;
261 dev_dbg(dev, "min_sys_div: %u\n", *min_sys_div);
262 *min_sys_div = max_t(u16, *min_sys_div,
263 DIV_ROUND_UP(min_vt_div,
264 lim->vt_bk.max_pix_clk_div));
265 dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", *min_sys_div);
266 *min_sys_div = max_t(u16, *min_sys_div,
267 pll_fr->pll_op_clk_freq_hz
268 / lim->vt_bk.max_sys_clk_freq_hz);
269 dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", *min_sys_div);
270 *min_sys_div = clk_div_even_up(*min_sys_div);
271 dev_dbg(dev, "min_sys_div: one or even: %u\n", *min_sys_div);
272
273 *max_sys_div = lim->vt_bk.max_sys_clk_div;
274 dev_dbg(dev, "max_sys_div: %u\n", *max_sys_div);
275 *max_sys_div = min_t(u16, *max_sys_div,
276 DIV_ROUND_UP(max_vt_div,
277 lim->vt_bk.min_pix_clk_div));
278 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", *max_sys_div);
279 *max_sys_div = min_t(u16, *max_sys_div,
280 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
281 lim->vt_bk.min_pix_clk_freq_hz));
282 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", *max_sys_div);
283 }
284
285 #define CPHY_CONST 7
286 #define DPHY_CONST 16
287 #define PHY_CONST_DIV 16
288
289 static inline int
__ccs_pll_calculate_vt_tree(struct device * dev,const struct ccs_pll_limits * lim,struct ccs_pll * pll,u32 mul,u32 div)290 __ccs_pll_calculate_vt_tree(struct device *dev,
291 const struct ccs_pll_limits *lim,
292 struct ccs_pll *pll, u32 mul, u32 div)
293 {
294 const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
295 const struct ccs_pll_branch_limits_bk *lim_bk = &lim->vt_bk;
296 struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
297 struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk;
298 u32 more_mul;
299 u16 best_pix_div = SHRT_MAX >> 1, best_div = lim_bk->max_sys_clk_div;
300 u16 vt_div, min_sys_div, max_sys_div, sys_div;
301
302 pll_fr->pll_ip_clk_freq_hz =
303 pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div;
304
305 dev_dbg(dev, "vt_pll_ip_clk_freq_hz %u\n", pll_fr->pll_ip_clk_freq_hz);
306
307 more_mul = one_or_more(DIV_ROUND_UP(lim_fr->min_pll_op_clk_freq_hz,
308 pll_fr->pll_ip_clk_freq_hz * mul));
309
310 dev_dbg(dev, "more_mul: %u\n", more_mul);
311 more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul);
312 dev_dbg(dev, "more_mul2: %u\n", more_mul);
313
314 pll_fr->pll_multiplier = mul * more_mul;
315 if (pll_fr->pll_multiplier > lim_fr->max_pll_multiplier) {
316 dev_dbg(dev, "pll multiplier %u too high\n",
317 pll_fr->pll_multiplier);
318 return -EINVAL;
319 }
320
321 if (pll_fr->pll_multiplier * pll_fr->pll_ip_clk_freq_hz >
322 lim_fr->max_pll_op_clk_freq_hz)
323 return -EINVAL;
324
325 pll_fr->pll_op_clk_freq_hz =
326 pll_fr->pll_ip_clk_freq_hz * pll_fr->pll_multiplier;
327
328 vt_div = div * more_mul;
329
330 ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, vt_div, vt_div,
331 &min_sys_div, &max_sys_div);
332
333 max_sys_div = (vt_div & 1) ? 1 : max_sys_div;
334
335 dev_dbg(dev, "vt min/max_sys_div: %u,%u\n", min_sys_div, max_sys_div);
336
337 for (sys_div = min_sys_div; sys_div <= max_sys_div;
338 sys_div += 2 - (sys_div & 1)) {
339 u16 pix_div;
340
341 if (vt_div % sys_div)
342 continue;
343
344 pix_div = vt_div / sys_div;
345
346 if (pix_div < lim_bk->min_pix_clk_div ||
347 pix_div > lim_bk->max_pix_clk_div) {
348 dev_dbg(dev,
349 "pix_div %u too small or too big (%u--%u)\n",
350 pix_div,
351 lim_bk->min_pix_clk_div,
352 lim_bk->max_pix_clk_div);
353 continue;
354 }
355
356 dev_dbg(dev, "sys/pix/best_pix: %u,%u,%u\n", sys_div, pix_div,
357 best_pix_div);
358
359 if (pix_div * sys_div <= best_pix_div) {
360 best_pix_div = pix_div;
361 best_div = pix_div * sys_div;
362 }
363 }
364 if (best_pix_div == SHRT_MAX >> 1)
365 return -EINVAL;
366
367 pll_bk->sys_clk_div = best_div / best_pix_div;
368 pll_bk->pix_clk_div = best_pix_div;
369
370 pll_bk->sys_clk_freq_hz =
371 pll_fr->pll_op_clk_freq_hz / pll_bk->sys_clk_div;
372 pll_bk->pix_clk_freq_hz =
373 pll_bk->sys_clk_freq_hz / pll_bk->pix_clk_div;
374
375 pll->pixel_rate_pixel_array =
376 pll_bk->pix_clk_freq_hz * pll->vt_lanes;
377
378 return 0;
379 }
380
ccs_pll_calculate_vt_tree(struct device * dev,const struct ccs_pll_limits * lim,struct ccs_pll * pll)381 static int ccs_pll_calculate_vt_tree(struct device *dev,
382 const struct ccs_pll_limits *lim,
383 struct ccs_pll *pll)
384 {
385 const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
386 struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
387 u16 min_pre_pll_clk_div = lim_fr->min_pre_pll_clk_div;
388 u16 max_pre_pll_clk_div = lim_fr->max_pre_pll_clk_div;
389 u32 pre_mul, pre_div;
390
391 pre_div = gcd(pll->pixel_rate_csi,
392 pll->ext_clk_freq_hz * pll->vt_lanes);
393 pre_mul = pll->pixel_rate_csi / pre_div;
394 pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div;
395
396 /* Make sure PLL input frequency is within limits */
397 max_pre_pll_clk_div =
398 min_t(u16, max_pre_pll_clk_div,
399 DIV_ROUND_UP(pll->ext_clk_freq_hz,
400 lim_fr->min_pll_ip_clk_freq_hz));
401
402 min_pre_pll_clk_div = max_t(u16, min_pre_pll_clk_div,
403 pll->ext_clk_freq_hz /
404 lim_fr->max_pll_ip_clk_freq_hz);
405 if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER))
406 min_pre_pll_clk_div = clk_div_even(min_pre_pll_clk_div);
407
408 dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n",
409 min_pre_pll_clk_div, max_pre_pll_clk_div);
410
411 for (pll_fr->pre_pll_clk_div = min_pre_pll_clk_div;
412 pll_fr->pre_pll_clk_div <= max_pre_pll_clk_div;
413 pll_fr->pre_pll_clk_div +=
414 (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
415 2 - (pll_fr->pre_pll_clk_div & 1)) {
416 u32 mul, div;
417 int rval;
418
419 div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div);
420 mul = pre_mul * pll_fr->pre_pll_clk_div / div;
421 div = pre_div / div;
422
423 dev_dbg(dev, "vt pre-div/mul/div: %u,%u,%u\n",
424 pll_fr->pre_pll_clk_div, mul, div);
425
426 rval = __ccs_pll_calculate_vt_tree(dev, lim, pll,
427 mul, div);
428 if (rval)
429 continue;
430
431 rval = check_fr_bounds(dev, lim, pll, PLL_VT);
432 if (rval)
433 continue;
434
435 rval = check_bk_bounds(dev, lim, pll, PLL_VT);
436 if (rval)
437 continue;
438
439 return 0;
440 }
441
442 return -EINVAL;
443 }
444
445 static void
ccs_pll_calculate_vt(struct device * dev,const struct ccs_pll_limits * lim,const struct ccs_pll_branch_limits_bk * op_lim_bk,struct ccs_pll * pll,struct ccs_pll_branch_fr * pll_fr,struct ccs_pll_branch_bk * op_pll_bk,bool cphy,u32 phy_const)446 ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
447 const struct ccs_pll_branch_limits_bk *op_lim_bk,
448 struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
449 struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
450 u32 phy_const)
451 {
452 u16 sys_div;
453 u16 best_pix_div = SHRT_MAX >> 1;
454 u16 vt_op_binning_div;
455 u16 min_vt_div, max_vt_div, vt_div;
456 u16 min_sys_div, max_sys_div;
457
458 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
459 goto out_calc_pixel_rate;
460
461 /*
462 * Find out whether a sensor supports derating. If it does not, VT and
463 * OP domains are required to run at the same pixel rate.
464 */
465 if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) {
466 min_vt_div =
467 op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div
468 * pll->vt_lanes * phy_const / pll->op_lanes
469 / (PHY_CONST_DIV << op_pix_ddr(pll->flags));
470 } else {
471 /*
472 * Some sensors perform analogue binning and some do this
473 * digitally. The ones doing this digitally can be roughly be
474 * found out using this formula. The ones doing this digitally
475 * should run at higher clock rate, so smaller divisor is used
476 * on video timing side.
477 */
478 if (lim->min_line_length_pck_bin > lim->min_line_length_pck
479 / pll->binning_horizontal)
480 vt_op_binning_div = pll->binning_horizontal;
481 else
482 vt_op_binning_div = 1;
483 dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
484
485 /*
486 * Profile 2 supports vt_pix_clk_div E [4, 10]
487 *
488 * Horizontal binning can be used as a base for difference in
489 * divisors. One must make sure that horizontal blanking is
490 * enough to accommodate the CSI-2 sync codes.
491 *
492 * Take scaling factor and number of VT lanes into account as well.
493 *
494 * Find absolute limits for the factor of vt divider.
495 */
496 dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
497 min_vt_div =
498 DIV_ROUND_UP(pll->bits_per_pixel
499 * op_pll_bk->sys_clk_div * pll->scale_n
500 * pll->vt_lanes * phy_const,
501 (pll->flags &
502 CCS_PLL_FLAG_LANE_SPEED_MODEL ?
503 pll->csi2.lanes : 1)
504 * vt_op_binning_div * pll->scale_m
505 * PHY_CONST_DIV << op_pix_ddr(pll->flags));
506 }
507
508 /* Find smallest and biggest allowed vt divisor. */
509 dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
510 min_vt_div = max_t(u16, min_vt_div,
511 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
512 lim->vt_bk.max_pix_clk_freq_hz));
513 dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
514 min_vt_div);
515 min_vt_div = max_t(u16, min_vt_div, lim->vt_bk.min_pix_clk_div
516 * lim->vt_bk.min_sys_clk_div);
517 dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
518
519 max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
520 dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
521 max_vt_div = min_t(u16, max_vt_div,
522 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
523 lim->vt_bk.min_pix_clk_freq_hz));
524 dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
525 max_vt_div);
526
527 ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, min_vt_div,
528 max_vt_div, &min_sys_div, &max_sys_div);
529
530 /*
531 * Find pix_div such that a legal pix_div * sys_div results
532 * into a value which is not smaller than div, the desired
533 * divisor.
534 */
535 for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) {
536 u16 __max_sys_div = vt_div & 1 ? 1 : max_sys_div;
537
538 for (sys_div = min_sys_div; sys_div <= __max_sys_div;
539 sys_div += 2 - (sys_div & 1)) {
540 u16 pix_div;
541 u16 rounded_div;
542
543 pix_div = DIV_ROUND_UP(vt_div, sys_div);
544
545 if (pix_div < lim->vt_bk.min_pix_clk_div
546 || pix_div > lim->vt_bk.max_pix_clk_div) {
547 dev_dbg(dev,
548 "pix_div %u too small or too big (%u--%u)\n",
549 pix_div,
550 lim->vt_bk.min_pix_clk_div,
551 lim->vt_bk.max_pix_clk_div);
552 continue;
553 }
554
555 rounded_div = roundup(vt_div, best_pix_div);
556
557 /* Check if this one is better. */
558 if (pix_div * sys_div <= rounded_div)
559 best_pix_div = pix_div;
560
561 /* Bail out if we've already found the best value. */
562 if (vt_div == rounded_div)
563 break;
564 }
565 if (best_pix_div < SHRT_MAX >> 1)
566 break;
567 }
568
569 pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
570 pll->vt_bk.pix_clk_div = best_pix_div;
571
572 pll->vt_bk.sys_clk_freq_hz =
573 pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
574 pll->vt_bk.pix_clk_freq_hz =
575 pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
576
577 out_calc_pixel_rate:
578 pll->pixel_rate_pixel_array =
579 pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
580 }
581
582 /*
583 * Heuristically guess the PLL tree for a given common multiplier and
584 * divisor. Begin with the operational timing and continue to video
585 * timing once operational timing has been verified.
586 *
587 * @mul is the PLL multiplier and @div is the common divisor
588 * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
589 * multiplier will be a multiple of @mul.
590 *
591 * @return Zero on success, error code on error.
592 */
593 static int
ccs_pll_calculate_op(struct device * dev,const struct ccs_pll_limits * lim,const struct ccs_pll_branch_limits_fr * op_lim_fr,const struct ccs_pll_branch_limits_bk * op_lim_bk,struct ccs_pll * pll,struct ccs_pll_branch_fr * op_pll_fr,struct ccs_pll_branch_bk * op_pll_bk,u32 mul,u32 div,u32 op_sys_clk_freq_hz_sdr,u32 l,bool cphy,u32 phy_const)594 ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
595 const struct ccs_pll_branch_limits_fr *op_lim_fr,
596 const struct ccs_pll_branch_limits_bk *op_lim_bk,
597 struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
598 struct ccs_pll_branch_bk *op_pll_bk, u32 mul,
599 u32 div, u32 op_sys_clk_freq_hz_sdr, u32 l,
600 bool cphy, u32 phy_const)
601 {
602 /*
603 * Higher multipliers (and divisors) are often required than
604 * necessitated by the external clock and the output clocks.
605 * There are limits for all values in the clock tree. These
606 * are the minimum and maximum multiplier for mul.
607 */
608 u32 more_mul_min, more_mul_max;
609 u32 more_mul_factor;
610 u32 i;
611
612 /*
613 * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
614 * too high.
615 */
616 dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div);
617
618 /* Don't go above max pll multiplier. */
619 more_mul_max = op_lim_fr->max_pll_multiplier / mul;
620 dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n",
621 more_mul_max);
622 /* Don't go above max pll op frequency. */
623 more_mul_max =
624 min_t(u32,
625 more_mul_max,
626 op_lim_fr->max_pll_op_clk_freq_hz
627 / (pll->ext_clk_freq_hz /
628 op_pll_fr->pre_pll_clk_div * mul));
629 dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n",
630 more_mul_max);
631 /* Don't go above the division capability of op sys clock divider. */
632 more_mul_max = min(more_mul_max,
633 op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div
634 / div);
635 dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
636 more_mul_max);
637 /* Ensure we won't go above max_pll_multiplier. */
638 more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul);
639 dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
640 more_mul_max);
641
642 /* Ensure we won't go below min_pll_op_clk_freq_hz. */
643 more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz,
644 pll->ext_clk_freq_hz /
645 op_pll_fr->pre_pll_clk_div * mul);
646 dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n",
647 more_mul_min);
648 /* Ensure we won't go below min_pll_multiplier. */
649 more_mul_min = max(more_mul_min,
650 DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul));
651 dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n",
652 more_mul_min);
653
654 if (more_mul_min > more_mul_max) {
655 dev_dbg(dev,
656 "unable to compute more_mul_min and more_mul_max\n");
657 return -EINVAL;
658 }
659
660 more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div;
661 dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
662 more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div);
663 dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
664 more_mul_factor);
665 i = roundup(more_mul_min, more_mul_factor);
666 if (!is_one_or_even(i))
667 i <<= 1;
668
669 dev_dbg(dev, "final more_mul: %u\n", i);
670 if (i > more_mul_max) {
671 dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
672 return -EINVAL;
673 }
674
675 op_pll_fr->pll_multiplier = mul * i;
676 op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div;
677 dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div);
678
679 op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
680 / op_pll_fr->pre_pll_clk_div;
681
682 op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
683 * op_pll_fr->pll_multiplier;
684
685 if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
686 op_pll_bk->pix_clk_div =
687 (pll->bits_per_pixel
688 * pll->op_lanes * (phy_const << op_sys_ddr(pll->flags))
689 / PHY_CONST_DIV / pll->csi2.lanes / l)
690 >> op_pix_ddr(pll->flags);
691 else
692 op_pll_bk->pix_clk_div =
693 (pll->bits_per_pixel
694 * (phy_const << op_sys_ddr(pll->flags))
695 / PHY_CONST_DIV / l) >> op_pix_ddr(pll->flags);
696
697 op_pll_bk->pix_clk_freq_hz =
698 (op_sys_clk_freq_hz_sdr >> op_pix_ddr(pll->flags))
699 / op_pll_bk->pix_clk_div;
700 op_pll_bk->sys_clk_freq_hz =
701 op_sys_clk_freq_hz_sdr >> op_sys_ddr(pll->flags);
702
703 dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
704
705 return 0;
706 }
707
ccs_pll_calculate(struct device * dev,const struct ccs_pll_limits * lim,struct ccs_pll * pll)708 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
709 struct ccs_pll *pll)
710 {
711 const struct ccs_pll_branch_limits_fr *op_lim_fr;
712 const struct ccs_pll_branch_limits_bk *op_lim_bk;
713 struct ccs_pll_branch_fr *op_pll_fr;
714 struct ccs_pll_branch_bk *op_pll_bk;
715 bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY;
716 u32 phy_const = cphy ? CPHY_CONST : DPHY_CONST;
717 u32 op_sys_clk_freq_hz_sdr;
718 u16 min_op_pre_pll_clk_div;
719 u16 max_op_pre_pll_clk_div;
720 u32 mul, div;
721 u32 l = (!pll->op_bits_per_lane ||
722 pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2;
723 u32 i;
724 int rval = -EINVAL;
725
726 if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) {
727 pll->op_lanes = 1;
728 pll->vt_lanes = 1;
729 }
730
731 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
732 op_lim_fr = &lim->op_fr;
733 op_lim_bk = &lim->op_bk;
734 op_pll_fr = &pll->op_fr;
735 op_pll_bk = &pll->op_bk;
736 } else if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
737 /*
738 * If there's no OP PLL at all, use the VT values
739 * instead. The OP values are ignored for the rest of
740 * the PLL calculation.
741 */
742 op_lim_fr = &lim->vt_fr;
743 op_lim_bk = &lim->vt_bk;
744 op_pll_fr = &pll->vt_fr;
745 op_pll_bk = &pll->vt_bk;
746 } else {
747 op_lim_fr = &lim->vt_fr;
748 op_lim_bk = &lim->op_bk;
749 op_pll_fr = &pll->vt_fr;
750 op_pll_bk = &pll->op_bk;
751 }
752
753 if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel ||
754 !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m ||
755 !op_lim_fr->min_pll_ip_clk_freq_hz ||
756 !op_lim_fr->max_pll_ip_clk_freq_hz ||
757 !op_lim_fr->min_pll_op_clk_freq_hz ||
758 !op_lim_fr->max_pll_op_clk_freq_hz ||
759 !op_lim_bk->max_sys_clk_div || !op_lim_fr->max_pll_multiplier)
760 return -EINVAL;
761
762 /*
763 * Make sure op_pix_clk_div will be integer --- unless flexible
764 * op_pix_clk_div is supported
765 */
766 if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) &&
767 (pll->bits_per_pixel * pll->op_lanes) %
768 (pll->csi2.lanes * l << op_pix_ddr(pll->flags))) {
769 dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n",
770 pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l);
771 return -EINVAL;
772 }
773
774 dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
775 dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
776
777 dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
778 pll->binning_vertical);
779
780 switch (pll->bus_type) {
781 case CCS_PLL_BUS_TYPE_CSI2_DPHY:
782 case CCS_PLL_BUS_TYPE_CSI2_CPHY:
783 op_sys_clk_freq_hz_sdr = pll->link_freq * 2
784 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
785 1 : pll->csi2.lanes);
786 break;
787 default:
788 return -EINVAL;
789 }
790
791 pll->pixel_rate_csi =
792 div_u64((uint64_t)op_sys_clk_freq_hz_sdr
793 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
794 pll->csi2.lanes : 1) * PHY_CONST_DIV,
795 phy_const * pll->bits_per_pixel * l);
796
797 /* Figure out limits for OP pre-pll divider based on extclk */
798 dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
799 op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div);
800 max_op_pre_pll_clk_div =
801 min_t(u16, op_lim_fr->max_pre_pll_clk_div,
802 DIV_ROUND_UP(pll->ext_clk_freq_hz,
803 op_lim_fr->min_pll_ip_clk_freq_hz));
804 min_op_pre_pll_clk_div =
805 max_t(u16, op_lim_fr->min_pre_pll_clk_div,
806 clk_div_even_up(
807 DIV_ROUND_UP(pll->ext_clk_freq_hz,
808 op_lim_fr->max_pll_ip_clk_freq_hz)));
809 dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n",
810 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
811
812 i = gcd(op_sys_clk_freq_hz_sdr,
813 pll->ext_clk_freq_hz << op_pix_ddr(pll->flags));
814 mul = op_sys_clk_freq_hz_sdr / i;
815 div = (pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)) / i;
816 dev_dbg(dev, "mul %u / div %u\n", mul, div);
817
818 min_op_pre_pll_clk_div =
819 max_t(u16, min_op_pre_pll_clk_div,
820 clk_div_even_up(
821 mul /
822 one_or_more(
823 DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz,
824 pll->ext_clk_freq_hz))));
825 if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER))
826 min_op_pre_pll_clk_div = clk_div_even(min_op_pre_pll_clk_div);
827 dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
828 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
829
830 for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div;
831 op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
832 op_pll_fr->pre_pll_clk_div +=
833 (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
834 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
835 rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll,
836 op_pll_fr, op_pll_bk, mul, div,
837 op_sys_clk_freq_hz_sdr, l, cphy,
838 phy_const);
839 if (rval)
840 continue;
841
842 rval = check_fr_bounds(dev, lim, pll,
843 pll->flags & CCS_PLL_FLAG_DUAL_PLL ?
844 PLL_OP : PLL_VT);
845 if (rval)
846 continue;
847
848 rval = check_bk_bounds(dev, lim, pll, PLL_OP);
849 if (rval)
850 continue;
851
852 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL)
853 break;
854
855 ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
856 op_pll_bk, cphy, phy_const);
857
858 rval = check_bk_bounds(dev, lim, pll, PLL_VT);
859 if (rval)
860 continue;
861 rval = check_ext_bounds(dev, pll);
862 if (rval)
863 continue;
864
865 break;
866 }
867
868 if (rval) {
869 dev_dbg(dev, "unable to compute pre_pll divisor\n");
870
871 return rval;
872 }
873
874 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
875 rval = ccs_pll_calculate_vt_tree(dev, lim, pll);
876
877 if (rval)
878 return rval;
879 }
880
881 print_pll(dev, pll);
882
883 return 0;
884 }
885 EXPORT_SYMBOL_GPL(ccs_pll_calculate);
886
887 MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
888 MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator");
889 MODULE_LICENSE("GPL");
890