1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 8 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 9 #define __QCOM_CLK_ALPHA_PLL_H__ 10 11 #include <linux/clk-provider.h> 12 #include "clk-regmap.h" 13 14 /* Alpha PLL types */ 15 enum { 16 CLK_ALPHA_PLL_TYPE_DEFAULT, 17 CLK_ALPHA_PLL_TYPE_HUAYRA, 18 CLK_ALPHA_PLL_TYPE_BRAMMO, 19 CLK_ALPHA_PLL_TYPE_FABIA, 20 CLK_ALPHA_PLL_TYPE_TRION, 21 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 22 CLK_ALPHA_PLL_TYPE_AGERA, 23 CLK_ALPHA_PLL_TYPE_ZONDA, 24 CLK_ALPHA_PLL_TYPE_ZONDA_OLE, 25 CLK_ALPHA_PLL_TYPE_LUCID_EVO, 26 CLK_ALPHA_PLL_TYPE_LUCID_OLE, 27 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, 28 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, 29 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, 30 CLK_ALPHA_PLL_TYPE_STROMER, 31 CLK_ALPHA_PLL_TYPE_STROMER_PLUS, 32 CLK_ALPHA_PLL_TYPE_NSS_HUAYRA, 33 CLK_ALPHA_PLL_TYPE_MAX, 34 }; 35 36 enum { 37 PLL_OFF_L_VAL, 38 PLL_OFF_CAL_L_VAL, 39 PLL_OFF_ALPHA_VAL, 40 PLL_OFF_ALPHA_VAL_U, 41 PLL_OFF_USER_CTL, 42 PLL_OFF_USER_CTL_U, 43 PLL_OFF_USER_CTL_U1, 44 PLL_OFF_CONFIG_CTL, 45 PLL_OFF_CONFIG_CTL_U, 46 PLL_OFF_CONFIG_CTL_U1, 47 PLL_OFF_CONFIG_CTL_U2, 48 PLL_OFF_TEST_CTL, 49 PLL_OFF_TEST_CTL_U, 50 PLL_OFF_TEST_CTL_U1, 51 PLL_OFF_TEST_CTL_U2, 52 PLL_OFF_STATE, 53 PLL_OFF_STATUS, 54 PLL_OFF_OPMODE, 55 PLL_OFF_FRAC, 56 PLL_OFF_CAL_VAL, 57 PLL_OFF_MAX_REGS 58 }; 59 60 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 61 62 struct pll_vco { 63 unsigned long min_freq; 64 unsigned long max_freq; 65 u32 val; 66 }; 67 68 #define VCO(a, b, c) { \ 69 .val = a,\ 70 .min_freq = b,\ 71 .max_freq = c,\ 72 } 73 74 /** 75 * struct clk_alpha_pll - phase locked loop (PLL) 76 * @offset: base address of registers 77 * @vco_table: array of VCO settings 78 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 79 * @clkr: regmap clock handle 80 */ 81 struct clk_alpha_pll { 82 u32 offset; 83 const u8 *regs; 84 85 const struct pll_vco *vco_table; 86 size_t num_vco; 87 #define SUPPORTS_OFFLINE_REQ BIT(0) 88 #define SUPPORTS_FSM_MODE BIT(2) 89 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 90 #define SUPPORTS_FSM_LEGACY_MODE BIT(4) 91 u8 flags; 92 93 struct clk_regmap clkr; 94 }; 95 96 /** 97 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 98 * @offset: base address of registers 99 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 100 * @width: width of post-divider 101 * @post_div_shift: shift to differentiate between odd & even post-divider 102 * @post_div_table: table with PLL odd and even post-divider settings 103 * @num_post_div: Number of PLL post-divider settings 104 * 105 * @clkr: regmap clock handle 106 */ 107 struct clk_alpha_pll_postdiv { 108 u32 offset; 109 u8 width; 110 const u8 *regs; 111 112 struct clk_regmap clkr; 113 int post_div_shift; 114 const struct clk_div_table *post_div_table; 115 size_t num_post_div; 116 }; 117 118 struct alpha_pll_config { 119 u32 l; 120 u32 alpha; 121 u32 alpha_hi; 122 u32 config_ctl_val; 123 u32 config_ctl_hi_val; 124 u32 config_ctl_hi1_val; 125 u32 config_ctl_hi2_val; 126 u32 user_ctl_val; 127 u32 user_ctl_hi_val; 128 u32 user_ctl_hi1_val; 129 u32 test_ctl_val; 130 u32 test_ctl_mask; 131 u32 test_ctl_hi_val; 132 u32 test_ctl_hi_mask; 133 u32 test_ctl_hi1_val; 134 u32 test_ctl_hi2_val; 135 u32 main_output_mask; 136 u32 aux_output_mask; 137 u32 aux2_output_mask; 138 u32 early_output_mask; 139 u32 alpha_en_mask; 140 u32 alpha_mode_mask; 141 u32 pre_div_val; 142 u32 pre_div_mask; 143 u32 post_div_val; 144 u32 post_div_mask; 145 u32 vco_val; 146 u32 vco_mask; 147 u32 status_val; 148 u32 status_mask; 149 u32 lock_det; 150 }; 151 152 extern const struct clk_ops clk_alpha_pll_ops; 153 extern const struct clk_ops clk_alpha_pll_fixed_ops; 154 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 155 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 156 extern const struct clk_ops clk_alpha_pll_huayra_ops; 157 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 158 extern const struct clk_ops clk_alpha_pll_stromer_ops; 159 extern const struct clk_ops clk_alpha_pll_stromer_plus_ops; 160 161 extern const struct clk_ops clk_alpha_pll_fabia_ops; 162 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 163 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 164 165 extern const struct clk_ops clk_alpha_pll_trion_ops; 166 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops; 167 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; 168 169 extern const struct clk_ops clk_alpha_pll_lucid_ops; 170 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops 171 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 172 extern const struct clk_ops clk_alpha_pll_agera_ops; 173 174 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; 175 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; 176 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; 177 178 extern const struct clk_ops clk_alpha_pll_zonda_ops; 179 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops 180 #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops 181 182 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; 183 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; 184 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops 185 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; 186 #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops 187 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; 188 #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops 189 190 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; 191 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops 192 193 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 194 const struct alpha_pll_config *config); 195 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 196 const struct alpha_pll_config *config); 197 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 198 const struct alpha_pll_config *config); 199 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 200 const struct alpha_pll_config *config); 201 #define clk_lucid_pll_configure(pll, regmap, config) \ 202 clk_trion_pll_configure(pll, regmap, config) 203 204 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 205 const struct alpha_pll_config *config); 206 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 207 const struct alpha_pll_config *config); 208 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 209 const struct alpha_pll_config *config); 210 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 211 const struct alpha_pll_config *config); 212 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 213 const struct alpha_pll_config *config); 214 215 #endif 216