1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
16 #include <linux/suspend.h>
17
18 #include "xhci.h"
19 #include "xhci-trace.h"
20 #include "xhci-pci.h"
21
22 #define SSIC_PORT_NUM 2
23 #define SSIC_PORT_CFG2 0x880c
24 #define SSIC_PORT_CFG2_OFFSET 0x30
25 #define PROG_DONE (1 << 30)
26 #define SSIC_PORT_UNUSED (1 << 31)
27 #define SPARSE_DISABLE_BIT 17
28 #define SPARSE_CNTL_ENABLE 0xC12C
29
30 /* Device for a quirk */
31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
36
37 #define PCI_VENDOR_ID_ETRON 0x1b6f
38 #define PCI_DEVICE_ID_EJ168 0x7023
39 #define PCI_DEVICE_ID_EJ188 0x7052
40
41 #define PCI_DEVICE_ID_VIA_VL805 0x3483
42
43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
44 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
45 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
46 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
47 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
48 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
49 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
50 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
51 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
52 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
55 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
56 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
57 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
58 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
59 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
60 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
61 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
62 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
63 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
64 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
65 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
66 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed
67
68 #define PCI_DEVICE_ID_AMD_ARIEL_TYPEC_XHCI 0x13ed
69 #define PCI_DEVICE_ID_AMD_ARIEL_TYPEA_XHCI 0x13ee
70 #define PCI_DEVICE_ID_AMD_STARSHIP_XHCI 0x148c
71 #define PCI_DEVICE_ID_AMD_FIREFLIGHT_15D4_XHCI 0x15d4
72 #define PCI_DEVICE_ID_AMD_FIREFLIGHT_15D5_XHCI 0x15d5
73 #define PCI_DEVICE_ID_AMD_RAVEN_15E0_XHCI 0x15e0
74 #define PCI_DEVICE_ID_AMD_RAVEN_15E1_XHCI 0x15e1
75 #define PCI_DEVICE_ID_AMD_RAVEN2_XHCI 0x15e5
76 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
77 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
78 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
79 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
80 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
81
82 #define PCI_DEVICE_ID_ATI_NAVI10_7316_XHCI 0x7316
83
84 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
85 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
86 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
87 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
88 #define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042
89 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
90
91 #define PCI_DEVICE_ID_CADENCE 0x17CD
92 #define PCI_DEVICE_ID_CADENCE_SSP 0x0200
93
94 static const char hcd_name[] = "xhci_hcd";
95
96 static struct hc_driver __read_mostly xhci_pci_hc_driver;
97
98 static int xhci_pci_setup(struct usb_hcd *hcd);
99 static int xhci_pci_run(struct usb_hcd *hcd);
100 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
101 struct usb_tt *tt, gfp_t mem_flags);
102
103 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
104 .reset = xhci_pci_setup,
105 .start = xhci_pci_run,
106 .update_hub_device = xhci_pci_update_hub_device,
107 };
108
xhci_msix_sync_irqs(struct xhci_hcd * xhci)109 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
110 {
111 struct usb_hcd *hcd = xhci_to_hcd(xhci);
112
113 if (hcd->msix_enabled) {
114 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
115 int i;
116
117 for (i = 0; i < xhci->msix_count; i++)
118 synchronize_irq(pci_irq_vector(pdev, i));
119 }
120 }
121
122 /* Free any IRQs and disable MSI-X */
xhci_cleanup_msix(struct xhci_hcd * xhci)123 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
124 {
125 struct usb_hcd *hcd = xhci_to_hcd(xhci);
126 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
127
128 /* return if using legacy interrupt */
129 if (hcd->irq > 0)
130 return;
131
132 if (hcd->msix_enabled) {
133 int i;
134
135 for (i = 0; i < xhci->msix_count; i++)
136 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
137 } else {
138 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
139 }
140
141 pci_free_irq_vectors(pdev);
142 hcd->msix_enabled = 0;
143 }
144
145 /*
146 * Set up MSI
147 */
xhci_setup_msi(struct xhci_hcd * xhci)148 static int xhci_setup_msi(struct xhci_hcd *xhci)
149 {
150 int ret;
151 /*
152 * TODO:Check with MSI Soc for sysdev
153 */
154 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
155
156 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
157 if (ret < 0) {
158 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
159 "failed to allocate MSI entry");
160 return ret;
161 }
162
163 ret = request_irq(pdev->irq, xhci_msi_irq,
164 0, "xhci_hcd", xhci_to_hcd(xhci));
165 if (ret) {
166 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
167 "disable MSI interrupt");
168 pci_free_irq_vectors(pdev);
169 }
170
171 return ret;
172 }
173
174 /*
175 * Set up MSI-X
176 */
xhci_setup_msix(struct xhci_hcd * xhci)177 static int xhci_setup_msix(struct xhci_hcd *xhci)
178 {
179 int i, ret;
180 struct usb_hcd *hcd = xhci_to_hcd(xhci);
181 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
182
183 /*
184 * calculate number of msi-x vectors supported.
185 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
186 * with max number of interrupters based on the xhci HCSPARAMS1.
187 * - num_online_cpus: maximum msi-x vectors per CPUs core.
188 * Add additional 1 vector to ensure always available interrupt.
189 */
190 xhci->msix_count = min(num_online_cpus() + 1,
191 HCS_MAX_INTRS(xhci->hcs_params1));
192
193 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
194 PCI_IRQ_MSIX);
195 if (ret < 0) {
196 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
197 "Failed to enable MSI-X");
198 return ret;
199 }
200
201 for (i = 0; i < xhci->msix_count; i++) {
202 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
203 "xhci_hcd", xhci_to_hcd(xhci));
204 if (ret)
205 goto disable_msix;
206 }
207
208 hcd->msix_enabled = 1;
209 return ret;
210
211 disable_msix:
212 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
213 while (--i >= 0)
214 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
215 pci_free_irq_vectors(pdev);
216 return ret;
217 }
218
xhci_try_enable_msi(struct usb_hcd * hcd)219 static int xhci_try_enable_msi(struct usb_hcd *hcd)
220 {
221 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
222 struct pci_dev *pdev;
223 int ret;
224
225 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
226 /*
227 * Some Fresco Logic host controllers advertise MSI, but fail to
228 * generate interrupts. Don't even try to enable MSI.
229 */
230 if (xhci->quirks & XHCI_BROKEN_MSI)
231 goto legacy_irq;
232
233 /* unregister the legacy interrupt */
234 if (hcd->irq)
235 free_irq(hcd->irq, hcd);
236 hcd->irq = 0;
237
238 ret = xhci_setup_msix(xhci);
239 if (ret)
240 /* fall back to msi*/
241 ret = xhci_setup_msi(xhci);
242
243 if (!ret) {
244 hcd->msi_enabled = 1;
245 return 0;
246 }
247
248 if (!pdev->irq) {
249 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
250 return -EINVAL;
251 }
252
253 legacy_irq:
254 if (!strlen(hcd->irq_descr))
255 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
256 hcd->driver->description, hcd->self.busnum);
257
258 /* fall back to legacy interrupt*/
259 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
260 hcd->irq_descr, hcd);
261 if (ret) {
262 xhci_err(xhci, "request interrupt %d failed\n",
263 pdev->irq);
264 return ret;
265 }
266 hcd->irq = pdev->irq;
267 return 0;
268 }
269
xhci_pci_run(struct usb_hcd * hcd)270 static int xhci_pci_run(struct usb_hcd *hcd)
271 {
272 int ret;
273
274 if (usb_hcd_is_primary_hcd(hcd)) {
275 ret = xhci_try_enable_msi(hcd);
276 if (ret)
277 return ret;
278 }
279
280 return xhci_run(hcd);
281 }
282
xhci_pci_stop(struct usb_hcd * hcd)283 static void xhci_pci_stop(struct usb_hcd *hcd)
284 {
285 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
286
287 xhci_stop(hcd);
288
289 if (usb_hcd_is_primary_hcd(hcd))
290 xhci_cleanup_msix(xhci);
291 }
292
293 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)294 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
295 {
296 /*
297 * TODO: Implement finding debug ports later.
298 * TODO: see if there are any quirks that need to be added to handle
299 * new extended capabilities.
300 */
301
302 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
303 if (!pci_set_mwi(pdev))
304 xhci_dbg(xhci, "MWI active\n");
305
306 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
307 return 0;
308 }
309
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)310 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
311 {
312 struct pci_dev *pdev = to_pci_dev(dev);
313 struct xhci_driver_data *driver_data;
314 const struct pci_device_id *id;
315
316 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
317
318 if (id && id->driver_data) {
319 driver_data = (struct xhci_driver_data *)id->driver_data;
320 xhci->quirks |= driver_data->quirks;
321 }
322
323 /* Look for vendor-specific quirks */
324 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
325 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
326 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
327 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
328 pdev->revision == 0x0) {
329 xhci->quirks |= XHCI_RESET_EP_QUIRK;
330 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
331 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
332 }
333 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
334 pdev->revision == 0x4) {
335 xhci->quirks |= XHCI_SLOW_SUSPEND;
336 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
337 "QUIRK: Fresco Logic xHC revision %u"
338 "must be suspended extra slowly",
339 pdev->revision);
340 }
341 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
342 xhci->quirks |= XHCI_BROKEN_STREAMS;
343 /* Fresco Logic confirms: all revisions of this chip do not
344 * support MSI, even though some of them claim to in their PCI
345 * capabilities.
346 */
347 xhci->quirks |= XHCI_BROKEN_MSI;
348 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
349 "QUIRK: Fresco Logic revision %u "
350 "has broken MSI implementation",
351 pdev->revision);
352 }
353
354 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
355 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
356 xhci->quirks |= XHCI_BROKEN_STREAMS;
357
358 if (pdev->vendor == PCI_VENDOR_ID_NEC)
359 xhci->quirks |= XHCI_NEC_HOST;
360
361 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
362 (pdev->device == PCI_DEVICE_ID_AMD_ARIEL_TYPEC_XHCI ||
363 pdev->device == PCI_DEVICE_ID_AMD_ARIEL_TYPEA_XHCI ||
364 pdev->device == PCI_DEVICE_ID_AMD_STARSHIP_XHCI ||
365 pdev->device == PCI_DEVICE_ID_AMD_FIREFLIGHT_15D4_XHCI ||
366 pdev->device == PCI_DEVICE_ID_AMD_FIREFLIGHT_15D5_XHCI ||
367 pdev->device == PCI_DEVICE_ID_AMD_RAVEN_15E0_XHCI ||
368 pdev->device == PCI_DEVICE_ID_AMD_RAVEN_15E1_XHCI ||
369 pdev->device == PCI_DEVICE_ID_AMD_RAVEN2_XHCI))
370 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_9;
371
372 if (pdev->vendor == PCI_VENDOR_ID_ATI &&
373 pdev->device == PCI_DEVICE_ID_ATI_NAVI10_7316_XHCI)
374 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_9;
375
376 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
377 xhci->quirks |= XHCI_AMD_0x96_HOST;
378
379 /* AMD PLL quirk */
380 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
381 xhci->quirks |= XHCI_AMD_PLL_FIX;
382
383 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
384 (pdev->device == 0x145c ||
385 pdev->device == 0x15e0 ||
386 pdev->device == 0x15e1 ||
387 pdev->device == 0x43bb))
388 xhci->quirks |= XHCI_SUSPEND_DELAY;
389
390 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
391 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
392 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
393
394 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
395 xhci->quirks |= XHCI_DISABLE_SPARSE;
396 xhci->quirks |= XHCI_RESET_ON_RESUME;
397 }
398
399 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7)
400 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
401
402 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
403 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
404 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
405 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
406 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
407 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
408
409 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
410 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
411 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I;
412
413 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
414 xhci->quirks |= XHCI_LPM_SUPPORT;
415 xhci->quirks |= XHCI_INTEL_HOST;
416 xhci->quirks |= XHCI_AVOID_BEI;
417 }
418 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
419 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
420 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
421 xhci->limit_active_eps = 64;
422 xhci->quirks |= XHCI_SW_BW_CHECKING;
423 /*
424 * PPT desktop boards DH77EB and DH77DF will power back on after
425 * a few seconds of being shutdown. The fix for this is to
426 * switch the ports from xHCI to EHCI on shutdown. We can't use
427 * DMI information to find those particular boards (since each
428 * vendor will change the board name), so we have to key off all
429 * PPT chipsets.
430 */
431 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
432 }
433 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
434 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
435 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
436 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
437 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
438 }
439 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
440 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
441 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
442 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
443 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
444 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
445 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
446 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
447 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
448 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
449 }
450 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
451 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
452 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
453 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
454 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
455 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
456 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
457 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
458 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
459 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
460 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
461 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
462 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
463 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
464 xhci->quirks |= XHCI_MISSING_CAS;
465
466 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
467 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
468 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
469 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
470
471 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
472 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
473 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
474 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
475 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
476 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
477 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
478 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
479 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
480 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
481 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
482 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
483 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
484
485 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
486 (pdev->device == PCI_DEVICE_ID_EJ168 ||
487 pdev->device == PCI_DEVICE_ID_EJ188)) {
488 xhci->quirks |= XHCI_ETRON_HOST;
489 xhci->quirks |= XHCI_RESET_ON_RESUME;
490 xhci->quirks |= XHCI_BROKEN_STREAMS;
491 }
492
493 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
494 pdev->device == 0x0014) {
495 xhci->quirks |= XHCI_ZERO_64B_REGS;
496 }
497 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
498 pdev->device == 0x0015) {
499 xhci->quirks |= XHCI_RESET_ON_RESUME;
500 xhci->quirks |= XHCI_ZERO_64B_REGS;
501 }
502 if (pdev->vendor == PCI_VENDOR_ID_VIA)
503 xhci->quirks |= XHCI_RESET_ON_RESUME;
504
505 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
506 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
507 pdev->device == 0x3432)
508 xhci->quirks |= XHCI_BROKEN_STREAMS;
509
510 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == PCI_DEVICE_ID_VIA_VL805) {
511 xhci->quirks |= XHCI_LPM_SUPPORT;
512 xhci->quirks |= XHCI_TRB_OVERFETCH;
513 }
514
515 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
516 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
517 /*
518 * try to tame the ASMedia 1042 controller which reports 0.96
519 * but appears to behave more like 1.0
520 */
521 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
522 xhci->quirks |= XHCI_BROKEN_STREAMS;
523 }
524 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
525 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
526 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
527 }
528 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
529 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
530 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
531 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
532 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
533
534 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
535 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
536 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
537
538 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
539 pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI)
540 xhci->quirks |= XHCI_RESET_ON_RESUME;
541
542 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
543 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
544
545 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
546 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
547 pdev->device == 0x9026)
548 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
549
550 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
551 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
552 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
553 xhci->quirks |= XHCI_NO_SOFT_RETRY;
554
555 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
556 xhci->quirks |= XHCI_ZHAOXIN_HOST;
557 xhci->quirks |= XHCI_LPM_SUPPORT;
558
559 if (pdev->device == 0x9202) {
560 xhci->quirks |= XHCI_RESET_ON_RESUME;
561 xhci->quirks |= XHCI_TRB_OVERFETCH;
562 }
563
564 if (pdev->device == 0x9203)
565 xhci->quirks |= XHCI_TRB_OVERFETCH;
566 }
567
568 if (pdev->vendor == PCI_DEVICE_ID_CADENCE &&
569 pdev->device == PCI_DEVICE_ID_CADENCE_SSP)
570 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK;
571
572 /* xHC spec requires PCI devices to support D3hot and D3cold */
573 if (xhci->hci_version >= 0x120)
574 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
575
576 if (xhci->quirks & XHCI_RESET_ON_RESUME)
577 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
578 "QUIRK: Resetting on resume");
579 }
580
581 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)582 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
583 {
584 static const guid_t intel_dsm_guid =
585 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
586 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
587 union acpi_object *obj;
588
589 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
590 NULL);
591 ACPI_FREE(obj);
592 }
593
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)594 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
595 {
596 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
597 struct xhci_hub *rhub = &xhci->usb3_rhub;
598 int ret;
599 int i;
600
601 /* This is not the usb3 roothub we are looking for */
602 if (hcd != rhub->hcd)
603 return;
604
605 if (hdev->maxchild > rhub->num_ports) {
606 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
607 return;
608 }
609
610 for (i = 0; i < hdev->maxchild; i++) {
611 ret = usb_acpi_port_lpm_incapable(hdev, i);
612
613 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
614
615 if (ret >= 0) {
616 rhub->ports[i]->lpm_incapable = ret;
617 continue;
618 }
619 }
620 }
621
622 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)623 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)624 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
625 #endif /* CONFIG_ACPI */
626
627 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)628 static int xhci_pci_setup(struct usb_hcd *hcd)
629 {
630 struct xhci_hcd *xhci;
631 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
632 int retval;
633
634 xhci = hcd_to_xhci(hcd);
635 if (!xhci->sbrn)
636 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
637
638 /* imod_interval is the interrupt moderation value in nanoseconds. */
639 xhci->imod_interval = 40000;
640
641 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
642 if (retval)
643 return retval;
644
645 if (!usb_hcd_is_primary_hcd(hcd))
646 return 0;
647
648 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
649 xhci_pme_acpi_rtd3_enable(pdev);
650
651 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
652
653 /* Find any debug ports */
654 return xhci_pci_reinit(xhci, pdev);
655 }
656
xhci_pci_update_hub_device(struct usb_hcd * hcd,struct usb_device * hdev,struct usb_tt * tt,gfp_t mem_flags)657 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
658 struct usb_tt *tt, gfp_t mem_flags)
659 {
660 /* Check if acpi claims some USB3 roothub ports are lpm incapable */
661 if (!hdev->parent)
662 xhci_find_lpm_incapable_ports(hcd, hdev);
663
664 return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
665 }
666
667 /*
668 * We need to register our own PCI probe function (instead of the USB core's
669 * function) in order to create a second roothub under xHCI.
670 */
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)671 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
672 {
673 int retval;
674 struct xhci_hcd *xhci;
675 struct usb_hcd *hcd;
676 struct xhci_driver_data *driver_data;
677 struct reset_control *reset;
678
679 driver_data = (struct xhci_driver_data *)id->driver_data;
680 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
681 retval = renesas_xhci_check_request_fw(dev, id);
682 if (retval)
683 return retval;
684 }
685
686 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
687 if (IS_ERR(reset))
688 return PTR_ERR(reset);
689 reset_control_reset(reset);
690
691 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
692 pm_runtime_get_noresume(&dev->dev);
693
694 /* Register the USB 2.0 roothub.
695 * FIXME: USB core must know to register the USB 2.0 roothub first.
696 * This is sort of silly, because we could just set the HCD driver flags
697 * to say USB 2.0, but I'm not sure what the implications would be in
698 * the other parts of the HCD code.
699 */
700 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
701
702 if (retval)
703 goto put_runtime_pm;
704
705 /* USB 2.0 roothub is stored in the PCI device now. */
706 hcd = dev_get_drvdata(&dev->dev);
707 xhci = hcd_to_xhci(hcd);
708 xhci->reset = reset;
709 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
710 pci_name(dev), hcd);
711 if (!xhci->shared_hcd) {
712 retval = -ENOMEM;
713 goto dealloc_usb2_hcd;
714 }
715
716 retval = xhci_ext_cap_init(xhci);
717 if (retval)
718 goto put_usb3_hcd;
719
720 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
721 IRQF_SHARED);
722 if (retval)
723 goto put_usb3_hcd;
724 /* Roothub already marked as USB 3.0 speed */
725
726 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
727 HCC_MAX_PSA(xhci->hcc_params) >= 4)
728 xhci->shared_hcd->can_do_streams = 1;
729
730 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
731 pm_runtime_put_noidle(&dev->dev);
732
733 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
734 pm_runtime_get(&dev->dev);
735 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
736 pm_runtime_allow(&dev->dev);
737
738 dma_set_max_seg_size(&dev->dev, UINT_MAX);
739
740 return 0;
741
742 put_usb3_hcd:
743 usb_put_hcd(xhci->shared_hcd);
744 dealloc_usb2_hcd:
745 usb_hcd_pci_remove(dev);
746 put_runtime_pm:
747 pm_runtime_put_noidle(&dev->dev);
748 return retval;
749 }
750
xhci_pci_remove(struct pci_dev * dev)751 static void xhci_pci_remove(struct pci_dev *dev)
752 {
753 struct xhci_hcd *xhci;
754 bool set_power_d3;
755
756 xhci = hcd_to_xhci(pci_get_drvdata(dev));
757 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP;
758
759 xhci->xhc_state |= XHCI_STATE_REMOVING;
760
761 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
762 pm_runtime_put(&dev->dev);
763 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
764 pm_runtime_forbid(&dev->dev);
765
766 if (xhci->shared_hcd) {
767 usb_remove_hcd(xhci->shared_hcd);
768 usb_put_hcd(xhci->shared_hcd);
769 xhci->shared_hcd = NULL;
770 }
771
772 usb_hcd_pci_remove(dev);
773
774 /* Workaround for spurious wakeups at shutdown with HSW */
775 if (set_power_d3)
776 pci_set_power_state(dev, PCI_D3hot);
777 }
778
779 /*
780 * In some Intel xHCI controllers, in order to get D3 working,
781 * through a vendor specific SSIC CONFIG register at offset 0x883c,
782 * SSIC PORT need to be marked as "unused" before putting xHCI
783 * into D3. After D3 exit, the SSIC port need to be marked as "used".
784 * Without this change, xHCI might not enter D3 state.
785 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)786 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
787 {
788 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
789 u32 val;
790 void __iomem *reg;
791 int i;
792
793 for (i = 0; i < SSIC_PORT_NUM; i++) {
794 reg = (void __iomem *) xhci->cap_regs +
795 SSIC_PORT_CFG2 +
796 i * SSIC_PORT_CFG2_OFFSET;
797
798 /* Notify SSIC that SSIC profile programming is not done. */
799 val = readl(reg) & ~PROG_DONE;
800 writel(val, reg);
801
802 /* Mark SSIC port as unused(suspend) or used(resume) */
803 val = readl(reg);
804 if (suspend)
805 val |= SSIC_PORT_UNUSED;
806 else
807 val &= ~SSIC_PORT_UNUSED;
808 writel(val, reg);
809
810 /* Notify SSIC that SSIC profile programming is done */
811 val = readl(reg) | PROG_DONE;
812 writel(val, reg);
813 readl(reg);
814 }
815 }
816
817 /*
818 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
819 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
820 */
xhci_pme_quirk(struct usb_hcd * hcd)821 static void xhci_pme_quirk(struct usb_hcd *hcd)
822 {
823 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
824 void __iomem *reg;
825 u32 val;
826
827 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
828 val = readl(reg);
829 writel(val | BIT(28), reg);
830 readl(reg);
831 }
832
xhci_sparse_control_quirk(struct usb_hcd * hcd)833 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
834 {
835 u32 reg;
836
837 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
838 reg &= ~BIT(SPARSE_DISABLE_BIT);
839 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
840 }
841
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)842 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
843 {
844 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
845 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
846 int ret;
847
848 /*
849 * Systems with the TI redriver that loses port status change events
850 * need to have the registers polled during D3, so avoid D3cold.
851 */
852 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
853 pci_d3cold_disable(pdev);
854
855 #ifdef CONFIG_SUSPEND
856 /* d3cold is broken, but only when s2idle is used */
857 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE &&
858 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I))
859 pci_d3cold_disable(pdev);
860 #endif
861
862 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
863 xhci_pme_quirk(hcd);
864
865 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
866 xhci_ssic_port_unused_quirk(hcd, true);
867
868 if (xhci->quirks & XHCI_DISABLE_SPARSE)
869 xhci_sparse_control_quirk(hcd);
870
871 ret = xhci_suspend(xhci, do_wakeup);
872
873 /* synchronize irq when using MSI-X */
874 xhci_msix_sync_irqs(xhci);
875
876 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
877 xhci_ssic_port_unused_quirk(hcd, false);
878
879 return ret;
880 }
881
xhci_pci_resume(struct usb_hcd * hcd,pm_message_t msg)882 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
883 {
884 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
885 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
886 int retval = 0;
887
888 reset_control_reset(xhci->reset);
889
890 /* The BIOS on systems with the Intel Panther Point chipset may or may
891 * not support xHCI natively. That means that during system resume, it
892 * may switch the ports back to EHCI so that users can use their
893 * keyboard to select a kernel from GRUB after resume from hibernate.
894 *
895 * The BIOS is supposed to remember whether the OS had xHCI ports
896 * enabled before resume, and switch the ports back to xHCI when the
897 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
898 * writers.
899 *
900 * Unconditionally switch the ports back to xHCI after a system resume.
901 * It should not matter whether the EHCI or xHCI controller is
902 * resumed first. It's enough to do the switchover in xHCI because
903 * USB core won't notice anything as the hub driver doesn't start
904 * running again until after all the devices (including both EHCI and
905 * xHCI host controllers) have been resumed.
906 */
907
908 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
909 usb_enable_intel_xhci_ports(pdev);
910
911 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
912 xhci_ssic_port_unused_quirk(hcd, false);
913
914 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
915 xhci_pme_quirk(hcd);
916
917 retval = xhci_resume(xhci, msg);
918 return retval;
919 }
920
xhci_pci_poweroff_late(struct usb_hcd * hcd,bool do_wakeup)921 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
922 {
923 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
924 struct xhci_port *port;
925 struct usb_device *udev;
926 unsigned int slot_id;
927 u32 portsc;
928 int i;
929
930 /*
931 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
932 * cause significant boot delay if usb ports are in suspended U3 state
933 * during boot. Some USB devices survive in U3 state over S4 hibernate
934 *
935 * Disable ports that are in U3 if remote wake is not enabled for either
936 * host controller or connected device
937 */
938
939 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
940 return 0;
941
942 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
943 port = &xhci->hw_ports[i];
944 portsc = readl(port->addr);
945
946 if ((portsc & PORT_PLS_MASK) != XDEV_U3)
947 continue;
948
949 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci,
950 port->hcd_portnum + 1);
951 if (!slot_id || !xhci->devs[slot_id]) {
952 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
953 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
954 continue;
955 }
956
957 udev = xhci->devs[slot_id]->udev;
958
959 /* if wakeup is enabled then don't disable the port */
960 if (udev->do_remote_wakeup && do_wakeup)
961 continue;
962
963 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
964 port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
965 portsc = xhci_port_state_to_neutral(portsc);
966 writel(portsc | PORT_PE, port->addr);
967 }
968
969 return 0;
970 }
971
xhci_pci_shutdown(struct usb_hcd * hcd)972 static void xhci_pci_shutdown(struct usb_hcd *hcd)
973 {
974 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
975 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
976
977 xhci_shutdown(hcd);
978 xhci_cleanup_msix(xhci);
979
980 /* Yet another workaround for spurious wakeups at shutdown with HSW */
981 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
982 pci_set_power_state(pdev, PCI_D3hot);
983 }
984
985 /*-------------------------------------------------------------------------*/
986
987 static const struct xhci_driver_data reneses_data = {
988 .quirks = XHCI_RENESAS_FW_QUIRK,
989 .firmware = "renesas_usb_fw.mem",
990 };
991
992 /* PCI driver selection metadata; PCI hotplugging uses this */
993 static const struct pci_device_id pci_ids[] = {
994 { PCI_DEVICE(0x1912, 0x0014),
995 .driver_data = (unsigned long)&reneses_data,
996 },
997 { PCI_DEVICE(0x1912, 0x0015),
998 .driver_data = (unsigned long)&reneses_data,
999 },
1000 /* handle any USB 3.0 xHCI controller */
1001 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
1002 },
1003 { /* end: all zeroes */ }
1004 };
1005 MODULE_DEVICE_TABLE(pci, pci_ids);
1006
1007 /*
1008 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
1009 * load firmware, so don't encumber the xhci-pci driver with it.
1010 */
1011 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
1012 MODULE_FIRMWARE("renesas_usb_fw.mem");
1013 #endif
1014
1015 /* pci driver glue; this is a "new style" PCI driver module */
1016 static struct pci_driver xhci_pci_driver = {
1017 .name = hcd_name,
1018 .id_table = pci_ids,
1019
1020 .probe = xhci_pci_probe,
1021 .remove = xhci_pci_remove,
1022 /* suspend and resume implemented later */
1023
1024 .shutdown = usb_hcd_pci_shutdown,
1025 .driver = {
1026 .pm = pm_ptr(&usb_hcd_pci_pm_ops),
1027 },
1028 };
1029
xhci_pci_init(void)1030 static int __init xhci_pci_init(void)
1031 {
1032 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1033 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend);
1034 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume);
1035 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late);
1036 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown);
1037 xhci_pci_hc_driver.stop = xhci_pci_stop;
1038 return pci_register_driver(&xhci_pci_driver);
1039 }
1040 module_init(xhci_pci_init);
1041
xhci_pci_exit(void)1042 static void __exit xhci_pci_exit(void)
1043 {
1044 pci_unregister_driver(&xhci_pci_driver);
1045 }
1046 module_exit(xhci_pci_exit);
1047
1048 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
1049 MODULE_LICENSE("GPL");
1050