1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2022 Microchip Technology Inc.
3 // pci1xxxx gpio driver
4
5 #include <linux/module.h>
6 #include <linux/spinlock.h>
7 #include <linux/gpio/driver.h>
8 #include <linux/bio.h>
9 #include <linux/mutex.h>
10 #include <linux/kthread.h>
11 #include <linux/interrupt.h>
12
13 #include "mchp_pci1xxxx_gp.h"
14
15 #define PCI1XXXX_NR_PINS 93
16 #define PERI_GEN_RESET 0
17 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400)
18 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10)
19 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20)
20 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30)
21 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40)
22 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50)
23 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60)
24 #define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70)
25 #define MODE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x80)
26 #define INTR_LO_TO_HI_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0x90)
27 #define INTR_HI_TO_LO_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0xA0)
28 #define INTR_LEVEL_CONFIG_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xB0)
29 #define INTR_LEVEL_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xC0)
30 #define INTR_STAT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xD0)
31 #define DEBOUNCE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xE0)
32 #define PIO_GLOBAL_CONFIG_OFFSET (0x400 + 0xF0)
33 #define PIO_PCI_CTRL_REG_OFFSET (0x400 + 0xF4)
34 #define INTR_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x100)
35 #define INTR_STATUS_OFFSET(x) (((x) * 4) + 0x400 + 0xD0)
36
37 struct pci1xxxx_gpio {
38 struct auxiliary_device *aux_dev;
39 void __iomem *reg_base;
40 raw_spinlock_t wa_lock;
41 struct gpio_chip gpio;
42 spinlock_t lock;
43 int irq_base;
44 };
45
pci1xxxx_gpio_get_direction(struct gpio_chip * gpio,unsigned int nr)46 static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
47 {
48 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
49 u32 data;
50 int ret = -EINVAL;
51
52 data = readl(priv->reg_base + INP_EN_OFFSET(nr));
53 if (data & BIT(nr % 32)) {
54 ret = 1;
55 } else {
56 data = readl(priv->reg_base + OUT_EN_OFFSET(nr));
57 if (data & BIT(nr % 32))
58 ret = 0;
59 }
60
61 return ret;
62 }
63
pci1xxx_assign_bit(void __iomem * base_addr,unsigned int reg_offset,unsigned int bitpos,bool set)64 static inline void pci1xxx_assign_bit(void __iomem *base_addr, unsigned int reg_offset,
65 unsigned int bitpos, bool set)
66 {
67 u32 data;
68
69 data = readl(base_addr + reg_offset);
70 if (set)
71 data |= BIT(bitpos);
72 else
73 data &= ~BIT(bitpos);
74 writel(data, base_addr + reg_offset);
75 }
76
pci1xxxx_gpio_direction_input(struct gpio_chip * gpio,unsigned int nr)77 static int pci1xxxx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
78 {
79 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
80 unsigned long flags;
81
82 spin_lock_irqsave(&priv->lock, flags);
83 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true);
84 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false);
85 spin_unlock_irqrestore(&priv->lock, flags);
86
87 return 0;
88 }
89
pci1xxxx_gpio_get(struct gpio_chip * gpio,unsigned int nr)90 static int pci1xxxx_gpio_get(struct gpio_chip *gpio, unsigned int nr)
91 {
92 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
93
94 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1;
95 }
96
pci1xxxx_gpio_direction_output(struct gpio_chip * gpio,unsigned int nr,int val)97 static int pci1xxxx_gpio_direction_output(struct gpio_chip *gpio,
98 unsigned int nr, int val)
99 {
100 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
101 unsigned long flags;
102 u32 data;
103
104 spin_lock_irqsave(&priv->lock, flags);
105 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false);
106 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true);
107 data = readl(priv->reg_base + OUT_OFFSET(nr));
108 if (val)
109 data |= (1 << (nr % 32));
110 else
111 data &= ~(1 << (nr % 32));
112 writel(data, priv->reg_base + OUT_OFFSET(nr));
113 spin_unlock_irqrestore(&priv->lock, flags);
114
115 return 0;
116 }
117
pci1xxxx_gpio_set(struct gpio_chip * gpio,unsigned int nr,int val)118 static void pci1xxxx_gpio_set(struct gpio_chip *gpio,
119 unsigned int nr, int val)
120 {
121 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
122 unsigned long flags;
123
124 spin_lock_irqsave(&priv->lock, flags);
125 pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val);
126 spin_unlock_irqrestore(&priv->lock, flags);
127 }
128
pci1xxxx_gpio_set_config(struct gpio_chip * gpio,unsigned int offset,unsigned long config)129 static int pci1xxxx_gpio_set_config(struct gpio_chip *gpio, unsigned int offset,
130 unsigned long config)
131 {
132 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
133 unsigned long flags;
134 int ret = 0;
135
136 spin_lock_irqsave(&priv->lock, flags);
137 switch (pinconf_to_config_param(config)) {
138 case PIN_CONFIG_BIAS_PULL_UP:
139 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true);
140 break;
141 case PIN_CONFIG_BIAS_PULL_DOWN:
142 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true);
143 break;
144 case PIN_CONFIG_BIAS_DISABLE:
145 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false);
146 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false);
147 break;
148 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
149 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true);
150 break;
151 default:
152 ret = -ENOTSUPP;
153 break;
154 }
155 spin_unlock_irqrestore(&priv->lock, flags);
156
157 return ret;
158 }
159
pci1xxxx_gpio_irq_ack(struct irq_data * data)160 static void pci1xxxx_gpio_irq_ack(struct irq_data *data)
161 {
162 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
163 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
164 unsigned int gpio = irqd_to_hwirq(data);
165 unsigned long flags;
166
167 spin_lock_irqsave(&priv->lock, flags);
168 writel(BIT(gpio % 32), priv->reg_base + INTR_STAT_OFFSET(gpio));
169 spin_unlock_irqrestore(&priv->lock, flags);
170 }
171
pci1xxxx_gpio_irq_set_mask(struct irq_data * data,bool set)172 static void pci1xxxx_gpio_irq_set_mask(struct irq_data *data, bool set)
173 {
174 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
175 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
176 unsigned int gpio = irqd_to_hwirq(data);
177 unsigned long flags;
178
179 if (!set)
180 gpiochip_enable_irq(chip, gpio);
181 spin_lock_irqsave(&priv->lock, flags);
182 pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set);
183 spin_unlock_irqrestore(&priv->lock, flags);
184 if (set)
185 gpiochip_disable_irq(chip, gpio);
186 }
187
pci1xxxx_gpio_irq_mask(struct irq_data * data)188 static void pci1xxxx_gpio_irq_mask(struct irq_data *data)
189 {
190 pci1xxxx_gpio_irq_set_mask(data, true);
191 }
192
pci1xxxx_gpio_irq_unmask(struct irq_data * data)193 static void pci1xxxx_gpio_irq_unmask(struct irq_data *data)
194 {
195 pci1xxxx_gpio_irq_set_mask(data, false);
196 }
197
pci1xxxx_gpio_set_type(struct irq_data * data,unsigned int trigger_type)198 static int pci1xxxx_gpio_set_type(struct irq_data *data, unsigned int trigger_type)
199 {
200 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
201 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
202 unsigned int gpio = irqd_to_hwirq(data);
203 unsigned int bitpos = gpio % 32;
204
205 if (trigger_type & IRQ_TYPE_EDGE_FALLING) {
206 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
207 bitpos, false);
208 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio),
209 bitpos, false);
210 irq_set_handler_locked(data, handle_edge_irq);
211 } else {
212 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
213 bitpos, true);
214 }
215
216 if (trigger_type & IRQ_TYPE_EDGE_RISING) {
217 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
218 bitpos, false);
219 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
220 false);
221 irq_set_handler_locked(data, handle_edge_irq);
222 } else {
223 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
224 bitpos, true);
225 }
226
227 if (trigger_type & IRQ_TYPE_LEVEL_LOW) {
228 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
229 bitpos, true);
230 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
231 bitpos, false);
232 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
233 true);
234 irq_set_handler_locked(data, handle_edge_irq);
235 }
236
237 if (trigger_type & IRQ_TYPE_LEVEL_HIGH) {
238 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
239 bitpos, false);
240 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
241 bitpos, false);
242 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
243 true);
244 irq_set_handler_locked(data, handle_edge_irq);
245 }
246
247 if ((!(trigger_type & IRQ_TYPE_LEVEL_LOW)) && (!(trigger_type & IRQ_TYPE_LEVEL_HIGH)))
248 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true);
249
250 return true;
251 }
252
pci1xxxx_gpio_irq_handler(int irq,void * dev_id)253 static irqreturn_t pci1xxxx_gpio_irq_handler(int irq, void *dev_id)
254 {
255 struct pci1xxxx_gpio *priv = dev_id;
256 struct gpio_chip *gc = &priv->gpio;
257 unsigned long int_status = 0;
258 unsigned long wa_flags;
259 unsigned long flags;
260 u8 pincount;
261 int bit;
262 u8 gpiobank;
263
264 spin_lock_irqsave(&priv->lock, flags);
265 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true);
266 spin_unlock_irqrestore(&priv->lock, flags);
267 for (gpiobank = 0; gpiobank < 3; gpiobank++) {
268 spin_lock_irqsave(&priv->lock, flags);
269 int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
270 spin_unlock_irqrestore(&priv->lock, flags);
271 if (gpiobank == 2)
272 pincount = 29;
273 else
274 pincount = 32;
275 for_each_set_bit(bit, &int_status, pincount) {
276 unsigned int irq;
277
278 spin_lock_irqsave(&priv->lock, flags);
279 writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
280 spin_unlock_irqrestore(&priv->lock, flags);
281 irq = irq_find_mapping(gc->irq.domain, (bit + (gpiobank * 32)));
282 raw_spin_lock_irqsave(&priv->wa_lock, wa_flags);
283 generic_handle_irq(irq);
284 raw_spin_unlock_irqrestore(&priv->wa_lock, wa_flags);
285 }
286 }
287 spin_lock_irqsave(&priv->lock, flags);
288 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false);
289 spin_unlock_irqrestore(&priv->lock, flags);
290
291 return IRQ_HANDLED;
292 }
293
294 static const struct irq_chip pci1xxxx_gpio_irqchip = {
295 .name = "pci1xxxx_gpio",
296 .irq_ack = pci1xxxx_gpio_irq_ack,
297 .irq_mask = pci1xxxx_gpio_irq_mask,
298 .irq_unmask = pci1xxxx_gpio_irq_unmask,
299 .irq_set_type = pci1xxxx_gpio_set_type,
300 .flags = IRQCHIP_IMMUTABLE,
301 GPIOCHIP_IRQ_RESOURCE_HELPERS,
302 };
303
pci1xxxx_gpio_suspend(struct device * dev)304 static int pci1xxxx_gpio_suspend(struct device *dev)
305 {
306 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
307 unsigned long flags;
308
309 spin_lock_irqsave(&priv->lock, flags);
310 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
311 16, true);
312 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
313 17, false);
314 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true);
315 spin_unlock_irqrestore(&priv->lock, flags);
316
317 return 0;
318 }
319
pci1xxxx_gpio_resume(struct device * dev)320 static int pci1xxxx_gpio_resume(struct device *dev)
321 {
322 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
323 unsigned long flags;
324
325 spin_lock_irqsave(&priv->lock, flags);
326 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
327 17, true);
328 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
329 16, false);
330 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false);
331 spin_unlock_irqrestore(&priv->lock, flags);
332
333 return 0;
334 }
335
pci1xxxx_gpio_setup(struct pci1xxxx_gpio * priv,int irq)336 static int pci1xxxx_gpio_setup(struct pci1xxxx_gpio *priv, int irq)
337 {
338 struct gpio_chip *gchip = &priv->gpio;
339 struct gpio_irq_chip *girq;
340 int retval;
341
342 gchip->label = dev_name(&priv->aux_dev->dev);
343 gchip->parent = &priv->aux_dev->dev;
344 gchip->owner = THIS_MODULE;
345 gchip->direction_input = pci1xxxx_gpio_direction_input;
346 gchip->direction_output = pci1xxxx_gpio_direction_output;
347 gchip->get_direction = pci1xxxx_gpio_get_direction;
348 gchip->get = pci1xxxx_gpio_get;
349 gchip->set = pci1xxxx_gpio_set;
350 gchip->set_config = pci1xxxx_gpio_set_config;
351 gchip->dbg_show = NULL;
352 gchip->base = -1;
353 gchip->ngpio = PCI1XXXX_NR_PINS;
354 gchip->can_sleep = false;
355
356 retval = devm_request_threaded_irq(&priv->aux_dev->dev, irq,
357 NULL, pci1xxxx_gpio_irq_handler,
358 IRQF_ONESHOT, "PCI1xxxxGPIO", priv);
359
360 if (retval)
361 return retval;
362
363 girq = &priv->gpio.irq;
364 gpio_irq_chip_set_chip(girq, &pci1xxxx_gpio_irqchip);
365 girq->parent_handler = NULL;
366 girq->num_parents = 0;
367 girq->parents = NULL;
368 girq->default_type = IRQ_TYPE_NONE;
369 girq->handler = handle_bad_irq;
370
371 return 0;
372 }
373
pci1xxxx_gpio_probe(struct auxiliary_device * aux_dev,const struct auxiliary_device_id * id)374 static int pci1xxxx_gpio_probe(struct auxiliary_device *aux_dev,
375 const struct auxiliary_device_id *id)
376
377 {
378 struct auxiliary_device_wrapper *aux_dev_wrapper;
379 struct gp_aux_data_type *pdata;
380 struct pci1xxxx_gpio *priv;
381 int retval;
382
383 aux_dev_wrapper = (struct auxiliary_device_wrapper *)
384 container_of(aux_dev, struct auxiliary_device_wrapper, aux_dev);
385
386 pdata = &aux_dev_wrapper->gp_aux_data;
387
388 if (!pdata)
389 return -EINVAL;
390
391 priv = devm_kzalloc(&aux_dev->dev, sizeof(struct pci1xxxx_gpio), GFP_KERNEL);
392 if (!priv)
393 return -ENOMEM;
394
395 spin_lock_init(&priv->lock);
396 priv->aux_dev = aux_dev;
397
398 if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start, 0x800, aux_dev->name))
399 return -EBUSY;
400
401 priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800);
402 if (!priv->reg_base)
403 return -ENOMEM;
404
405 writel(0x0264, (priv->reg_base + 0x400 + 0xF0));
406
407 retval = pci1xxxx_gpio_setup(priv, pdata->irq_num);
408
409 if (retval < 0)
410 return retval;
411
412 dev_set_drvdata(&aux_dev->dev, priv);
413
414 return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv);
415 }
416
417 static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_gpio_pm_ops, pci1xxxx_gpio_suspend, pci1xxxx_gpio_resume);
418
419 static const struct auxiliary_device_id pci1xxxx_gpio_auxiliary_id_table[] = {
420 {.name = "mchp_pci1xxxx_gp.gp_gpio"},
421 {}
422 };
423 MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_gpio_auxiliary_id_table);
424
425 static struct auxiliary_driver pci1xxxx_gpio_driver = {
426 .driver = {
427 .name = "PCI1xxxxGPIO",
428 .pm = &pci1xxxx_gpio_pm_ops,
429 },
430 .probe = pci1xxxx_gpio_probe,
431 .id_table = pci1xxxx_gpio_auxiliary_id_table
432 };
433 module_auxiliary_driver(pci1xxxx_gpio_driver);
434
435 MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx GPIO controller");
436 MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
437 MODULE_LICENSE("GPL");
438