1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Microchip Corporation
4 * Wenyou.Yang <wenyou.yang@microchip.com>
5 */
6
7 #include <common.h>
8 #include <debug_uart.h>
9 #include <asm/io.h>
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/atmel_pio4.h>
12 #include <asm/arch/atmel_mpddrc.h>
13 #include <asm/arch/atmel_sdhci.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/sama5d2.h>
17
18 extern void at91_pda_detect(void);
19
20 DECLARE_GLOBAL_DATA_PTR;
21
board_usb_hw_init(void)22 static void board_usb_hw_init(void)
23 {
24 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
25 }
26
27 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)28 int board_late_init(void)
29 {
30 #ifdef CONFIG_DM_VIDEO
31 at91_video_show_board_info();
32 #endif
33 at91_pda_detect();
34 return 0;
35 }
36 #endif
37
38 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_uart1_hw_init(void)39 static void board_uart1_hw_init(void)
40 {
41 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK); /* URXD1 */
42 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
43
44 at91_periph_clk_enable(ATMEL_ID_UART1);
45 }
46
board_debug_uart_init(void)47 void board_debug_uart_init(void)
48 {
49 board_uart1_hw_init();
50 }
51 #endif
52
53 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)54 int board_early_init_f(void)
55 {
56 #ifdef CONFIG_DEBUG_UART
57 debug_uart_init();
58 #endif
59
60 return 0;
61 }
62 #endif
63
board_init(void)64 int board_init(void)
65 {
66 /* address of boot parameters */
67 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
68
69 #ifdef CONFIG_CMD_USB
70 board_usb_hw_init();
71 #endif
72
73 return 0;
74 }
75
dram_init(void)76 int dram_init(void)
77 {
78 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
79 CONFIG_SYS_SDRAM_SIZE);
80 return 0;
81 }
82
83 #define MAC24AA_MAC_OFFSET 0xfa
84
85 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)86 int misc_init_r(void)
87 {
88 #ifdef CONFIG_I2C_EEPROM
89 at91_set_ethaddr(MAC24AA_MAC_OFFSET);
90 #endif
91 return 0;
92 }
93 #endif
94
95 /* SPL */
96 #ifdef CONFIG_SPL_BUILD
spl_board_init(void)97 void spl_board_init(void)
98 {
99 }
100
ddrc_conf(struct atmel_mpddrc_config * ddrc)101 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
102 {
103 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
104
105 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
106 ATMEL_MPDDRC_CR_NR_ROW_13 |
107 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
108 ATMEL_MPDDRC_CR_DIC_DS |
109 ATMEL_MPDDRC_CR_ZQ_LONG |
110 ATMEL_MPDDRC_CR_NB_8BANKS |
111 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
112 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
113
114 ddrc->rtr = 0x511;
115
116 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
117 (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
118 (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
119 (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
120 (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
121 (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
122 (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
123 (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
124
125 ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
126 (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
127 (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
128 (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
129
130 ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
131 (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
132 (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
133 (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
134 (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
135 }
136
mem_init(void)137 void mem_init(void)
138 {
139 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
140 struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
141 struct atmel_mpddrc_config ddrc_config;
142 u32 reg;
143
144 ddrc_conf(&ddrc_config);
145
146 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
147 writel(AT91_PMC_DDR, &pmc->scer);
148
149 reg = readl(&mpddrc->io_calibr);
150 reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
151 reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
152 reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
153 reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
154 writel(reg, &mpddrc->io_calibr);
155
156 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
157 &mpddrc->rd_data_path);
158
159 ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
160
161 writel(0x3, &mpddrc->cal_mr4);
162 writel(64, &mpddrc->tim_cal);
163 }
164
at91_pmc_init(void)165 void at91_pmc_init(void)
166 {
167 u32 tmp;
168
169 /*
170 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
171 * so we need to slow down and configure MCKR accordingly.
172 * This is why we have a special flavor of the switching function.
173 */
174 tmp = AT91_PMC_MCKR_PLLADIV_2 |
175 AT91_PMC_MCKR_MDIV_3 |
176 AT91_PMC_MCKR_CSS_MAIN;
177 at91_mck_init_down(tmp);
178
179 tmp = AT91_PMC_PLLAR_29 |
180 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
181 AT91_PMC_PLLXR_MUL(40) |
182 AT91_PMC_PLLXR_DIV(1);
183 at91_plla_init(tmp);
184
185 tmp = AT91_PMC_MCKR_H32MXDIV |
186 AT91_PMC_MCKR_PLLADIV_2 |
187 AT91_PMC_MCKR_MDIV_3 |
188 AT91_PMC_MCKR_CSS_PLLA;
189 at91_mck_init(tmp);
190 }
191 #endif
192