xref: /openbmc/linux/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h (revision b181f7029bd71238ac2754ce7052dffd69432085)
1  /* SPDX-License-Identifier: GPL-2.0 */
2  /* Copyright(c) 1999 - 2018 Intel Corporation. */
3  
4  #ifndef _IXGBE_TYPE_H_
5  #define _IXGBE_TYPE_H_
6  
7  #include <linux/types.h>
8  #include <linux/mdio.h>
9  #include <linux/netdevice.h>
10  
11  /* Device IDs */
12  #define IXGBE_DEV_ID_82598               0x10B6
13  #define IXGBE_DEV_ID_82598_BX            0x1508
14  #define IXGBE_DEV_ID_82598AF_DUAL_PORT   0x10C6
15  #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
16  #define IXGBE_DEV_ID_82598EB_SFP_LOM     0x10DB
17  #define IXGBE_DEV_ID_82598AT             0x10C8
18  #define IXGBE_DEV_ID_82598AT2            0x150B
19  #define IXGBE_DEV_ID_82598EB_CX4         0x10DD
20  #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
21  #define IXGBE_DEV_ID_82598_DA_DUAL_PORT  0x10F1
22  #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
23  #define IXGBE_DEV_ID_82598EB_XF_LR       0x10F4
24  #define IXGBE_DEV_ID_82599_KX4           0x10F7
25  #define IXGBE_DEV_ID_82599_KX4_MEZZ      0x1514
26  #define IXGBE_DEV_ID_82599_KR            0x1517
27  #define IXGBE_DEV_ID_82599_T3_LOM        0x151C
28  #define IXGBE_DEV_ID_82599_CX4           0x10F9
29  #define IXGBE_DEV_ID_82599_SFP           0x10FB
30  #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152a
31  #define IXGBE_DEV_ID_82599_SFP_FCOE      0x1529
32  #define IXGBE_SUBDEV_ID_82599_SFP        0x11A9
33  #define IXGBE_SUBDEV_ID_82599_SFP_WOL0   0x1071
34  #define IXGBE_SUBDEV_ID_82599_RNDC       0x1F72
35  #define IXGBE_SUBDEV_ID_82599_560FLR     0x17D0
36  #define IXGBE_SUBDEV_ID_82599_SP_560FLR  0x211B
37  #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6		0x2159
38  #define IXGBE_SUBDEV_ID_82599_SFP_1OCP		0x000D
39  #define IXGBE_SUBDEV_ID_82599_SFP_2OCP		0x0008
40  #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1	0x8976
41  #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2	0x06EE
42  #define IXGBE_SUBDEV_ID_82599_ECNA_DP    0x0470
43  #define IXGBE_DEV_ID_82599_SFP_EM        0x1507
44  #define IXGBE_DEV_ID_82599_SFP_SF2       0x154D
45  #define IXGBE_DEV_ID_82599EN_SFP         0x1557
46  #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
47  #define IXGBE_DEV_ID_82599_XAUI_LOM      0x10FC
48  #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
49  #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ  0x000C
50  #define IXGBE_DEV_ID_82599_LS            0x154F
51  #define IXGBE_DEV_ID_X540T               0x1528
52  #define IXGBE_DEV_ID_82599_SFP_SF_QP     0x154A
53  #define IXGBE_DEV_ID_82599_QSFP_SF_QP    0x1558
54  #define IXGBE_DEV_ID_X540T1              0x1560
55  
56  #define IXGBE_DEV_ID_X550T		0x1563
57  #define IXGBE_DEV_ID_X550T1		0x15D1
58  #define IXGBE_DEV_ID_X550EM_X_KX4	0x15AA
59  #define IXGBE_DEV_ID_X550EM_X_KR	0x15AB
60  #define IXGBE_DEV_ID_X550EM_X_SFP	0x15AC
61  #define IXGBE_DEV_ID_X550EM_X_10G_T	0x15AD
62  #define IXGBE_DEV_ID_X550EM_X_1G_T	0x15AE
63  #define IXGBE_DEV_ID_X550EM_X_XFI	0x15B0
64  #define IXGBE_DEV_ID_X550EM_A_KR	0x15C2
65  #define IXGBE_DEV_ID_X550EM_A_KR_L	0x15C3
66  #define IXGBE_DEV_ID_X550EM_A_SFP_N	0x15C4
67  #define IXGBE_DEV_ID_X550EM_A_SGMII	0x15C6
68  #define IXGBE_DEV_ID_X550EM_A_SGMII_L	0x15C7
69  #define IXGBE_DEV_ID_X550EM_A_10G_T	0x15C8
70  #define IXGBE_DEV_ID_X550EM_A_SFP	0x15CE
71  #define IXGBE_DEV_ID_X550EM_A_1G_T	0x15E4
72  #define IXGBE_DEV_ID_X550EM_A_1G_T_L	0x15E5
73  
74  /* VF Device IDs */
75  #define IXGBE_DEV_ID_82599_VF		0x10ED
76  #define IXGBE_DEV_ID_X540_VF		0x1515
77  #define IXGBE_DEV_ID_X550_VF		0x1565
78  #define IXGBE_DEV_ID_X550EM_X_VF	0x15A8
79  #define IXGBE_DEV_ID_X550EM_A_VF	0x15C5
80  
81  #define IXGBE_CAT(r, m)	IXGBE_##r##_##m
82  
83  #define IXGBE_BY_MAC(_hw, r)	((_hw)->mvals[IXGBE_CAT(r, IDX)])
84  
85  /* General Registers */
86  #define IXGBE_CTRL      0x00000
87  #define IXGBE_STATUS    0x00008
88  #define IXGBE_CTRL_EXT  0x00018
89  #define IXGBE_ESDP      0x00020
90  #define IXGBE_EODSDP    0x00028
91  
92  #define IXGBE_I2CCTL_8259X	0x00028
93  #define IXGBE_I2CCTL_X540	IXGBE_I2CCTL_8259X
94  #define IXGBE_I2CCTL_X550	0x15F5C
95  #define IXGBE_I2CCTL_X550EM_x	IXGBE_I2CCTL_X550
96  #define IXGBE_I2CCTL_X550EM_a	IXGBE_I2CCTL_X550
97  #define IXGBE_I2CCTL(_hw)	IXGBE_BY_MAC((_hw), I2CCTL)
98  
99  #define IXGBE_LEDCTL    0x00200
100  #define IXGBE_FRTIMER   0x00048
101  #define IXGBE_TCPTIMER  0x0004C
102  #define IXGBE_CORESPARE 0x00600
103  #define IXGBE_EXVET     0x05078
104  
105  /* NVM Registers */
106  #define IXGBE_EEC_8259X		0x10010
107  #define IXGBE_EEC_X540		IXGBE_EEC_8259X
108  #define IXGBE_EEC_X550		IXGBE_EEC_8259X
109  #define IXGBE_EEC_X550EM_x	IXGBE_EEC_8259X
110  #define IXGBE_EEC_X550EM_a	0x15FF8
111  #define IXGBE_EEC(_hw)		IXGBE_BY_MAC((_hw), EEC)
112  #define IXGBE_EERD      0x10014
113  #define IXGBE_EEWR      0x10018
114  #define IXGBE_FLA_8259X		0x1001C
115  #define IXGBE_FLA_X540		IXGBE_FLA_8259X
116  #define IXGBE_FLA_X550		IXGBE_FLA_8259X
117  #define IXGBE_FLA_X550EM_x	IXGBE_FLA_8259X
118  #define IXGBE_FLA_X550EM_a	0x15F68
119  #define IXGBE_FLA(_hw)		IXGBE_BY_MAC((_hw), FLA)
120  #define IXGBE_EEMNGCTL  0x10110
121  #define IXGBE_EEMNGDATA 0x10114
122  #define IXGBE_FLMNGCTL  0x10118
123  #define IXGBE_FLMNGDATA 0x1011C
124  #define IXGBE_FLMNGCNT  0x10120
125  #define IXGBE_FLOP      0x1013C
126  #define IXGBE_GRC_8259X		0x10200
127  #define IXGBE_GRC_X540		IXGBE_GRC_8259X
128  #define IXGBE_GRC_X550		IXGBE_GRC_8259X
129  #define IXGBE_GRC_X550EM_x	IXGBE_GRC_8259X
130  #define IXGBE_GRC_X550EM_a	0x15F64
131  #define IXGBE_GRC(_hw)		IXGBE_BY_MAC((_hw), GRC)
132  
133  /* General Receive Control */
134  #define IXGBE_GRC_MNG  0x00000001 /* Manageability Enable */
135  #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
136  
137  #define IXGBE_VPDDIAG0  0x10204
138  #define IXGBE_VPDDIAG1  0x10208
139  
140  /* I2CCTL Bit Masks */
141  #define IXGBE_I2C_CLK_IN_8259X		0x00000001
142  #define IXGBE_I2C_CLK_IN_X540		IXGBE_I2C_CLK_IN_8259X
143  #define IXGBE_I2C_CLK_IN_X550		0x00004000
144  #define IXGBE_I2C_CLK_IN_X550EM_x	IXGBE_I2C_CLK_IN_X550
145  #define IXGBE_I2C_CLK_IN_X550EM_a	IXGBE_I2C_CLK_IN_X550
146  #define IXGBE_I2C_CLK_IN(_hw)		IXGBE_BY_MAC((_hw), I2C_CLK_IN)
147  
148  #define IXGBE_I2C_CLK_OUT_8259X		0x00000002
149  #define IXGBE_I2C_CLK_OUT_X540		IXGBE_I2C_CLK_OUT_8259X
150  #define IXGBE_I2C_CLK_OUT_X550		0x00000200
151  #define IXGBE_I2C_CLK_OUT_X550EM_x	IXGBE_I2C_CLK_OUT_X550
152  #define IXGBE_I2C_CLK_OUT_X550EM_a	IXGBE_I2C_CLK_OUT_X550
153  #define IXGBE_I2C_CLK_OUT(_hw)		IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
154  
155  #define IXGBE_I2C_DATA_IN_8259X		0x00000004
156  #define IXGBE_I2C_DATA_IN_X540		IXGBE_I2C_DATA_IN_8259X
157  #define IXGBE_I2C_DATA_IN_X550		0x00001000
158  #define IXGBE_I2C_DATA_IN_X550EM_x	IXGBE_I2C_DATA_IN_X550
159  #define IXGBE_I2C_DATA_IN_X550EM_a	IXGBE_I2C_DATA_IN_X550
160  #define IXGBE_I2C_DATA_IN(_hw)		IXGBE_BY_MAC((_hw), I2C_DATA_IN)
161  
162  #define IXGBE_I2C_DATA_OUT_8259X	0x00000008
163  #define IXGBE_I2C_DATA_OUT_X540		IXGBE_I2C_DATA_OUT_8259X
164  #define IXGBE_I2C_DATA_OUT_X550		0x00000400
165  #define IXGBE_I2C_DATA_OUT_X550EM_x	IXGBE_I2C_DATA_OUT_X550
166  #define IXGBE_I2C_DATA_OUT_X550EM_a	IXGBE_I2C_DATA_OUT_X550
167  #define IXGBE_I2C_DATA_OUT(_hw)		IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
168  
169  #define IXGBE_I2C_DATA_OE_N_EN_8259X	0
170  #define IXGBE_I2C_DATA_OE_N_EN_X540	IXGBE_I2C_DATA_OE_N_EN_8259X
171  #define IXGBE_I2C_DATA_OE_N_EN_X550	0x00000800
172  #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x	IXGBE_I2C_DATA_OE_N_EN_X550
173  #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a	IXGBE_I2C_DATA_OE_N_EN_X550
174  #define IXGBE_I2C_DATA_OE_N_EN(_hw)	IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
175  
176  #define IXGBE_I2C_BB_EN_8259X		0
177  #define IXGBE_I2C_BB_EN_X540		IXGBE_I2C_BB_EN_8259X
178  #define IXGBE_I2C_BB_EN_X550		0x00000100
179  #define IXGBE_I2C_BB_EN_X550EM_x	IXGBE_I2C_BB_EN_X550
180  #define IXGBE_I2C_BB_EN_X550EM_a	IXGBE_I2C_BB_EN_X550
181  #define IXGBE_I2C_BB_EN(_hw)		IXGBE_BY_MAC((_hw), I2C_BB_EN)
182  
183  #define IXGBE_I2C_CLK_OE_N_EN_8259X	0
184  #define IXGBE_I2C_CLK_OE_N_EN_X540	IXGBE_I2C_CLK_OE_N_EN_8259X
185  #define IXGBE_I2C_CLK_OE_N_EN_X550	0x00002000
186  #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x	IXGBE_I2C_CLK_OE_N_EN_X550
187  #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a	IXGBE_I2C_CLK_OE_N_EN_X550
188  #define IXGBE_I2C_CLK_OE_N_EN(_hw)	 IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
189  
190  #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT	500
191  
192  #define IXGBE_I2C_THERMAL_SENSOR_ADDR	0xF8
193  #define IXGBE_EMC_INTERNAL_DATA		0x00
194  #define IXGBE_EMC_INTERNAL_THERM_LIMIT	0x20
195  #define IXGBE_EMC_DIODE1_DATA		0x01
196  #define IXGBE_EMC_DIODE1_THERM_LIMIT	0x19
197  #define IXGBE_EMC_DIODE2_DATA		0x23
198  #define IXGBE_EMC_DIODE2_THERM_LIMIT	0x1A
199  
200  #define IXGBE_MAX_SENSORS		3
201  
202  struct ixgbe_thermal_diode_data {
203  	u8 location;
204  	u8 temp;
205  	u8 caution_thresh;
206  	u8 max_op_thresh;
207  };
208  
209  struct ixgbe_thermal_sensor_data {
210  	struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
211  };
212  
213  #define NVM_OROM_OFFSET		0x17
214  #define NVM_OROM_BLK_LOW	0x83
215  #define NVM_OROM_BLK_HI		0x84
216  #define NVM_OROM_PATCH_MASK	0xFF
217  #define NVM_OROM_SHIFT		8
218  
219  #define NVM_VER_MASK		0x00FF	/* version mask */
220  #define NVM_VER_SHIFT		8	/* version bit shift */
221  #define NVM_OEM_PROD_VER_PTR	0x1B /* OEM Product version block pointer */
222  #define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */
223  #define NVM_OEM_PROD_VER_OFF_L	0x2  /* OEM Product version offset low */
224  #define NVM_OEM_PROD_VER_OFF_H	0x3  /* OEM Product version offset high */
225  #define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */
226  #define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */
227  #define NVM_ETK_OFF_LOW		0x2D /* version low order word */
228  #define NVM_ETK_OFF_HI		0x2E /* version high order word */
229  #define NVM_ETK_SHIFT		16   /* high version word shift */
230  #define NVM_VER_INVALID		0xFFFF
231  #define NVM_ETK_VALID		0x8000
232  #define NVM_INVALID_PTR		0xFFFF
233  #define NVM_VER_SIZE		32   /* version sting size */
234  
235  struct ixgbe_nvm_version {
236  	u32 etk_id;
237  	u8  nvm_major;
238  	u16 nvm_minor;
239  	u8  nvm_id;
240  
241  	bool oem_valid;
242  	u8   oem_major;
243  	u8   oem_minor;
244  	u16  oem_release;
245  
246  	bool or_valid;
247  	u8  or_major;
248  	u16 or_build;
249  	u8  or_patch;
250  };
251  
252  /* Interrupt Registers */
253  #define IXGBE_EICR      0x00800
254  #define IXGBE_EICS      0x00808
255  #define IXGBE_EIMS      0x00880
256  #define IXGBE_EIMC      0x00888
257  #define IXGBE_EIAC      0x00810
258  #define IXGBE_EIAM      0x00890
259  #define IXGBE_EICS_EX(_i)   (0x00A90 + (_i) * 4)
260  #define IXGBE_EIMS_EX(_i)   (0x00AA0 + (_i) * 4)
261  #define IXGBE_EIMC_EX(_i)   (0x00AB0 + (_i) * 4)
262  #define IXGBE_EIAM_EX(_i)   (0x00AD0 + (_i) * 4)
263  /*
264   * 82598 EITR is 16 bits but set the limits based on the max
265   * supported by all ixgbe hardware.  82599 EITR is only 12 bits,
266   * with the lower 3 always zero.
267   */
268  #define IXGBE_MAX_INT_RATE 488281
269  #define IXGBE_MIN_INT_RATE 956
270  #define IXGBE_MAX_EITR     0x00000FF8
271  #define IXGBE_MIN_EITR     8
272  #define IXGBE_EITR(_i)  (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
273  			 (0x012300 + (((_i) - 24) * 4)))
274  #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
275  #define IXGBE_EITR_LLI_MOD      0x00008000
276  #define IXGBE_EITR_CNT_WDIS     0x80000000
277  #define IXGBE_IVAR(_i)  (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
278  #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
279  #define IXGBE_EITRSEL   0x00894
280  #define IXGBE_MSIXT     0x00000 /* MSI-X Table. 0x0000 - 0x01C */
281  #define IXGBE_MSIXPBA   0x02000 /* MSI-X Pending bit array */
282  #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
283  #define IXGBE_GPIE      0x00898
284  
285  /* Flow Control Registers */
286  #define IXGBE_FCADBUL   0x03210
287  #define IXGBE_FCADBUH   0x03214
288  #define IXGBE_FCAMACL   0x04328
289  #define IXGBE_FCAMACH   0x0432C
290  #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
291  #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
292  #define IXGBE_PFCTOP    0x03008
293  #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
294  #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
295  #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
296  #define IXGBE_FCRTV     0x032A0
297  #define IXGBE_FCCFG     0x03D00
298  #define IXGBE_TFCS      0x0CE00
299  
300  /* Receive DMA Registers */
301  #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
302  			 (0x0D000 + (((_i) - 64) * 0x40)))
303  #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
304  			 (0x0D004 + (((_i) - 64) * 0x40)))
305  #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
306  			 (0x0D008 + (((_i) - 64) * 0x40)))
307  #define IXGBE_RDH(_i)   (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
308  			 (0x0D010 + (((_i) - 64) * 0x40)))
309  #define IXGBE_RDT(_i)   (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
310  			 (0x0D018 + (((_i) - 64) * 0x40)))
311  #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
312  			 (0x0D028 + (((_i) - 64) * 0x40)))
313  #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
314  			 (0x0D02C + (((_i) - 64) * 0x40)))
315  #define IXGBE_RSCDBU     0x03028
316  #define IXGBE_RDDCC      0x02F20
317  #define IXGBE_RXMEMWRAP  0x03190
318  #define IXGBE_STARCTRL   0x03024
319  /*
320   * Split and Replication Receive Control Registers
321   * 00-15 : 0x02100 + n*4
322   * 16-64 : 0x01014 + n*0x40
323   * 64-127: 0x0D014 + (n-64)*0x40
324   */
325  #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
326  			  (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
327  			  (0x0D014 + (((_i) - 64) * 0x40))))
328  /*
329   * Rx DCA Control Register:
330   * 00-15 : 0x02200 + n*4
331   * 16-64 : 0x0100C + n*0x40
332   * 64-127: 0x0D00C + (n-64)*0x40
333   */
334  #define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
335  				 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
336  				 (0x0D00C + (((_i) - 64) * 0x40))))
337  #define IXGBE_RDRXCTL           0x02F00
338  #define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
339  					     /* 8 of these 0x03C00 - 0x03C1C */
340  #define IXGBE_RXCTRL    0x03000
341  #define IXGBE_DROPEN    0x03D04
342  #define IXGBE_RXPBSIZE_SHIFT 10
343  
344  /* Receive Registers */
345  #define IXGBE_RXCSUM    0x05000
346  #define IXGBE_RFCTL     0x05008
347  #define IXGBE_DRECCCTL  0x02F08
348  #define IXGBE_DRECCCTL_DISABLE 0
349  /* Multicast Table Array - 128 entries */
350  #define IXGBE_MTA(_i)   (0x05200 + ((_i) * 4))
351  #define IXGBE_RAL(_i)   (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
352  			 (0x0A200 + ((_i) * 8)))
353  #define IXGBE_RAH(_i)   (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
354  			 (0x0A204 + ((_i) * 8)))
355  #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
356  #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
357  /* Packet split receive type */
358  #define IXGBE_PSRTYPE(_i)    (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
359  			      (0x0EA00 + ((_i) * 4)))
360  /* array of 4096 1-bit vlan filters */
361  #define IXGBE_VFTA(_i)  (0x0A000 + ((_i) * 4))
362  /*array of 4096 4-bit vlan vmdq indices */
363  #define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
364  #define IXGBE_FCTRL     0x05080
365  #define IXGBE_VLNCTRL   0x05088
366  #define IXGBE_MCSTCTRL  0x05090
367  #define IXGBE_MRQC      0x05818
368  #define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
369  #define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
370  #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
371  #define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
372  #define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
373  #define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
374  #define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
375  #define IXGBE_RQTC      0x0EC70
376  #define IXGBE_MTQC      0x08120
377  #define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
378  #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
379  #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
380  #define IXGBE_PFFLPL	0x050B0
381  #define IXGBE_PFFLPH	0x050B4
382  #define IXGBE_VT_CTL         0x051B0
383  #define IXGBE_PFMAILBOX(_i)  (0x04B00 + (4 * (_i))) /* 64 total */
384  #define IXGBE_PFMBMEM(_i)    (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */
385  #define IXGBE_PFMBICR(_i)    (0x00710 + (4 * (_i))) /* 4 total */
386  #define IXGBE_PFMBIMR(_i)    (0x00720 + (4 * (_i))) /* 4 total */
387  #define IXGBE_VFRE(_i)       (0x051E0 + ((_i) * 4))
388  #define IXGBE_VFTE(_i)       (0x08110 + ((_i) * 4))
389  #define IXGBE_VMECM(_i)      (0x08790 + ((_i) * 4))
390  #define IXGBE_QDE            0x2F04
391  #define IXGBE_VMTXSW(_i)     (0x05180 + ((_i) * 4)) /* 2 total */
392  #define IXGBE_VMOLR(_i)      (0x0F000 + ((_i) * 4)) /* 64 total */
393  #define IXGBE_UTA(_i)        (0x0F400 + ((_i) * 4))
394  #define IXGBE_MRCTL(_i)      (0x0F600 + ((_i) * 4))
395  #define IXGBE_VMRVLAN(_i)    (0x0F610 + ((_i) * 4))
396  #define IXGBE_VMRVM(_i)      (0x0F630 + ((_i) * 4))
397  #define IXGBE_WQBR_RX(_i)    (0x2FB0 + ((_i) * 4)) /* 4 total */
398  #define IXGBE_WQBR_TX(_i)    (0x8130 + ((_i) * 4)) /* 4 total */
399  #define IXGBE_L34T_IMIR(_i)  (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
400  #define IXGBE_RXFECCERR0         0x051B8
401  #define IXGBE_LLITHRESH 0x0EC90
402  #define IXGBE_IMIR(_i)  (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
403  #define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
404  #define IXGBE_IMIRVP    0x05AC0
405  #define IXGBE_VMD_CTL   0x0581C
406  #define IXGBE_RETA(_i)  (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
407  #define IXGBE_ERETA(_i)	(0x0EE80 + ((_i) * 4))  /* 96 of these (0-95) */
408  #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
409  
410  /* Registers for setting up RSS on X550 with SRIOV
411   * _p - pool number (0..63)
412   * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
413   */
414  #define IXGBE_PFVFMRQC(_p)	(0x03400 + ((_p) * 4))
415  #define IXGBE_PFVFRSSRK(_i, _p)	(0x018000 + ((_i) * 4) + ((_p) * 0x40))
416  #define IXGBE_PFVFRETA(_i, _p)	(0x019000 + ((_i) * 4) + ((_p) * 0x40))
417  
418  /* Flow Director registers */
419  #define IXGBE_FDIRCTRL  0x0EE00
420  #define IXGBE_FDIRHKEY  0x0EE68
421  #define IXGBE_FDIRSKEY  0x0EE6C
422  #define IXGBE_FDIRDIP4M 0x0EE3C
423  #define IXGBE_FDIRSIP4M 0x0EE40
424  #define IXGBE_FDIRTCPM  0x0EE44
425  #define IXGBE_FDIRUDPM  0x0EE48
426  #define IXGBE_FDIRSCTPM	0x0EE78
427  #define IXGBE_FDIRIP6M  0x0EE74
428  #define IXGBE_FDIRM     0x0EE70
429  
430  /* Flow Director Stats registers */
431  #define IXGBE_FDIRFREE  0x0EE38
432  #define IXGBE_FDIRLEN   0x0EE4C
433  #define IXGBE_FDIRUSTAT 0x0EE50
434  #define IXGBE_FDIRFSTAT 0x0EE54
435  #define IXGBE_FDIRMATCH 0x0EE58
436  #define IXGBE_FDIRMISS  0x0EE5C
437  
438  /* Flow Director Programming registers */
439  #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
440  #define IXGBE_FDIRIPSA      0x0EE18
441  #define IXGBE_FDIRIPDA      0x0EE1C
442  #define IXGBE_FDIRPORT      0x0EE20
443  #define IXGBE_FDIRVLAN      0x0EE24
444  #define IXGBE_FDIRHASH      0x0EE28
445  #define IXGBE_FDIRCMD       0x0EE2C
446  
447  /* Transmit DMA registers */
448  #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
449  #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
450  #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
451  #define IXGBE_TDH(_i)   (0x06010 + ((_i) * 0x40))
452  #define IXGBE_TDT(_i)   (0x06018 + ((_i) * 0x40))
453  #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
454  #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
455  #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
456  #define IXGBE_DTXCTL    0x07E00
457  
458  #define IXGBE_DMATXCTL      0x04A80
459  #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
460  #define IXGBE_PFDTXGSWC     0x08220
461  #define IXGBE_DTXMXSZRQ     0x08100
462  #define IXGBE_DTXTCPFLGL    0x04A88
463  #define IXGBE_DTXTCPFLGH    0x04A8C
464  #define IXGBE_LBDRPEN       0x0CA00
465  #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
466  
467  #define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
468  #define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
469  #define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
470  #define IXGBE_DMATXCTL_MDP_EN   0x20 /* Bit 5 */
471  #define IXGBE_DMATXCTL_MBINTEN  0x40 /* Bit 6 */
472  #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
473  
474  #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
475  
476  /* Anti-spoofing defines */
477  #define IXGBE_SPOOF_MACAS_MASK          0xFF
478  #define IXGBE_SPOOF_VLANAS_MASK         0xFF00
479  #define IXGBE_SPOOF_VLANAS_SHIFT        8
480  #define IXGBE_SPOOF_ETHERTYPEAS		0xFF000000
481  #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT	16
482  #define IXGBE_PFVFSPOOF_REG_COUNT       8
483  
484  #define IXGBE_DCA_TXCTRL(_i)    (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
485  /* Tx DCA Control register : 128 of these (0-127) */
486  #define IXGBE_DCA_TXCTRL_82599(_i)  (0x0600C + ((_i) * 0x40))
487  #define IXGBE_TIPG      0x0CB00
488  #define IXGBE_TXPBSIZE(_i)      (0x0CC00 + ((_i) * 4)) /* 8 of these */
489  #define IXGBE_MNGTXMAP  0x0CD10
490  #define IXGBE_TIPG_FIBER_DEFAULT 3
491  #define IXGBE_TXPBSIZE_SHIFT    10
492  
493  /* Wake up registers */
494  #define IXGBE_WUC       0x05800
495  #define IXGBE_WUFC      0x05808
496  #define IXGBE_WUS       0x05810
497  #define IXGBE_IPAV      0x05838
498  #define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
499  #define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
500  
501  #define IXGBE_WUPL      0x05900
502  #define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
503  #define IXGBE_VXLANCTRL	0x0000507C /* Rx filter VXLAN UDPPORT Register */
504  #define IXGBE_FHFT(_n)	(0x09000 + ((_n) * 0x100)) /* Flex host filter table */
505  #define IXGBE_FHFT_EXT(_n)	(0x09800 + ((_n) * 0x100)) /* Ext Flexible Host
506  							    * Filter Table */
507  
508  /* masks for accessing VXLAN and GENEVE UDP ports */
509  #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK     0x0000ffff /* VXLAN port */
510  #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK    0xffff0000 /* GENEVE port */
511  #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK       0xffffffff /* GENEVE/VXLAN */
512  
513  #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT   16
514  
515  #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4
516  #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
517  
518  /* Each Flexible Filter is at most 128 (0x80) bytes in length */
519  #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX  128
520  #define IXGBE_FHFT_LENGTH_OFFSET        0xFC  /* Length byte in FHFT */
521  #define IXGBE_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
522  
523  /* Definitions for power management and wakeup registers */
524  /* Wake Up Control */
525  #define IXGBE_WUC_PME_EN     0x00000002 /* PME Enable */
526  #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
527  #define IXGBE_WUC_WKEN       0x00000010 /* Enable PE_WAKE_N pin assertion  */
528  
529  /* Wake Up Filter Control */
530  #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
531  #define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
532  #define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
533  #define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
534  #define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
535  #define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
536  #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
537  #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
538  #define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
539  
540  #define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
541  #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
542  #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
543  #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
544  #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
545  #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
546  #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
547  #define IXGBE_WUFC_FLX_FILTERS     0x000F0000 /* Mask for 4 flex filters */
548  #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
549  #define IXGBE_WUFC_ALL_FILTERS     0x003F00FF /* Mask for all wakeup filters */
550  #define IXGBE_WUFC_FLX_OFFSET      16 /* Offset to the Flexible Filters bits */
551  
552  /* Wake Up Status */
553  #define IXGBE_WUS_LNKC  IXGBE_WUFC_LNKC
554  #define IXGBE_WUS_MAG   IXGBE_WUFC_MAG
555  #define IXGBE_WUS_EX    IXGBE_WUFC_EX
556  #define IXGBE_WUS_MC    IXGBE_WUFC_MC
557  #define IXGBE_WUS_BC    IXGBE_WUFC_BC
558  #define IXGBE_WUS_ARP   IXGBE_WUFC_ARP
559  #define IXGBE_WUS_IPV4  IXGBE_WUFC_IPV4
560  #define IXGBE_WUS_IPV6  IXGBE_WUFC_IPV6
561  #define IXGBE_WUS_MNG   IXGBE_WUFC_MNG
562  #define IXGBE_WUS_FLX0  IXGBE_WUFC_FLX0
563  #define IXGBE_WUS_FLX1  IXGBE_WUFC_FLX1
564  #define IXGBE_WUS_FLX2  IXGBE_WUFC_FLX2
565  #define IXGBE_WUS_FLX3  IXGBE_WUFC_FLX3
566  #define IXGBE_WUS_FLX4  IXGBE_WUFC_FLX4
567  #define IXGBE_WUS_FLX5  IXGBE_WUFC_FLX5
568  #define IXGBE_WUS_FLX_FILTERS  IXGBE_WUFC_FLX_FILTERS
569  
570  /* Wake Up Packet Length */
571  #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
572  
573  /* DCB registers */
574  #define MAX_TRAFFIC_CLASS        8
575  #define X540_TRAFFIC_CLASS       4
576  #define DEF_TRAFFIC_CLASS        1
577  #define IXGBE_RMCS      0x03D00
578  #define IXGBE_DPMCS     0x07F40
579  #define IXGBE_PDPMCS    0x0CD00
580  #define IXGBE_RUPPBMR   0x050A0
581  #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
582  #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
583  #define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
584  #define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
585  #define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
586  #define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
587  
588  /* Security Control Registers */
589  #define IXGBE_SECTXCTRL         0x08800
590  #define IXGBE_SECTXSTAT         0x08804
591  #define IXGBE_SECTXBUFFAF       0x08808
592  #define IXGBE_SECTXMINIFG       0x08810
593  #define IXGBE_SECRXCTRL         0x08D00
594  #define IXGBE_SECRXSTAT         0x08D04
595  
596  /* Security Bit Fields and Masks */
597  #define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
598  #define IXGBE_SECTXCTRL_TX_DIS          0x00000002
599  #define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
600  
601  #define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
602  #define IXGBE_SECTXSTAT_SECTX_OFF_DIS   0x00000002
603  #define IXGBE_SECTXSTAT_ECC_TXERR       0x00000004
604  
605  #define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
606  #define IXGBE_SECRXCTRL_RX_DIS          0x00000002
607  
608  #define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001
609  #define IXGBE_SECRXSTAT_SECRX_OFF_DIS   0x00000002
610  #define IXGBE_SECRXSTAT_ECC_RXERR       0x00000004
611  
612  /* LinkSec (MacSec) Registers */
613  #define IXGBE_LSECTXCAP         0x08A00
614  #define IXGBE_LSECRXCAP         0x08F00
615  #define IXGBE_LSECTXCTRL        0x08A04
616  #define IXGBE_LSECTXSCL         0x08A08 /* SCI Low */
617  #define IXGBE_LSECTXSCH         0x08A0C /* SCI High */
618  #define IXGBE_LSECTXSA          0x08A10
619  #define IXGBE_LSECTXPN0         0x08A14
620  #define IXGBE_LSECTXPN1         0x08A18
621  #define IXGBE_LSECTXKEY0(_n)    (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
622  #define IXGBE_LSECTXKEY1(_n)    (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
623  #define IXGBE_LSECRXCTRL        0x08F04
624  #define IXGBE_LSECRXSCL         0x08F08
625  #define IXGBE_LSECRXSCH         0x08F0C
626  #define IXGBE_LSECRXSA(_i)      (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
627  #define IXGBE_LSECRXPN(_i)      (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
628  #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
629  #define IXGBE_LSECTXUT          0x08A3C /* OutPktsUntagged */
630  #define IXGBE_LSECTXPKTE        0x08A40 /* OutPktsEncrypted */
631  #define IXGBE_LSECTXPKTP        0x08A44 /* OutPktsProtected */
632  #define IXGBE_LSECTXOCTE        0x08A48 /* OutOctetsEncrypted */
633  #define IXGBE_LSECTXOCTP        0x08A4C /* OutOctetsProtected */
634  #define IXGBE_LSECRXUT          0x08F40 /* InPktsUntagged/InPktsNoTag */
635  #define IXGBE_LSECRXOCTD        0x08F44 /* InOctetsDecrypted */
636  #define IXGBE_LSECRXOCTV        0x08F48 /* InOctetsValidated */
637  #define IXGBE_LSECRXBAD         0x08F4C /* InPktsBadTag */
638  #define IXGBE_LSECRXNOSCI       0x08F50 /* InPktsNoSci */
639  #define IXGBE_LSECRXUNSCI       0x08F54 /* InPktsUnknownSci */
640  #define IXGBE_LSECRXUNCH        0x08F58 /* InPktsUnchecked */
641  #define IXGBE_LSECRXDELAY       0x08F5C /* InPktsDelayed */
642  #define IXGBE_LSECRXLATE        0x08F60 /* InPktsLate */
643  #define IXGBE_LSECRXOK(_n)      (0x08F64 + (0x04 * (_n))) /* InPktsOk */
644  #define IXGBE_LSECRXINV(_n)     (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
645  #define IXGBE_LSECRXNV(_n)      (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
646  #define IXGBE_LSECRXUNSA        0x08F7C /* InPktsUnusedSa */
647  #define IXGBE_LSECRXNUSA        0x08F80 /* InPktsNotUsingSa */
648  
649  /* LinkSec (MacSec) Bit Fields and Masks */
650  #define IXGBE_LSECTXCAP_SUM_MASK        0x00FF0000
651  #define IXGBE_LSECTXCAP_SUM_SHIFT       16
652  #define IXGBE_LSECRXCAP_SUM_MASK        0x00FF0000
653  #define IXGBE_LSECRXCAP_SUM_SHIFT       16
654  
655  #define IXGBE_LSECTXCTRL_EN_MASK        0x00000003
656  #define IXGBE_LSECTXCTRL_DISABLE        0x0
657  #define IXGBE_LSECTXCTRL_AUTH           0x1
658  #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT   0x2
659  #define IXGBE_LSECTXCTRL_AISCI          0x00000020
660  #define IXGBE_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
661  #define IXGBE_LSECTXCTRL_RSV_MASK       0x000000D8
662  
663  #define IXGBE_LSECRXCTRL_EN_MASK        0x0000000C
664  #define IXGBE_LSECRXCTRL_EN_SHIFT       2
665  #define IXGBE_LSECRXCTRL_DISABLE        0x0
666  #define IXGBE_LSECRXCTRL_CHECK          0x1
667  #define IXGBE_LSECRXCTRL_STRICT         0x2
668  #define IXGBE_LSECRXCTRL_DROP           0x3
669  #define IXGBE_LSECRXCTRL_PLSH           0x00000040
670  #define IXGBE_LSECRXCTRL_RP             0x00000080
671  #define IXGBE_LSECRXCTRL_RSV_MASK       0xFFFFFF33
672  
673  /* IpSec Registers */
674  #define IXGBE_IPSTXIDX          0x08900
675  #define IXGBE_IPSTXSALT         0x08904
676  #define IXGBE_IPSTXKEY(_i)      (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
677  #define IXGBE_IPSRXIDX          0x08E00
678  #define IXGBE_IPSRXIPADDR(_i)   (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
679  #define IXGBE_IPSRXSPI          0x08E14
680  #define IXGBE_IPSRXIPIDX        0x08E18
681  #define IXGBE_IPSRXKEY(_i)      (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
682  #define IXGBE_IPSRXSALT         0x08E2C
683  #define IXGBE_IPSRXMOD          0x08E30
684  
685  #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE    0x4
686  
687  /* DCB registers */
688  #define IXGBE_RTRPCS      0x02430
689  #define IXGBE_RTTDCS      0x04900
690  #define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
691  #define IXGBE_RTTPCS      0x0CD00
692  #define IXGBE_RTRUP2TC    0x03020
693  #define IXGBE_RTTUP2TC    0x0C800
694  #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
695  #define IXGBE_TXLLQ(_i)   (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
696  #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
697  #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
698  #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
699  #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
700  #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
701  #define IXGBE_RTTDQSEL    0x04904
702  #define IXGBE_RTTDT1C     0x04908
703  #define IXGBE_RTTDT1S     0x0490C
704  #define IXGBE_RTTQCNCR    0x08B00
705  #define IXGBE_RTTQCNTG    0x04A90
706  #define IXGBE_RTTBCNRD    0x0498C
707  #define IXGBE_RTTQCNRR    0x0498C
708  #define IXGBE_RTTDTECC    0x04990
709  #define IXGBE_RTTDTECC_NO_BCN   0x00000100
710  #define IXGBE_RTTBCNRC    0x04984
711  #define IXGBE_RTTBCNRC_RS_ENA	0x80000000
712  #define IXGBE_RTTBCNRC_RF_DEC_MASK	0x00003FFF
713  #define IXGBE_RTTBCNRC_RF_INT_SHIFT	14
714  #define IXGBE_RTTBCNRC_RF_INT_MASK	\
715  	(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
716  #define IXGBE_RTTBCNRM    0x04980
717  #define IXGBE_RTTQCNRM    0x04980
718  
719  /* FCoE Direct DMA Context */
720  #define IXGBE_FCDDC(_i, _j)	(0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
721  /* FCoE DMA Context Registers */
722  #define IXGBE_FCPTRL    0x02410 /* FC User Desc. PTR Low */
723  #define IXGBE_FCPTRH    0x02414 /* FC USer Desc. PTR High */
724  #define IXGBE_FCBUFF    0x02418 /* FC Buffer Control */
725  #define IXGBE_FCDMARW   0x02420 /* FC Receive DMA RW */
726  #define IXGBE_FCINVST0  0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
727  #define IXGBE_FCINVST(_i)       (IXGBE_FCINVST0 + ((_i) * 4))
728  #define IXGBE_FCBUFF_VALID      BIT(0)    /* DMA Context Valid */
729  #define IXGBE_FCBUFF_BUFFSIZE   (3u << 3) /* User Buffer Size */
730  #define IXGBE_FCBUFF_WRCONTX    BIT(7)    /* 0: Initiator, 1: Target */
731  #define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
732  #define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
733  #define IXGBE_FCBUFF_BUFFSIZE_SHIFT  3
734  #define IXGBE_FCBUFF_BUFFCNT_SHIFT   8
735  #define IXGBE_FCBUFF_OFFSET_SHIFT    16
736  #define IXGBE_FCDMARW_WE        BIT(14)   /* Write enable */
737  #define IXGBE_FCDMARW_RE        BIT(15)   /* Read enable */
738  #define IXGBE_FCDMARW_FCOESEL   0x000001ff  /* FC X_ID: 11 bits */
739  #define IXGBE_FCDMARW_LASTSIZE  0xffff0000  /* Last User Buffer Size */
740  #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
741  
742  /* FCoE SOF/EOF */
743  #define IXGBE_TEOFF     0x04A94 /* Tx FC EOF */
744  #define IXGBE_TSOFF     0x04A98 /* Tx FC SOF */
745  #define IXGBE_REOFF     0x05158 /* Rx FC EOF */
746  #define IXGBE_RSOFF     0x051F8 /* Rx FC SOF */
747  /* FCoE Direct Filter Context */
748  #define IXGBE_FCDFC(_i, _j)	(0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
749  #define IXGBE_FCDFCD(_i)	(0x30000 + ((_i) * 0x4))
750  /* FCoE Filter Context Registers */
751  #define IXGBE_FCFLT     0x05108 /* FC FLT Context */
752  #define IXGBE_FCFLTRW   0x05110 /* FC Filter RW Control */
753  #define IXGBE_FCPARAM   0x051d8 /* FC Offset Parameter */
754  #define IXGBE_FCFLT_VALID       BIT(0)   /* Filter Context Valid */
755  #define IXGBE_FCFLT_FIRST       BIT(1)   /* Filter First */
756  #define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
757  #define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
758  #define IXGBE_FCFLTRW_RVALDT    BIT(13)  /* Fast Re-Validation */
759  #define IXGBE_FCFLTRW_WE        BIT(14)  /* Write Enable */
760  #define IXGBE_FCFLTRW_RE        BIT(15)  /* Read Enable */
761  /* FCoE Receive Control */
762  #define IXGBE_FCRXCTRL  0x05100 /* FC Receive Control */
763  #define IXGBE_FCRXCTRL_FCOELLI  BIT(0)   /* Low latency interrupt */
764  #define IXGBE_FCRXCTRL_SAVBAD   BIT(1)   /* Save Bad Frames */
765  #define IXGBE_FCRXCTRL_FRSTRDH  BIT(2)   /* EN 1st Read Header */
766  #define IXGBE_FCRXCTRL_LASTSEQH BIT(3)   /* EN Last Header in Seq */
767  #define IXGBE_FCRXCTRL_ALLH     BIT(4)   /* EN All Headers */
768  #define IXGBE_FCRXCTRL_FRSTSEQH BIT(5)   /* EN 1st Seq. Header */
769  #define IXGBE_FCRXCTRL_ICRC     BIT(6)   /* Ignore Bad FC CRC */
770  #define IXGBE_FCRXCTRL_FCCRCBO  BIT(7)   /* FC CRC Byte Ordering */
771  #define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
772  #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
773  /* FCoE Redirection */
774  #define IXGBE_FCRECTL   0x0ED00 /* FC Redirection Control */
775  #define IXGBE_FCRETA0   0x0ED10 /* FC Redirection Table 0 */
776  #define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
777  #define IXGBE_FCRECTL_ENA       0x1        /* FCoE Redir Table Enable */
778  #define IXGBE_FCRETA_SIZE       8          /* Max entries in FCRETA */
779  #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
780  #define IXGBE_FCRETA_SIZE_X550	32 /* Max entries in FCRETA */
781  /* Higher 7 bits for the queue index */
782  #define IXGBE_FCRETA_ENTRY_HIGH_MASK	0x007F0000
783  #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT	16
784  
785  /* Stats registers */
786  #define IXGBE_CRCERRS   0x04000
787  #define IXGBE_ILLERRC   0x04004
788  #define IXGBE_ERRBC     0x04008
789  #define IXGBE_MSPDC     0x04010
790  #define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
791  #define IXGBE_MLFC      0x04034
792  #define IXGBE_MRFC      0x04038
793  #define IXGBE_RLEC      0x04040
794  #define IXGBE_LXONTXC   0x03F60
795  #define IXGBE_LXONRXC   0x0CF60
796  #define IXGBE_LXOFFTXC  0x03F68
797  #define IXGBE_LXOFFRXC  0x0CF68
798  #define IXGBE_LXONRXCNT 0x041A4
799  #define IXGBE_LXOFFRXCNT 0x041A8
800  #define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
801  #define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
802  #define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
803  #define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
804  #define IXGBE_PXONRXC(_i)       (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
805  #define IXGBE_PXOFFTXC(_i)      (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
806  #define IXGBE_PXOFFRXC(_i)      (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
807  #define IXGBE_PRC64     0x0405C
808  #define IXGBE_PRC127    0x04060
809  #define IXGBE_PRC255    0x04064
810  #define IXGBE_PRC511    0x04068
811  #define IXGBE_PRC1023   0x0406C
812  #define IXGBE_PRC1522   0x04070
813  #define IXGBE_GPRC      0x04074
814  #define IXGBE_BPRC      0x04078
815  #define IXGBE_MPRC      0x0407C
816  #define IXGBE_GPTC      0x04080
817  #define IXGBE_GORCL     0x04088
818  #define IXGBE_GORCH     0x0408C
819  #define IXGBE_GOTCL     0x04090
820  #define IXGBE_GOTCH     0x04094
821  #define IXGBE_RNBC(_i)  (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
822  #define IXGBE_RUC       0x040A4
823  #define IXGBE_RFC       0x040A8
824  #define IXGBE_ROC       0x040AC
825  #define IXGBE_RJC       0x040B0
826  #define IXGBE_MNGPRC    0x040B4
827  #define IXGBE_MNGPDC    0x040B8
828  #define IXGBE_MNGPTC    0x0CF90
829  #define IXGBE_TORL      0x040C0
830  #define IXGBE_TORH      0x040C4
831  #define IXGBE_TPR       0x040D0
832  #define IXGBE_TPT       0x040D4
833  #define IXGBE_PTC64     0x040D8
834  #define IXGBE_PTC127    0x040DC
835  #define IXGBE_PTC255    0x040E0
836  #define IXGBE_PTC511    0x040E4
837  #define IXGBE_PTC1023   0x040E8
838  #define IXGBE_PTC1522   0x040EC
839  #define IXGBE_MPTC      0x040F0
840  #define IXGBE_BPTC      0x040F4
841  #define IXGBE_XEC       0x04120
842  #define IXGBE_SSVPC     0x08780
843  
844  #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
845  #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
846  			 (0x08600 + ((_i) * 4)))
847  #define IXGBE_TQSM(_i)  (0x08600 + ((_i) * 4))
848  
849  #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
850  #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
851  #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
852  #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
853  #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
854  #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
855  #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
856  #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
857  #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
858  #define IXGBE_FCCRC     0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
859  #define IXGBE_FCOERPDC  0x0241C /* FCoE Rx Packets Dropped Count */
860  #define IXGBE_FCLAST    0x02424 /* FCoE Last Error Count */
861  #define IXGBE_FCOEPRC   0x02428 /* Number of FCoE Packets Received */
862  #define IXGBE_FCOEDWRC  0x0242C /* Number of FCoE DWords Received */
863  #define IXGBE_FCOEPTC   0x08784 /* Number of FCoE Packets Transmitted */
864  #define IXGBE_FCOEDWTC  0x08788 /* Number of FCoE DWords Transmitted */
865  #define IXGBE_O2BGPTC   0x041C4
866  #define IXGBE_O2BSPC    0x087B0
867  #define IXGBE_B2OSPC    0x041C0
868  #define IXGBE_B2OGPRC   0x02F90
869  #define IXGBE_PCRC8ECL  0x0E810
870  #define IXGBE_PCRC8ECH  0x0E811
871  #define IXGBE_PCRC8ECH_MASK     0x1F
872  #define IXGBE_LDPCECL   0x0E820
873  #define IXGBE_LDPCECH   0x0E821
874  
875  /* MII clause 22/28 definitions */
876  #define IXGBE_MDIO_PHY_LOW_POWER_MODE	0x0800
877  
878  #define IXGBE_MDIO_XENPAK_LASI_STATUS	0x9005 /* XENPAK LASI Status register */
879  #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */
880  
881  #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS	0x4 /* Indicates if link is up */
882  
883  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK	0x7 /* Speed/Duplex Mask */
884  #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK	0x6 /* Speed Mask */
885  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */
886  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */
887  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s H Duplex */
888  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s F Duplex */
889  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */
890  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */
891  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */
892  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */
893  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB	0x4 /* 1Gb/s */
894  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB	0x6 /* 10Gb/s */
895  
896  #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400	/* 1G Provisioning 1 */
897  #define IXGBE_MII_AUTONEG_XNP_TX_REG		0x17	/* 1G XNP Transmit */
898  #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX	0x4000	/* full duplex, bit:14*/
899  #define IXGBE_MII_1GBASE_T_ADVERTISE		0x8000	/* full duplex, bit:15*/
900  #define IXGBE_MII_2_5GBASE_T_ADVERTISE		0x0400
901  #define IXGBE_MII_5GBASE_T_ADVERTISE		0x0800
902  #define IXGBE_MII_RESTART			0x200
903  #define IXGBE_MII_AUTONEG_LINK_UP		0x04
904  #define IXGBE_MII_AUTONEG_REG			0x0
905  
906  /* Management */
907  #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
908  #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
909  #define IXGBE_MANC      0x05820
910  #define IXGBE_MFVAL     0x05824
911  #define IXGBE_MANC2H    0x05860
912  #define IXGBE_MDEF(_i)  (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
913  #define IXGBE_MIPAF     0x058B0
914  #define IXGBE_MMAL(_i)  (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
915  #define IXGBE_MMAH(_i)  (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
916  #define IXGBE_FTFT      0x09400 /* 0x9400-0x97FC */
917  #define IXGBE_METF(_i)  (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
918  #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
919  #define IXGBE_LSWFW     0x15014
920  
921  /* Management Bit Fields and Masks */
922  #define IXGBE_MANC_RCV_TCO_EN	0x00020000 /* Rcv TCO packet enable */
923  
924  /* Firmware Semaphore Register */
925  #define IXGBE_FWSM_MODE_MASK	0xE
926  #define IXGBE_FWSM_FW_MODE_PT	0x4
927  #define IXGBE_FWSM_FW_NVM_RECOVERY_MODE	BIT(5)
928  #define IXGBE_FWSM_EXT_ERR_IND_MASK	0x01F80000
929  #define IXGBE_FWSM_FW_VAL_BIT	BIT(15)
930  
931  /* ARC Subsystem registers */
932  #define IXGBE_HICR      0x15F00
933  #define IXGBE_FWSTS     0x15F0C
934  #define IXGBE_HSMC0R    0x15F04
935  #define IXGBE_HSMC1R    0x15F08
936  #define IXGBE_SWSR      0x15F10
937  #define IXGBE_HFDR      0x15FE8
938  #define IXGBE_FLEX_MNG  0x15800 /* 0x15800 - 0x15EFC */
939  
940  #define IXGBE_HICR_EN              0x01  /* Enable bit - RO */
941  /* Driver sets this bit when done to put command in RAM */
942  #define IXGBE_HICR_C               0x02
943  #define IXGBE_HICR_SV              0x04  /* Status Validity */
944  #define IXGBE_HICR_FW_RESET_ENABLE 0x40
945  #define IXGBE_HICR_FW_RESET        0x80
946  
947  /* PCI-E registers */
948  #define IXGBE_GCR       0x11000
949  #define IXGBE_GTV       0x11004
950  #define IXGBE_FUNCTAG   0x11008
951  #define IXGBE_GLT       0x1100C
952  #define IXGBE_GSCL_1    0x11010
953  #define IXGBE_GSCL_2    0x11014
954  #define IXGBE_GSCL_3    0x11018
955  #define IXGBE_GSCL_4    0x1101C
956  #define IXGBE_GSCN_0    0x11020
957  #define IXGBE_GSCN_1    0x11024
958  #define IXGBE_GSCN_2    0x11028
959  #define IXGBE_GSCN_3    0x1102C
960  #define IXGBE_FACTPS_8259X	0x10150
961  #define IXGBE_FACTPS_X540	IXGBE_FACTPS_8259X
962  #define IXGBE_FACTPS_X550	IXGBE_FACTPS_8259X
963  #define IXGBE_FACTPS_X550EM_x	IXGBE_FACTPS_8259X
964  #define IXGBE_FACTPS_X550EM_a	0x15FEC
965  #define IXGBE_FACTPS(_hw)	IXGBE_BY_MAC((_hw), FACTPS)
966  
967  #define IXGBE_PCIEANACTL  0x11040
968  #define IXGBE_SWSM_8259X	0x10140
969  #define IXGBE_SWSM_X540		IXGBE_SWSM_8259X
970  #define IXGBE_SWSM_X550		IXGBE_SWSM_8259X
971  #define IXGBE_SWSM_X550EM_x	IXGBE_SWSM_8259X
972  #define IXGBE_SWSM_X550EM_a	0x15F70
973  #define IXGBE_SWSM(_hw)		IXGBE_BY_MAC((_hw), SWSM)
974  #define IXGBE_FWSM_8259X	0x10148
975  #define IXGBE_FWSM_X540		IXGBE_FWSM_8259X
976  #define IXGBE_FWSM_X550		IXGBE_FWSM_8259X
977  #define IXGBE_FWSM_X550EM_x	IXGBE_FWSM_8259X
978  #define IXGBE_FWSM_X550EM_a	0x15F74
979  #define IXGBE_FWSM(_hw)		IXGBE_BY_MAC((_hw), FWSM)
980  #define IXGBE_GSSR      0x10160
981  #define IXGBE_MREVID    0x11064
982  #define IXGBE_DCA_ID    0x11070
983  #define IXGBE_DCA_CTRL  0x11074
984  #define IXGBE_SWFW_SYNC_8259X		IXGBE_GSSR
985  #define IXGBE_SWFW_SYNC_X540		IXGBE_SWFW_SYNC_8259X
986  #define IXGBE_SWFW_SYNC_X550		IXGBE_SWFW_SYNC_8259X
987  #define IXGBE_SWFW_SYNC_X550EM_x	IXGBE_SWFW_SYNC_8259X
988  #define IXGBE_SWFW_SYNC_X550EM_a	0x15F78
989  #define IXGBE_SWFW_SYNC(_hw)		IXGBE_BY_MAC((_hw), SWFW_SYNC)
990  
991  /* PCIe registers 82599-specific */
992  #define IXGBE_GCR_EXT           0x11050
993  #define IXGBE_GSCL_5_82599      0x11030
994  #define IXGBE_GSCL_6_82599      0x11034
995  #define IXGBE_GSCL_7_82599      0x11038
996  #define IXGBE_GSCL_8_82599      0x1103C
997  #define IXGBE_PHYADR_82599      0x11040
998  #define IXGBE_PHYDAT_82599      0x11044
999  #define IXGBE_PHYCTL_82599      0x11048
1000  #define IXGBE_PBACLR_82599      0x11068
1001  
1002  #define IXGBE_CIAA_8259X	0x11088
1003  #define IXGBE_CIAA_X540		IXGBE_CIAA_8259X
1004  #define IXGBE_CIAA_X550		0x11508
1005  #define IXGBE_CIAA_X550EM_x	IXGBE_CIAA_X550
1006  #define IXGBE_CIAA_X550EM_a	IXGBE_CIAA_X550
1007  #define IXGBE_CIAA(_hw)		IXGBE_BY_MAC((_hw), CIAA)
1008  
1009  #define IXGBE_CIAD_8259X	0x1108C
1010  #define IXGBE_CIAD_X540		IXGBE_CIAD_8259X
1011  #define IXGBE_CIAD_X550		0x11510
1012  #define IXGBE_CIAD_X550EM_x	IXGBE_CIAD_X550
1013  #define IXGBE_CIAD_X550EM_a	IXGBE_CIAD_X550
1014  #define IXGBE_CIAD(_hw)		IXGBE_BY_MAC((_hw), CIAD)
1015  
1016  #define IXGBE_PICAUSE           0x110B0
1017  #define IXGBE_PIENA             0x110B8
1018  #define IXGBE_CDQ_MBR_82599     0x110B4
1019  #define IXGBE_PCIESPARE         0x110BC
1020  #define IXGBE_MISC_REG_82599    0x110F0
1021  #define IXGBE_ECC_CTRL_0_82599  0x11100
1022  #define IXGBE_ECC_CTRL_1_82599  0x11104
1023  #define IXGBE_ECC_STATUS_82599  0x110E0
1024  #define IXGBE_BAR_CTRL_82599    0x110F4
1025  
1026  /* PCI Express Control */
1027  #define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
1028  #define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
1029  #define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
1030  #define IXGBE_GCR_CAP_VER2              0x00040000
1031  
1032  #define IXGBE_GCR_EXT_MSIX_EN           0x80000000
1033  #define IXGBE_GCR_EXT_BUFFERS_CLEAR     0x40000000
1034  #define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
1035  #define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
1036  #define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
1037  #define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
1038  					 IXGBE_GCR_EXT_VT_MODE_64)
1039  
1040  /* Time Sync Registers */
1041  #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
1042  #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
1043  #define IXGBE_RXSTMPL    0x051E8 /* Rx timestamp Low - RO */
1044  #define IXGBE_RXSTMPH    0x051A4 /* Rx timestamp High - RO */
1045  #define IXGBE_RXSATRL    0x051A0 /* Rx timestamp attribute low - RO */
1046  #define IXGBE_RXSATRH    0x051A8 /* Rx timestamp attribute high - RO */
1047  #define IXGBE_RXMTRL     0x05120 /* RX message type register low - RW */
1048  #define IXGBE_TXSTMPL    0x08C04 /* Tx timestamp value Low - RO */
1049  #define IXGBE_TXSTMPH    0x08C08 /* Tx timestamp value High - RO */
1050  #define IXGBE_SYSTIML    0x08C0C /* System time register Low - RO */
1051  #define IXGBE_SYSTIMH    0x08C10 /* System time register High - RO */
1052  #define IXGBE_SYSTIMR    0x08C58 /* System time register Residue - RO */
1053  #define IXGBE_TIMINCA    0x08C14 /* Increment attributes register - RW */
1054  #define IXGBE_TIMADJL    0x08C18 /* Time Adjustment Offset register Low - RW */
1055  #define IXGBE_TIMADJH    0x08C1C /* Time Adjustment Offset register High - RW */
1056  #define IXGBE_TSAUXC     0x08C20 /* TimeSync Auxiliary Control register - RW */
1057  #define IXGBE_TRGTTIML0  0x08C24 /* Target Time Register 0 Low - RW */
1058  #define IXGBE_TRGTTIMH0  0x08C28 /* Target Time Register 0 High - RW */
1059  #define IXGBE_TRGTTIML1  0x08C2C /* Target Time Register 1 Low - RW */
1060  #define IXGBE_TRGTTIMH1  0x08C30 /* Target Time Register 1 High - RW */
1061  #define IXGBE_CLKTIML    0x08C34 /* Clock Out Time Register Low - RW */
1062  #define IXGBE_CLKTIMH    0x08C38 /* Clock Out Time Register High - RW */
1063  #define IXGBE_FREQOUT0   0x08C34 /* Frequency Out 0 Control register - RW */
1064  #define IXGBE_FREQOUT1   0x08C38 /* Frequency Out 1 Control register - RW */
1065  #define IXGBE_AUXSTMPL0  0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
1066  #define IXGBE_AUXSTMPH0  0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
1067  #define IXGBE_AUXSTMPL1  0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
1068  #define IXGBE_AUXSTMPH1  0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
1069  #define IXGBE_TSIM       0x08C68 /* TimeSync Interrupt Mask Register - RW */
1070  #define IXGBE_TSSDP      0x0003C /* TimeSync SDP Configuration Register - RW */
1071  
1072  /* Diagnostic Registers */
1073  #define IXGBE_RDSTATCTL   0x02C20
1074  #define IXGBE_RDSTAT(_i)  (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
1075  #define IXGBE_RDHMPN      0x02F08
1076  #define IXGBE_RIC_DW(_i)  (0x02F10 + ((_i) * 4))
1077  #define IXGBE_RDPROBE     0x02F20
1078  #define IXGBE_RDMAM       0x02F30
1079  #define IXGBE_RDMAD       0x02F34
1080  #define IXGBE_TDSTATCTL   0x07C20
1081  #define IXGBE_TDSTAT(_i)  (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
1082  #define IXGBE_TDHMPN      0x07F08
1083  #define IXGBE_TDHMPN2     0x082FC
1084  #define IXGBE_TXDESCIC    0x082CC
1085  #define IXGBE_TIC_DW(_i)  (0x07F10 + ((_i) * 4))
1086  #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
1087  #define IXGBE_TDPROBE     0x07F20
1088  #define IXGBE_TXBUFCTRL   0x0C600
1089  #define IXGBE_TXBUFDATA(_i) (0x0C610 + ((_i) * 4)) /* 4 of these (0-3) */
1090  #define IXGBE_RXBUFCTRL   0x03600
1091  #define IXGBE_RXBUFDATA(_i) (0x03610 + ((_i) * 4)) /* 4 of these (0-3) */
1092  #define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
1093  #define IXGBE_RFVAL     0x050A4
1094  #define IXGBE_MDFTC1    0x042B8
1095  #define IXGBE_MDFTC2    0x042C0
1096  #define IXGBE_MDFTFIFO1 0x042C4
1097  #define IXGBE_MDFTFIFO2 0x042C8
1098  #define IXGBE_MDFTS     0x042CC
1099  #define IXGBE_RXDATAWRPTR(_i)   (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
1100  #define IXGBE_RXDESCWRPTR(_i)   (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
1101  #define IXGBE_RXDATARDPTR(_i)   (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
1102  #define IXGBE_RXDESCRDPTR(_i)   (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
1103  #define IXGBE_TXDATAWRPTR(_i)   (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
1104  #define IXGBE_TXDESCWRPTR(_i)   (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
1105  #define IXGBE_TXDATARDPTR(_i)   (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
1106  #define IXGBE_TXDESCRDPTR(_i)   (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
1107  #define IXGBE_PCIEECCCTL 0x1106C
1108  #define IXGBE_RXWRPTR(_i)       (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
1109  #define IXGBE_RXUSED(_i)        (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
1110  #define IXGBE_RXRDPTR(_i)       (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
1111  #define IXGBE_RXRDWRPTR(_i)     (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
1112  #define IXGBE_TXWRPTR(_i)       (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
1113  #define IXGBE_TXUSED(_i)        (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
1114  #define IXGBE_TXRDPTR(_i)       (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
1115  #define IXGBE_TXRDWRPTR(_i)     (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
1116  #define IXGBE_PCIEECCCTL0 0x11100
1117  #define IXGBE_PCIEECCCTL1 0x11104
1118  #define IXGBE_RXDBUECC  0x03F70
1119  #define IXGBE_TXDBUECC  0x0CF70
1120  #define IXGBE_RXDBUEST 0x03F74
1121  #define IXGBE_TXDBUEST 0x0CF74
1122  #define IXGBE_PBTXECC   0x0C300
1123  #define IXGBE_PBRXECC   0x03300
1124  #define IXGBE_GHECCR    0x110B0
1125  
1126  /* MAC Registers */
1127  #define IXGBE_PCS1GCFIG 0x04200
1128  #define IXGBE_PCS1GLCTL 0x04208
1129  #define IXGBE_PCS1GLSTA 0x0420C
1130  #define IXGBE_PCS1GDBG0 0x04210
1131  #define IXGBE_PCS1GDBG1 0x04214
1132  #define IXGBE_PCS1GANA  0x04218
1133  #define IXGBE_PCS1GANLP 0x0421C
1134  #define IXGBE_PCS1GANNP 0x04220
1135  #define IXGBE_PCS1GANLPNP 0x04224
1136  #define IXGBE_HLREG0    0x04240
1137  #define IXGBE_HLREG1    0x04244
1138  #define IXGBE_PAP       0x04248
1139  #define IXGBE_MACA      0x0424C
1140  #define IXGBE_APAE      0x04250
1141  #define IXGBE_ARD       0x04254
1142  #define IXGBE_AIS       0x04258
1143  #define IXGBE_MSCA      0x0425C
1144  #define IXGBE_MSRWD     0x04260
1145  #define IXGBE_MLADD     0x04264
1146  #define IXGBE_MHADD     0x04268
1147  #define IXGBE_MAXFRS    0x04268
1148  #define IXGBE_TREG      0x0426C
1149  #define IXGBE_PCSS1     0x04288
1150  #define IXGBE_PCSS2     0x0428C
1151  #define IXGBE_XPCSS     0x04290
1152  #define IXGBE_MFLCN     0x04294
1153  #define IXGBE_SERDESC   0x04298
1154  #define IXGBE_MAC_SGMII_BUSY 0x04298
1155  #define IXGBE_MACS      0x0429C
1156  #define IXGBE_AUTOC     0x042A0
1157  #define IXGBE_LINKS     0x042A4
1158  #define IXGBE_LINKS2    0x04324
1159  #define IXGBE_AUTOC2    0x042A8
1160  #define IXGBE_AUTOC3    0x042AC
1161  #define IXGBE_ANLP1     0x042B0
1162  #define IXGBE_ANLP2     0x042B4
1163  #define IXGBE_MACC      0x04330
1164  #define IXGBE_ATLASCTL  0x04800
1165  #define IXGBE_MMNGC     0x042D0
1166  #define IXGBE_ANLPNP1   0x042D4
1167  #define IXGBE_ANLPNP2   0x042D8
1168  #define IXGBE_KRPCSFC   0x042E0
1169  #define IXGBE_KRPCSS    0x042E4
1170  #define IXGBE_FECS1     0x042E8
1171  #define IXGBE_FECS2     0x042EC
1172  #define IXGBE_SMADARCTL 0x14F10
1173  #define IXGBE_MPVC      0x04318
1174  #define IXGBE_SGMIIC    0x04314
1175  
1176  /* Statistics Registers */
1177  #define IXGBE_RXNFGPC      0x041B0
1178  #define IXGBE_RXNFGBCL     0x041B4
1179  #define IXGBE_RXNFGBCH     0x041B8
1180  #define IXGBE_RXDGPC       0x02F50
1181  #define IXGBE_RXDGBCL      0x02F54
1182  #define IXGBE_RXDGBCH      0x02F58
1183  #define IXGBE_RXDDGPC      0x02F5C
1184  #define IXGBE_RXDDGBCL     0x02F60
1185  #define IXGBE_RXDDGBCH     0x02F64
1186  #define IXGBE_RXLPBKGPC    0x02F68
1187  #define IXGBE_RXLPBKGBCL   0x02F6C
1188  #define IXGBE_RXLPBKGBCH   0x02F70
1189  #define IXGBE_RXDLPBKGPC   0x02F74
1190  #define IXGBE_RXDLPBKGBCL  0x02F78
1191  #define IXGBE_RXDLPBKGBCH  0x02F7C
1192  #define IXGBE_TXDGPC       0x087A0
1193  #define IXGBE_TXDGBCL      0x087A4
1194  #define IXGBE_TXDGBCH      0x087A8
1195  
1196  #define IXGBE_RXDSTATCTRL 0x02F40
1197  
1198  /* Copper Pond 2 link timeout */
1199  #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1200  
1201  /* Omer CORECTL */
1202  #define IXGBE_CORECTL           0x014F00
1203  /* BARCTRL */
1204  #define IXGBE_BARCTRL               0x110F4
1205  #define IXGBE_BARCTRL_FLSIZE        0x0700
1206  #define IXGBE_BARCTRL_FLSIZE_SHIFT  8
1207  #define IXGBE_BARCTRL_CSRSIZE       0x2000
1208  
1209  /* RSCCTL Bit Masks */
1210  #define IXGBE_RSCCTL_RSCEN          0x01
1211  #define IXGBE_RSCCTL_MAXDESC_1      0x00
1212  #define IXGBE_RSCCTL_MAXDESC_4      0x04
1213  #define IXGBE_RSCCTL_MAXDESC_8      0x08
1214  #define IXGBE_RSCCTL_MAXDESC_16     0x0C
1215  
1216  /* RSCDBU Bit Masks */
1217  #define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
1218  #define IXGBE_RSCDBU_RSCACKDIS          0x00000080
1219  
1220  /* RDRXCTL Bit Masks */
1221  #define IXGBE_RDRXCTL_RDMTS_1_2     0x00000000 /* Rx Desc Min Threshold Size */
1222  #define IXGBE_RDRXCTL_CRCSTRIP      0x00000002 /* CRC Strip */
1223  #define IXGBE_RDRXCTL_PSP           0x00000004 /* Pad small packet */
1224  #define IXGBE_RDRXCTL_MVMEN         0x00000020
1225  #define IXGBE_RDRXCTL_DMAIDONE      0x00000008 /* DMA init cycle done */
1226  #define IXGBE_RDRXCTL_AGGDIS        0x00010000 /* Aggregation disable */
1227  #define IXGBE_RDRXCTL_RSCFRSTSIZE   0x003E0000 /* RSC First packet size */
1228  #define IXGBE_RDRXCTL_RSCLLIDIS     0x00800000 /* Disable RSC compl on LLI */
1229  #define IXGBE_RDRXCTL_RSCACKC       0x02000000 /* must set 1 when RSC enabled */
1230  #define IXGBE_RDRXCTL_FCOE_WRFIX    0x04000000 /* must set 1 when RSC enabled */
1231  #define IXGBE_RDRXCTL_MBINTEN       0x10000000
1232  #define IXGBE_RDRXCTL_MDP_EN        0x20000000
1233  
1234  /* RQTC Bit Masks and Shifts */
1235  #define IXGBE_RQTC_SHIFT_TC(_i)     ((_i) * 4)
1236  #define IXGBE_RQTC_TC0_MASK         (0x7 << 0)
1237  #define IXGBE_RQTC_TC1_MASK         (0x7 << 4)
1238  #define IXGBE_RQTC_TC2_MASK         (0x7 << 8)
1239  #define IXGBE_RQTC_TC3_MASK         (0x7 << 12)
1240  #define IXGBE_RQTC_TC4_MASK         (0x7 << 16)
1241  #define IXGBE_RQTC_TC5_MASK         (0x7 << 20)
1242  #define IXGBE_RQTC_TC6_MASK         (0x7 << 24)
1243  #define IXGBE_RQTC_TC7_MASK         (0x7 << 28)
1244  
1245  /* PSRTYPE.RQPL Bit masks and shift */
1246  #define IXGBE_PSRTYPE_RQPL_MASK     0x7
1247  #define IXGBE_PSRTYPE_RQPL_SHIFT    29
1248  
1249  /* CTRL Bit Masks */
1250  #define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Primary Disable bit */
1251  #define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
1252  #define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
1253  #define IXGBE_CTRL_RST_MASK     (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1254  
1255  /* FACTPS */
1256  #define IXGBE_FACTPS_MNGCG      0x20000000 /* Manageblility Clock Gated */
1257  #define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
1258  
1259  /* MHADD Bit Masks */
1260  #define IXGBE_MHADD_MFS_MASK    0xFFFF0000
1261  #define IXGBE_MHADD_MFS_SHIFT   16
1262  
1263  /* Extended Device Control */
1264  #define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
1265  #define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
1266  #define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
1267  #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1268  
1269  /* Direct Cache Access (DCA) definitions */
1270  #define IXGBE_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
1271  #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
1272  
1273  #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
1274  #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
1275  
1276  #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1277  #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599  0xFF000000 /* Rx CPUID Mask */
1278  #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1279  #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
1280  #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
1281  #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
1282  #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
1283  #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */
1284  #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */
1285  
1286  #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1287  #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599  0xFF000000 /* Tx CPUID Mask */
1288  #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1289  #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
1290  #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
1291  #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */
1292  #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
1293  #define IXGBE_DCA_MAX_QUEUES_82598   16 /* DCA regs only on 16 queues */
1294  
1295  /* MSCA Bit Masks */
1296  #define IXGBE_MSCA_NP_ADDR_MASK      0x0000FFFF /* MDI Address (new protocol) */
1297  #define IXGBE_MSCA_NP_ADDR_SHIFT     0
1298  #define IXGBE_MSCA_DEV_TYPE_MASK     0x001F0000 /* Device Type (new protocol) */
1299  #define IXGBE_MSCA_DEV_TYPE_SHIFT    16 /* Register Address (old protocol */
1300  #define IXGBE_MSCA_PHY_ADDR_MASK     0x03E00000 /* PHY Address mask */
1301  #define IXGBE_MSCA_PHY_ADDR_SHIFT    21 /* PHY Address shift*/
1302  #define IXGBE_MSCA_OP_CODE_MASK      0x0C000000 /* OP CODE mask */
1303  #define IXGBE_MSCA_OP_CODE_SHIFT     26 /* OP CODE shift */
1304  #define IXGBE_MSCA_ADDR_CYCLE        0x00000000 /* OP CODE 00 (addr cycle) */
1305  #define IXGBE_MSCA_WRITE             0x04000000 /* OP CODE 01 (write) */
1306  #define IXGBE_MSCA_READ              0x0C000000 /* OP CODE 11 (read) */
1307  #define IXGBE_MSCA_READ_AUTOINC      0x08000000 /* OP CODE 10 (read, auto inc)*/
1308  #define IXGBE_MSCA_ST_CODE_MASK      0x30000000 /* ST Code mask */
1309  #define IXGBE_MSCA_ST_CODE_SHIFT     28 /* ST Code shift */
1310  #define IXGBE_MSCA_NEW_PROTOCOL      0x00000000 /* ST CODE 00 (new protocol) */
1311  #define IXGBE_MSCA_OLD_PROTOCOL      0x10000000 /* ST CODE 01 (old protocol) */
1312  #define IXGBE_MSCA_MDI_COMMAND       0x40000000 /* Initiate MDI command */
1313  #define IXGBE_MSCA_MDI_IN_PROG_EN    0x80000000 /* MDI in progress enable */
1314  
1315  /* MSRWD bit masks */
1316  #define IXGBE_MSRWD_WRITE_DATA_MASK     0x0000FFFF
1317  #define IXGBE_MSRWD_WRITE_DATA_SHIFT    0
1318  #define IXGBE_MSRWD_READ_DATA_MASK      0xFFFF0000
1319  #define IXGBE_MSRWD_READ_DATA_SHIFT     16
1320  
1321  /* Atlas registers */
1322  #define IXGBE_ATLAS_PDN_LPBK    0x24
1323  #define IXGBE_ATLAS_PDN_10G     0xB
1324  #define IXGBE_ATLAS_PDN_1G      0xC
1325  #define IXGBE_ATLAS_PDN_AN      0xD
1326  
1327  /* Atlas bit masks */
1328  #define IXGBE_ATLASCTL_WRITE_CMD        0x00010000
1329  #define IXGBE_ATLAS_PDN_TX_REG_EN       0x10
1330  #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0
1331  #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0
1332  #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0
1333  
1334  /* Omer bit masks */
1335  #define IXGBE_CORECTL_WRITE_CMD         0x00010000
1336  
1337  /* MDIO definitions */
1338  
1339  #define IXGBE_MDIO_ZERO_DEV_TYPE		0x0
1340  #define IXGBE_MDIO_PCS_DEV_TYPE		0x3
1341  #define IXGBE_TWINAX_DEV			1
1342  
1343  #define IXGBE_MDIO_COMMAND_TIMEOUT     100 /* PHY Timeout for 1 GB mode */
1344  
1345  #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS  0x0008 /* 1 = Link Up */
1346  #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1347  #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED    0x0018
1348  #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED     0x0010
1349  
1350  #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT	0xC800 /* AUTO_NEG Vendor Status Reg */
1351  #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM  0xCC00 /* AUTO_NEG Vendor TX Reg */
1352  #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */
1353  #define IXGBE_MDIO_AUTO_NEG_VEN_LSC	0x1 /* AUTO_NEG Vendor Tx LSC */
1354  #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT	0x3C /* AUTO_NEG EEE Advt Reg */
1355  
1356  #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE	 0x0800 /* Set low power mode */
1357  #define IXGBE_AUTO_NEG_LP_STATUS	0xE820 /* AUTO NEG Rx LP Status Reg */
1358  #define IXGBE_AUTO_NEG_LP_1000BASE_CAP	0x8000 /* AUTO NEG Rx LP 1000BaseT */
1359  #define IXGBE_MDIO_TX_VENDOR_ALARMS_3	0xCC02 /* Vendor Alarms 3 Reg */
1360  #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */
1361  #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
1362  #define IXGBE_MDIO_POWER_UP_STALL	0x8000 /* Power Up Stall */
1363  #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK	0xFF00 /* int std mask */
1364  #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG	0xFC00 /* chip std int flag */
1365  #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK	0xFF01 /* int chip-wide mask */
1366  #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG	0xFC01 /* int chip-wide mask */
1367  #define IXGBE_MDIO_GLOBAL_ALARM_1		0xCC00 /* Global alarm 1 */
1368  #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT	0x0010 /* device fault */
1369  #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL	0x4000 /* high temp failure */
1370  #define IXGBE_MDIO_GLOBAL_FAULT_MSG		0xC850 /* global fault msg */
1371  #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP	0x8007 /* high temp failure */
1372  #define IXGBE_MDIO_GLOBAL_INT_MASK		0xD400 /* Global int mask */
1373  /* autoneg vendor alarm int enable */
1374  #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN	0x1000
1375  #define IXGBE_MDIO_GLOBAL_ALARM_1_INT		0x4 /* int in Global alarm 1 */
1376  #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN	0x1 /* vendor alarm int enable */
1377  #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT		0x200 /* vendor alarm2 int mask */
1378  #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN	0x4000 /* int high temp enable */
1379  #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN	0x0010 /*int dev fault enable */
1380  
1381  #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR	0xC30A /* PHY_XS SDA/SCL Addr Reg */
1382  #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA	0xC30B /* PHY_XS SDA/SCL Data Reg */
1383  #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT	0xC30C /* PHY_XS SDA/SCL Stat Reg */
1384  #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK	0xD401 /* PHY TX Vendor LASI */
1385  #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN	0x1 /* PHY TX Vendor LASI enable */
1386  #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR	0x9 /* Standard Tx Dis Reg */
1387  #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE	0x0001 /* PMD Global Tx Dis */
1388  
1389  /* MII clause 22/28 definitions */
1390  #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1391  #define IXGBE_MII_AUTONEG_XNP_TX_REG             0x17   /* 1G XNP Transmit */
1392  #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX      0x4000 /* full duplex, bit:14*/
1393  #define IXGBE_MII_1GBASE_T_ADVERTISE             0x8000 /* full duplex, bit:15*/
1394  #define IXGBE_MII_AUTONEG_REG                    0x0
1395  
1396  #define IXGBE_PHY_REVISION_MASK        0xFFFFFFF0
1397  #define IXGBE_MAX_PHY_ADDR             32
1398  
1399  /* PHY IDs*/
1400  #define TN1010_PHY_ID    0x00A19410
1401  #define TNX_FW_REV       0xB
1402  #define X540_PHY_ID      0x01540200
1403  #define X550_PHY_ID2	0x01540223
1404  #define X550_PHY_ID3	0x01540221
1405  #define X557_PHY_ID      0x01540240
1406  #define X557_PHY_ID2	0x01540250
1407  #define QT2022_PHY_ID    0x0043A400
1408  #define ATH_PHY_ID       0x03429050
1409  #define AQ_FW_REV        0x20
1410  #define BCM54616S_E_PHY_ID 0x03625D10
1411  
1412  /* Special PHY Init Routine */
1413  #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1414  #define IXGBE_PHY_INIT_END_NL    0xFFFF
1415  #define IXGBE_CONTROL_MASK_NL    0xF000
1416  #define IXGBE_DATA_MASK_NL       0x0FFF
1417  #define IXGBE_CONTROL_SHIFT_NL   12
1418  #define IXGBE_DELAY_NL           0
1419  #define IXGBE_DATA_NL            1
1420  #define IXGBE_CONTROL_NL         0x000F
1421  #define IXGBE_CONTROL_EOL_NL     0x0FFF
1422  #define IXGBE_CONTROL_SOL_NL     0x0000
1423  
1424  /* General purpose Interrupt Enable */
1425  #define IXGBE_SDP0_GPIEN_8259X		0x00000001 /* SDP0 */
1426  #define IXGBE_SDP1_GPIEN_8259X		0x00000002 /* SDP1 */
1427  #define IXGBE_SDP2_GPIEN_8259X		0x00000004 /* SDP2 */
1428  #define IXGBE_SDP0_GPIEN_X540		0x00000002 /* SDP0 on X540 and X550 */
1429  #define IXGBE_SDP1_GPIEN_X540		0x00000004 /* SDP1 on X540 and X550 */
1430  #define IXGBE_SDP2_GPIEN_X540		0x00000008 /* SDP2 on X540 and X550 */
1431  #define IXGBE_SDP0_GPIEN_X550		IXGBE_SDP0_GPIEN_X540
1432  #define IXGBE_SDP1_GPIEN_X550		IXGBE_SDP1_GPIEN_X540
1433  #define IXGBE_SDP2_GPIEN_X550		IXGBE_SDP2_GPIEN_X540
1434  #define IXGBE_SDP0_GPIEN_X550EM_x	IXGBE_SDP0_GPIEN_X540
1435  #define IXGBE_SDP1_GPIEN_X550EM_x	IXGBE_SDP1_GPIEN_X540
1436  #define IXGBE_SDP2_GPIEN_X550EM_x	IXGBE_SDP2_GPIEN_X540
1437  #define IXGBE_SDP0_GPIEN_X550EM_a	IXGBE_SDP0_GPIEN_X540
1438  #define IXGBE_SDP1_GPIEN_X550EM_a	IXGBE_SDP1_GPIEN_X540
1439  #define IXGBE_SDP2_GPIEN_X550EM_a	IXGBE_SDP2_GPIEN_X540
1440  #define IXGBE_SDP0_GPIEN(_hw)		IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1441  #define IXGBE_SDP1_GPIEN(_hw)		IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1442  #define IXGBE_SDP2_GPIEN(_hw)		IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1443  
1444  #define IXGBE_GPIE_MSIX_MODE     0x00000010 /* MSI-X mode */
1445  #define IXGBE_GPIE_OCD           0x00000020 /* Other Clear Disable */
1446  #define IXGBE_GPIE_EIMEN         0x00000040 /* Immediate Interrupt Enable */
1447  #define IXGBE_GPIE_EIAME         0x40000000
1448  #define IXGBE_GPIE_PBA_SUPPORT   0x80000000
1449  #define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1450  #define IXGBE_GPIE_VTMODE_MASK   0x0000C000 /* VT Mode Mask */
1451  #define IXGBE_GPIE_VTMODE_16     0x00004000 /* 16 VFs 8 queues per VF */
1452  #define IXGBE_GPIE_VTMODE_32     0x00008000 /* 32 VFs 4 queues per VF */
1453  #define IXGBE_GPIE_VTMODE_64     0x0000C000 /* 64 VFs 2 queues per VF */
1454  
1455  /* Packet Buffer Initialization */
1456  #define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
1457  #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
1458  #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
1459  #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
1460  #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
1461  #define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
1462  #define IXGBE_RXPBSIZE_MAX      0x00080000 /* 512KB Packet Buffer*/
1463  #define IXGBE_TXPBSIZE_MAX      0x00028000 /* 160KB Packet Buffer*/
1464  
1465  #define IXGBE_TXPKT_SIZE_MAX    0xA        /* Max Tx Packet size  */
1466  #define IXGBE_MAX_PB		8
1467  
1468  /* Packet buffer allocation strategies */
1469  enum {
1470  	PBA_STRATEGY_EQUAL	= 0,	/* Distribute PB space equally */
1471  #define PBA_STRATEGY_EQUAL	PBA_STRATEGY_EQUAL
1472  	PBA_STRATEGY_WEIGHTED	= 1,	/* Weight front half of TCs */
1473  #define PBA_STRATEGY_WEIGHTED	PBA_STRATEGY_WEIGHTED
1474  };
1475  
1476  /* Transmit Flow Control status */
1477  #define IXGBE_TFCS_TXOFF         0x00000001
1478  #define IXGBE_TFCS_TXOFF0        0x00000100
1479  #define IXGBE_TFCS_TXOFF1        0x00000200
1480  #define IXGBE_TFCS_TXOFF2        0x00000400
1481  #define IXGBE_TFCS_TXOFF3        0x00000800
1482  #define IXGBE_TFCS_TXOFF4        0x00001000
1483  #define IXGBE_TFCS_TXOFF5        0x00002000
1484  #define IXGBE_TFCS_TXOFF6        0x00004000
1485  #define IXGBE_TFCS_TXOFF7        0x00008000
1486  
1487  /* TCP Timer */
1488  #define IXGBE_TCPTIMER_KS            0x00000100
1489  #define IXGBE_TCPTIMER_COUNT_ENABLE  0x00000200
1490  #define IXGBE_TCPTIMER_COUNT_FINISH  0x00000400
1491  #define IXGBE_TCPTIMER_LOOP          0x00000800
1492  #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1493  
1494  /* HLREG0 Bit Masks */
1495  #define IXGBE_HLREG0_TXCRCEN      0x00000001   /* bit  0 */
1496  #define IXGBE_HLREG0_RXCRCSTRP    0x00000002   /* bit  1 */
1497  #define IXGBE_HLREG0_JUMBOEN      0x00000004   /* bit  2 */
1498  #define IXGBE_HLREG0_TXPADEN      0x00000400   /* bit 10 */
1499  #define IXGBE_HLREG0_TXPAUSEEN    0x00001000   /* bit 12 */
1500  #define IXGBE_HLREG0_RXPAUSEEN    0x00004000   /* bit 14 */
1501  #define IXGBE_HLREG0_LPBK         0x00008000   /* bit 15 */
1502  #define IXGBE_HLREG0_MDCSPD       0x00010000   /* bit 16 */
1503  #define IXGBE_HLREG0_CONTMDC      0x00020000   /* bit 17 */
1504  #define IXGBE_HLREG0_CTRLFLTR     0x00040000   /* bit 18 */
1505  #define IXGBE_HLREG0_PREPEND      0x00F00000   /* bits 20-23 */
1506  #define IXGBE_HLREG0_PRIPAUSEEN   0x01000000   /* bit 24 */
1507  #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000   /* bits 25-26 */
1508  #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000   /* bit 27 */
1509  #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000   /* bit 28 */
1510  
1511  /* VMD_CTL bitmasks */
1512  #define IXGBE_VMD_CTL_VMDQ_EN     0x00000001
1513  #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1514  
1515  /* VT_CTL bitmasks */
1516  #define IXGBE_VT_CTL_DIS_DEFPL  0x20000000 /* disable default pool */
1517  #define IXGBE_VT_CTL_REPLEN     0x40000000 /* replication enabled */
1518  #define IXGBE_VT_CTL_VT_ENABLE  0x00000001  /* Enable VT Mode */
1519  #define IXGBE_VT_CTL_POOL_SHIFT 7
1520  #define IXGBE_VT_CTL_POOL_MASK  (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1521  
1522  /* VMOLR bitmasks */
1523  #define IXGBE_VMOLR_UPE		0x00400000 /* unicast promiscuous */
1524  #define IXGBE_VMOLR_VPE		0x00800000 /* VLAN promiscuous */
1525  #define IXGBE_VMOLR_AUPE        0x01000000 /* accept untagged packets */
1526  #define IXGBE_VMOLR_ROMPE       0x02000000 /* accept packets in MTA tbl */
1527  #define IXGBE_VMOLR_ROPE        0x04000000 /* accept packets in UC tbl */
1528  #define IXGBE_VMOLR_BAM         0x08000000 /* accept broadcast packets */
1529  #define IXGBE_VMOLR_MPE         0x10000000 /* multicast promiscuous */
1530  
1531  /* VFRE bitmask */
1532  #define IXGBE_VFRE_ENABLE_ALL   0xFFFFFFFF
1533  
1534  #define IXGBE_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
1535  
1536  /* RDHMPN and TDHMPN bitmasks */
1537  #define IXGBE_RDHMPN_RDICADDR       0x007FF800
1538  #define IXGBE_RDHMPN_RDICRDREQ      0x00800000
1539  #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1540  #define IXGBE_TDHMPN_TDICADDR       0x003FF800
1541  #define IXGBE_TDHMPN_TDICRDREQ      0x00800000
1542  #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1543  
1544  #define IXGBE_RDMAM_MEM_SEL_SHIFT   13
1545  #define IXGBE_RDMAM_DWORD_SHIFT     9
1546  #define IXGBE_RDMAM_DESC_COMP_FIFO  1
1547  #define IXGBE_RDMAM_DFC_CMD_FIFO    2
1548  #define IXGBE_RDMAM_TCN_STATUS_RAM  4
1549  #define IXGBE_RDMAM_WB_COLL_FIFO    5
1550  #define IXGBE_RDMAM_QSC_CNT_RAM     6
1551  #define IXGBE_RDMAM_QSC_QUEUE_CNT   8
1552  #define IXGBE_RDMAM_QSC_QUEUE_RAM   0xA
1553  #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE     135
1554  #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT     4
1555  #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE      48
1556  #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT      7
1557  #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE    256
1558  #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT    9
1559  #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE      8
1560  #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT      4
1561  #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE       64
1562  #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT       4
1563  #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE     32
1564  #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT     4
1565  #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE     128
1566  #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT     8
1567  
1568  #define IXGBE_TXDESCIC_READY        0x80000000
1569  
1570  /* Receive Checksum Control */
1571  #define IXGBE_RXCSUM_IPPCSE     0x00001000   /* IP payload checksum enable */
1572  #define IXGBE_RXCSUM_PCSD       0x00002000   /* packet checksum disabled */
1573  
1574  /* FCRTL Bit Masks */
1575  #define IXGBE_FCRTL_XONE        0x80000000  /* XON enable */
1576  #define IXGBE_FCRTH_FCEN        0x80000000  /* Packet buffer fc enable */
1577  
1578  /* PAP bit masks*/
1579  #define IXGBE_PAP_TXPAUSECNT_MASK   0x0000FFFF /* Pause counter mask */
1580  
1581  /* RMCS Bit Masks */
1582  #define IXGBE_RMCS_RRM          0x00000002 /* Receive Recycle Mode enable */
1583  /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1584  #define IXGBE_RMCS_RAC          0x00000004
1585  #define IXGBE_RMCS_DFP          IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
1586  #define IXGBE_RMCS_TFCE_802_3X         0x00000008 /* Tx Priority FC ena */
1587  #define IXGBE_RMCS_TFCE_PRIORITY       0x00000010 /* Tx Priority FC ena */
1588  #define IXGBE_RMCS_ARBDIS       0x00000040 /* Arbitration disable bit */
1589  
1590  /* FCCFG Bit Masks */
1591  #define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
1592  #define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
1593  
1594  /* Interrupt register bitmasks */
1595  
1596  /* Extended Interrupt Cause Read */
1597  #define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
1598  #define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
1599  #define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
1600  #define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
1601  #define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
1602  #define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
1603  #define IXGBE_EICR_LINKSEC      0x00200000 /* PN Threshold */
1604  #define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
1605  #define IXGBE_EICR_TS           0x00800000 /* Thermal Sensor Event */
1606  #define IXGBE_EICR_TIMESYNC     0x01000000 /* Timesync Event */
1607  #define IXGBE_EICR_GPI_SDP0_8259X	0x01000000 /* Gen Purpose INT on SDP0 */
1608  #define IXGBE_EICR_GPI_SDP1_8259X	0x02000000 /* Gen Purpose INT on SDP1 */
1609  #define IXGBE_EICR_GPI_SDP2_8259X	0x04000000 /* Gen Purpose INT on SDP2 */
1610  #define IXGBE_EICR_GPI_SDP0_X540	0x02000000
1611  #define IXGBE_EICR_GPI_SDP1_X540	0x04000000
1612  #define IXGBE_EICR_GPI_SDP2_X540	0x08000000
1613  #define IXGBE_EICR_GPI_SDP0_X550	IXGBE_EICR_GPI_SDP0_X540
1614  #define IXGBE_EICR_GPI_SDP1_X550	IXGBE_EICR_GPI_SDP1_X540
1615  #define IXGBE_EICR_GPI_SDP2_X550	IXGBE_EICR_GPI_SDP2_X540
1616  #define IXGBE_EICR_GPI_SDP0_X550EM_x	IXGBE_EICR_GPI_SDP0_X540
1617  #define IXGBE_EICR_GPI_SDP1_X550EM_x	IXGBE_EICR_GPI_SDP1_X540
1618  #define IXGBE_EICR_GPI_SDP2_X550EM_x	IXGBE_EICR_GPI_SDP2_X540
1619  #define IXGBE_EICR_GPI_SDP0_X550EM_a	IXGBE_EICR_GPI_SDP0_X540
1620  #define IXGBE_EICR_GPI_SDP1_X550EM_a	IXGBE_EICR_GPI_SDP1_X540
1621  #define IXGBE_EICR_GPI_SDP2_X550EM_a	IXGBE_EICR_GPI_SDP2_X540
1622  #define IXGBE_EICR_GPI_SDP0(_hw)	IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1623  #define IXGBE_EICR_GPI_SDP1(_hw)	IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1624  #define IXGBE_EICR_GPI_SDP2(_hw)	IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1625  
1626  #define IXGBE_EICR_ECC          0x10000000 /* ECC Error */
1627  #define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
1628  #define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
1629  #define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
1630  #define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
1631  
1632  /* Extended Interrupt Cause Set */
1633  #define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1634  #define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1635  #define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
1636  #define IXGBE_EICS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1637  #define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1638  #define IXGBE_EICS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1639  #define IXGBE_EICS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1640  #define IXGBE_EICS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1641  #define IXGBE_EICS_GPI_SDP0(_hw)	IXGBE_EICR_GPI_SDP0(_hw)
1642  #define IXGBE_EICS_GPI_SDP1(_hw)	IXGBE_EICR_GPI_SDP1(_hw)
1643  #define IXGBE_EICS_GPI_SDP2(_hw)	IXGBE_EICR_GPI_SDP2(_hw)
1644  #define IXGBE_EICS_ECC          IXGBE_EICR_ECC       /* ECC Error */
1645  #define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1646  #define IXGBE_EICS_DHER         IXGBE_EICR_DHER      /* Desc Handler Error */
1647  #define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1648  #define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1649  
1650  /* Extended Interrupt Mask Set */
1651  #define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1652  #define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1653  #define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
1654  #define IXGBE_EIMS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1655  #define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1656  #define IXGBE_EIMS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1657  #define IXGBE_EIMS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1658  #define IXGBE_EIMS_TS           IXGBE_EICR_TS        /* Thermel Sensor Event */
1659  #define IXGBE_EIMS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1660  #define IXGBE_EIMS_GPI_SDP0(_hw)	IXGBE_EICR_GPI_SDP0(_hw)
1661  #define IXGBE_EIMS_GPI_SDP1(_hw)	IXGBE_EICR_GPI_SDP1(_hw)
1662  #define IXGBE_EIMS_GPI_SDP2(_hw)	IXGBE_EICR_GPI_SDP2(_hw)
1663  #define IXGBE_EIMS_ECC          IXGBE_EICR_ECC       /* ECC Error */
1664  #define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1665  #define IXGBE_EIMS_DHER         IXGBE_EICR_DHER      /* Descr Handler Error */
1666  #define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1667  #define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1668  
1669  /* Extended Interrupt Mask Clear */
1670  #define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1671  #define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1672  #define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
1673  #define IXGBE_EIMC_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1674  #define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1675  #define IXGBE_EIMC_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1676  #define IXGBE_EIMC_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1677  #define IXGBE_EIMC_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1678  #define IXGBE_EIMC_GPI_SDP0(_hw)	IXGBE_EICR_GPI_SDP0(_hw)
1679  #define IXGBE_EIMC_GPI_SDP1(_hw)	IXGBE_EICR_GPI_SDP1(_hw)
1680  #define IXGBE_EIMC_GPI_SDP2(_hw)	IXGBE_EICR_GPI_SDP2(_hw)
1681  #define IXGBE_EIMC_ECC          IXGBE_EICR_ECC       /* ECC Error */
1682  #define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1683  #define IXGBE_EIMC_DHER         IXGBE_EICR_DHER      /* Desc Handler Err */
1684  #define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1685  #define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1686  
1687  #define IXGBE_EIMS_ENABLE_MASK ( \
1688  				IXGBE_EIMS_RTX_QUEUE       | \
1689  				IXGBE_EIMS_LSC             | \
1690  				IXGBE_EIMS_TCP_TIMER       | \
1691  				IXGBE_EIMS_OTHER)
1692  
1693  /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1694  #define IXGBE_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
1695  #define IXGBE_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
1696  #define IXGBE_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
1697  #define IXGBE_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
1698  #define IXGBE_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
1699  #define IXGBE_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
1700  #define IXGBE_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
1701  #define IXGBE_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
1702  #define IXGBE_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
1703  #define IXGBE_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of control bits */
1704  #define IXGBE_IMIR_SIZE_BP_82599  0x00001000 /* Packet size bypass */
1705  #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1706  #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1707  #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1708  #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1709  #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1710  #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1711  #define IXGBE_IMIR_CTRL_BP_82599  0x00080000 /* Bypass check of control bits */
1712  #define IXGBE_IMIR_LLI_EN_82599   0x00100000 /* Enables low latency Int */
1713  #define IXGBE_IMIR_RX_QUEUE_MASK_82599  0x0000007F /* Rx Queue Mask */
1714  #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1715  #define IXGBE_IMIRVP_PRIORITY_MASK      0x00000007 /* VLAN priority mask */
1716  #define IXGBE_IMIRVP_PRIORITY_EN        0x00000008 /* VLAN priority enable */
1717  
1718  #define IXGBE_MAX_FTQF_FILTERS          128
1719  #define IXGBE_FTQF_PROTOCOL_MASK        0x00000003
1720  #define IXGBE_FTQF_PROTOCOL_TCP         0x00000000
1721  #define IXGBE_FTQF_PROTOCOL_UDP         0x00000001
1722  #define IXGBE_FTQF_PROTOCOL_SCTP        2
1723  #define IXGBE_FTQF_PRIORITY_MASK        0x00000007
1724  #define IXGBE_FTQF_PRIORITY_SHIFT       2
1725  #define IXGBE_FTQF_POOL_MASK            0x0000003F
1726  #define IXGBE_FTQF_POOL_SHIFT           8
1727  #define IXGBE_FTQF_5TUPLE_MASK_MASK     0x0000001F
1728  #define IXGBE_FTQF_5TUPLE_MASK_SHIFT    25
1729  #define IXGBE_FTQF_SOURCE_ADDR_MASK     0x1E
1730  #define IXGBE_FTQF_DEST_ADDR_MASK       0x1D
1731  #define IXGBE_FTQF_SOURCE_PORT_MASK     0x1B
1732  #define IXGBE_FTQF_DEST_PORT_MASK       0x17
1733  #define IXGBE_FTQF_PROTOCOL_COMP_MASK   0x0F
1734  #define IXGBE_FTQF_POOL_MASK_EN         0x40000000
1735  #define IXGBE_FTQF_QUEUE_ENABLE         0x80000000
1736  
1737  /* Interrupt clear mask */
1738  #define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF
1739  
1740  /* Interrupt Vector Allocation Registers */
1741  #define IXGBE_IVAR_REG_NUM      25
1742  #define IXGBE_IVAR_REG_NUM_82599       64
1743  #define IXGBE_IVAR_TXRX_ENTRY   96
1744  #define IXGBE_IVAR_RX_ENTRY     64
1745  #define IXGBE_IVAR_RX_QUEUE(_i)    (0 + (_i))
1746  #define IXGBE_IVAR_TX_QUEUE(_i)    (64 + (_i))
1747  #define IXGBE_IVAR_TX_ENTRY     32
1748  
1749  #define IXGBE_IVAR_TCP_TIMER_INDEX       96 /* 0 based index */
1750  #define IXGBE_IVAR_OTHER_CAUSES_INDEX    97 /* 0 based index */
1751  
1752  #define IXGBE_MSIX_VECTOR(_i)   (0 + (_i))
1753  
1754  #define IXGBE_IVAR_ALLOC_VAL    0x80 /* Interrupt Allocation valid */
1755  
1756  /* ETYPE Queue Filter/Select Bit Masks */
1757  #define IXGBE_MAX_ETQF_FILTERS  8
1758  #define IXGBE_ETQF_FCOE         0x08000000 /* bit 27 */
1759  #define IXGBE_ETQF_BCN          0x10000000 /* bit 28 */
1760  #define IXGBE_ETQF_TX_ANTISPOOF	0x20000000 /* bit 29 */
1761  #define IXGBE_ETQF_1588         0x40000000 /* bit 30 */
1762  #define IXGBE_ETQF_FILTER_EN    0x80000000 /* bit 31 */
1763  #define IXGBE_ETQF_POOL_ENABLE   BIT(26) /* bit 26 */
1764  #define IXGBE_ETQF_POOL_SHIFT		20
1765  
1766  #define IXGBE_ETQS_RX_QUEUE     0x007F0000 /* bits 22:16 */
1767  #define IXGBE_ETQS_RX_QUEUE_SHIFT       16
1768  #define IXGBE_ETQS_LLI          0x20000000 /* bit 29 */
1769  #define IXGBE_ETQS_QUEUE_EN     0x80000000 /* bit 31 */
1770  
1771  /*
1772   * ETQF filter list: one static filter per filter consumer. This is
1773   *                   to avoid filter collisions later. Add new filters
1774   *                   here!!
1775   *
1776   * Current filters:
1777   *    EAPOL 802.1x (0x888e): Filter 0
1778   *    FCoE (0x8906):         Filter 2
1779   *    1588 (0x88f7):         Filter 3
1780   *    FIP  (0x8914):         Filter 4
1781   *    LLDP (0x88CC):         Filter 5
1782   *    LACP (0x8809):         Filter 6
1783   *    FC   (0x8808):         Filter 7
1784   */
1785  #define IXGBE_ETQF_FILTER_EAPOL          0
1786  #define IXGBE_ETQF_FILTER_FCOE           2
1787  #define IXGBE_ETQF_FILTER_1588           3
1788  #define IXGBE_ETQF_FILTER_FIP            4
1789  #define IXGBE_ETQF_FILTER_LLDP		 5
1790  #define IXGBE_ETQF_FILTER_LACP		 6
1791  #define IXGBE_ETQF_FILTER_FC		 7
1792  
1793  /* VLAN Control Bit Masks */
1794  #define IXGBE_VLNCTRL_VET       0x0000FFFF  /* bits 0-15 */
1795  #define IXGBE_VLNCTRL_CFI       0x10000000  /* bit 28 */
1796  #define IXGBE_VLNCTRL_CFIEN     0x20000000  /* bit 29 */
1797  #define IXGBE_VLNCTRL_VFE       0x40000000  /* bit 30 */
1798  #define IXGBE_VLNCTRL_VME       0x80000000  /* bit 31 */
1799  
1800  /* VLAN pool filtering masks */
1801  #define IXGBE_VLVF_VIEN         0x80000000  /* filter is valid */
1802  #define IXGBE_VLVF_ENTRIES      64
1803  #define IXGBE_VLVF_VLANID_MASK  0x00000FFF
1804  
1805  /* Per VF Port VLAN insertion rules */
1806  #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1807  #define IXGBE_VMVIR_VLANA_NEVER   0x80000000 /* Never insert VLAN tag */
1808  
1809  #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.1q protocol */
1810  
1811  /* STATUS Bit Masks */
1812  #define IXGBE_STATUS_LAN_ID         0x0000000C /* LAN ID */
1813  #define IXGBE_STATUS_LAN_ID_SHIFT   2          /* LAN ID Shift*/
1814  #define IXGBE_STATUS_GIO            0x00080000 /* GIO Primary Enable Status */
1815  
1816  #define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
1817  #define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
1818  
1819  /* ESDP Bit Masks */
1820  #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1821  #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1822  #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1823  #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1824  #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1825  #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1826  #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1827  #define IXGBE_ESDP_SDP0_DIR     0x00000100 /* SDP0 IO direction */
1828  #define IXGBE_ESDP_SDP1_DIR     0x00000200 /* SDP1 IO direction */
1829  #define IXGBE_ESDP_SDP4_DIR     0x00000004 /* SDP4 IO direction */
1830  #define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
1831  #define IXGBE_ESDP_SDP0_NATIVE  0x00010000 /* SDP0 Native Function */
1832  #define IXGBE_ESDP_SDP1_NATIVE  0x00020000 /* SDP1 IO mode */
1833  
1834  /* LEDCTL Bit Masks */
1835  #define IXGBE_LED_IVRT_BASE      0x00000040
1836  #define IXGBE_LED_BLINK_BASE     0x00000080
1837  #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1838  #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1839  #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))
1840  #define IXGBE_LED_IVRT(_i)       IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1841  #define IXGBE_LED_BLINK(_i)      IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1842  #define IXGBE_LED_MODE_MASK(_i)  IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1843  #define IXGBE_X557_LED_MANUAL_SET_MASK	BIT(8)
1844  #define IXGBE_X557_MAX_LED_INDEX	3
1845  #define IXGBE_X557_LED_PROVISIONING	0xC430
1846  
1847  /* LED modes */
1848  #define IXGBE_LED_LINK_UP       0x0
1849  #define IXGBE_LED_LINK_10G      0x1
1850  #define IXGBE_LED_MAC           0x2
1851  #define IXGBE_LED_FILTER        0x3
1852  #define IXGBE_LED_LINK_ACTIVE   0x4
1853  #define IXGBE_LED_LINK_1G       0x5
1854  #define IXGBE_LED_ON            0xE
1855  #define IXGBE_LED_OFF           0xF
1856  
1857  /* AUTOC Bit Masks */
1858  #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1859  #define IXGBE_AUTOC_KX4_SUPP    0x80000000
1860  #define IXGBE_AUTOC_KX_SUPP     0x40000000
1861  #define IXGBE_AUTOC_PAUSE       0x30000000
1862  #define IXGBE_AUTOC_ASM_PAUSE   0x20000000
1863  #define IXGBE_AUTOC_SYM_PAUSE   0x10000000
1864  #define IXGBE_AUTOC_RF          0x08000000
1865  #define IXGBE_AUTOC_PD_TMR      0x06000000
1866  #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1867  #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1868  #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1869  #define IXGBE_AUTOC_FECA        0x00040000
1870  #define IXGBE_AUTOC_FECR        0x00020000
1871  #define IXGBE_AUTOC_KR_SUPP     0x00010000
1872  #define IXGBE_AUTOC_AN_RESTART  0x00001000
1873  #define IXGBE_AUTOC_FLU         0x00000001
1874  #define IXGBE_AUTOC_LMS_SHIFT   13
1875  #define IXGBE_AUTOC_LMS_10G_SERIAL      (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1876  #define IXGBE_AUTOC_LMS_KX4_KX_KR       (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1877  #define IXGBE_AUTOC_LMS_SGMII_1G_100M   (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1878  #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1879  #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1880  #define IXGBE_AUTOC_LMS_MASK            (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1881  #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN   (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1882  #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN  (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1883  #define IXGBE_AUTOC_LMS_1G_AN           (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1884  #define IXGBE_AUTOC_LMS_KX4_AN          (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1885  #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN    (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1886  #define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1887  
1888  #define IXGBE_AUTOC_1G_PMA_PMD_MASK    0x00000200
1889  #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT   9
1890  #define IXGBE_AUTOC_10G_PMA_PMD_MASK   0x00000180
1891  #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT  7
1892  #define IXGBE_AUTOC_10G_XAUI   (0u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1893  #define IXGBE_AUTOC_10G_KX4    (1u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1894  #define IXGBE_AUTOC_10G_CX4    (2u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1895  #define IXGBE_AUTOC_1G_BX      (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1896  #define IXGBE_AUTOC_1G_KX      (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1897  #define IXGBE_AUTOC_1G_SFI     (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1898  #define IXGBE_AUTOC_1G_KX_BX   (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1899  
1900  #define IXGBE_AUTOC2_UPPER_MASK  0xFFFF0000
1901  #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK  0x00030000
1902  #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1903  #define IXGBE_AUTOC2_10G_KR  (0u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1904  #define IXGBE_AUTOC2_10G_XFI (1u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1905  #define IXGBE_AUTOC2_10G_SFI (2u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1906  #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK  0x50000000
1907  #define IXGBE_AUTOC2_LINK_DISABLE_MASK        0x70000000
1908  
1909  #define IXGBE_MACC_FLU       0x00000001
1910  #define IXGBE_MACC_FSV_10G   0x00030000
1911  #define IXGBE_MACC_FS        0x00040000
1912  #define IXGBE_MAC_RX2TX_LPBK 0x00000002
1913  
1914  /* Veto Bit definition */
1915  #define IXGBE_MMNGC_MNG_VETO  0x00000001
1916  
1917  /* LINKS Bit Masks */
1918  #define IXGBE_LINKS_KX_AN_COMP  0x80000000
1919  #define IXGBE_LINKS_UP          0x40000000
1920  #define IXGBE_LINKS_SPEED       0x20000000
1921  #define IXGBE_LINKS_MODE        0x18000000
1922  #define IXGBE_LINKS_RX_MODE     0x06000000
1923  #define IXGBE_LINKS_TX_MODE     0x01800000
1924  #define IXGBE_LINKS_XGXS_EN     0x00400000
1925  #define IXGBE_LINKS_SGMII_EN    0x02000000
1926  #define IXGBE_LINKS_PCS_1G_EN   0x00200000
1927  #define IXGBE_LINKS_1G_AN_EN    0x00100000
1928  #define IXGBE_LINKS_KX_AN_IDLE  0x00080000
1929  #define IXGBE_LINKS_1G_SYNC     0x00040000
1930  #define IXGBE_LINKS_10G_ALIGN   0x00020000
1931  #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1932  #define IXGBE_LINKS_TL_FAULT    0x00001000
1933  #define IXGBE_LINKS_SIGNAL      0x00000F00
1934  
1935  #define IXGBE_LINKS_SPEED_NON_STD   0x08000000
1936  #define IXGBE_LINKS_SPEED_82599     0x30000000
1937  #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1938  #define IXGBE_LINKS_SPEED_1G_82599  0x20000000
1939  #define IXGBE_LINKS_SPEED_100_82599 0x10000000
1940  #define IXGBE_LINKS_SPEED_10_X550EM_A 0
1941  #define IXGBE_LINK_UP_TIME      90 /* 9.0 Seconds */
1942  #define IXGBE_AUTO_NEG_TIME     45 /* 4.5 Seconds */
1943  
1944  #define IXGBE_LINKS2_AN_SUPPORTED   0x00000040
1945  
1946  /* PCS1GLSTA Bit Masks */
1947  #define IXGBE_PCS1GLSTA_LINK_OK         1
1948  #define IXGBE_PCS1GLSTA_SYNK_OK         0x10
1949  #define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
1950  #define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
1951  #define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
1952  #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1953  #define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
1954  
1955  #define IXGBE_PCS1GANA_SYM_PAUSE        0x80
1956  #define IXGBE_PCS1GANA_ASM_PAUSE        0x100
1957  
1958  /* PCS1GLCTL Bit Masks */
1959  #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN  0x00040000 /* PCS 1G autoneg to en */
1960  #define IXGBE_PCS1GLCTL_FLV_LINK_UP     1
1961  #define IXGBE_PCS1GLCTL_FORCE_LINK      0x20
1962  #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH  0x40
1963  #define IXGBE_PCS1GLCTL_AN_ENABLE       0x10000
1964  #define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
1965  
1966  /* ANLP1 Bit Masks */
1967  #define IXGBE_ANLP1_PAUSE               0x0C00
1968  #define IXGBE_ANLP1_SYM_PAUSE           0x0400
1969  #define IXGBE_ANLP1_ASM_PAUSE           0x0800
1970  #define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
1971  
1972  /* SW Semaphore Register bitmasks */
1973  #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1974  #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1975  #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1976  #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1977  
1978  /* SW_FW_SYNC/GSSR definitions */
1979  #define IXGBE_GSSR_EEP_SM		0x0001
1980  #define IXGBE_GSSR_PHY0_SM		0x0002
1981  #define IXGBE_GSSR_PHY1_SM		0x0004
1982  #define IXGBE_GSSR_MAC_CSR_SM		0x0008
1983  #define IXGBE_GSSR_FLASH_SM		0x0010
1984  #define IXGBE_GSSR_NVM_UPDATE_SM	0x0200
1985  #define IXGBE_GSSR_SW_MNG_SM		0x0400
1986  #define IXGBE_GSSR_TOKEN_SM	0x40000000 /* SW bit for shared access */
1987  #define IXGBE_GSSR_SHARED_I2C_SM	0x1806 /* Wait for both phys & I2Cs */
1988  #define IXGBE_GSSR_I2C_MASK		0x1800
1989  #define IXGBE_GSSR_NVM_PHY_MASK		0xF
1990  
1991  /* FW Status register bitmask */
1992  #define IXGBE_FWSTS_FWRI    0x00000200 /* Firmware Reset Indication */
1993  
1994  /* EEC Register */
1995  #define IXGBE_EEC_SK        0x00000001 /* EEPROM Clock */
1996  #define IXGBE_EEC_CS        0x00000002 /* EEPROM Chip Select */
1997  #define IXGBE_EEC_DI        0x00000004 /* EEPROM Data In */
1998  #define IXGBE_EEC_DO        0x00000008 /* EEPROM Data Out */
1999  #define IXGBE_EEC_FWE_MASK  0x00000030 /* FLASH Write Enable */
2000  #define IXGBE_EEC_FWE_DIS   0x00000010 /* Disable FLASH writes */
2001  #define IXGBE_EEC_FWE_EN    0x00000020 /* Enable FLASH writes */
2002  #define IXGBE_EEC_FWE_SHIFT 4
2003  #define IXGBE_EEC_REQ       0x00000040 /* EEPROM Access Request */
2004  #define IXGBE_EEC_GNT       0x00000080 /* EEPROM Access Grant */
2005  #define IXGBE_EEC_PRES      0x00000100 /* EEPROM Present */
2006  #define IXGBE_EEC_ARD       0x00000200 /* EEPROM Auto Read Done */
2007  #define IXGBE_EEC_FLUP      0x00800000 /* Flash update command */
2008  #define IXGBE_EEC_SEC1VAL   0x02000000 /* Sector 1 Valid */
2009  #define IXGBE_EEC_FLUDONE   0x04000000 /* Flash update done */
2010  /* EEPROM Addressing bits based on type (0-small, 1-large) */
2011  #define IXGBE_EEC_ADDR_SIZE 0x00000400
2012  #define IXGBE_EEC_SIZE      0x00007800 /* EEPROM Size */
2013  #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
2014  
2015  #define IXGBE_EEC_SIZE_SHIFT          11
2016  #define IXGBE_EEPROM_WORD_SIZE_SHIFT  6
2017  #define IXGBE_EEPROM_OPCODE_BITS      8
2018  
2019  /* Part Number String Length */
2020  #define IXGBE_PBANUM_LENGTH 11
2021  
2022  /* Checksum and EEPROM pointers */
2023  #define IXGBE_PBANUM_PTR_GUARD		0xFAFA
2024  #define IXGBE_EEPROM_CHECKSUM		0x3F
2025  #define IXGBE_EEPROM_SUM		0xBABA
2026  #define IXGBE_EEPROM_CTRL_4		0x45
2027  #define IXGBE_EE_CTRL_4_INST_ID		0x10
2028  #define IXGBE_EE_CTRL_4_INST_ID_SHIFT	4
2029  #define IXGBE_PCIE_ANALOG_PTR		0x03
2030  #define IXGBE_ATLAS0_CONFIG_PTR		0x04
2031  #define IXGBE_PHY_PTR			0x04
2032  #define IXGBE_ATLAS1_CONFIG_PTR		0x05
2033  #define IXGBE_OPTION_ROM_PTR		0x05
2034  #define IXGBE_PCIE_GENERAL_PTR		0x06
2035  #define IXGBE_PCIE_CONFIG0_PTR		0x07
2036  #define IXGBE_PCIE_CONFIG1_PTR		0x08
2037  #define IXGBE_CORE0_PTR			0x09
2038  #define IXGBE_CORE1_PTR			0x0A
2039  #define IXGBE_MAC0_PTR			0x0B
2040  #define IXGBE_MAC1_PTR			0x0C
2041  #define IXGBE_CSR0_CONFIG_PTR		0x0D
2042  #define IXGBE_CSR1_CONFIG_PTR		0x0E
2043  #define IXGBE_PCIE_ANALOG_PTR_X550	0x02
2044  #define IXGBE_SHADOW_RAM_SIZE_X550	0x4000
2045  #define IXGBE_IXGBE_PCIE_GENERAL_SIZE	0x24
2046  #define IXGBE_PCIE_CONFIG_SIZE		0x08
2047  #define IXGBE_EEPROM_LAST_WORD		0x41
2048  #define IXGBE_FW_PTR			0x0F
2049  #define IXGBE_PBANUM0_PTR		0x15
2050  #define IXGBE_PBANUM1_PTR		0x16
2051  #define IXGBE_FREE_SPACE_PTR		0X3E
2052  
2053  /* External Thermal Sensor Config */
2054  #define IXGBE_ETS_CFG                   0x26
2055  #define IXGBE_ETS_LTHRES_DELTA_MASK     0x07C0
2056  #define IXGBE_ETS_LTHRES_DELTA_SHIFT    6
2057  #define IXGBE_ETS_TYPE_MASK             0x0038
2058  #define IXGBE_ETS_TYPE_SHIFT            3
2059  #define IXGBE_ETS_TYPE_EMC              0x000
2060  #define IXGBE_ETS_TYPE_EMC_SHIFTED      0x000
2061  #define IXGBE_ETS_NUM_SENSORS_MASK      0x0007
2062  #define IXGBE_ETS_DATA_LOC_MASK         0x3C00
2063  #define IXGBE_ETS_DATA_LOC_SHIFT        10
2064  #define IXGBE_ETS_DATA_INDEX_MASK       0x0300
2065  #define IXGBE_ETS_DATA_INDEX_SHIFT      8
2066  #define IXGBE_ETS_DATA_HTHRESH_MASK     0x00FF
2067  
2068  #define IXGBE_SAN_MAC_ADDR_PTR  0x28
2069  #define IXGBE_DEVICE_CAPS       0x2C
2070  #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
2071  #define IXGBE_PCIE_MSIX_82599_CAPS  0x72
2072  #define IXGBE_MAX_MSIX_VECTORS_82599	0x40
2073  #define IXGBE_PCIE_MSIX_82598_CAPS  0x62
2074  #define IXGBE_MAX_MSIX_VECTORS_82598	0x13
2075  
2076  /* MSI-X capability fields masks */
2077  #define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
2078  
2079  /* Legacy EEPROM word offsets */
2080  #define IXGBE_ISCSI_BOOT_CAPS           0x0033
2081  #define IXGBE_ISCSI_SETUP_PORT_0        0x0030
2082  #define IXGBE_ISCSI_SETUP_PORT_1        0x0034
2083  
2084  /* EEPROM Commands - SPI */
2085  #define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */
2086  #define IXGBE_EEPROM_STATUS_RDY_SPI     0x01
2087  #define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
2088  #define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
2089  #define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
2090  #define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
2091  /* EEPROM reset Write Enable latch */
2092  #define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
2093  #define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
2094  #define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
2095  #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
2096  #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */
2097  #define IXGBE_EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B */
2098  
2099  /* EEPROM Read Register */
2100  #define IXGBE_EEPROM_RW_REG_DATA   16 /* data offset in EEPROM read reg */
2101  #define IXGBE_EEPROM_RW_REG_DONE   2  /* Offset to READ done bit */
2102  #define IXGBE_EEPROM_RW_REG_START  1  /* First bit to start operation */
2103  #define IXGBE_EEPROM_RW_ADDR_SHIFT 2  /* Shift to the address bits */
2104  #define IXGBE_NVM_POLL_WRITE       1  /* Flag for polling for write complete */
2105  #define IXGBE_NVM_POLL_READ        0  /* Flag for polling for read complete */
2106  
2107  #define NVM_INIT_CTRL_3			0x38
2108  #define NVM_INIT_CTRL_3_LPLU		0x8
2109  #define NVM_INIT_CTRL_3_D10GMP_PORT0	0x40
2110  #define NVM_INIT_CTRL_3_D10GMP_PORT1	0x100
2111  
2112  #define IXGBE_EEPROM_PAGE_SIZE_MAX       128
2113  #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
2114  #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
2115  
2116  #define IXGBE_EEPROM_CTRL_2	1 /* EEPROM CTRL word 2 */
2117  #define IXGBE_EEPROM_CCD_BIT	2 /* EEPROM Core Clock Disable bit */
2118  
2119  #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
2120  #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
2121  #endif
2122  
2123  #ifndef IXGBE_EERD_EEWR_ATTEMPTS
2124  /* Number of 5 microseconds we wait for EERD read and
2125   * EERW write to complete */
2126  #define IXGBE_EERD_EEWR_ATTEMPTS 100000
2127  #endif
2128  
2129  #ifndef IXGBE_FLUDONE_ATTEMPTS
2130  /* # attempts we wait for flush update to complete */
2131  #define IXGBE_FLUDONE_ATTEMPTS 20000
2132  #endif
2133  
2134  #define IXGBE_PCIE_CTRL2                 0x5   /* PCIe Control 2 Offset */
2135  #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE    0x8   /* Dummy Function Enable */
2136  #define IXGBE_PCIE_CTRL2_LAN_DISABLE     0x2   /* LAN PCI Disable */
2137  #define IXGBE_PCIE_CTRL2_DISABLE_SELECT  0x1   /* LAN Disable Select */
2138  
2139  #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET  0x0
2140  #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET  0x3
2141  #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP  0x1
2142  #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS  0x2
2143  #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR	BIT(7)
2144  #define IXGBE_FW_LESM_PARAMETERS_PTR     0x2
2145  #define IXGBE_FW_LESM_STATE_1            0x1
2146  #define IXGBE_FW_LESM_STATE_ENABLED      0x8000 /* LESM Enable bit */
2147  #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
2148  #define IXGBE_FW_PATCH_VERSION_4         0x7
2149  #define IXGBE_FCOE_IBA_CAPS_BLK_PTR         0x33 /* iSCSI/FCOE block */
2150  #define IXGBE_FCOE_IBA_CAPS_FCOE            0x20 /* FCOE flags */
2151  #define IXGBE_ISCSI_FCOE_BLK_PTR            0x17 /* iSCSI/FCOE block */
2152  #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET       0x0  /* FCOE flags */
2153  #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE       0x1  /* FCOE flags enable bit */
2154  #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR      0x27 /* Alt. SAN MAC block */
2155  #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET  0x0 /* Alt. SAN MAC capability */
2156  #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
2157  #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
2158  #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET  0x7 /* Alt. WWNN prefix offset */
2159  #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET  0x8 /* Alt. WWPN prefix offset */
2160  #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC  0x0 /* Alt. SAN MAC exists */
2161  #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN  0x1 /* Alt. WWN base exists */
2162  
2163  #define IXGBE_DEVICE_CAPS_WOL_PORT0_1  0x4 /* WoL supported on ports 0 & 1 */
2164  #define IXGBE_DEVICE_CAPS_WOL_PORT0    0x8 /* WoL supported on port 0 */
2165  #define IXGBE_DEVICE_CAPS_WOL_MASK     0xC /* Mask for WoL capabilities */
2166  
2167  /* PCI Bus Info */
2168  #define IXGBE_PCI_DEVICE_STATUS   0xAA
2169  #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING   0x0020
2170  #define IXGBE_PCI_LINK_STATUS     0xB2
2171  #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
2172  #define IXGBE_PCI_LINK_WIDTH      0x3F0
2173  #define IXGBE_PCI_LINK_WIDTH_1    0x10
2174  #define IXGBE_PCI_LINK_WIDTH_2    0x20
2175  #define IXGBE_PCI_LINK_WIDTH_4    0x40
2176  #define IXGBE_PCI_LINK_WIDTH_8    0x80
2177  #define IXGBE_PCI_LINK_SPEED      0xF
2178  #define IXGBE_PCI_LINK_SPEED_2500 0x1
2179  #define IXGBE_PCI_LINK_SPEED_5000 0x2
2180  #define IXGBE_PCI_LINK_SPEED_8000 0x3
2181  #define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
2182  #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
2183  #define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
2184  
2185  #define IXGBE_PCIDEVCTRL2_TIMEO_MASK	0xf
2186  #define IXGBE_PCIDEVCTRL2_16_32ms_def	0x0
2187  #define IXGBE_PCIDEVCTRL2_50_100us	0x1
2188  #define IXGBE_PCIDEVCTRL2_1_2ms		0x2
2189  #define IXGBE_PCIDEVCTRL2_16_32ms	0x5
2190  #define IXGBE_PCIDEVCTRL2_65_130ms	0x6
2191  #define IXGBE_PCIDEVCTRL2_260_520ms	0x9
2192  #define IXGBE_PCIDEVCTRL2_1_2s		0xa
2193  #define IXGBE_PCIDEVCTRL2_4_8s		0xd
2194  #define IXGBE_PCIDEVCTRL2_17_34s	0xe
2195  
2196  /* Number of 100 microseconds we wait for PCI Express primary disable */
2197  #define IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT	800
2198  
2199  /* RAH */
2200  #define IXGBE_RAH_VIND_MASK     0x003C0000
2201  #define IXGBE_RAH_VIND_SHIFT    18
2202  #define IXGBE_RAH_AV            0x80000000
2203  #define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
2204  
2205  /* Header split receive */
2206  #define IXGBE_RFCTL_ISCSI_DIS       0x00000001
2207  #define IXGBE_RFCTL_ISCSI_DWC_MASK  0x0000003E
2208  #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
2209  #define IXGBE_RFCTL_RSC_DIS		0x00000020
2210  #define IXGBE_RFCTL_NFSW_DIS        0x00000040
2211  #define IXGBE_RFCTL_NFSR_DIS        0x00000080
2212  #define IXGBE_RFCTL_NFS_VER_MASK    0x00000300
2213  #define IXGBE_RFCTL_NFS_VER_SHIFT   8
2214  #define IXGBE_RFCTL_NFS_VER_2       0
2215  #define IXGBE_RFCTL_NFS_VER_3       1
2216  #define IXGBE_RFCTL_NFS_VER_4       2
2217  #define IXGBE_RFCTL_IPV6_DIS        0x00000400
2218  #define IXGBE_RFCTL_IPV6_XSUM_DIS   0x00000800
2219  #define IXGBE_RFCTL_IPFRSP_DIS      0x00004000
2220  #define IXGBE_RFCTL_IPV6_EX_DIS     0x00010000
2221  #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
2222  
2223  /* Transmit Config masks */
2224  #define IXGBE_TXDCTL_ENABLE     0x02000000 /* Enable specific Tx Queue */
2225  #define IXGBE_TXDCTL_SWFLSH     0x04000000 /* Tx Desc. write-back flushing */
2226  #define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
2227  /* Enable short packet padding to 64 bytes */
2228  #define IXGBE_TX_PAD_ENABLE     0x00000400
2229  #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004  /* Allow jumbo frames */
2230  /* This allows for 16K packets + 4k for vlan */
2231  #define IXGBE_MAX_FRAME_SZ      0x40040000
2232  
2233  #define IXGBE_TDWBAL_HEAD_WB_ENABLE   0x1      /* Tx head write-back enable */
2234  #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2      /* Tx seq# write-back enable */
2235  
2236  /* Receive Config masks */
2237  #define IXGBE_RXCTRL_RXEN       0x00000001  /* Enable Receiver */
2238  #define IXGBE_RXCTRL_DMBYPS     0x00000002  /* Descriptor Monitor Bypass */
2239  #define IXGBE_RXDCTL_ENABLE     0x02000000  /* Enable specific Rx Queue */
2240  #define IXGBE_RXDCTL_SWFLSH     0x04000000  /* Rx Desc. write-back flushing */
2241  #define IXGBE_RXDCTL_RLPMLMASK  0x00003FFF  /* Only supported on the X540 */
2242  #define IXGBE_RXDCTL_RLPML_EN   0x00008000
2243  #define IXGBE_RXDCTL_VME        0x40000000  /* VLAN mode enable */
2244  
2245  #define IXGBE_TSAUXC_EN_CLK		0x00000004
2246  #define IXGBE_TSAUXC_SYNCLK		0x00000008
2247  #define IXGBE_TSAUXC_SDP0_INT		0x00000040
2248  #define IXGBE_TSAUXC_EN_TT0		0x00000001
2249  #define IXGBE_TSAUXC_EN_TT1		0x00000002
2250  #define IXGBE_TSAUXC_ST0		0x00000010
2251  #define IXGBE_TSAUXC_DISABLE_SYSTIME	0x80000000
2252  
2253  #define IXGBE_TSSDP_TS_SDP0_SEL_MASK	0x000000C0
2254  #define IXGBE_TSSDP_TS_SDP0_CLK0	0x00000080
2255  #define IXGBE_TSSDP_TS_SDP0_EN		0x00000100
2256  
2257  #define IXGBE_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
2258  #define IXGBE_TSYNCTXCTL_ENABLED	0x00000010 /* Tx timestamping enabled */
2259  
2260  #define IXGBE_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
2261  #define IXGBE_TSYNCRXCTL_TYPE_MASK	0x0000000E /* Rx type mask */
2262  #define IXGBE_TSYNCRXCTL_TYPE_L2_V2	0x00
2263  #define IXGBE_TSYNCRXCTL_TYPE_L4_V1	0x02
2264  #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2	0x04
2265  #define IXGBE_TSYNCRXCTL_TYPE_ALL	0x08
2266  #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2	0x0A
2267  #define IXGBE_TSYNCRXCTL_ENABLED	0x00000010 /* Rx Timestamping enabled */
2268  #define IXGBE_TSYNCRXCTL_TSIP_UT_EN	0x00800000 /* Rx Timestamp in Packet */
2269  
2270  #define IXGBE_TSIM_TXTS			0x00000002
2271  
2272  #define IXGBE_RXMTRL_V1_CTRLT_MASK	0x000000FF
2273  #define IXGBE_RXMTRL_V1_SYNC_MSG	0x00
2274  #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG	0x01
2275  #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG	0x02
2276  #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG	0x03
2277  #define IXGBE_RXMTRL_V1_MGMT_MSG	0x04
2278  
2279  #define IXGBE_RXMTRL_V2_MSGID_MASK		0x0000FF00
2280  #define IXGBE_RXMTRL_V2_SYNC_MSG		0x0000
2281  #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG		0x0100
2282  #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG		0x0200
2283  #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG		0x0300
2284  #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG		0x0800
2285  #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG		0x0900
2286  #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG	0x0A00
2287  #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG		0x0B00
2288  #define IXGBE_RXMTRL_V2_SIGNALING_MSG		0x0C00
2289  #define IXGBE_RXMTRL_V2_MGMT_MSG		0x0D00
2290  
2291  #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
2292  #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
2293  #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
2294  #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
2295  #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
2296  #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
2297  /* Receive Priority Flow Control Enable */
2298  #define IXGBE_FCTRL_RPFCE 0x00004000
2299  #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
2300  #define IXGBE_MFLCN_PMCF        0x00000001 /* Pass MAC Control Frames */
2301  #define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
2302  #define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
2303  #define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
2304  #define IXGBE_MFLCN_RPFCE_MASK	0x00000FF4 /* Receive FC Mask */
2305  
2306  #define IXGBE_MFLCN_RPFCE_SHIFT		 4
2307  
2308  /* Multiple Receive Queue Control */
2309  #define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */
2310  #define IXGBE_MRQC_MRQE_MASK                    0xF /* Bits 3:0 */
2311  #define IXGBE_MRQC_RT8TCEN               0x00000002 /* 8 TC no RSS */
2312  #define IXGBE_MRQC_RT4TCEN               0x00000003 /* 4 TC no RSS */
2313  #define IXGBE_MRQC_RTRSS8TCEN            0x00000004 /* 8 TC w/ RSS */
2314  #define IXGBE_MRQC_RTRSS4TCEN            0x00000005 /* 4 TC w/ RSS */
2315  #define IXGBE_MRQC_VMDQEN                0x00000008 /* VMDq2 64 pools no RSS */
2316  #define IXGBE_MRQC_VMDQRSS32EN           0x0000000A /* VMDq2 32 pools w/ RSS */
2317  #define IXGBE_MRQC_VMDQRSS64EN           0x0000000B /* VMDq2 64 pools w/ RSS */
2318  #define IXGBE_MRQC_VMDQRT8TCEN           0x0000000C /* VMDq2/RT 16 pool 8 TC */
2319  #define IXGBE_MRQC_VMDQRT4TCEN           0x0000000D /* VMDq2/RT 32 pool 4 TC */
2320  #define IXGBE_MRQC_RSS_FIELD_MASK        0xFFFF0000
2321  #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP    0x00010000
2322  #define IXGBE_MRQC_RSS_FIELD_IPV4        0x00020000
2323  #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2324  #define IXGBE_MRQC_RSS_FIELD_IPV6_EX     0x00080000
2325  #define IXGBE_MRQC_RSS_FIELD_IPV6        0x00100000
2326  #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP    0x00200000
2327  #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP    0x00400000
2328  #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP    0x00800000
2329  #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2330  #define IXGBE_MRQC_MULTIPLE_RSS          0x00002000
2331  #define IXGBE_MRQC_L3L4TXSWEN            0x00008000
2332  
2333  #define IXGBE_FWSM_TS_ENABLED	0x1
2334  
2335  /* Queue Drop Enable */
2336  #define IXGBE_QDE_ENABLE	0x00000001
2337  #define IXGBE_QDE_HIDE_VLAN	0x00000002
2338  #define IXGBE_QDE_IDX_MASK	0x00007F00
2339  #define IXGBE_QDE_IDX_SHIFT	8
2340  #define IXGBE_QDE_WRITE		0x00010000
2341  
2342  #define IXGBE_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
2343  #define IXGBE_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
2344  #define IXGBE_TXD_CMD_EOP    0x01000000 /* End of Packet */
2345  #define IXGBE_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
2346  #define IXGBE_TXD_CMD_IC     0x04000000 /* Insert Checksum */
2347  #define IXGBE_TXD_CMD_RS     0x08000000 /* Report Status */
2348  #define IXGBE_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
2349  #define IXGBE_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
2350  #define IXGBE_TXD_STAT_DD    0x00000001 /* Descriptor Done */
2351  
2352  /* Multiple Transmit Queue Command Register */
2353  #define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
2354  #define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
2355  #define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
2356  #define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
2357  #define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
2358  #define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2359  #define IXGBE_MTQC_4TC_4TQ	0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */
2360  
2361  /* Receive Descriptor bit definitions */
2362  #define IXGBE_RXD_STAT_DD       0x01    /* Descriptor Done */
2363  #define IXGBE_RXD_STAT_EOP      0x02    /* End of Packet */
2364  #define IXGBE_RXD_STAT_FLM      0x04    /* FDir Match */
2365  #define IXGBE_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
2366  #define IXGBE_RXDADV_NEXTP_MASK   0x000FFFF0 /* Next Descriptor Index */
2367  #define IXGBE_RXDADV_NEXTP_SHIFT  0x00000004
2368  #define IXGBE_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
2369  #define IXGBE_RXD_STAT_L4CS     0x20    /* L4 xsum calculated */
2370  #define IXGBE_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
2371  #define IXGBE_RXD_STAT_PIF      0x80    /* passed in-exact filter */
2372  #define IXGBE_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
2373  #define IXGBE_RXD_STAT_OUTERIPCS  0x100 /* Cloud IP xsum calculated */
2374  #define IXGBE_RXD_STAT_VEXT     0x200   /* 1st VLAN found */
2375  #define IXGBE_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
2376  #define IXGBE_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
2377  #define IXGBE_RXD_STAT_LLINT    0x800   /* Pkt caused Low Latency Interrupt */
2378  #define IXGBE_RXD_STAT_TSIP     0x08000 /* Time Stamp in packet buffer */
2379  #define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
2380  #define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
2381  #define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
2382  #define IXGBE_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
2383  #define IXGBE_RXD_ERR_CE        0x01    /* CRC Error */
2384  #define IXGBE_RXD_ERR_LE        0x02    /* Length Error */
2385  #define IXGBE_RXD_ERR_PE        0x08    /* Packet Error */
2386  #define IXGBE_RXD_ERR_OSE       0x10    /* Oversize Error */
2387  #define IXGBE_RXD_ERR_USE       0x20    /* Undersize Error */
2388  #define IXGBE_RXD_ERR_TCPE      0x40    /* TCP/UDP Checksum Error */
2389  #define IXGBE_RXD_ERR_IPE       0x80    /* IP Checksum Error */
2390  #define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
2391  #define IXGBE_RXDADV_ERR_SHIFT          20         /* RDESC.ERRORS shift */
2392  #define IXGBE_RXDADV_ERR_OUTERIPER	0x04000000 /* CRC IP Header error */
2393  #define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCoEFe/IPE */
2394  #define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
2395  #define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
2396  #define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
2397  #define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
2398  #define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
2399  #define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
2400  #define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
2401  #define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
2402  #define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
2403  #define IXGBE_RXDADV_ERR_IPSEC_INV_PROTOCOL  0x08000000 /* overlap ERR_PE  */
2404  #define IXGBE_RXDADV_ERR_IPSEC_INV_LENGTH    0x10000000 /* overlap ERR_OSE */
2405  #define IXGBE_RXDADV_ERR_IPSEC_AUTH_FAILED   0x18000000
2406  #define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
2407  #define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
2408  #define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
2409  #define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
2410  #define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
2411  #define IXGBE_RXD_PRI_SHIFT     13
2412  #define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
2413  #define IXGBE_RXD_CFI_SHIFT     12
2414  
2415  #define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
2416  #define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
2417  #define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
2418  #define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
2419  #define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
2420  #define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
2421  #define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
2422  #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2423  #define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
2424  #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2425  #define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
2426  #define IXGBE_RXDADV_STAT_TS		0x00010000 /* IEEE 1588 Time Stamp */
2427  #define IXGBE_RXDADV_STAT_SECP		0x00020000 /* IPsec/MACsec pkt found */
2428  
2429  /* PSRTYPE bit definitions */
2430  #define IXGBE_PSRTYPE_TCPHDR    0x00000010
2431  #define IXGBE_PSRTYPE_UDPHDR    0x00000020
2432  #define IXGBE_PSRTYPE_IPV4HDR   0x00000100
2433  #define IXGBE_PSRTYPE_IPV6HDR   0x00000200
2434  #define IXGBE_PSRTYPE_L2HDR     0x00001000
2435  
2436  /* SRRCTL bit definitions */
2437  #define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10     /* so many KBs */
2438  #define IXGBE_SRRCTL_RDMTS_SHIFT        22
2439  #define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
2440  #define IXGBE_SRRCTL_DROP_EN            0x10000000
2441  #define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
2442  #define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
2443  #define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
2444  #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2445  #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT  0x04000000
2446  #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2447  #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2448  #define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
2449  
2450  #define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
2451  #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2452  
2453  #define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
2454  #define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
2455  #define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
2456  #define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
2457  #define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000
2458  #define IXGBE_RXDADV_RSCCNT_SHIFT       17
2459  #define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
2460  #define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000
2461  #define IXGBE_RXDADV_SPH                0x8000
2462  
2463  /* RSS Hash results */
2464  #define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
2465  #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
2466  #define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
2467  #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
2468  #define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
2469  #define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
2470  #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2471  #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
2472  #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
2473  #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2474  
2475  /* RSS Packet Types as indicated in the receive descriptor. */
2476  #define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
2477  #define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
2478  #define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
2479  #define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
2480  #define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
2481  #define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
2482  #define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
2483  #define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
2484  #define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
2485  #define IXGBE_RXDADV_PKTTYPE_VXLAN	0x00000800 /* VXLAN hdr present */
2486  #define IXGBE_RXDADV_PKTTYPE_TUNNEL	0x00010000 /* Tunnel type */
2487  #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
2488  #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
2489  #define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
2490  #define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
2491  #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
2492  #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4          /* Right-shift 4 bits */
2493  
2494  /* Masks to determine if packets should be dropped due to frame errors */
2495  #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2496  				      IXGBE_RXD_ERR_CE | \
2497  				      IXGBE_RXD_ERR_LE | \
2498  				      IXGBE_RXD_ERR_PE | \
2499  				      IXGBE_RXD_ERR_OSE | \
2500  				      IXGBE_RXD_ERR_USE)
2501  
2502  #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2503  				      IXGBE_RXDADV_ERR_CE | \
2504  				      IXGBE_RXDADV_ERR_LE | \
2505  				      IXGBE_RXDADV_ERR_PE | \
2506  				      IXGBE_RXDADV_ERR_OSE | \
2507  				      IXGBE_RXDADV_ERR_IPSEC_INV_PROTOCOL | \
2508  				      IXGBE_RXDADV_ERR_IPSEC_INV_LENGTH | \
2509  				      IXGBE_RXDADV_ERR_USE)
2510  
2511  /* Multicast bit mask */
2512  #define IXGBE_MCSTCTRL_MFE      0x4
2513  
2514  /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2515  #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE  8
2516  #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE  8
2517  #define IXGBE_REQ_TX_BUFFER_GRANULARITY   1024
2518  
2519  /* Vlan-specific macros */
2520  #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF /* VLAN ID in lower 12 bits */
2521  #define IXGBE_RX_DESC_SPECIAL_PRI_MASK   0xE000 /* Priority in upper 3 bits */
2522  #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */
2523  #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2524  
2525  /* SR-IOV specific macros */
2526  #define IXGBE_MBVFICR_INDEX(vf_number)   (vf_number >> 4)
2527  #define IXGBE_MBVFICR(_i)		(0x00710 + ((_i) * 4))
2528  #define IXGBE_VFLRE(_i)		((((_i) & 1) ? 0x001C0 : 0x00600))
2529  #define IXGBE_VFLREC(_i)		(0x00700 + ((_i) * 4))
2530  /* Translated register #defines */
2531  #define IXGBE_PVFTDH(P)		(0x06010 + (0x40 * (P)))
2532  #define IXGBE_PVFTDT(P)		(0x06018 + (0x40 * (P)))
2533  #define IXGBE_PVFTXDCTL(P)	(0x06028 + (0x40 * (P)))
2534  #define IXGBE_PVFTDWBAL(P)	(0x06038 + (0x40 * (P)))
2535  #define IXGBE_PVFTDWBAH(P)	(0x0603C + (0x40 * (P)))
2536  #define IXGBE_PVFGPRC(x)	(0x0101C + (0x40 * (x)))
2537  #define IXGBE_PVFGPTC(x)	(0x08300 + (0x04 * (x)))
2538  #define IXGBE_PVFGORC_LSB(x)	(0x01020 + (0x40 * (x)))
2539  #define IXGBE_PVFGORC_MSB(x)	(0x0D020 + (0x40 * (x)))
2540  #define IXGBE_PVFGOTC_LSB(x)	(0x08400 + (0x08 * (x)))
2541  #define IXGBE_PVFGOTC_MSB(x)	(0x08404 + (0x08 * (x)))
2542  #define IXGBE_PVFMPRC(x)	(0x0D01C + (0x40 * (x)))
2543  
2544  #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2545  		(IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2546  #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2547  		(IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2548  
2549  #define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \
2550  		(IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2551  #define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \
2552  		(IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2553  
2554  enum ixgbe_fdir_pballoc_type {
2555  	IXGBE_FDIR_PBALLOC_NONE = 0,
2556  	IXGBE_FDIR_PBALLOC_64K  = 1,
2557  	IXGBE_FDIR_PBALLOC_128K = 2,
2558  	IXGBE_FDIR_PBALLOC_256K = 3,
2559  };
2560  #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT           16
2561  
2562  /* Flow Director register values */
2563  #define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
2564  #define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
2565  #define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
2566  #define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
2567  #define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
2568  #define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
2569  #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
2570  #define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
2571  #define IXGBE_FDIRCTRL_FLEX_SHIFT               16
2572  #define IXGBE_FDIRCTRL_DROP_NO_MATCH		0x00008000
2573  #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT		21
2574  #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN	0x0001 /* bit 23:21, 001b */
2575  #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD		0x0002 /* bit 23:21, 010b */
2576  #define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
2577  #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
2578  #define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
2579  #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
2580  
2581  #define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
2582  #define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
2583  #define IXGBE_FDIRIP6M_DIPM_SHIFT               16
2584  #define IXGBE_FDIRM_VLANID                      0x00000001
2585  #define IXGBE_FDIRM_VLANP                       0x00000002
2586  #define IXGBE_FDIRM_POOL                        0x00000004
2587  #define IXGBE_FDIRM_L4P                         0x00000008
2588  #define IXGBE_FDIRM_FLEX                        0x00000010
2589  #define IXGBE_FDIRM_DIPv6                       0x00000020
2590  
2591  #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
2592  #define IXGBE_FDIRFREE_FREE_SHIFT               0
2593  #define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
2594  #define IXGBE_FDIRFREE_COLL_SHIFT               16
2595  #define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
2596  #define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
2597  #define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
2598  #define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
2599  #define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
2600  #define IXGBE_FDIRUSTAT_ADD_SHIFT               0
2601  #define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
2602  #define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
2603  #define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
2604  #define IXGBE_FDIRFSTAT_FADD_SHIFT              0
2605  #define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
2606  #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
2607  #define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
2608  #define IXGBE_FDIRVLAN_FLEX_SHIFT               16
2609  #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
2610  #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
2611  
2612  #define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
2613  #define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
2614  #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
2615  #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
2616  #define IXGBE_FDIRCMD_FILTER_VALID              0x00000004
2617  #define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
2618  #define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
2619  #define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
2620  #define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
2621  #define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
2622  #define IXGBE_FDIRCMD_IPV6                      0x00000080
2623  #define IXGBE_FDIRCMD_CLEARHT                   0x00000100
2624  #define IXGBE_FDIRCMD_DROP                      0x00000200
2625  #define IXGBE_FDIRCMD_INT                       0x00000400
2626  #define IXGBE_FDIRCMD_LAST                      0x00000800
2627  #define IXGBE_FDIRCMD_COLLISION                 0x00001000
2628  #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
2629  #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
2630  #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
2631  #define IXGBE_FDIRCMD_RX_TUNNEL_FILTER_SHIFT	23
2632  #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
2633  #define IXGBE_FDIR_INIT_DONE_POLL               10
2634  #define IXGBE_FDIRCMD_CMD_POLL                  10
2635  #define IXGBE_FDIRCMD_TUNNEL_FILTER		0x00800000
2636  
2637  #define IXGBE_FDIR_DROP_QUEUE                   127
2638  
2639  /* Manageablility Host Interface defines */
2640  #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH	1792 /* Num of bytes in range */
2641  #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH	448 /* Num of dwords in range */
2642  #define IXGBE_HI_COMMAND_TIMEOUT	500 /* Process HI command limit */
2643  #define IXGBE_HI_FLASH_ERASE_TIMEOUT	1000 /* Process Erase command limit */
2644  #define IXGBE_HI_FLASH_UPDATE_TIMEOUT	5000 /* Process Update command limit */
2645  #define IXGBE_HI_FLASH_APPLY_TIMEOUT	0 /* Process Apply command limit */
2646  
2647  /* CEM Support */
2648  #define FW_CEM_HDR_LEN			0x4
2649  #define FW_CEM_CMD_DRIVER_INFO		0xDD
2650  #define FW_CEM_CMD_DRIVER_INFO_LEN	0x5
2651  #define FW_CEM_CMD_RESERVED		0x0
2652  #define FW_CEM_UNUSED_VER		0x0
2653  #define FW_CEM_MAX_RETRIES		3
2654  #define FW_CEM_RESP_STATUS_SUCCESS	0x1
2655  #define FW_CEM_DRIVER_VERSION_SIZE	39 /* +9 would send 48 bytes to fw */
2656  #define FW_READ_SHADOW_RAM_CMD		0x31
2657  #define FW_READ_SHADOW_RAM_LEN		0x6
2658  #define FW_WRITE_SHADOW_RAM_CMD		0x33
2659  #define FW_WRITE_SHADOW_RAM_LEN		0xA /* 8 plus 1 WORD to write */
2660  #define FW_SHADOW_RAM_DUMP_CMD		0x36
2661  #define FW_SHADOW_RAM_DUMP_LEN		0
2662  #define FW_DEFAULT_CHECKSUM		0xFF /* checksum always 0xFF */
2663  #define FW_NVM_DATA_OFFSET		3
2664  #define FW_MAX_READ_BUFFER_SIZE		1024
2665  #define FW_DISABLE_RXEN_CMD		0xDE
2666  #define FW_DISABLE_RXEN_LEN		0x1
2667  #define FW_PHY_MGMT_REQ_CMD		0x20
2668  #define FW_PHY_TOKEN_REQ_CMD		0x0A
2669  #define FW_PHY_TOKEN_REQ_LEN		2
2670  #define FW_PHY_TOKEN_REQ		0
2671  #define FW_PHY_TOKEN_REL		1
2672  #define FW_PHY_TOKEN_OK			1
2673  #define FW_PHY_TOKEN_RETRY		0x80
2674  #define FW_PHY_TOKEN_DELAY		5	/* milliseconds */
2675  #define FW_PHY_TOKEN_WAIT		5	/* seconds */
2676  #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
2677  #define FW_INT_PHY_REQ_CMD		0xB
2678  #define FW_INT_PHY_REQ_LEN		10
2679  #define FW_INT_PHY_REQ_READ		0
2680  #define FW_INT_PHY_REQ_WRITE		1
2681  #define FW_PHY_ACT_REQ_CMD		5
2682  #define FW_PHY_ACT_DATA_COUNT		4
2683  #define FW_PHY_ACT_REQ_LEN		(4 + 4 * FW_PHY_ACT_DATA_COUNT)
2684  #define FW_PHY_ACT_INIT_PHY		1
2685  #define FW_PHY_ACT_SETUP_LINK		2
2686  #define FW_PHY_ACT_LINK_SPEED_10	BIT(0)
2687  #define FW_PHY_ACT_LINK_SPEED_100	BIT(1)
2688  #define FW_PHY_ACT_LINK_SPEED_1G	BIT(2)
2689  #define FW_PHY_ACT_LINK_SPEED_2_5G	BIT(3)
2690  #define FW_PHY_ACT_LINK_SPEED_5G	BIT(4)
2691  #define FW_PHY_ACT_LINK_SPEED_10G	BIT(5)
2692  #define FW_PHY_ACT_LINK_SPEED_20G	BIT(6)
2693  #define FW_PHY_ACT_LINK_SPEED_25G	BIT(7)
2694  #define FW_PHY_ACT_LINK_SPEED_40G	BIT(8)
2695  #define FW_PHY_ACT_LINK_SPEED_50G	BIT(9)
2696  #define FW_PHY_ACT_LINK_SPEED_100G	BIT(10)
2697  #define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
2698  #define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3 << \
2699  					  HW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
2700  #define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
2701  #define FW_PHY_ACT_SETUP_LINK_PAUSE_TX	1u
2702  #define FW_PHY_ACT_SETUP_LINK_PAUSE_RX	2u
2703  #define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
2704  #define FW_PHY_ACT_SETUP_LINK_LP	BIT(18)
2705  #define FW_PHY_ACT_SETUP_LINK_HP	BIT(19)
2706  #define FW_PHY_ACT_SETUP_LINK_EEE	BIT(20)
2707  #define FW_PHY_ACT_SETUP_LINK_AN	BIT(22)
2708  #define FW_PHY_ACT_SETUP_LINK_RSP_DOWN	BIT(0)
2709  #define FW_PHY_ACT_GET_LINK_INFO	3
2710  #define FW_PHY_ACT_GET_LINK_INFO_EEE	BIT(19)
2711  #define FW_PHY_ACT_GET_LINK_INFO_FC_TX	BIT(20)
2712  #define FW_PHY_ACT_GET_LINK_INFO_FC_RX	BIT(21)
2713  #define FW_PHY_ACT_GET_LINK_INFO_POWER	BIT(22)
2714  #define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE	BIT(24)
2715  #define FW_PHY_ACT_GET_LINK_INFO_TEMP	BIT(25)
2716  #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX	BIT(28)
2717  #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX	BIT(29)
2718  #define FW_PHY_ACT_FORCE_LINK_DOWN	4
2719  #define FW_PHY_ACT_FORCE_LINK_DOWN_OFF	BIT(0)
2720  #define FW_PHY_ACT_PHY_SW_RESET		5
2721  #define FW_PHY_ACT_PHY_HW_RESET		6
2722  #define FW_PHY_ACT_GET_PHY_INFO		7
2723  #define FW_PHY_ACT_UD_2			0x1002
2724  #define FW_PHY_ACT_UD_2_10G_KR_EEE	BIT(6)
2725  #define FW_PHY_ACT_UD_2_10G_KX4_EEE	BIT(5)
2726  #define FW_PHY_ACT_UD_2_1G_KX_EEE	BIT(4)
2727  #define FW_PHY_ACT_UD_2_10G_T_EEE	BIT(3)
2728  #define FW_PHY_ACT_UD_2_1G_T_EEE	BIT(2)
2729  #define FW_PHY_ACT_UD_2_100M_TX_EEE	BIT(1)
2730  #define FW_PHY_ACT_RETRIES		50
2731  #define FW_PHY_INFO_SPEED_MASK		0xFFFu
2732  #define FW_PHY_INFO_ID_HI_MASK		0xFFFF0000u
2733  #define FW_PHY_INFO_ID_LO_MASK		0x0000FFFFu
2734  
2735  /* Host Interface Command Structures */
2736  struct ixgbe_hic_hdr {
2737  	u8 cmd;
2738  	u8 buf_len;
2739  	union {
2740  		u8 cmd_resv;
2741  		u8 ret_status;
2742  	} cmd_or_resp;
2743  	u8 checksum;
2744  };
2745  
2746  struct ixgbe_hic_hdr2_req {
2747  	u8 cmd;
2748  	u8 buf_lenh;
2749  	u8 buf_lenl;
2750  	u8 checksum;
2751  };
2752  
2753  struct ixgbe_hic_hdr2_rsp {
2754  	u8 cmd;
2755  	u8 buf_lenl;
2756  	u8 buf_lenh_status;     /* 7-5: high bits of buf_len, 4-0: status */
2757  	u8 checksum;
2758  };
2759  
2760  union ixgbe_hic_hdr2 {
2761  	struct ixgbe_hic_hdr2_req req;
2762  	struct ixgbe_hic_hdr2_rsp rsp;
2763  };
2764  
2765  struct ixgbe_hic_drv_info {
2766  	struct ixgbe_hic_hdr hdr;
2767  	u8 port_num;
2768  	u8 ver_sub;
2769  	u8 ver_build;
2770  	u8 ver_min;
2771  	u8 ver_maj;
2772  	u8 pad; /* end spacing to ensure length is mult. of dword */
2773  	u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2774  };
2775  
2776  struct ixgbe_hic_drv_info2 {
2777  	struct ixgbe_hic_hdr hdr;
2778  	u8 port_num;
2779  	u8 ver_sub;
2780  	u8 ver_build;
2781  	u8 ver_min;
2782  	u8 ver_maj;
2783  	char driver_string[FW_CEM_DRIVER_VERSION_SIZE];
2784  };
2785  
2786  /* These need to be dword aligned */
2787  struct ixgbe_hic_read_shadow_ram {
2788  	union ixgbe_hic_hdr2 hdr;
2789  	u32 address;
2790  	u16 length;
2791  	u16 pad2;
2792  	u16 data;
2793  	u16 pad3;
2794  };
2795  
2796  struct ixgbe_hic_write_shadow_ram {
2797  	union ixgbe_hic_hdr2 hdr;
2798  	__be32 address;
2799  	__be16 length;
2800  	u16 pad2;
2801  	u16 data;
2802  	u16 pad3;
2803  };
2804  
2805  struct ixgbe_hic_disable_rxen {
2806  	struct ixgbe_hic_hdr hdr;
2807  	u8  port_number;
2808  	u8  pad2;
2809  	u16 pad3;
2810  };
2811  
2812  struct ixgbe_hic_phy_token_req {
2813  	struct ixgbe_hic_hdr hdr;
2814  	u8 port_number;
2815  	u8 command_type;
2816  	u16 pad;
2817  };
2818  
2819  struct ixgbe_hic_internal_phy_req {
2820  	struct ixgbe_hic_hdr hdr;
2821  	u8 port_number;
2822  	u8 command_type;
2823  	__be16 address;
2824  	u16 rsv1;
2825  	__be32 write_data;
2826  	u16 pad;
2827  } __packed;
2828  
2829  struct ixgbe_hic_internal_phy_resp {
2830  	struct ixgbe_hic_hdr hdr;
2831  	__be32 read_data;
2832  };
2833  
2834  struct ixgbe_hic_phy_activity_req {
2835  	struct ixgbe_hic_hdr hdr;
2836  	u8 port_number;
2837  	u8 pad;
2838  	__le16 activity_id;
2839  	__be32 data[FW_PHY_ACT_DATA_COUNT];
2840  };
2841  
2842  struct ixgbe_hic_phy_activity_resp {
2843  	struct ixgbe_hic_hdr hdr;
2844  	__be32 data[FW_PHY_ACT_DATA_COUNT];
2845  };
2846  
2847  /* Transmit Descriptor - Advanced */
2848  union ixgbe_adv_tx_desc {
2849  	struct {
2850  		__le64 buffer_addr;      /* Address of descriptor's data buf */
2851  		__le32 cmd_type_len;
2852  		__le32 olinfo_status;
2853  	} read;
2854  	struct {
2855  		__le64 rsvd;       /* Reserved */
2856  		__le32 nxtseq_seed;
2857  		__le32 status;
2858  	} wb;
2859  };
2860  
2861  /* Receive Descriptor - Advanced */
2862  union ixgbe_adv_rx_desc {
2863  	struct {
2864  		__le64 pkt_addr; /* Packet buffer address */
2865  		__le64 hdr_addr; /* Header buffer address */
2866  	} read;
2867  	struct {
2868  		struct {
2869  			union {
2870  				__le32 data;
2871  				struct {
2872  					__le16 pkt_info; /* RSS, Pkt type */
2873  					__le16 hdr_info; /* Splithdr, hdrlen */
2874  				} hs_rss;
2875  			} lo_dword;
2876  			union {
2877  				__le32 rss; /* RSS Hash */
2878  				struct {
2879  					__le16 ip_id; /* IP id */
2880  					__le16 csum; /* Packet Checksum */
2881  				} csum_ip;
2882  			} hi_dword;
2883  		} lower;
2884  		struct {
2885  			__le32 status_error; /* ext status/error */
2886  			__le16 length; /* Packet length */
2887  			__le16 vlan; /* VLAN tag */
2888  		} upper;
2889  	} wb;  /* writeback */
2890  };
2891  
2892  /* Context descriptors */
2893  struct ixgbe_adv_tx_context_desc {
2894  	__le32 vlan_macip_lens;
2895  	__le32 fceof_saidx;
2896  	__le32 type_tucmd_mlhl;
2897  	__le32 mss_l4len_idx;
2898  };
2899  
2900  /* Adv Transmit Descriptor Config Masks */
2901  #define IXGBE_ADVTXD_DTALEN_MASK      0x0000FFFF /* Data buf length(bytes) */
2902  #define IXGBE_ADVTXD_MAC_LINKSEC      0x00040000 /* Insert LinkSec */
2903  #define IXGBE_ADVTXD_MAC_TSTAMP	      0x00080000 /* IEEE 1588 Time Stamp */
2904  #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK   0x000003FF /* IPSec SA index */
2905  #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK    0x000001FF /* IPSec ESP length */
2906  #define IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */
2907  #define IXGBE_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Desc */
2908  #define IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
2909  #define IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */
2910  #define IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */
2911  #define IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */
2912  #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000    /* DDP hdr type or iSCSI */
2913  #define IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2914  #define IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
2915  #define IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
2916  #define IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */
2917  #define IXGBE_ADVTXD_STAT_SN_CRC      0x00000002 /* NXTSEQ/SEED pres in WB */
2918  #define IXGBE_ADVTXD_STAT_RSV   0x0000000C /* STA Reserved */
2919  #define IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */
2920  #define IXGBE_ADVTXD_CC         0x00000080 /* Check Context */
2921  #define IXGBE_ADVTXD_POPTS_SHIFT      8  /* Adv desc POPTS shift */
2922  #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2923  				 IXGBE_ADVTXD_POPTS_SHIFT)
2924  #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2925  				 IXGBE_ADVTXD_POPTS_SHIFT)
2926  #define IXGBE_ADVTXD_POPTS_IPSEC     0x00000400 /* IPSec offload request */
2927  #define IXGBE_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
2928  #define IXGBE_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
2929  #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2930  #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2931  #define IXGBE_ADVTXD_POPTS_RSV       0x00002000 /* POPTS Reserved */
2932  #define IXGBE_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
2933  #define IXGBE_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
2934  #define IXGBE_ADVTXD_VLAN_SHIFT      16  /* Adv ctxt vlan tag shift */
2935  #define IXGBE_ADVTXD_TUCMD_IPV4      0x00000400  /* IP Packet Type: 1=IPv4 */
2936  #define IXGBE_ADVTXD_TUCMD_IPV6      0x00000000  /* IP Packet Type: 0=IPv6 */
2937  #define IXGBE_ADVTXD_TUCMD_L4T_UDP   0x00000000  /* L4 Packet TYPE of UDP */
2938  #define IXGBE_ADVTXD_TUCMD_L4T_TCP   0x00000800  /* L4 Packet TYPE of TCP */
2939  #define IXGBE_ADVTXD_TUCMD_L4T_SCTP  0x00001000  /* L4 Packet TYPE of SCTP */
2940  #define IXGBE_ADVTXD_TUCMD_L4T_RSV     0x00001800 /* RSV L4 Packet TYPE */
2941  #define IXGBE_ADVTXD_TUCMD_MKRREQ    0x00002000 /*Req requires Markers and CRC*/
2942  #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2943  #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2944  #define IXGBE_ADVTXT_TUCMD_FCOE      0x00008000       /* FCoE Frame Type */
2945  #define IXGBE_ADVTXD_FCOEF_SOF       (BIT(2) << 10) /* FC SOF index */
2946  #define IXGBE_ADVTXD_FCOEF_PARINC    (BIT(3) << 10) /* Rel_Off in F_CTL */
2947  #define IXGBE_ADVTXD_FCOEF_ORIE      (BIT(4) << 10) /* Orientation: End */
2948  #define IXGBE_ADVTXD_FCOEF_ORIS      (BIT(5) << 10) /* Orientation: Start */
2949  #define IXGBE_ADVTXD_FCOEF_EOF_N     (0u << 10)  /* 00: EOFn */
2950  #define IXGBE_ADVTXD_FCOEF_EOF_T     (1u << 10)  /* 01: EOFt */
2951  #define IXGBE_ADVTXD_FCOEF_EOF_NI    (2u << 10)  /* 10: EOFni */
2952  #define IXGBE_ADVTXD_FCOEF_EOF_A     (3u << 10)  /* 11: EOFa */
2953  #define IXGBE_ADVTXD_FCOEF_EOF_MASK  (3u << 10)  /* FC EOF index */
2954  #define IXGBE_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
2955  #define IXGBE_ADVTXD_MSS_SHIFT       16  /* Adv ctxt MSS shift */
2956  
2957  /* Autonegotiation advertised speeds */
2958  typedef u32 ixgbe_autoneg_advertised;
2959  /* Link speed */
2960  typedef u32 ixgbe_link_speed;
2961  #define IXGBE_LINK_SPEED_UNKNOWN	0
2962  #define IXGBE_LINK_SPEED_10_FULL	0x0002
2963  #define IXGBE_LINK_SPEED_100_FULL	0x0008
2964  #define IXGBE_LINK_SPEED_1GB_FULL	0x0020
2965  #define IXGBE_LINK_SPEED_2_5GB_FULL	0x0400
2966  #define IXGBE_LINK_SPEED_5GB_FULL	0x0800
2967  #define IXGBE_LINK_SPEED_10GB_FULL	0x0080
2968  #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2969  					IXGBE_LINK_SPEED_10GB_FULL)
2970  #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2971  					IXGBE_LINK_SPEED_1GB_FULL | \
2972  					IXGBE_LINK_SPEED_10GB_FULL)
2973  
2974  /* Flow Control Data Sheet defined values
2975   * Calculation and defines taken from 802.1bb Annex O
2976   */
2977  
2978  /* BitTimes (BT) conversion */
2979  #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
2980  #define IXGBE_B2BT(BT) (BT * 8)
2981  
2982  /* Calculate Delay to respond to PFC */
2983  #define IXGBE_PFC_D	672
2984  
2985  /* Calculate Cable Delay */
2986  #define IXGBE_CABLE_DC	5556 /* Delay Copper */
2987  #define IXGBE_CABLE_DO	5000 /* Delay Optical */
2988  
2989  /* Calculate Interface Delay X540 */
2990  #define IXGBE_PHY_DC	25600	/* Delay 10G BASET */
2991  #define IXGBE_MAC_DC	8192	/* Delay Copper XAUI interface */
2992  #define IXGBE_XAUI_DC	(2 * 2048) /* Delay Copper Phy */
2993  
2994  #define IXGBE_ID_X540	(IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
2995  
2996  /* Calculate Interface Delay 82598, 82599 */
2997  #define IXGBE_PHY_D	12800
2998  #define IXGBE_MAC_D	4096
2999  #define IXGBE_XAUI_D	(2 * 1024)
3000  
3001  #define IXGBE_ID	(IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
3002  
3003  /* Calculate Delay incurred from higher layer */
3004  #define IXGBE_HD	6144
3005  
3006  /* Calculate PCI Bus delay for low thresholds */
3007  #define IXGBE_PCI_DELAY	10000
3008  
3009  /* Calculate X540 delay value in bit times */
3010  #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
3011  			((36 * \
3012  			  (IXGBE_B2BT(_max_frame_link) + \
3013  			   IXGBE_PFC_D + \
3014  			   (2 * IXGBE_CABLE_DC) + \
3015  			   (2 * IXGBE_ID_X540) + \
3016  			   IXGBE_HD) / 25 + 1) + \
3017  			 2 * IXGBE_B2BT(_max_frame_tc))
3018  
3019  /* Calculate 82599, 82598 delay value in bit times */
3020  #define IXGBE_DV(_max_frame_link, _max_frame_tc) \
3021  			((36 * \
3022  			  (IXGBE_B2BT(_max_frame_link) + \
3023  			   IXGBE_PFC_D + \
3024  			   (2 * IXGBE_CABLE_DC) + \
3025  			   (2 * IXGBE_ID) + \
3026  			   IXGBE_HD) / 25 + 1) + \
3027  			 2 * IXGBE_B2BT(_max_frame_tc))
3028  
3029  /* Calculate low threshold delay values */
3030  #define IXGBE_LOW_DV_X540(_max_frame_tc) \
3031  			(2 * IXGBE_B2BT(_max_frame_tc) + \
3032  			(36 * IXGBE_PCI_DELAY / 25) + 1)
3033  #define IXGBE_LOW_DV(_max_frame_tc) \
3034  			(2 * IXGBE_LOW_DV_X540(_max_frame_tc))
3035  
3036  /* Software ATR hash keys */
3037  #define IXGBE_ATR_BUCKET_HASH_KEY    0x3DAD14E2
3038  #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
3039  
3040  /* Software ATR input stream values and masks */
3041  #define IXGBE_ATR_HASH_MASK		0x7fff
3042  #define IXGBE_ATR_L4TYPE_MASK		0x3
3043  #define IXGBE_ATR_L4TYPE_UDP		0x1
3044  #define IXGBE_ATR_L4TYPE_TCP		0x2
3045  #define IXGBE_ATR_L4TYPE_SCTP		0x3
3046  #define IXGBE_ATR_L4TYPE_IPV6_MASK	0x4
3047  #define IXGBE_ATR_L4TYPE_TUNNEL_MASK	0x10
3048  enum ixgbe_atr_flow_type {
3049  	IXGBE_ATR_FLOW_TYPE_IPV4   = 0x0,
3050  	IXGBE_ATR_FLOW_TYPE_UDPV4  = 0x1,
3051  	IXGBE_ATR_FLOW_TYPE_TCPV4  = 0x2,
3052  	IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
3053  	IXGBE_ATR_FLOW_TYPE_IPV6   = 0x4,
3054  	IXGBE_ATR_FLOW_TYPE_UDPV6  = 0x5,
3055  	IXGBE_ATR_FLOW_TYPE_TCPV6  = 0x6,
3056  	IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
3057  };
3058  
3059  /* Flow Director ATR input struct. */
3060  union ixgbe_atr_input {
3061  	/*
3062  	 * Byte layout in order, all values with MSB first:
3063  	 *
3064  	 * vm_pool    - 1 byte
3065  	 * flow_type  - 1 byte
3066  	 * vlan_id    - 2 bytes
3067  	 * src_ip     - 16 bytes
3068  	 * dst_ip     - 16 bytes
3069  	 * src_port   - 2 bytes
3070  	 * dst_port   - 2 bytes
3071  	 * flex_bytes - 2 bytes
3072  	 * bkt_hash   - 2 bytes
3073  	 */
3074  	struct {
3075  		u8     vm_pool;
3076  		u8     flow_type;
3077  		__be16 vlan_id;
3078  		__be32 dst_ip[4];
3079  		__be32 src_ip[4];
3080  		__be16 src_port;
3081  		__be16 dst_port;
3082  		__be16 flex_bytes;
3083  		__be16 bkt_hash;
3084  	} formatted;
3085  	__be32 dword_stream[11];
3086  };
3087  
3088  /* Flow Director compressed ATR hash input struct */
3089  union ixgbe_atr_hash_dword {
3090  	struct {
3091  		u8 vm_pool;
3092  		u8 flow_type;
3093  		__be16 vlan_id;
3094  	} formatted;
3095  	__be32 ip;
3096  	struct {
3097  		__be16 src;
3098  		__be16 dst;
3099  	} port;
3100  	__be16 flex_bytes;
3101  	__be32 dword;
3102  };
3103  
3104  #define IXGBE_MVALS_INIT(m)		\
3105  	IXGBE_CAT(EEC, m),		\
3106  	IXGBE_CAT(FLA, m),		\
3107  	IXGBE_CAT(GRC, m),		\
3108  	IXGBE_CAT(FACTPS, m),		\
3109  	IXGBE_CAT(SWSM, m),		\
3110  	IXGBE_CAT(SWFW_SYNC, m),	\
3111  	IXGBE_CAT(FWSM, m),		\
3112  	IXGBE_CAT(SDP0_GPIEN, m),	\
3113  	IXGBE_CAT(SDP1_GPIEN, m),	\
3114  	IXGBE_CAT(SDP2_GPIEN, m),	\
3115  	IXGBE_CAT(EICR_GPI_SDP0, m),	\
3116  	IXGBE_CAT(EICR_GPI_SDP1, m),	\
3117  	IXGBE_CAT(EICR_GPI_SDP2, m),	\
3118  	IXGBE_CAT(CIAA, m),		\
3119  	IXGBE_CAT(CIAD, m),		\
3120  	IXGBE_CAT(I2C_CLK_IN, m),	\
3121  	IXGBE_CAT(I2C_CLK_OUT, m),	\
3122  	IXGBE_CAT(I2C_DATA_IN, m),	\
3123  	IXGBE_CAT(I2C_DATA_OUT, m),	\
3124  	IXGBE_CAT(I2C_DATA_OE_N_EN, m),	\
3125  	IXGBE_CAT(I2C_BB_EN, m),	\
3126  	IXGBE_CAT(I2C_CLK_OE_N_EN, m),	\
3127  	IXGBE_CAT(I2CCTL, m)
3128  
3129  enum ixgbe_mvals {
3130  	IXGBE_MVALS_INIT(IDX),
3131  	IXGBE_MVALS_IDX_LIMIT
3132  };
3133  
3134  enum ixgbe_eeprom_type {
3135  	ixgbe_eeprom_uninitialized = 0,
3136  	ixgbe_eeprom_spi,
3137  	ixgbe_flash,
3138  	ixgbe_eeprom_none /* No NVM support */
3139  };
3140  
3141  enum ixgbe_mac_type {
3142  	ixgbe_mac_unknown = 0,
3143  	ixgbe_mac_82598EB,
3144  	ixgbe_mac_82599EB,
3145  	ixgbe_mac_X540,
3146  	ixgbe_mac_X550,
3147  	ixgbe_mac_X550EM_x,
3148  	ixgbe_mac_x550em_a,
3149  	ixgbe_num_macs
3150  };
3151  
3152  enum ixgbe_phy_type {
3153  	ixgbe_phy_unknown = 0,
3154  	ixgbe_phy_none,
3155  	ixgbe_phy_tn,
3156  	ixgbe_phy_aq,
3157  	ixgbe_phy_x550em_kr,
3158  	ixgbe_phy_x550em_kx4,
3159  	ixgbe_phy_x550em_xfi,
3160  	ixgbe_phy_x550em_ext_t,
3161  	ixgbe_phy_ext_1g_t,
3162  	ixgbe_phy_cu_unknown,
3163  	ixgbe_phy_qt,
3164  	ixgbe_phy_xaui,
3165  	ixgbe_phy_nl,
3166  	ixgbe_phy_sfp_passive_tyco,
3167  	ixgbe_phy_sfp_passive_unknown,
3168  	ixgbe_phy_sfp_active_unknown,
3169  	ixgbe_phy_sfp_avago,
3170  	ixgbe_phy_sfp_ftl,
3171  	ixgbe_phy_sfp_ftl_active,
3172  	ixgbe_phy_sfp_unknown,
3173  	ixgbe_phy_sfp_intel,
3174  	ixgbe_phy_qsfp_passive_unknown,
3175  	ixgbe_phy_qsfp_active_unknown,
3176  	ixgbe_phy_qsfp_intel,
3177  	ixgbe_phy_qsfp_unknown,
3178  	ixgbe_phy_sfp_unsupported,
3179  	ixgbe_phy_sgmii,
3180  	ixgbe_phy_fw,
3181  	ixgbe_phy_generic
3182  };
3183  
3184  /*
3185   * SFP+ module type IDs:
3186   *
3187   * ID   Module Type
3188   * =============
3189   * 0    SFP_DA_CU
3190   * 1    SFP_SR
3191   * 2    SFP_LR
3192   * 3    SFP_DA_CU_CORE0 - 82599-specific
3193   * 4    SFP_DA_CU_CORE1 - 82599-specific
3194   * 5    SFP_SR/LR_CORE0 - 82599-specific
3195   * 6    SFP_SR/LR_CORE1 - 82599-specific
3196   */
3197  enum ixgbe_sfp_type {
3198  	ixgbe_sfp_type_da_cu = 0,
3199  	ixgbe_sfp_type_sr = 1,
3200  	ixgbe_sfp_type_lr = 2,
3201  	ixgbe_sfp_type_da_cu_core0 = 3,
3202  	ixgbe_sfp_type_da_cu_core1 = 4,
3203  	ixgbe_sfp_type_srlr_core0 = 5,
3204  	ixgbe_sfp_type_srlr_core1 = 6,
3205  	ixgbe_sfp_type_da_act_lmt_core0 = 7,
3206  	ixgbe_sfp_type_da_act_lmt_core1 = 8,
3207  	ixgbe_sfp_type_1g_cu_core0 = 9,
3208  	ixgbe_sfp_type_1g_cu_core1 = 10,
3209  	ixgbe_sfp_type_1g_sx_core0 = 11,
3210  	ixgbe_sfp_type_1g_sx_core1 = 12,
3211  	ixgbe_sfp_type_1g_lx_core0 = 13,
3212  	ixgbe_sfp_type_1g_lx_core1 = 14,
3213  	ixgbe_sfp_type_not_present = 0xFFFE,
3214  	ixgbe_sfp_type_unknown = 0xFFFF
3215  };
3216  
3217  enum ixgbe_media_type {
3218  	ixgbe_media_type_unknown = 0,
3219  	ixgbe_media_type_fiber,
3220  	ixgbe_media_type_fiber_qsfp,
3221  	ixgbe_media_type_fiber_lco,
3222  	ixgbe_media_type_copper,
3223  	ixgbe_media_type_backplane,
3224  	ixgbe_media_type_cx4,
3225  	ixgbe_media_type_virtual
3226  };
3227  
3228  /* Flow Control Settings */
3229  enum ixgbe_fc_mode {
3230  	ixgbe_fc_none = 0,
3231  	ixgbe_fc_rx_pause,
3232  	ixgbe_fc_tx_pause,
3233  	ixgbe_fc_full,
3234  	ixgbe_fc_default
3235  };
3236  
3237  /* Smart Speed Settings */
3238  #define IXGBE_SMARTSPEED_MAX_RETRIES	3
3239  enum ixgbe_smart_speed {
3240  	ixgbe_smart_speed_auto = 0,
3241  	ixgbe_smart_speed_on,
3242  	ixgbe_smart_speed_off
3243  };
3244  
3245  /* PCI bus types */
3246  enum ixgbe_bus_type {
3247  	ixgbe_bus_type_unknown = 0,
3248  	ixgbe_bus_type_pci_express,
3249  	ixgbe_bus_type_internal,
3250  	ixgbe_bus_type_reserved
3251  };
3252  
3253  /* PCI bus speeds */
3254  enum ixgbe_bus_speed {
3255  	ixgbe_bus_speed_unknown = 0,
3256  	ixgbe_bus_speed_33      = 33,
3257  	ixgbe_bus_speed_66      = 66,
3258  	ixgbe_bus_speed_100     = 100,
3259  	ixgbe_bus_speed_120     = 120,
3260  	ixgbe_bus_speed_133     = 133,
3261  	ixgbe_bus_speed_2500    = 2500,
3262  	ixgbe_bus_speed_5000    = 5000,
3263  	ixgbe_bus_speed_8000    = 8000,
3264  	ixgbe_bus_speed_reserved
3265  };
3266  
3267  /* PCI bus widths */
3268  enum ixgbe_bus_width {
3269  	ixgbe_bus_width_unknown = 0,
3270  	ixgbe_bus_width_pcie_x1 = 1,
3271  	ixgbe_bus_width_pcie_x2 = 2,
3272  	ixgbe_bus_width_pcie_x4 = 4,
3273  	ixgbe_bus_width_pcie_x8 = 8,
3274  	ixgbe_bus_width_32      = 32,
3275  	ixgbe_bus_width_64      = 64,
3276  	ixgbe_bus_width_reserved
3277  };
3278  
3279  struct ixgbe_addr_filter_info {
3280  	u32 num_mc_addrs;
3281  	u32 rar_used_count;
3282  	u32 mta_in_use;
3283  	u32 overflow_promisc;
3284  	bool uc_set_promisc;
3285  	bool user_set_promisc;
3286  };
3287  
3288  /* Bus parameters */
3289  struct ixgbe_bus_info {
3290  	enum ixgbe_bus_speed speed;
3291  	enum ixgbe_bus_width width;
3292  	enum ixgbe_bus_type type;
3293  
3294  	u8 func;
3295  	u8 lan_id;
3296  	u8 instance_id;
3297  };
3298  
3299  /* Flow control parameters */
3300  struct ixgbe_fc_info {
3301  	u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */
3302  	u32 low_water[MAX_TRAFFIC_CLASS]; /* Flow Control Low-water */
3303  	u16 pause_time; /* Flow Control Pause timer */
3304  	bool send_xon; /* Flow control send XON */
3305  	bool strict_ieee; /* Strict IEEE mode */
3306  	bool disable_fc_autoneg; /* Do not autonegotiate FC */
3307  	bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
3308  	enum ixgbe_fc_mode current_mode; /* FC mode in effect */
3309  	enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
3310  };
3311  
3312  /* Statistics counters collected by the MAC */
3313  struct ixgbe_hw_stats {
3314  	u64 crcerrs;
3315  	u64 illerrc;
3316  	u64 errbc;
3317  	u64 mspdc;
3318  	u64 mpctotal;
3319  	u64 mpc[8];
3320  	u64 mlfc;
3321  	u64 mrfc;
3322  	u64 rlec;
3323  	u64 lxontxc;
3324  	u64 lxonrxc;
3325  	u64 lxofftxc;
3326  	u64 lxoffrxc;
3327  	u64 pxontxc[8];
3328  	u64 pxonrxc[8];
3329  	u64 pxofftxc[8];
3330  	u64 pxoffrxc[8];
3331  	u64 prc64;
3332  	u64 prc127;
3333  	u64 prc255;
3334  	u64 prc511;
3335  	u64 prc1023;
3336  	u64 prc1522;
3337  	u64 gprc;
3338  	u64 bprc;
3339  	u64 mprc;
3340  	u64 gptc;
3341  	u64 gorc;
3342  	u64 gotc;
3343  	u64 rnbc[8];
3344  	u64 ruc;
3345  	u64 rfc;
3346  	u64 roc;
3347  	u64 rjc;
3348  	u64 mngprc;
3349  	u64 mngpdc;
3350  	u64 mngptc;
3351  	u64 tor;
3352  	u64 tpr;
3353  	u64 tpt;
3354  	u64 ptc64;
3355  	u64 ptc127;
3356  	u64 ptc255;
3357  	u64 ptc511;
3358  	u64 ptc1023;
3359  	u64 ptc1522;
3360  	u64 mptc;
3361  	u64 bptc;
3362  	u64 xec;
3363  	u64 rqsmr[16];
3364  	u64 tqsmr[8];
3365  	u64 qprc[16];
3366  	u64 qptc[16];
3367  	u64 qbrc[16];
3368  	u64 qbtc[16];
3369  	u64 qprdc[16];
3370  	u64 pxon2offc[8];
3371  	u64 fdirustat_add;
3372  	u64 fdirustat_remove;
3373  	u64 fdirfstat_fadd;
3374  	u64 fdirfstat_fremove;
3375  	u64 fdirmatch;
3376  	u64 fdirmiss;
3377  	u64 fccrc;
3378  	u64 fcoerpdc;
3379  	u64 fcoeprc;
3380  	u64 fcoeptc;
3381  	u64 fcoedwrc;
3382  	u64 fcoedwtc;
3383  	u64 fcoe_noddp;
3384  	u64 fcoe_noddp_ext_buff;
3385  	u64 b2ospc;
3386  	u64 b2ogprc;
3387  	u64 o2bgptc;
3388  	u64 o2bspc;
3389  };
3390  
3391  /* forward declaration */
3392  struct ixgbe_hw;
3393  
3394  /* Function pointer table */
3395  struct ixgbe_eeprom_operations {
3396  	s32 (*init_params)(struct ixgbe_hw *);
3397  	s32 (*read)(struct ixgbe_hw *, u16, u16 *);
3398  	s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3399  	s32 (*write)(struct ixgbe_hw *, u16, u16);
3400  	s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3401  	s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
3402  	s32 (*update_checksum)(struct ixgbe_hw *);
3403  	s32 (*calc_checksum)(struct ixgbe_hw *);
3404  };
3405  
3406  struct ixgbe_mac_operations {
3407  	s32 (*init_hw)(struct ixgbe_hw *);
3408  	s32 (*reset_hw)(struct ixgbe_hw *);
3409  	s32 (*start_hw)(struct ixgbe_hw *);
3410  	s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
3411  	enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3412  	s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3413  	s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3414  	s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3415  	s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3416  	s32 (*stop_adapter)(struct ixgbe_hw *);
3417  	s32 (*get_bus_info)(struct ixgbe_hw *);
3418  	void (*set_lan_id)(struct ixgbe_hw *);
3419  	s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3420  	s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3421  	s32 (*setup_sfp)(struct ixgbe_hw *);
3422  	s32 (*disable_rx_buff)(struct ixgbe_hw *);
3423  	s32 (*enable_rx_buff)(struct ixgbe_hw *);
3424  	s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3425  	s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3426  	void (*release_swfw_sync)(struct ixgbe_hw *, u32);
3427  	void (*init_swfw_sync)(struct ixgbe_hw *);
3428  	s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3429  	s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3430  
3431  	/* Link */
3432  	void (*disable_tx_laser)(struct ixgbe_hw *);
3433  	void (*enable_tx_laser)(struct ixgbe_hw *);
3434  	void (*flap_tx_laser)(struct ixgbe_hw *);
3435  	void (*stop_link_on_d3)(struct ixgbe_hw *);
3436  	s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3437  	s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3438  	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3439  	s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3440  				     bool *);
3441  	void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3442  
3443  	/* Packet Buffer Manipulation */
3444  	void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
3445  
3446  	/* LED */
3447  	s32 (*led_on)(struct ixgbe_hw *, u32);
3448  	s32 (*led_off)(struct ixgbe_hw *, u32);
3449  	s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3450  	s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
3451  	s32 (*init_led_link_act)(struct ixgbe_hw *);
3452  
3453  	/* RAR, Multicast, VLAN */
3454  	s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3455  	s32 (*clear_rar)(struct ixgbe_hw *, u32);
3456  	s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3457  	s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3458  	s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3459  	s32 (*init_rx_addrs)(struct ixgbe_hw *);
3460  	s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
3461  	s32 (*enable_mc)(struct ixgbe_hw *);
3462  	s32 (*disable_mc)(struct ixgbe_hw *);
3463  	s32 (*clear_vfta)(struct ixgbe_hw *);
3464  	s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);
3465  	s32 (*init_uta_tables)(struct ixgbe_hw *);
3466  	void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3467  	void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3468  
3469  	/* Flow Control */
3470  	s32 (*fc_enable)(struct ixgbe_hw *);
3471  	s32 (*setup_fc)(struct ixgbe_hw *);
3472  	void (*fc_autoneg)(struct ixgbe_hw *);
3473  
3474  	/* Manageability interface */
3475  	s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16,
3476  			      const char *);
3477  	s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
3478  	s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
3479  	bool (*fw_recovery_mode)(struct ixgbe_hw *hw);
3480  	void (*disable_rx)(struct ixgbe_hw *hw);
3481  	void (*enable_rx)(struct ixgbe_hw *hw);
3482  	void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3483  					   unsigned int);
3484  	void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
3485  
3486  	/* DMA Coalescing */
3487  	s32 (*dmac_config)(struct ixgbe_hw *hw);
3488  	s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
3489  	s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
3490  	s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);
3491  	s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);
3492  };
3493  
3494  struct ixgbe_phy_operations {
3495  	s32 (*identify)(struct ixgbe_hw *);
3496  	s32 (*identify_sfp)(struct ixgbe_hw *);
3497  	s32 (*init)(struct ixgbe_hw *);
3498  	s32 (*reset)(struct ixgbe_hw *);
3499  	s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3500  	s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3501  	s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
3502  	s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
3503  	s32 (*setup_link)(struct ixgbe_hw *);
3504  	s32 (*setup_internal_link)(struct ixgbe_hw *);
3505  	s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3506  	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3507  	s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3508  	s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3509  	s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
3510  	s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3511  	s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3512  	bool (*check_overtemp)(struct ixgbe_hw *);
3513  	s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
3514  	s32 (*enter_lplu)(struct ixgbe_hw *);
3515  	s32 (*handle_lasi)(struct ixgbe_hw *hw, bool *);
3516  	s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3517  				      u8 *value);
3518  	s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3519  				       u8 value);
3520  };
3521  
3522  struct ixgbe_link_operations {
3523  	s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
3524  	s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3525  				  u16 *val);
3526  	s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
3527  	s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3528  				   u16 val);
3529  };
3530  
3531  struct ixgbe_link_info {
3532  	struct ixgbe_link_operations ops;
3533  	u8 addr;
3534  };
3535  
3536  struct ixgbe_eeprom_info {
3537  	struct ixgbe_eeprom_operations  ops;
3538  	enum ixgbe_eeprom_type          type;
3539  	u32                             semaphore_delay;
3540  	u16                             word_size;
3541  	u16                             address_bits;
3542  	u16                             word_page_size;
3543  	u16				ctrl_word_3;
3544  };
3545  
3546  #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED	0x01
3547  struct ixgbe_mac_info {
3548  	struct ixgbe_mac_operations     ops;
3549  	enum ixgbe_mac_type             type;
3550  	u8                              addr[ETH_ALEN];
3551  	u8                              perm_addr[ETH_ALEN];
3552  	u8                              san_addr[ETH_ALEN];
3553  	/* prefix for World Wide Node Name (WWNN) */
3554  	u16                             wwnn_prefix;
3555  	/* prefix for World Wide Port Name (WWPN) */
3556  	u16                             wwpn_prefix;
3557  	u16				max_msix_vectors;
3558  #define IXGBE_MAX_MTA			128
3559  	u32				mta_shadow[IXGBE_MAX_MTA];
3560  	s32                             mc_filter_type;
3561  	u32                             mcft_size;
3562  	u32                             vft_size;
3563  	u32                             num_rar_entries;
3564  	u32                             rar_highwater;
3565  	u32				rx_pb_size;
3566  	u32                             max_tx_queues;
3567  	u32                             max_rx_queues;
3568  	u32                             orig_autoc;
3569  	u32                             orig_autoc2;
3570  	bool                            orig_link_settings_stored;
3571  	bool                            autotry_restart;
3572  	u8                              flags;
3573  	u8				san_mac_rar_index;
3574  	struct ixgbe_thermal_sensor_data  thermal_sensor_data;
3575  	bool				set_lben;
3576  	u8				led_link_act;
3577  };
3578  
3579  struct ixgbe_phy_info {
3580  	struct ixgbe_phy_operations     ops;
3581  	struct mdio_if_info		mdio;
3582  	enum ixgbe_phy_type             type;
3583  	u32                             id;
3584  	enum ixgbe_sfp_type             sfp_type;
3585  	bool                            sfp_setup_needed;
3586  	u32                             revision;
3587  	enum ixgbe_media_type           media_type;
3588  	u32				phy_semaphore_mask;
3589  	bool                            reset_disable;
3590  	ixgbe_autoneg_advertised        autoneg_advertised;
3591  	ixgbe_link_speed		speeds_supported;
3592  	ixgbe_link_speed		eee_speeds_supported;
3593  	ixgbe_link_speed		eee_speeds_advertised;
3594  	enum ixgbe_smart_speed          smart_speed;
3595  	bool                            smart_speed_active;
3596  	bool                            multispeed_fiber;
3597  	bool                            reset_if_overtemp;
3598  	bool                            qsfp_shared_i2c_bus;
3599  	u32				nw_mng_if_sel;
3600  };
3601  
3602  #include "ixgbe_mbx.h"
3603  
3604  struct ixgbe_mbx_operations {
3605  	s32 (*init_params)(struct ixgbe_hw *hw);
3606  	s32 (*read)(struct ixgbe_hw *, u32 *, u16,  u16);
3607  	s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
3608  	s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16,  u16);
3609  	s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3610  	s32 (*check_for_msg)(struct ixgbe_hw *, u16);
3611  	s32 (*check_for_ack)(struct ixgbe_hw *, u16);
3612  	s32 (*check_for_rst)(struct ixgbe_hw *, u16);
3613  };
3614  
3615  struct ixgbe_mbx_stats {
3616  	u32 msgs_tx;
3617  	u32 msgs_rx;
3618  
3619  	u32 acks;
3620  	u32 reqs;
3621  	u32 rsts;
3622  };
3623  
3624  struct ixgbe_mbx_info {
3625  	const struct ixgbe_mbx_operations *ops;
3626  	struct ixgbe_mbx_stats stats;
3627  	u32 timeout;
3628  	u32 usec_delay;
3629  	u32 v2p_mailbox;
3630  	u16 size;
3631  };
3632  
3633  struct ixgbe_hw {
3634  	u8 __iomem			*hw_addr;
3635  	void				*back;
3636  	struct ixgbe_mac_info		mac;
3637  	struct ixgbe_addr_filter_info	addr_ctrl;
3638  	struct ixgbe_fc_info		fc;
3639  	struct ixgbe_phy_info		phy;
3640  	struct ixgbe_link_info		link;
3641  	struct ixgbe_eeprom_info	eeprom;
3642  	struct ixgbe_bus_info		bus;
3643  	struct ixgbe_mbx_info		mbx;
3644  	const u32			*mvals;
3645  	u16				device_id;
3646  	u16				vendor_id;
3647  	u16				subsystem_device_id;
3648  	u16				subsystem_vendor_id;
3649  	u8				revision_id;
3650  	bool				adapter_stopped;
3651  	bool				force_full_reset;
3652  	bool				allow_unsupported_sfp;
3653  	bool				wol_enabled;
3654  	bool				need_crosstalk_fix;
3655  };
3656  
3657  struct ixgbe_info {
3658  	enum ixgbe_mac_type		mac;
3659  	s32 				(*get_invariants)(struct ixgbe_hw *);
3660  	const struct ixgbe_mac_operations	*mac_ops;
3661  	const struct ixgbe_eeprom_operations	*eeprom_ops;
3662  	const struct ixgbe_phy_operations	*phy_ops;
3663  	const struct ixgbe_mbx_operations	*mbx_ops;
3664  	const struct ixgbe_link_operations	*link_ops;
3665  	const u32			*mvals;
3666  };
3667  
3668  #define IXGBE_FUSES0_GROUP(_i)		(0x11158 + ((_i) * 4))
3669  #define IXGBE_FUSES0_300MHZ		BIT(5)
3670  #define IXGBE_FUSES0_REV_MASK		(3u << 6)
3671  
3672  #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)	((P) ? 0x8010 : 0x4010)
3673  #define IXGBE_KRM_LINK_S1(P)		((P) ? 0x8200 : 0x4200)
3674  #define IXGBE_KRM_LINK_CTRL_1(P)	((P) ? 0x820C : 0x420C)
3675  #define IXGBE_KRM_AN_CNTL_1(P)		((P) ? 0x822C : 0x422C)
3676  #define IXGBE_KRM_AN_CNTL_8(P)		((P) ? 0x8248 : 0x4248)
3677  #define IXGBE_KRM_SGMII_CTRL(P)		((P) ? 0x82A0 : 0x42A0)
3678  #define IXGBE_KRM_LP_BASE_PAGE_HIGH(P)	((P) ? 0x836C : 0x436C)
3679  #define IXGBE_KRM_DSP_TXFFE_STATE_4(P)	((P) ? 0x8634 : 0x4634)
3680  #define IXGBE_KRM_DSP_TXFFE_STATE_5(P)	((P) ? 0x8638 : 0x4638)
3681  #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)	((P) ? 0x8B00 : 0x4B00)
3682  #define IXGBE_KRM_PMD_DFX_BURNIN(P)	((P) ? 0x8E00 : 0x4E00)
3683  #define IXGBE_KRM_PMD_FLX_MASK_ST20(P)	((P) ? 0x9054 : 0x5054)
3684  #define IXGBE_KRM_TX_COEFF_CTRL_1(P)	((P) ? 0x9520 : 0x5520)
3685  #define IXGBE_KRM_RX_ANA_CTL(P)		((P) ? 0x9A00 : 0x5A00)
3686  
3687  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA		~(0x3 << 20)
3688  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR		BIT(20)
3689  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR		(0x2 << 20)
3690  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN		BIT(25)
3691  #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN		BIT(26)
3692  #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN		BIT(27)
3693  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M		~(0x7 << 28)
3694  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M		BIT(28)
3695  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G		(0x2 << 28)
3696  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G		(0x3 << 28)
3697  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN		(0x4 << 28)
3698  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G		(0x7 << 28)
3699  #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK		(0x7 << 28)
3700  #define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART	BIT(31)
3701  
3702  #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B		BIT(9)
3703  #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS		BIT(11)
3704  
3705  #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK	(7u << 8)
3706  #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G	(2u << 8)
3707  #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G	(4u << 8)
3708  #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN		BIT(12)
3709  #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN	BIT(13)
3710  #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ		BIT(14)
3711  #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC		BIT(15)
3712  #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX		BIT(16)
3713  #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR		BIT(18)
3714  #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX		BIT(24)
3715  #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR		BIT(26)
3716  #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE		BIT(28)
3717  #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE		BIT(29)
3718  #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART		BIT(31)
3719  
3720  #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE			BIT(28)
3721  #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE			BIT(29)
3722  
3723  #define IXGBE_KRM_AN_CNTL_8_LINEAR			BIT(0)
3724  #define IXGBE_KRM_AN_CNTL_8_LIMITING			BIT(1)
3725  
3726  #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE		BIT(10)
3727  #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE		BIT(11)
3728  #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D	BIT(12)
3729  #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D		BIT(19)
3730  
3731  #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN			BIT(6)
3732  #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN		BIT(15)
3733  #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN		BIT(16)
3734  
3735  #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL	BIT(4)
3736  #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS	BIT(2)
3737  
3738  #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK	(3u << 16)
3739  
3740  #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN	BIT(1)
3741  #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN	BIT(2)
3742  #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN		BIT(3)
3743  #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN		BIT(31)
3744  
3745  #define IXGBE_SB_IOSF_INDIRECT_CTRL		0x00011144
3746  #define IXGBE_SB_IOSF_INDIRECT_DATA		0x00011148
3747  
3748  #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT		0
3749  #define IXGBE_SB_IOSF_CTRL_ADDR_MASK		0xFF
3750  #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT	18
3751  #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
3752  				(0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
3753  #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT	20
3754  #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
3755  				(0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
3756  #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT	28
3757  #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK	0x7
3758  #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT		31
3759  #define IXGBE_SB_IOSF_CTRL_BUSY		BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
3760  #define IXGBE_SB_IOSF_TARGET_KR_PHY	0
3761  
3762  #define IXGBE_NW_MNG_IF_SEL		0x00011178
3763  #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT		BIT(1)
3764  #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M	BIT(17)
3765  #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M	BIT(18)
3766  #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G	BIT(19)
3767  #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G	BIT(20)
3768  #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G	BIT(21)
3769  #define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE	BIT(25)
3770  #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE	BIT(24) /* X552 only */
3771  #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT	3
3772  #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD	\
3773  				(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
3774  #endif /* _IXGBE_TYPE_H_ */
3775