1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Azoteq IQS7222A/B/C/D Capacitive Touch Controller
4 *
5 * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com>
6 */
7
8 #include <linux/bits.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/input.h>
15 #include <linux/input/touchscreen.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/ktime.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/property.h>
22 #include <linux/slab.h>
23 #include <asm/unaligned.h>
24
25 #define IQS7222_PROD_NUM 0x00
26 #define IQS7222_PROD_NUM_A 840
27 #define IQS7222_PROD_NUM_B 698
28 #define IQS7222_PROD_NUM_C 863
29 #define IQS7222_PROD_NUM_D 1046
30
31 #define IQS7222_SYS_STATUS 0x10
32 #define IQS7222_SYS_STATUS_RESET BIT(3)
33 #define IQS7222_SYS_STATUS_ATI_ERROR BIT(1)
34 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
35
36 #define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14)
37 #define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15)
38 #define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14)
39 #define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8)
40
41 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
42 #define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8)
43 #define IQS7222_SLDR_SETUP_2_RES_SHIFT 8
44 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
45
46 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
47
48 #define IQS7222_SYS_SETUP 0xD0
49 #define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6)
50 #define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7)
51 #define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6)
52 #define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4)
53 #define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK
54 #define IQS7222_SYS_SETUP_REDO_ATI BIT(2)
55 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
56
57 #define IQS7222_EVENT_MASK_ATI BIT(12)
58 #define IQS7222_EVENT_MASK_SLDR BIT(10)
59 #define IQS7222_EVENT_MASK_TPAD IQS7222_EVENT_MASK_SLDR
60 #define IQS7222_EVENT_MASK_TOUCH BIT(1)
61 #define IQS7222_EVENT_MASK_PROX BIT(0)
62
63 #define IQS7222_COMMS_HOLD BIT(0)
64 #define IQS7222_COMMS_ERROR 0xEEEE
65 #define IQS7222_COMMS_RETRY_MS 50
66 #define IQS7222_COMMS_TIMEOUT_MS 100
67 #define IQS7222_RESET_TIMEOUT_MS 250
68 #define IQS7222_ATI_TIMEOUT_MS 2000
69
70 #define IQS7222_MAX_COLS_STAT 8
71 #define IQS7222_MAX_COLS_CYCLE 3
72 #define IQS7222_MAX_COLS_GLBL 3
73 #define IQS7222_MAX_COLS_BTN 3
74 #define IQS7222_MAX_COLS_CHAN 6
75 #define IQS7222_MAX_COLS_FILT 2
76 #define IQS7222_MAX_COLS_SLDR 11
77 #define IQS7222_MAX_COLS_TPAD 24
78 #define IQS7222_MAX_COLS_GPIO 3
79 #define IQS7222_MAX_COLS_SYS 13
80
81 #define IQS7222_MAX_CHAN 20
82 #define IQS7222_MAX_SLDR 2
83
84 #define IQS7222_NUM_RETRIES 5
85 #define IQS7222_REG_OFFSET 0x100
86
87 enum iqs7222_reg_key_id {
88 IQS7222_REG_KEY_NONE,
89 IQS7222_REG_KEY_PROX,
90 IQS7222_REG_KEY_TOUCH,
91 IQS7222_REG_KEY_DEBOUNCE,
92 IQS7222_REG_KEY_TAP,
93 IQS7222_REG_KEY_TAP_LEGACY,
94 IQS7222_REG_KEY_AXIAL,
95 IQS7222_REG_KEY_AXIAL_LEGACY,
96 IQS7222_REG_KEY_WHEEL,
97 IQS7222_REG_KEY_NO_WHEEL,
98 IQS7222_REG_KEY_RESERVED
99 };
100
101 enum iqs7222_reg_grp_id {
102 IQS7222_REG_GRP_STAT,
103 IQS7222_REG_GRP_CYCLE,
104 IQS7222_REG_GRP_GLBL,
105 IQS7222_REG_GRP_BTN,
106 IQS7222_REG_GRP_CHAN,
107 IQS7222_REG_GRP_FILT,
108 IQS7222_REG_GRP_SLDR,
109 IQS7222_REG_GRP_TPAD,
110 IQS7222_REG_GRP_GPIO,
111 IQS7222_REG_GRP_SYS,
112 IQS7222_NUM_REG_GRPS
113 };
114
115 static const char * const iqs7222_reg_grp_names[IQS7222_NUM_REG_GRPS] = {
116 [IQS7222_REG_GRP_CYCLE] = "cycle-%d",
117 [IQS7222_REG_GRP_CHAN] = "channel-%d",
118 [IQS7222_REG_GRP_SLDR] = "slider-%d",
119 [IQS7222_REG_GRP_TPAD] = "trackpad",
120 [IQS7222_REG_GRP_GPIO] = "gpio-%d",
121 };
122
123 static const unsigned int iqs7222_max_cols[IQS7222_NUM_REG_GRPS] = {
124 [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT,
125 [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE,
126 [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL,
127 [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN,
128 [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN,
129 [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT,
130 [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR,
131 [IQS7222_REG_GRP_TPAD] = IQS7222_MAX_COLS_TPAD,
132 [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO,
133 [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS,
134 };
135
136 static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, };
137
138 struct iqs7222_event_desc {
139 const char *name;
140 u16 link;
141 u16 mask;
142 u16 val;
143 u16 strict;
144 u16 enable;
145 enum iqs7222_reg_key_id reg_key;
146 };
147
148 static const struct iqs7222_event_desc iqs7222_kp_events[] = {
149 {
150 .name = "event-prox",
151 .enable = IQS7222_EVENT_MASK_PROX,
152 .reg_key = IQS7222_REG_KEY_PROX,
153 },
154 {
155 .name = "event-touch",
156 .enable = IQS7222_EVENT_MASK_TOUCH,
157 .reg_key = IQS7222_REG_KEY_TOUCH,
158 },
159 };
160
161 static const struct iqs7222_event_desc iqs7222_sl_events[] = {
162 { .name = "event-press", },
163 {
164 .name = "event-tap",
165 .mask = BIT(0),
166 .val = BIT(0),
167 .enable = BIT(0),
168 .reg_key = IQS7222_REG_KEY_TAP,
169 },
170 {
171 .name = "event-swipe-pos",
172 .mask = BIT(5) | BIT(1),
173 .val = BIT(1),
174 .enable = BIT(1),
175 .reg_key = IQS7222_REG_KEY_AXIAL,
176 },
177 {
178 .name = "event-swipe-neg",
179 .mask = BIT(5) | BIT(1),
180 .val = BIT(5) | BIT(1),
181 .enable = BIT(1),
182 .reg_key = IQS7222_REG_KEY_AXIAL,
183 },
184 {
185 .name = "event-flick-pos",
186 .mask = BIT(5) | BIT(2),
187 .val = BIT(2),
188 .enable = BIT(2),
189 .reg_key = IQS7222_REG_KEY_AXIAL,
190 },
191 {
192 .name = "event-flick-neg",
193 .mask = BIT(5) | BIT(2),
194 .val = BIT(5) | BIT(2),
195 .enable = BIT(2),
196 .reg_key = IQS7222_REG_KEY_AXIAL,
197 },
198 };
199
200 static const struct iqs7222_event_desc iqs7222_tp_events[] = {
201 {
202 .name = "event-press",
203 .link = BIT(7),
204 },
205 {
206 .name = "event-tap",
207 .link = BIT(0),
208 .mask = BIT(0),
209 .val = BIT(0),
210 .enable = BIT(0),
211 .reg_key = IQS7222_REG_KEY_TAP,
212 },
213 {
214 .name = "event-swipe-x-pos",
215 .link = BIT(2),
216 .mask = BIT(2) | BIT(1),
217 .val = BIT(2),
218 .strict = BIT(4),
219 .enable = BIT(1),
220 .reg_key = IQS7222_REG_KEY_AXIAL,
221 },
222 {
223 .name = "event-swipe-y-pos",
224 .link = BIT(3),
225 .mask = BIT(3) | BIT(1),
226 .val = BIT(3),
227 .strict = BIT(3),
228 .enable = BIT(1),
229 .reg_key = IQS7222_REG_KEY_AXIAL,
230 },
231 {
232 .name = "event-swipe-x-neg",
233 .link = BIT(4),
234 .mask = BIT(4) | BIT(1),
235 .val = BIT(4),
236 .strict = BIT(4),
237 .enable = BIT(1),
238 .reg_key = IQS7222_REG_KEY_AXIAL,
239 },
240 {
241 .name = "event-swipe-y-neg",
242 .link = BIT(5),
243 .mask = BIT(5) | BIT(1),
244 .val = BIT(5),
245 .strict = BIT(3),
246 .enable = BIT(1),
247 .reg_key = IQS7222_REG_KEY_AXIAL,
248 },
249 {
250 .name = "event-flick-x-pos",
251 .link = BIT(2),
252 .mask = BIT(2) | BIT(1),
253 .val = BIT(2) | BIT(1),
254 .strict = BIT(4),
255 .enable = BIT(2),
256 .reg_key = IQS7222_REG_KEY_AXIAL,
257 },
258 {
259 .name = "event-flick-y-pos",
260 .link = BIT(3),
261 .mask = BIT(3) | BIT(1),
262 .val = BIT(3) | BIT(1),
263 .strict = BIT(3),
264 .enable = BIT(2),
265 .reg_key = IQS7222_REG_KEY_AXIAL,
266 },
267 {
268 .name = "event-flick-x-neg",
269 .link = BIT(4),
270 .mask = BIT(4) | BIT(1),
271 .val = BIT(4) | BIT(1),
272 .strict = BIT(4),
273 .enable = BIT(2),
274 .reg_key = IQS7222_REG_KEY_AXIAL,
275 },
276 {
277 .name = "event-flick-y-neg",
278 .link = BIT(5),
279 .mask = BIT(5) | BIT(1),
280 .val = BIT(5) | BIT(1),
281 .strict = BIT(3),
282 .enable = BIT(2),
283 .reg_key = IQS7222_REG_KEY_AXIAL,
284 },
285 };
286
287 struct iqs7222_reg_grp_desc {
288 u16 base;
289 u16 val_len;
290 int num_row;
291 int num_col;
292 };
293
294 struct iqs7222_dev_desc {
295 u16 prod_num;
296 u16 fw_major;
297 u16 fw_minor;
298 u16 sldr_res;
299 u16 touch_link;
300 u16 wheel_enable;
301 int allow_offset;
302 int event_offset;
303 int comms_offset;
304 bool legacy_gesture;
305 struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS];
306 };
307
308 static const struct iqs7222_dev_desc iqs7222_devs[] = {
309 {
310 .prod_num = IQS7222_PROD_NUM_A,
311 .fw_major = 1,
312 .fw_minor = 13,
313 .sldr_res = U8_MAX * 16,
314 .touch_link = 1768,
315 .allow_offset = 9,
316 .event_offset = 10,
317 .comms_offset = 12,
318 .reg_grps = {
319 [IQS7222_REG_GRP_STAT] = {
320 .base = IQS7222_SYS_STATUS,
321 .num_row = 1,
322 .num_col = 8,
323 },
324 [IQS7222_REG_GRP_CYCLE] = {
325 .base = 0x8000,
326 .num_row = 7,
327 .num_col = 3,
328 },
329 [IQS7222_REG_GRP_GLBL] = {
330 .base = 0x8700,
331 .num_row = 1,
332 .num_col = 3,
333 },
334 [IQS7222_REG_GRP_BTN] = {
335 .base = 0x9000,
336 .num_row = 12,
337 .num_col = 3,
338 },
339 [IQS7222_REG_GRP_CHAN] = {
340 .base = 0xA000,
341 .num_row = 12,
342 .num_col = 6,
343 },
344 [IQS7222_REG_GRP_FILT] = {
345 .base = 0xAC00,
346 .val_len = 3,
347 .num_row = 1,
348 .num_col = 2,
349 },
350 [IQS7222_REG_GRP_SLDR] = {
351 .base = 0xB000,
352 .num_row = 2,
353 .num_col = 11,
354 },
355 [IQS7222_REG_GRP_GPIO] = {
356 .base = 0xC000,
357 .num_row = 1,
358 .num_col = 3,
359 },
360 [IQS7222_REG_GRP_SYS] = {
361 .base = IQS7222_SYS_SETUP,
362 .num_row = 1,
363 .num_col = 13,
364 },
365 },
366 },
367 {
368 .prod_num = IQS7222_PROD_NUM_A,
369 .fw_major = 1,
370 .fw_minor = 12,
371 .sldr_res = U8_MAX * 16,
372 .touch_link = 1768,
373 .allow_offset = 9,
374 .event_offset = 10,
375 .comms_offset = 12,
376 .legacy_gesture = true,
377 .reg_grps = {
378 [IQS7222_REG_GRP_STAT] = {
379 .base = IQS7222_SYS_STATUS,
380 .num_row = 1,
381 .num_col = 8,
382 },
383 [IQS7222_REG_GRP_CYCLE] = {
384 .base = 0x8000,
385 .num_row = 7,
386 .num_col = 3,
387 },
388 [IQS7222_REG_GRP_GLBL] = {
389 .base = 0x8700,
390 .num_row = 1,
391 .num_col = 3,
392 },
393 [IQS7222_REG_GRP_BTN] = {
394 .base = 0x9000,
395 .num_row = 12,
396 .num_col = 3,
397 },
398 [IQS7222_REG_GRP_CHAN] = {
399 .base = 0xA000,
400 .num_row = 12,
401 .num_col = 6,
402 },
403 [IQS7222_REG_GRP_FILT] = {
404 .base = 0xAC00,
405 .val_len = 3,
406 .num_row = 1,
407 .num_col = 2,
408 },
409 [IQS7222_REG_GRP_SLDR] = {
410 .base = 0xB000,
411 .num_row = 2,
412 .num_col = 11,
413 },
414 [IQS7222_REG_GRP_GPIO] = {
415 .base = 0xC000,
416 .num_row = 1,
417 .num_col = 3,
418 },
419 [IQS7222_REG_GRP_SYS] = {
420 .base = IQS7222_SYS_SETUP,
421 .num_row = 1,
422 .num_col = 13,
423 },
424 },
425 },
426 {
427 .prod_num = IQS7222_PROD_NUM_B,
428 .fw_major = 1,
429 .fw_minor = 43,
430 .event_offset = 10,
431 .comms_offset = 11,
432 .reg_grps = {
433 [IQS7222_REG_GRP_STAT] = {
434 .base = IQS7222_SYS_STATUS,
435 .num_row = 1,
436 .num_col = 6,
437 },
438 [IQS7222_REG_GRP_CYCLE] = {
439 .base = 0x8000,
440 .num_row = 10,
441 .num_col = 2,
442 },
443 [IQS7222_REG_GRP_GLBL] = {
444 .base = 0x8A00,
445 .num_row = 1,
446 .num_col = 3,
447 },
448 [IQS7222_REG_GRP_BTN] = {
449 .base = 0x9000,
450 .num_row = 20,
451 .num_col = 2,
452 },
453 [IQS7222_REG_GRP_CHAN] = {
454 .base = 0xB000,
455 .num_row = 20,
456 .num_col = 4,
457 },
458 [IQS7222_REG_GRP_FILT] = {
459 .base = 0xC400,
460 .val_len = 3,
461 .num_row = 1,
462 .num_col = 2,
463 },
464 [IQS7222_REG_GRP_SYS] = {
465 .base = IQS7222_SYS_SETUP,
466 .num_row = 1,
467 .num_col = 13,
468 },
469 },
470 },
471 {
472 .prod_num = IQS7222_PROD_NUM_B,
473 .fw_major = 1,
474 .fw_minor = 27,
475 .reg_grps = {
476 [IQS7222_REG_GRP_STAT] = {
477 .base = IQS7222_SYS_STATUS,
478 .num_row = 1,
479 .num_col = 6,
480 },
481 [IQS7222_REG_GRP_CYCLE] = {
482 .base = 0x8000,
483 .num_row = 10,
484 .num_col = 2,
485 },
486 [IQS7222_REG_GRP_GLBL] = {
487 .base = 0x8A00,
488 .num_row = 1,
489 .num_col = 3,
490 },
491 [IQS7222_REG_GRP_BTN] = {
492 .base = 0x9000,
493 .num_row = 20,
494 .num_col = 2,
495 },
496 [IQS7222_REG_GRP_CHAN] = {
497 .base = 0xB000,
498 .num_row = 20,
499 .num_col = 4,
500 },
501 [IQS7222_REG_GRP_FILT] = {
502 .base = 0xC400,
503 .val_len = 3,
504 .num_row = 1,
505 .num_col = 2,
506 },
507 [IQS7222_REG_GRP_SYS] = {
508 .base = IQS7222_SYS_SETUP,
509 .num_row = 1,
510 .num_col = 10,
511 },
512 },
513 },
514 {
515 .prod_num = IQS7222_PROD_NUM_C,
516 .fw_major = 2,
517 .fw_minor = 6,
518 .sldr_res = U16_MAX,
519 .touch_link = 1686,
520 .wheel_enable = BIT(3),
521 .event_offset = 9,
522 .comms_offset = 10,
523 .reg_grps = {
524 [IQS7222_REG_GRP_STAT] = {
525 .base = IQS7222_SYS_STATUS,
526 .num_row = 1,
527 .num_col = 6,
528 },
529 [IQS7222_REG_GRP_CYCLE] = {
530 .base = 0x8000,
531 .num_row = 5,
532 .num_col = 3,
533 },
534 [IQS7222_REG_GRP_GLBL] = {
535 .base = 0x8500,
536 .num_row = 1,
537 .num_col = 3,
538 },
539 [IQS7222_REG_GRP_BTN] = {
540 .base = 0x9000,
541 .num_row = 10,
542 .num_col = 3,
543 },
544 [IQS7222_REG_GRP_CHAN] = {
545 .base = 0xA000,
546 .num_row = 10,
547 .num_col = 6,
548 },
549 [IQS7222_REG_GRP_FILT] = {
550 .base = 0xAA00,
551 .val_len = 3,
552 .num_row = 1,
553 .num_col = 2,
554 },
555 [IQS7222_REG_GRP_SLDR] = {
556 .base = 0xB000,
557 .num_row = 2,
558 .num_col = 10,
559 },
560 [IQS7222_REG_GRP_GPIO] = {
561 .base = 0xC000,
562 .num_row = 3,
563 .num_col = 3,
564 },
565 [IQS7222_REG_GRP_SYS] = {
566 .base = IQS7222_SYS_SETUP,
567 .num_row = 1,
568 .num_col = 12,
569 },
570 },
571 },
572 {
573 .prod_num = IQS7222_PROD_NUM_C,
574 .fw_major = 1,
575 .fw_minor = 13,
576 .sldr_res = U16_MAX,
577 .touch_link = 1674,
578 .wheel_enable = BIT(3),
579 .event_offset = 9,
580 .comms_offset = 10,
581 .reg_grps = {
582 [IQS7222_REG_GRP_STAT] = {
583 .base = IQS7222_SYS_STATUS,
584 .num_row = 1,
585 .num_col = 6,
586 },
587 [IQS7222_REG_GRP_CYCLE] = {
588 .base = 0x8000,
589 .num_row = 5,
590 .num_col = 3,
591 },
592 [IQS7222_REG_GRP_GLBL] = {
593 .base = 0x8500,
594 .num_row = 1,
595 .num_col = 3,
596 },
597 [IQS7222_REG_GRP_BTN] = {
598 .base = 0x9000,
599 .num_row = 10,
600 .num_col = 3,
601 },
602 [IQS7222_REG_GRP_CHAN] = {
603 .base = 0xA000,
604 .num_row = 10,
605 .num_col = 6,
606 },
607 [IQS7222_REG_GRP_FILT] = {
608 .base = 0xAA00,
609 .val_len = 3,
610 .num_row = 1,
611 .num_col = 2,
612 },
613 [IQS7222_REG_GRP_SLDR] = {
614 .base = 0xB000,
615 .num_row = 2,
616 .num_col = 10,
617 },
618 [IQS7222_REG_GRP_GPIO] = {
619 .base = 0xC000,
620 .num_row = 1,
621 .num_col = 3,
622 },
623 [IQS7222_REG_GRP_SYS] = {
624 .base = IQS7222_SYS_SETUP,
625 .num_row = 1,
626 .num_col = 11,
627 },
628 },
629 },
630 {
631 .prod_num = IQS7222_PROD_NUM_D,
632 .fw_major = 1,
633 .fw_minor = 2,
634 .touch_link = 1770,
635 .allow_offset = 9,
636 .event_offset = 10,
637 .comms_offset = 11,
638 .reg_grps = {
639 [IQS7222_REG_GRP_STAT] = {
640 .base = IQS7222_SYS_STATUS,
641 .num_row = 1,
642 .num_col = 7,
643 },
644 [IQS7222_REG_GRP_CYCLE] = {
645 .base = 0x8000,
646 .num_row = 7,
647 .num_col = 2,
648 },
649 [IQS7222_REG_GRP_GLBL] = {
650 .base = 0x8700,
651 .num_row = 1,
652 .num_col = 3,
653 },
654 [IQS7222_REG_GRP_BTN] = {
655 .base = 0x9000,
656 .num_row = 14,
657 .num_col = 3,
658 },
659 [IQS7222_REG_GRP_CHAN] = {
660 .base = 0xA000,
661 .num_row = 14,
662 .num_col = 4,
663 },
664 [IQS7222_REG_GRP_FILT] = {
665 .base = 0xAE00,
666 .val_len = 3,
667 .num_row = 1,
668 .num_col = 2,
669 },
670 [IQS7222_REG_GRP_TPAD] = {
671 .base = 0xB000,
672 .num_row = 1,
673 .num_col = 24,
674 },
675 [IQS7222_REG_GRP_GPIO] = {
676 .base = 0xC000,
677 .num_row = 3,
678 .num_col = 3,
679 },
680 [IQS7222_REG_GRP_SYS] = {
681 .base = IQS7222_SYS_SETUP,
682 .num_row = 1,
683 .num_col = 12,
684 },
685 },
686 },
687 {
688 .prod_num = IQS7222_PROD_NUM_D,
689 .fw_major = 1,
690 .fw_minor = 1,
691 .touch_link = 1774,
692 .allow_offset = 9,
693 .event_offset = 10,
694 .comms_offset = 11,
695 .reg_grps = {
696 [IQS7222_REG_GRP_STAT] = {
697 .base = IQS7222_SYS_STATUS,
698 .num_row = 1,
699 .num_col = 7,
700 },
701 [IQS7222_REG_GRP_CYCLE] = {
702 .base = 0x8000,
703 .num_row = 7,
704 .num_col = 2,
705 },
706 [IQS7222_REG_GRP_GLBL] = {
707 .base = 0x8700,
708 .num_row = 1,
709 .num_col = 3,
710 },
711 [IQS7222_REG_GRP_BTN] = {
712 .base = 0x9000,
713 .num_row = 14,
714 .num_col = 3,
715 },
716 [IQS7222_REG_GRP_CHAN] = {
717 .base = 0xA000,
718 .num_row = 14,
719 .num_col = 4,
720 },
721 [IQS7222_REG_GRP_FILT] = {
722 .base = 0xAE00,
723 .val_len = 3,
724 .num_row = 1,
725 .num_col = 2,
726 },
727 [IQS7222_REG_GRP_TPAD] = {
728 .base = 0xB000,
729 .num_row = 1,
730 .num_col = 24,
731 },
732 [IQS7222_REG_GRP_GPIO] = {
733 .base = 0xC000,
734 .num_row = 3,
735 .num_col = 3,
736 },
737 [IQS7222_REG_GRP_SYS] = {
738 .base = IQS7222_SYS_SETUP,
739 .num_row = 1,
740 .num_col = 12,
741 },
742 },
743 },
744 {
745 .prod_num = IQS7222_PROD_NUM_D,
746 .fw_major = 0,
747 .fw_minor = 37,
748 .touch_link = 1770,
749 .allow_offset = 9,
750 .event_offset = 10,
751 .comms_offset = 11,
752 .reg_grps = {
753 [IQS7222_REG_GRP_STAT] = {
754 .base = IQS7222_SYS_STATUS,
755 .num_row = 1,
756 .num_col = 7,
757 },
758 [IQS7222_REG_GRP_CYCLE] = {
759 .base = 0x8000,
760 .num_row = 7,
761 .num_col = 2,
762 },
763 [IQS7222_REG_GRP_GLBL] = {
764 .base = 0x8700,
765 .num_row = 1,
766 .num_col = 3,
767 },
768 [IQS7222_REG_GRP_BTN] = {
769 .base = 0x9000,
770 .num_row = 14,
771 .num_col = 3,
772 },
773 [IQS7222_REG_GRP_CHAN] = {
774 .base = 0xA000,
775 .num_row = 14,
776 .num_col = 4,
777 },
778 [IQS7222_REG_GRP_FILT] = {
779 .base = 0xAE00,
780 .val_len = 3,
781 .num_row = 1,
782 .num_col = 2,
783 },
784 [IQS7222_REG_GRP_TPAD] = {
785 .base = 0xB000,
786 .num_row = 1,
787 .num_col = 24,
788 },
789 [IQS7222_REG_GRP_GPIO] = {
790 .base = 0xC000,
791 .num_row = 3,
792 .num_col = 3,
793 },
794 [IQS7222_REG_GRP_SYS] = {
795 .base = IQS7222_SYS_SETUP,
796 .num_row = 1,
797 .num_col = 12,
798 },
799 },
800 },
801 };
802
803 struct iqs7222_prop_desc {
804 const char *name;
805 enum iqs7222_reg_grp_id reg_grp;
806 enum iqs7222_reg_key_id reg_key;
807 int reg_offset;
808 int reg_shift;
809 int reg_width;
810 int val_pitch;
811 int val_min;
812 int val_max;
813 bool invert;
814 const char *label;
815 };
816
817 static const struct iqs7222_prop_desc iqs7222_props[] = {
818 {
819 .name = "azoteq,conv-period",
820 .reg_grp = IQS7222_REG_GRP_CYCLE,
821 .reg_offset = 0,
822 .reg_shift = 8,
823 .reg_width = 8,
824 .label = "conversion period",
825 },
826 {
827 .name = "azoteq,conv-frac",
828 .reg_grp = IQS7222_REG_GRP_CYCLE,
829 .reg_offset = 0,
830 .reg_shift = 0,
831 .reg_width = 8,
832 .label = "conversion frequency fractional divider",
833 },
834 {
835 .name = "azoteq,rx-float-inactive",
836 .reg_grp = IQS7222_REG_GRP_CYCLE,
837 .reg_offset = 1,
838 .reg_shift = 6,
839 .reg_width = 1,
840 .invert = true,
841 },
842 {
843 .name = "azoteq,dead-time-enable",
844 .reg_grp = IQS7222_REG_GRP_CYCLE,
845 .reg_offset = 1,
846 .reg_shift = 5,
847 .reg_width = 1,
848 },
849 {
850 .name = "azoteq,tx-freq-fosc",
851 .reg_grp = IQS7222_REG_GRP_CYCLE,
852 .reg_offset = 1,
853 .reg_shift = 4,
854 .reg_width = 1,
855 },
856 {
857 .name = "azoteq,vbias-enable",
858 .reg_grp = IQS7222_REG_GRP_CYCLE,
859 .reg_offset = 1,
860 .reg_shift = 3,
861 .reg_width = 1,
862 },
863 {
864 .name = "azoteq,sense-mode",
865 .reg_grp = IQS7222_REG_GRP_CYCLE,
866 .reg_offset = 1,
867 .reg_shift = 0,
868 .reg_width = 3,
869 .val_max = 3,
870 .label = "sensing mode",
871 },
872 {
873 .name = "azoteq,iref-enable",
874 .reg_grp = IQS7222_REG_GRP_CYCLE,
875 .reg_offset = 2,
876 .reg_shift = 10,
877 .reg_width = 1,
878 },
879 {
880 .name = "azoteq,iref-level",
881 .reg_grp = IQS7222_REG_GRP_CYCLE,
882 .reg_offset = 2,
883 .reg_shift = 4,
884 .reg_width = 4,
885 .label = "current reference level",
886 },
887 {
888 .name = "azoteq,iref-trim",
889 .reg_grp = IQS7222_REG_GRP_CYCLE,
890 .reg_offset = 2,
891 .reg_shift = 0,
892 .reg_width = 4,
893 .label = "current reference trim",
894 },
895 {
896 .name = "azoteq,max-counts",
897 .reg_grp = IQS7222_REG_GRP_GLBL,
898 .reg_offset = 0,
899 .reg_shift = 13,
900 .reg_width = 2,
901 .label = "maximum counts",
902 },
903 {
904 .name = "azoteq,auto-mode",
905 .reg_grp = IQS7222_REG_GRP_GLBL,
906 .reg_offset = 0,
907 .reg_shift = 2,
908 .reg_width = 2,
909 .label = "number of conversions",
910 },
911 {
912 .name = "azoteq,ati-frac-div-fine",
913 .reg_grp = IQS7222_REG_GRP_GLBL,
914 .reg_offset = 1,
915 .reg_shift = 9,
916 .reg_width = 5,
917 .label = "ATI fine fractional divider",
918 },
919 {
920 .name = "azoteq,ati-frac-div-coarse",
921 .reg_grp = IQS7222_REG_GRP_GLBL,
922 .reg_offset = 1,
923 .reg_shift = 0,
924 .reg_width = 5,
925 .label = "ATI coarse fractional divider",
926 },
927 {
928 .name = "azoteq,ati-comp-select",
929 .reg_grp = IQS7222_REG_GRP_GLBL,
930 .reg_offset = 2,
931 .reg_shift = 0,
932 .reg_width = 10,
933 .label = "ATI compensation selection",
934 },
935 {
936 .name = "azoteq,ati-band",
937 .reg_grp = IQS7222_REG_GRP_CHAN,
938 .reg_offset = 0,
939 .reg_shift = 12,
940 .reg_width = 2,
941 .label = "ATI band",
942 },
943 {
944 .name = "azoteq,global-halt",
945 .reg_grp = IQS7222_REG_GRP_CHAN,
946 .reg_offset = 0,
947 .reg_shift = 11,
948 .reg_width = 1,
949 },
950 {
951 .name = "azoteq,invert-enable",
952 .reg_grp = IQS7222_REG_GRP_CHAN,
953 .reg_offset = 0,
954 .reg_shift = 10,
955 .reg_width = 1,
956 },
957 {
958 .name = "azoteq,dual-direction",
959 .reg_grp = IQS7222_REG_GRP_CHAN,
960 .reg_offset = 0,
961 .reg_shift = 9,
962 .reg_width = 1,
963 },
964 {
965 .name = "azoteq,samp-cap-double",
966 .reg_grp = IQS7222_REG_GRP_CHAN,
967 .reg_offset = 0,
968 .reg_shift = 3,
969 .reg_width = 1,
970 },
971 {
972 .name = "azoteq,vref-half",
973 .reg_grp = IQS7222_REG_GRP_CHAN,
974 .reg_offset = 0,
975 .reg_shift = 2,
976 .reg_width = 1,
977 },
978 {
979 .name = "azoteq,proj-bias",
980 .reg_grp = IQS7222_REG_GRP_CHAN,
981 .reg_offset = 0,
982 .reg_shift = 0,
983 .reg_width = 2,
984 .label = "projected bias current",
985 },
986 {
987 .name = "azoteq,ati-target",
988 .reg_grp = IQS7222_REG_GRP_CHAN,
989 .reg_offset = 1,
990 .reg_shift = 8,
991 .reg_width = 8,
992 .val_pitch = 8,
993 .label = "ATI target",
994 },
995 {
996 .name = "azoteq,ati-base",
997 .reg_grp = IQS7222_REG_GRP_CHAN,
998 .reg_offset = 1,
999 .reg_shift = 3,
1000 .reg_width = 5,
1001 .val_pitch = 16,
1002 .label = "ATI base",
1003 },
1004 {
1005 .name = "azoteq,ati-mode",
1006 .reg_grp = IQS7222_REG_GRP_CHAN,
1007 .reg_offset = 1,
1008 .reg_shift = 0,
1009 .reg_width = 3,
1010 .val_max = 5,
1011 .label = "ATI mode",
1012 },
1013 {
1014 .name = "azoteq,ati-frac-div-fine",
1015 .reg_grp = IQS7222_REG_GRP_CHAN,
1016 .reg_offset = 2,
1017 .reg_shift = 9,
1018 .reg_width = 5,
1019 .label = "ATI fine fractional divider",
1020 },
1021 {
1022 .name = "azoteq,ati-frac-mult-coarse",
1023 .reg_grp = IQS7222_REG_GRP_CHAN,
1024 .reg_offset = 2,
1025 .reg_shift = 5,
1026 .reg_width = 4,
1027 .label = "ATI coarse fractional multiplier",
1028 },
1029 {
1030 .name = "azoteq,ati-frac-div-coarse",
1031 .reg_grp = IQS7222_REG_GRP_CHAN,
1032 .reg_offset = 2,
1033 .reg_shift = 0,
1034 .reg_width = 5,
1035 .label = "ATI coarse fractional divider",
1036 },
1037 {
1038 .name = "azoteq,ati-comp-div",
1039 .reg_grp = IQS7222_REG_GRP_CHAN,
1040 .reg_offset = 3,
1041 .reg_shift = 11,
1042 .reg_width = 5,
1043 .label = "ATI compensation divider",
1044 },
1045 {
1046 .name = "azoteq,ati-comp-select",
1047 .reg_grp = IQS7222_REG_GRP_CHAN,
1048 .reg_offset = 3,
1049 .reg_shift = 0,
1050 .reg_width = 10,
1051 .label = "ATI compensation selection",
1052 },
1053 {
1054 .name = "azoteq,debounce-exit",
1055 .reg_grp = IQS7222_REG_GRP_BTN,
1056 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
1057 .reg_offset = 0,
1058 .reg_shift = 12,
1059 .reg_width = 4,
1060 .label = "debounce exit factor",
1061 },
1062 {
1063 .name = "azoteq,debounce-enter",
1064 .reg_grp = IQS7222_REG_GRP_BTN,
1065 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
1066 .reg_offset = 0,
1067 .reg_shift = 8,
1068 .reg_width = 4,
1069 .label = "debounce entrance factor",
1070 },
1071 {
1072 .name = "azoteq,thresh",
1073 .reg_grp = IQS7222_REG_GRP_BTN,
1074 .reg_key = IQS7222_REG_KEY_PROX,
1075 .reg_offset = 0,
1076 .reg_shift = 0,
1077 .reg_width = 8,
1078 .val_max = 127,
1079 .label = "threshold",
1080 },
1081 {
1082 .name = "azoteq,thresh",
1083 .reg_grp = IQS7222_REG_GRP_BTN,
1084 .reg_key = IQS7222_REG_KEY_TOUCH,
1085 .reg_offset = 1,
1086 .reg_shift = 0,
1087 .reg_width = 8,
1088 .label = "threshold",
1089 },
1090 {
1091 .name = "azoteq,hyst",
1092 .reg_grp = IQS7222_REG_GRP_BTN,
1093 .reg_key = IQS7222_REG_KEY_TOUCH,
1094 .reg_offset = 1,
1095 .reg_shift = 8,
1096 .reg_width = 8,
1097 .label = "hysteresis",
1098 },
1099 {
1100 .name = "azoteq,lta-beta-lp",
1101 .reg_grp = IQS7222_REG_GRP_FILT,
1102 .reg_offset = 0,
1103 .reg_shift = 12,
1104 .reg_width = 4,
1105 .label = "low-power mode long-term average beta",
1106 },
1107 {
1108 .name = "azoteq,lta-beta-np",
1109 .reg_grp = IQS7222_REG_GRP_FILT,
1110 .reg_offset = 0,
1111 .reg_shift = 8,
1112 .reg_width = 4,
1113 .label = "normal-power mode long-term average beta",
1114 },
1115 {
1116 .name = "azoteq,counts-beta-lp",
1117 .reg_grp = IQS7222_REG_GRP_FILT,
1118 .reg_offset = 0,
1119 .reg_shift = 4,
1120 .reg_width = 4,
1121 .label = "low-power mode counts beta",
1122 },
1123 {
1124 .name = "azoteq,counts-beta-np",
1125 .reg_grp = IQS7222_REG_GRP_FILT,
1126 .reg_offset = 0,
1127 .reg_shift = 0,
1128 .reg_width = 4,
1129 .label = "normal-power mode counts beta",
1130 },
1131 {
1132 .name = "azoteq,lta-fast-beta-lp",
1133 .reg_grp = IQS7222_REG_GRP_FILT,
1134 .reg_offset = 1,
1135 .reg_shift = 4,
1136 .reg_width = 4,
1137 .label = "low-power mode long-term average fast beta",
1138 },
1139 {
1140 .name = "azoteq,lta-fast-beta-np",
1141 .reg_grp = IQS7222_REG_GRP_FILT,
1142 .reg_offset = 1,
1143 .reg_shift = 0,
1144 .reg_width = 4,
1145 .label = "normal-power mode long-term average fast beta",
1146 },
1147 {
1148 .name = "azoteq,lower-cal",
1149 .reg_grp = IQS7222_REG_GRP_SLDR,
1150 .reg_offset = 0,
1151 .reg_shift = 8,
1152 .reg_width = 8,
1153 .label = "lower calibration",
1154 },
1155 {
1156 .name = "azoteq,static-beta",
1157 .reg_grp = IQS7222_REG_GRP_SLDR,
1158 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
1159 .reg_offset = 0,
1160 .reg_shift = 6,
1161 .reg_width = 1,
1162 },
1163 {
1164 .name = "azoteq,bottom-beta",
1165 .reg_grp = IQS7222_REG_GRP_SLDR,
1166 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
1167 .reg_offset = 0,
1168 .reg_shift = 3,
1169 .reg_width = 3,
1170 .label = "bottom beta",
1171 },
1172 {
1173 .name = "azoteq,static-beta",
1174 .reg_grp = IQS7222_REG_GRP_SLDR,
1175 .reg_key = IQS7222_REG_KEY_WHEEL,
1176 .reg_offset = 0,
1177 .reg_shift = 7,
1178 .reg_width = 1,
1179 },
1180 {
1181 .name = "azoteq,bottom-beta",
1182 .reg_grp = IQS7222_REG_GRP_SLDR,
1183 .reg_key = IQS7222_REG_KEY_WHEEL,
1184 .reg_offset = 0,
1185 .reg_shift = 4,
1186 .reg_width = 3,
1187 .label = "bottom beta",
1188 },
1189 {
1190 .name = "azoteq,bottom-speed",
1191 .reg_grp = IQS7222_REG_GRP_SLDR,
1192 .reg_offset = 1,
1193 .reg_shift = 8,
1194 .reg_width = 8,
1195 .label = "bottom speed",
1196 },
1197 {
1198 .name = "azoteq,upper-cal",
1199 .reg_grp = IQS7222_REG_GRP_SLDR,
1200 .reg_offset = 1,
1201 .reg_shift = 0,
1202 .reg_width = 8,
1203 .label = "upper calibration",
1204 },
1205 {
1206 .name = "azoteq,gesture-max-ms",
1207 .reg_grp = IQS7222_REG_GRP_SLDR,
1208 .reg_key = IQS7222_REG_KEY_TAP,
1209 .reg_offset = 9,
1210 .reg_shift = 8,
1211 .reg_width = 8,
1212 .val_pitch = 16,
1213 .label = "maximum gesture time",
1214 },
1215 {
1216 .name = "azoteq,gesture-max-ms",
1217 .reg_grp = IQS7222_REG_GRP_SLDR,
1218 .reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1219 .reg_offset = 9,
1220 .reg_shift = 8,
1221 .reg_width = 8,
1222 .val_pitch = 4,
1223 .label = "maximum gesture time",
1224 },
1225 {
1226 .name = "azoteq,gesture-min-ms",
1227 .reg_grp = IQS7222_REG_GRP_SLDR,
1228 .reg_key = IQS7222_REG_KEY_TAP,
1229 .reg_offset = 9,
1230 .reg_shift = 3,
1231 .reg_width = 5,
1232 .val_pitch = 16,
1233 .label = "minimum gesture time",
1234 },
1235 {
1236 .name = "azoteq,gesture-min-ms",
1237 .reg_grp = IQS7222_REG_GRP_SLDR,
1238 .reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1239 .reg_offset = 9,
1240 .reg_shift = 3,
1241 .reg_width = 5,
1242 .val_pitch = 4,
1243 .label = "minimum gesture time",
1244 },
1245 {
1246 .name = "azoteq,gesture-dist",
1247 .reg_grp = IQS7222_REG_GRP_SLDR,
1248 .reg_key = IQS7222_REG_KEY_AXIAL,
1249 .reg_offset = 10,
1250 .reg_shift = 8,
1251 .reg_width = 8,
1252 .val_pitch = 16,
1253 .label = "gesture distance",
1254 },
1255 {
1256 .name = "azoteq,gesture-dist",
1257 .reg_grp = IQS7222_REG_GRP_SLDR,
1258 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1259 .reg_offset = 10,
1260 .reg_shift = 8,
1261 .reg_width = 8,
1262 .val_pitch = 16,
1263 .label = "gesture distance",
1264 },
1265 {
1266 .name = "azoteq,gesture-max-ms",
1267 .reg_grp = IQS7222_REG_GRP_SLDR,
1268 .reg_key = IQS7222_REG_KEY_AXIAL,
1269 .reg_offset = 10,
1270 .reg_shift = 0,
1271 .reg_width = 8,
1272 .val_pitch = 16,
1273 .label = "maximum gesture time",
1274 },
1275 {
1276 .name = "azoteq,gesture-max-ms",
1277 .reg_grp = IQS7222_REG_GRP_SLDR,
1278 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1279 .reg_offset = 10,
1280 .reg_shift = 0,
1281 .reg_width = 8,
1282 .val_pitch = 4,
1283 .label = "maximum gesture time",
1284 },
1285 {
1286 .name = "azoteq,num-rows",
1287 .reg_grp = IQS7222_REG_GRP_TPAD,
1288 .reg_offset = 0,
1289 .reg_shift = 4,
1290 .reg_width = 4,
1291 .val_min = 1,
1292 .val_max = 12,
1293 .label = "number of rows",
1294 },
1295 {
1296 .name = "azoteq,num-cols",
1297 .reg_grp = IQS7222_REG_GRP_TPAD,
1298 .reg_offset = 0,
1299 .reg_shift = 0,
1300 .reg_width = 4,
1301 .val_min = 1,
1302 .val_max = 12,
1303 .label = "number of columns",
1304 },
1305 {
1306 .name = "azoteq,lower-cal-y",
1307 .reg_grp = IQS7222_REG_GRP_TPAD,
1308 .reg_offset = 1,
1309 .reg_shift = 8,
1310 .reg_width = 8,
1311 .label = "lower vertical calibration",
1312 },
1313 {
1314 .name = "azoteq,lower-cal-x",
1315 .reg_grp = IQS7222_REG_GRP_TPAD,
1316 .reg_offset = 1,
1317 .reg_shift = 0,
1318 .reg_width = 8,
1319 .label = "lower horizontal calibration",
1320 },
1321 {
1322 .name = "azoteq,upper-cal-y",
1323 .reg_grp = IQS7222_REG_GRP_TPAD,
1324 .reg_offset = 2,
1325 .reg_shift = 8,
1326 .reg_width = 8,
1327 .label = "upper vertical calibration",
1328 },
1329 {
1330 .name = "azoteq,upper-cal-x",
1331 .reg_grp = IQS7222_REG_GRP_TPAD,
1332 .reg_offset = 2,
1333 .reg_shift = 0,
1334 .reg_width = 8,
1335 .label = "upper horizontal calibration",
1336 },
1337 {
1338 .name = "azoteq,top-speed",
1339 .reg_grp = IQS7222_REG_GRP_TPAD,
1340 .reg_offset = 3,
1341 .reg_shift = 8,
1342 .reg_width = 8,
1343 .val_pitch = 4,
1344 .label = "top speed",
1345 },
1346 {
1347 .name = "azoteq,bottom-speed",
1348 .reg_grp = IQS7222_REG_GRP_TPAD,
1349 .reg_offset = 3,
1350 .reg_shift = 0,
1351 .reg_width = 8,
1352 .label = "bottom speed",
1353 },
1354 {
1355 .name = "azoteq,gesture-min-ms",
1356 .reg_grp = IQS7222_REG_GRP_TPAD,
1357 .reg_key = IQS7222_REG_KEY_TAP,
1358 .reg_offset = 20,
1359 .reg_shift = 8,
1360 .reg_width = 8,
1361 .val_pitch = 16,
1362 .label = "minimum gesture time",
1363 },
1364 {
1365 .name = "azoteq,gesture-max-ms",
1366 .reg_grp = IQS7222_REG_GRP_TPAD,
1367 .reg_key = IQS7222_REG_KEY_AXIAL,
1368 .reg_offset = 21,
1369 .reg_shift = 8,
1370 .reg_width = 8,
1371 .val_pitch = 16,
1372 .label = "maximum gesture time",
1373 },
1374 {
1375 .name = "azoteq,gesture-max-ms",
1376 .reg_grp = IQS7222_REG_GRP_TPAD,
1377 .reg_key = IQS7222_REG_KEY_TAP,
1378 .reg_offset = 21,
1379 .reg_shift = 0,
1380 .reg_width = 8,
1381 .val_pitch = 16,
1382 .label = "maximum gesture time",
1383 },
1384 {
1385 .name = "azoteq,gesture-dist",
1386 .reg_grp = IQS7222_REG_GRP_TPAD,
1387 .reg_key = IQS7222_REG_KEY_TAP,
1388 .reg_offset = 22,
1389 .reg_shift = 0,
1390 .reg_width = 16,
1391 .label = "gesture distance",
1392 },
1393 {
1394 .name = "azoteq,gesture-dist",
1395 .reg_grp = IQS7222_REG_GRP_TPAD,
1396 .reg_key = IQS7222_REG_KEY_AXIAL,
1397 .reg_offset = 23,
1398 .reg_shift = 0,
1399 .reg_width = 16,
1400 .label = "gesture distance",
1401 },
1402 {
1403 .name = "drive-open-drain",
1404 .reg_grp = IQS7222_REG_GRP_GPIO,
1405 .reg_offset = 0,
1406 .reg_shift = 1,
1407 .reg_width = 1,
1408 },
1409 {
1410 .name = "azoteq,timeout-ati-ms",
1411 .reg_grp = IQS7222_REG_GRP_SYS,
1412 .reg_offset = 1,
1413 .reg_shift = 0,
1414 .reg_width = 16,
1415 .val_pitch = 500,
1416 .label = "ATI error timeout",
1417 },
1418 {
1419 .name = "azoteq,rate-ati-ms",
1420 .reg_grp = IQS7222_REG_GRP_SYS,
1421 .reg_offset = 2,
1422 .reg_shift = 0,
1423 .reg_width = 16,
1424 .label = "ATI report rate",
1425 },
1426 {
1427 .name = "azoteq,timeout-np-ms",
1428 .reg_grp = IQS7222_REG_GRP_SYS,
1429 .reg_offset = 3,
1430 .reg_shift = 0,
1431 .reg_width = 16,
1432 .label = "normal-power mode timeout",
1433 },
1434 {
1435 .name = "azoteq,rate-np-ms",
1436 .reg_grp = IQS7222_REG_GRP_SYS,
1437 .reg_offset = 4,
1438 .reg_shift = 0,
1439 .reg_width = 16,
1440 .val_max = 3000,
1441 .label = "normal-power mode report rate",
1442 },
1443 {
1444 .name = "azoteq,timeout-lp-ms",
1445 .reg_grp = IQS7222_REG_GRP_SYS,
1446 .reg_offset = 5,
1447 .reg_shift = 0,
1448 .reg_width = 16,
1449 .label = "low-power mode timeout",
1450 },
1451 {
1452 .name = "azoteq,rate-lp-ms",
1453 .reg_grp = IQS7222_REG_GRP_SYS,
1454 .reg_offset = 6,
1455 .reg_shift = 0,
1456 .reg_width = 16,
1457 .val_max = 3000,
1458 .label = "low-power mode report rate",
1459 },
1460 {
1461 .name = "azoteq,timeout-ulp-ms",
1462 .reg_grp = IQS7222_REG_GRP_SYS,
1463 .reg_offset = 7,
1464 .reg_shift = 0,
1465 .reg_width = 16,
1466 .label = "ultra-low-power mode timeout",
1467 },
1468 {
1469 .name = "azoteq,rate-ulp-ms",
1470 .reg_grp = IQS7222_REG_GRP_SYS,
1471 .reg_offset = 8,
1472 .reg_shift = 0,
1473 .reg_width = 16,
1474 .val_max = 3000,
1475 .label = "ultra-low-power mode report rate",
1476 },
1477 };
1478
1479 struct iqs7222_private {
1480 const struct iqs7222_dev_desc *dev_desc;
1481 struct gpio_desc *reset_gpio;
1482 struct gpio_desc *irq_gpio;
1483 struct i2c_client *client;
1484 struct input_dev *keypad;
1485 struct touchscreen_properties prop;
1486 unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1487 unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1488 unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)];
1489 unsigned int sl_axis[IQS7222_MAX_SLDR];
1490 unsigned int tp_code[ARRAY_SIZE(iqs7222_tp_events)];
1491 u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE];
1492 u16 glbl_setup[IQS7222_MAX_COLS_GLBL];
1493 u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN];
1494 u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN];
1495 u16 filt_setup[IQS7222_MAX_COLS_FILT];
1496 u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR];
1497 u16 tpad_setup[IQS7222_MAX_COLS_TPAD];
1498 u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO];
1499 u16 sys_setup[IQS7222_MAX_COLS_SYS];
1500 };
1501
iqs7222_setup(struct iqs7222_private * iqs7222,enum iqs7222_reg_grp_id reg_grp,int row)1502 static u16 *iqs7222_setup(struct iqs7222_private *iqs7222,
1503 enum iqs7222_reg_grp_id reg_grp, int row)
1504 {
1505 switch (reg_grp) {
1506 case IQS7222_REG_GRP_CYCLE:
1507 return iqs7222->cycle_setup[row];
1508
1509 case IQS7222_REG_GRP_GLBL:
1510 return iqs7222->glbl_setup;
1511
1512 case IQS7222_REG_GRP_BTN:
1513 return iqs7222->btn_setup[row];
1514
1515 case IQS7222_REG_GRP_CHAN:
1516 return iqs7222->chan_setup[row];
1517
1518 case IQS7222_REG_GRP_FILT:
1519 return iqs7222->filt_setup;
1520
1521 case IQS7222_REG_GRP_SLDR:
1522 return iqs7222->sldr_setup[row];
1523
1524 case IQS7222_REG_GRP_TPAD:
1525 return iqs7222->tpad_setup;
1526
1527 case IQS7222_REG_GRP_GPIO:
1528 return iqs7222->gpio_setup[row];
1529
1530 case IQS7222_REG_GRP_SYS:
1531 return iqs7222->sys_setup;
1532
1533 default:
1534 return NULL;
1535 }
1536 }
1537
iqs7222_irq_poll(struct iqs7222_private * iqs7222,u16 timeout_ms)1538 static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms)
1539 {
1540 ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms);
1541 int ret;
1542
1543 do {
1544 usleep_range(1000, 1100);
1545
1546 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1547 if (ret < 0)
1548 return ret;
1549 else if (ret > 0)
1550 return 0;
1551 } while (ktime_compare(ktime_get(), irq_timeout) < 0);
1552
1553 return -EBUSY;
1554 }
1555
iqs7222_hard_reset(struct iqs7222_private * iqs7222)1556 static int iqs7222_hard_reset(struct iqs7222_private *iqs7222)
1557 {
1558 struct i2c_client *client = iqs7222->client;
1559 int error;
1560
1561 if (!iqs7222->reset_gpio)
1562 return 0;
1563
1564 gpiod_set_value_cansleep(iqs7222->reset_gpio, 1);
1565 usleep_range(1000, 1100);
1566
1567 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0);
1568
1569 error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS);
1570 if (error)
1571 dev_err(&client->dev, "Failed to reset device: %d\n", error);
1572
1573 return error;
1574 }
1575
iqs7222_force_comms(struct iqs7222_private * iqs7222)1576 static int iqs7222_force_comms(struct iqs7222_private *iqs7222)
1577 {
1578 u8 msg_buf[] = { 0xFF, };
1579 int ret;
1580
1581 /*
1582 * The device cannot communicate until it asserts its interrupt (RDY)
1583 * pin. Attempts to do so while RDY is deasserted return an ACK; how-
1584 * ever all write data is ignored, and all read data returns 0xEE.
1585 *
1586 * Unsolicited communication must be preceded by a special force com-
1587 * munication command, after which the device eventually asserts its
1588 * RDY pin and agrees to communicate.
1589 *
1590 * Regardless of whether communication is forced or the result of an
1591 * interrupt, the device automatically deasserts its RDY pin once it
1592 * detects an I2C stop condition, or a timeout expires.
1593 */
1594 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1595 if (ret < 0)
1596 return ret;
1597 else if (ret > 0)
1598 return 0;
1599
1600 ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf));
1601 if (ret < (int)sizeof(msg_buf)) {
1602 if (ret >= 0)
1603 ret = -EIO;
1604
1605 /*
1606 * The datasheet states that the host must wait to retry any
1607 * failed attempt to communicate over I2C.
1608 */
1609 msleep(IQS7222_COMMS_RETRY_MS);
1610 return ret;
1611 }
1612
1613 return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS);
1614 }
1615
iqs7222_read_burst(struct iqs7222_private * iqs7222,u16 reg,void * val,u16 val_len)1616 static int iqs7222_read_burst(struct iqs7222_private *iqs7222,
1617 u16 reg, void *val, u16 val_len)
1618 {
1619 u8 reg_buf[sizeof(__be16)];
1620 int ret, i;
1621 struct i2c_client *client = iqs7222->client;
1622 struct i2c_msg msg[] = {
1623 {
1624 .addr = client->addr,
1625 .flags = 0,
1626 .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8),
1627 .buf = reg_buf,
1628 },
1629 {
1630 .addr = client->addr,
1631 .flags = I2C_M_RD,
1632 .len = val_len,
1633 .buf = (u8 *)val,
1634 },
1635 };
1636
1637 if (reg > U8_MAX)
1638 put_unaligned_be16(reg, reg_buf);
1639 else
1640 *reg_buf = (u8)reg;
1641
1642 /*
1643 * The following loop protects against an edge case in which the RDY
1644 * pin is automatically deasserted just as the read is initiated. In
1645 * that case, the read must be retried using forced communication.
1646 */
1647 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1648 ret = iqs7222_force_comms(iqs7222);
1649 if (ret < 0)
1650 continue;
1651
1652 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
1653 if (ret < (int)ARRAY_SIZE(msg)) {
1654 if (ret >= 0)
1655 ret = -EIO;
1656
1657 msleep(IQS7222_COMMS_RETRY_MS);
1658 continue;
1659 }
1660
1661 if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) {
1662 ret = -ENODATA;
1663 continue;
1664 }
1665
1666 ret = 0;
1667 break;
1668 }
1669
1670 /*
1671 * The following delay ensures the device has deasserted the RDY pin
1672 * following the I2C stop condition.
1673 */
1674 usleep_range(50, 100);
1675
1676 if (ret < 0)
1677 dev_err(&client->dev,
1678 "Failed to read from address 0x%04X: %d\n", reg, ret);
1679
1680 return ret;
1681 }
1682
iqs7222_read_word(struct iqs7222_private * iqs7222,u16 reg,u16 * val)1683 static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val)
1684 {
1685 __le16 val_buf;
1686 int error;
1687
1688 error = iqs7222_read_burst(iqs7222, reg, &val_buf, sizeof(val_buf));
1689 if (error)
1690 return error;
1691
1692 *val = le16_to_cpu(val_buf);
1693
1694 return 0;
1695 }
1696
iqs7222_write_burst(struct iqs7222_private * iqs7222,u16 reg,const void * val,u16 val_len)1697 static int iqs7222_write_burst(struct iqs7222_private *iqs7222,
1698 u16 reg, const void *val, u16 val_len)
1699 {
1700 int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8);
1701 int msg_len = reg_len + val_len;
1702 int ret, i;
1703 struct i2c_client *client = iqs7222->client;
1704 u8 *msg_buf;
1705
1706 msg_buf = kzalloc(msg_len, GFP_KERNEL);
1707 if (!msg_buf)
1708 return -ENOMEM;
1709
1710 if (reg > U8_MAX)
1711 put_unaligned_be16(reg, msg_buf);
1712 else
1713 *msg_buf = (u8)reg;
1714
1715 memcpy(msg_buf + reg_len, val, val_len);
1716
1717 /*
1718 * The following loop protects against an edge case in which the RDY
1719 * pin is automatically asserted just before the force communication
1720 * command is sent.
1721 *
1722 * In that case, the subsequent I2C stop condition tricks the device
1723 * into preemptively deasserting the RDY pin and the command must be
1724 * sent again.
1725 */
1726 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1727 ret = iqs7222_force_comms(iqs7222);
1728 if (ret < 0)
1729 continue;
1730
1731 ret = i2c_master_send(client, msg_buf, msg_len);
1732 if (ret < msg_len) {
1733 if (ret >= 0)
1734 ret = -EIO;
1735
1736 msleep(IQS7222_COMMS_RETRY_MS);
1737 continue;
1738 }
1739
1740 ret = 0;
1741 break;
1742 }
1743
1744 kfree(msg_buf);
1745
1746 usleep_range(50, 100);
1747
1748 if (ret < 0)
1749 dev_err(&client->dev,
1750 "Failed to write to address 0x%04X: %d\n", reg, ret);
1751
1752 return ret;
1753 }
1754
iqs7222_write_word(struct iqs7222_private * iqs7222,u16 reg,u16 val)1755 static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val)
1756 {
1757 __le16 val_buf = cpu_to_le16(val);
1758
1759 return iqs7222_write_burst(iqs7222, reg, &val_buf, sizeof(val_buf));
1760 }
1761
iqs7222_ati_trigger(struct iqs7222_private * iqs7222)1762 static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222)
1763 {
1764 struct i2c_client *client = iqs7222->client;
1765 ktime_t ati_timeout;
1766 u16 sys_status = 0;
1767 u16 sys_setup;
1768 int error, i;
1769
1770 /*
1771 * The reserved fields of the system setup register may have changed
1772 * as a result of other registers having been written. As such, read
1773 * the register's latest value to avoid unexpected behavior when the
1774 * register is written in the loop that follows.
1775 */
1776 error = iqs7222_read_word(iqs7222, IQS7222_SYS_SETUP, &sys_setup);
1777 if (error)
1778 return error;
1779
1780 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1781 /*
1782 * Trigger ATI from streaming and normal-power modes so that
1783 * the RDY pin continues to be asserted during ATI.
1784 */
1785 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1786 sys_setup |
1787 IQS7222_SYS_SETUP_REDO_ATI);
1788 if (error)
1789 return error;
1790
1791 ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS);
1792
1793 do {
1794 error = iqs7222_irq_poll(iqs7222,
1795 IQS7222_COMMS_TIMEOUT_MS);
1796 if (error)
1797 continue;
1798
1799 error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS,
1800 &sys_status);
1801 if (error)
1802 return error;
1803
1804 if (sys_status & IQS7222_SYS_STATUS_RESET)
1805 return 0;
1806
1807 if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR)
1808 break;
1809
1810 if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE)
1811 continue;
1812
1813 /*
1814 * Use stream-in-touch mode if either slider reports
1815 * absolute position.
1816 */
1817 sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit)
1818 ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH
1819 : IQS7222_SYS_SETUP_INTF_MODE_EVENT;
1820 sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO;
1821
1822 return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1823 sys_setup);
1824 } while (ktime_compare(ktime_get(), ati_timeout) < 0);
1825
1826 dev_err(&client->dev,
1827 "ATI attempt %d of %d failed with status 0x%02X, %s\n",
1828 i + 1, IQS7222_NUM_RETRIES, (u8)sys_status,
1829 i + 1 < IQS7222_NUM_RETRIES ? "retrying" : "stopping");
1830 }
1831
1832 return -ETIMEDOUT;
1833 }
1834
iqs7222_dev_init(struct iqs7222_private * iqs7222,int dir)1835 static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir)
1836 {
1837 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1838 int comms_offset = dev_desc->comms_offset;
1839 int error, i, j, k;
1840
1841 /*
1842 * Acknowledge reset before writing any registers in case the device
1843 * suffers a spurious reset during initialization.
1844 */
1845 if (dir == WRITE) {
1846 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1847 iqs7222->sys_setup[0] |
1848 IQS7222_SYS_SETUP_ACK_RESET);
1849 if (error)
1850 return error;
1851 }
1852
1853 /*
1854 * Take advantage of the stop-bit disable function, if available, to
1855 * save the trouble of having to reopen a communication window after
1856 * each burst read or write.
1857 */
1858 if (comms_offset) {
1859 u16 comms_setup;
1860
1861 error = iqs7222_read_word(iqs7222,
1862 IQS7222_SYS_SETUP + comms_offset,
1863 &comms_setup);
1864 if (error)
1865 return error;
1866
1867 error = iqs7222_write_word(iqs7222,
1868 IQS7222_SYS_SETUP + comms_offset,
1869 comms_setup | IQS7222_COMMS_HOLD);
1870 if (error)
1871 return error;
1872 }
1873
1874 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
1875 int num_row = dev_desc->reg_grps[i].num_row;
1876 int num_col = dev_desc->reg_grps[i].num_col;
1877 u16 reg = dev_desc->reg_grps[i].base;
1878 __le16 *val_buf;
1879 u16 val_len = dev_desc->reg_grps[i].val_len ? : num_col * sizeof(*val_buf);
1880 u16 *val;
1881
1882 if (!num_col)
1883 continue;
1884
1885 val = iqs7222_setup(iqs7222, i, 0);
1886 if (!val)
1887 continue;
1888
1889 val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL);
1890 if (!val_buf)
1891 return -ENOMEM;
1892
1893 for (j = 0; j < num_row; j++) {
1894 switch (dir) {
1895 case READ:
1896 error = iqs7222_read_burst(iqs7222, reg,
1897 val_buf, val_len);
1898 for (k = 0; k < num_col; k++)
1899 val[k] = le16_to_cpu(val_buf[k]);
1900 break;
1901
1902 case WRITE:
1903 for (k = 0; k < num_col; k++)
1904 val_buf[k] = cpu_to_le16(val[k]);
1905 error = iqs7222_write_burst(iqs7222, reg,
1906 val_buf, val_len);
1907 break;
1908
1909 default:
1910 error = -EINVAL;
1911 }
1912
1913 if (error)
1914 break;
1915
1916 reg += IQS7222_REG_OFFSET;
1917 val += iqs7222_max_cols[i];
1918 }
1919
1920 kfree(val_buf);
1921
1922 if (error)
1923 return error;
1924 }
1925
1926 if (comms_offset) {
1927 u16 comms_setup;
1928
1929 error = iqs7222_read_word(iqs7222,
1930 IQS7222_SYS_SETUP + comms_offset,
1931 &comms_setup);
1932 if (error)
1933 return error;
1934
1935 error = iqs7222_write_word(iqs7222,
1936 IQS7222_SYS_SETUP + comms_offset,
1937 comms_setup & ~IQS7222_COMMS_HOLD);
1938 if (error)
1939 return error;
1940 }
1941
1942 if (dir == READ) {
1943 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK;
1944 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK;
1945 return 0;
1946 }
1947
1948 return iqs7222_ati_trigger(iqs7222);
1949 }
1950
iqs7222_dev_info(struct iqs7222_private * iqs7222)1951 static int iqs7222_dev_info(struct iqs7222_private *iqs7222)
1952 {
1953 struct i2c_client *client = iqs7222->client;
1954 bool prod_num_valid = false;
1955 __le16 dev_id[3];
1956 int error, i;
1957
1958 error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id,
1959 sizeof(dev_id));
1960 if (error)
1961 return error;
1962
1963 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) {
1964 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num)
1965 continue;
1966
1967 prod_num_valid = true;
1968
1969 if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major)
1970 continue;
1971
1972 if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor)
1973 continue;
1974
1975 iqs7222->dev_desc = &iqs7222_devs[i];
1976 return 0;
1977 }
1978
1979 if (prod_num_valid)
1980 dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n",
1981 le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2]));
1982 else
1983 dev_err(&client->dev, "Unrecognized product number: %u\n",
1984 le16_to_cpu(dev_id[0]));
1985
1986 return -EINVAL;
1987 }
1988
iqs7222_gpio_select(struct iqs7222_private * iqs7222,struct fwnode_handle * child_node,int child_enable,u16 child_link)1989 static int iqs7222_gpio_select(struct iqs7222_private *iqs7222,
1990 struct fwnode_handle *child_node,
1991 int child_enable, u16 child_link)
1992 {
1993 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1994 struct i2c_client *client = iqs7222->client;
1995 int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row;
1996 int error, count, i;
1997 unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)];
1998
1999 if (!num_gpio)
2000 return 0;
2001
2002 if (!fwnode_property_present(child_node, "azoteq,gpio-select"))
2003 return 0;
2004
2005 count = fwnode_property_count_u32(child_node, "azoteq,gpio-select");
2006 if (count > num_gpio) {
2007 dev_err(&client->dev, "Invalid number of %s GPIOs\n",
2008 fwnode_get_name(child_node));
2009 return -EINVAL;
2010 } else if (count < 0) {
2011 dev_err(&client->dev, "Failed to count %s GPIOs: %d\n",
2012 fwnode_get_name(child_node), count);
2013 return count;
2014 }
2015
2016 error = fwnode_property_read_u32_array(child_node,
2017 "azoteq,gpio-select",
2018 gpio_sel, count);
2019 if (error) {
2020 dev_err(&client->dev, "Failed to read %s GPIOs: %d\n",
2021 fwnode_get_name(child_node), error);
2022 return error;
2023 }
2024
2025 for (i = 0; i < count; i++) {
2026 u16 *gpio_setup;
2027
2028 if (gpio_sel[i] >= num_gpio) {
2029 dev_err(&client->dev, "Invalid %s GPIO: %u\n",
2030 fwnode_get_name(child_node), gpio_sel[i]);
2031 return -EINVAL;
2032 }
2033
2034 gpio_setup = iqs7222->gpio_setup[gpio_sel[i]];
2035
2036 if (gpio_setup[2] && child_link != gpio_setup[2]) {
2037 dev_err(&client->dev,
2038 "Conflicting GPIO %u event types\n",
2039 gpio_sel[i]);
2040 return -EINVAL;
2041 }
2042
2043 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN;
2044 gpio_setup[1] |= child_enable;
2045 gpio_setup[2] = child_link;
2046 }
2047
2048 return 0;
2049 }
2050
iqs7222_parse_props(struct iqs7222_private * iqs7222,struct fwnode_handle * reg_grp_node,int reg_grp_index,enum iqs7222_reg_grp_id reg_grp,enum iqs7222_reg_key_id reg_key)2051 static int iqs7222_parse_props(struct iqs7222_private *iqs7222,
2052 struct fwnode_handle *reg_grp_node,
2053 int reg_grp_index,
2054 enum iqs7222_reg_grp_id reg_grp,
2055 enum iqs7222_reg_key_id reg_key)
2056 {
2057 u16 *setup = iqs7222_setup(iqs7222, reg_grp, reg_grp_index);
2058 struct i2c_client *client = iqs7222->client;
2059 int i;
2060
2061 if (!setup)
2062 return 0;
2063
2064 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) {
2065 const char *name = iqs7222_props[i].name;
2066 int reg_offset = iqs7222_props[i].reg_offset;
2067 int reg_shift = iqs7222_props[i].reg_shift;
2068 int reg_width = iqs7222_props[i].reg_width;
2069 int val_pitch = iqs7222_props[i].val_pitch ? : 1;
2070 int val_min = iqs7222_props[i].val_min;
2071 int val_max = iqs7222_props[i].val_max;
2072 bool invert = iqs7222_props[i].invert;
2073 const char *label = iqs7222_props[i].label ? : name;
2074 unsigned int val;
2075 int error;
2076
2077 if (iqs7222_props[i].reg_grp != reg_grp ||
2078 iqs7222_props[i].reg_key != reg_key)
2079 continue;
2080
2081 /*
2082 * Boolean register fields are one bit wide; they are forcibly
2083 * reset to provide a means to undo changes by a bootloader if
2084 * necessary.
2085 *
2086 * Scalar fields, on the other hand, are left untouched unless
2087 * their corresponding properties are present.
2088 */
2089 if (reg_width == 1) {
2090 if (invert)
2091 setup[reg_offset] |= BIT(reg_shift);
2092 else
2093 setup[reg_offset] &= ~BIT(reg_shift);
2094 }
2095
2096 if (!fwnode_property_present(reg_grp_node, name))
2097 continue;
2098
2099 if (reg_width == 1) {
2100 if (invert)
2101 setup[reg_offset] &= ~BIT(reg_shift);
2102 else
2103 setup[reg_offset] |= BIT(reg_shift);
2104
2105 continue;
2106 }
2107
2108 error = fwnode_property_read_u32(reg_grp_node, name, &val);
2109 if (error) {
2110 dev_err(&client->dev, "Failed to read %s %s: %d\n",
2111 fwnode_get_name(reg_grp_node), label, error);
2112 return error;
2113 }
2114
2115 if (!val_max)
2116 val_max = GENMASK(reg_width - 1, 0) * val_pitch;
2117
2118 if (val < val_min || val > val_max) {
2119 dev_err(&client->dev, "Invalid %s %s: %u\n",
2120 fwnode_get_name(reg_grp_node), label, val);
2121 return -EINVAL;
2122 }
2123
2124 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1,
2125 reg_shift);
2126 setup[reg_offset] |= (val / val_pitch << reg_shift);
2127 }
2128
2129 return 0;
2130 }
2131
iqs7222_parse_event(struct iqs7222_private * iqs7222,struct fwnode_handle * event_node,int reg_grp_index,enum iqs7222_reg_grp_id reg_grp,enum iqs7222_reg_key_id reg_key,u16 event_enable,u16 event_link,unsigned int * event_type,unsigned int * event_code)2132 static int iqs7222_parse_event(struct iqs7222_private *iqs7222,
2133 struct fwnode_handle *event_node,
2134 int reg_grp_index,
2135 enum iqs7222_reg_grp_id reg_grp,
2136 enum iqs7222_reg_key_id reg_key,
2137 u16 event_enable, u16 event_link,
2138 unsigned int *event_type,
2139 unsigned int *event_code)
2140 {
2141 struct i2c_client *client = iqs7222->client;
2142 int error;
2143
2144 error = iqs7222_parse_props(iqs7222, event_node, reg_grp_index,
2145 reg_grp, reg_key);
2146 if (error)
2147 return error;
2148
2149 error = iqs7222_gpio_select(iqs7222, event_node, event_enable,
2150 event_link);
2151 if (error)
2152 return error;
2153
2154 error = fwnode_property_read_u32(event_node, "linux,code", event_code);
2155 if (error == -EINVAL) {
2156 return 0;
2157 } else if (error) {
2158 dev_err(&client->dev, "Failed to read %s code: %d\n",
2159 fwnode_get_name(event_node), error);
2160 return error;
2161 }
2162
2163 if (!event_type) {
2164 input_set_capability(iqs7222->keypad, EV_KEY, *event_code);
2165 return 0;
2166 }
2167
2168 error = fwnode_property_read_u32(event_node, "linux,input-type",
2169 event_type);
2170 if (error == -EINVAL) {
2171 *event_type = EV_KEY;
2172 } else if (error) {
2173 dev_err(&client->dev, "Failed to read %s input type: %d\n",
2174 fwnode_get_name(event_node), error);
2175 return error;
2176 } else if (*event_type != EV_KEY && *event_type != EV_SW) {
2177 dev_err(&client->dev, "Invalid %s input type: %d\n",
2178 fwnode_get_name(event_node), *event_type);
2179 return -EINVAL;
2180 }
2181
2182 input_set_capability(iqs7222->keypad, *event_type, *event_code);
2183
2184 return 0;
2185 }
2186
iqs7222_parse_cycle(struct iqs7222_private * iqs7222,struct fwnode_handle * cycle_node,int cycle_index)2187 static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222,
2188 struct fwnode_handle *cycle_node, int cycle_index)
2189 {
2190 u16 *cycle_setup = iqs7222->cycle_setup[cycle_index];
2191 struct i2c_client *client = iqs7222->client;
2192 unsigned int pins[9];
2193 int error, count, i;
2194
2195 /*
2196 * Each channel shares a cycle with one other channel; the mapping of
2197 * channels to cycles is fixed. Properties defined for a cycle impact
2198 * both channels tied to the cycle.
2199 *
2200 * Unlike channels which are restricted to a select range of CRx pins
2201 * based on channel number, any cycle can claim any of the device's 9
2202 * CTx pins (CTx0-8).
2203 */
2204 if (!fwnode_property_present(cycle_node, "azoteq,tx-enable"))
2205 return 0;
2206
2207 count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable");
2208 if (count < 0) {
2209 dev_err(&client->dev, "Failed to count %s CTx pins: %d\n",
2210 fwnode_get_name(cycle_node), count);
2211 return count;
2212 } else if (count > ARRAY_SIZE(pins)) {
2213 dev_err(&client->dev, "Invalid number of %s CTx pins\n",
2214 fwnode_get_name(cycle_node));
2215 return -EINVAL;
2216 }
2217
2218 error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable",
2219 pins, count);
2220 if (error) {
2221 dev_err(&client->dev, "Failed to read %s CTx pins: %d\n",
2222 fwnode_get_name(cycle_node), error);
2223 return error;
2224 }
2225
2226 cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7);
2227
2228 for (i = 0; i < count; i++) {
2229 if (pins[i] > 8) {
2230 dev_err(&client->dev, "Invalid %s CTx pin: %u\n",
2231 fwnode_get_name(cycle_node), pins[i]);
2232 return -EINVAL;
2233 }
2234
2235 cycle_setup[1] |= BIT(pins[i] + 7);
2236 }
2237
2238 return 0;
2239 }
2240
iqs7222_parse_chan(struct iqs7222_private * iqs7222,struct fwnode_handle * chan_node,int chan_index)2241 static int iqs7222_parse_chan(struct iqs7222_private *iqs7222,
2242 struct fwnode_handle *chan_node, int chan_index)
2243 {
2244 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2245 struct i2c_client *client = iqs7222->client;
2246 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2247 int ext_chan = rounddown(num_chan, 10);
2248 int error, i;
2249 u16 *chan_setup = iqs7222->chan_setup[chan_index];
2250 u16 *sys_setup = iqs7222->sys_setup;
2251 unsigned int val;
2252
2253 if (dev_desc->allow_offset &&
2254 fwnode_property_present(chan_node, "azoteq,ulp-allow"))
2255 sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index);
2256
2257 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN;
2258
2259 /*
2260 * The reference channel function allows for differential measurements
2261 * and is only available in the case of IQS7222A or IQS7222C.
2262 */
2263 if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 &&
2264 fwnode_property_present(chan_node, "azoteq,ref-select")) {
2265 u16 *ref_setup;
2266
2267 error = fwnode_property_read_u32(chan_node, "azoteq,ref-select",
2268 &val);
2269 if (error) {
2270 dev_err(&client->dev,
2271 "Failed to read %s reference channel: %d\n",
2272 fwnode_get_name(chan_node), error);
2273 return error;
2274 }
2275
2276 if (val >= ext_chan) {
2277 dev_err(&client->dev,
2278 "Invalid %s reference channel: %u\n",
2279 fwnode_get_name(chan_node), val);
2280 return -EINVAL;
2281 }
2282
2283 ref_setup = iqs7222->chan_setup[val];
2284
2285 /*
2286 * Configure the current channel as a follower of the selected
2287 * reference channel.
2288 */
2289 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW;
2290 chan_setup[4] = val * 42 + 1048;
2291
2292 error = fwnode_property_read_u32(chan_node, "azoteq,ref-weight",
2293 &val);
2294 if (!error) {
2295 if (val > U16_MAX) {
2296 dev_err(&client->dev,
2297 "Invalid %s reference weight: %u\n",
2298 fwnode_get_name(chan_node), val);
2299 return -EINVAL;
2300 }
2301
2302 chan_setup[5] = val;
2303 } else if (error != -EINVAL) {
2304 dev_err(&client->dev,
2305 "Failed to read %s reference weight: %d\n",
2306 fwnode_get_name(chan_node), error);
2307 return error;
2308 }
2309
2310 /*
2311 * Configure the selected channel as a reference channel which
2312 * serves the current channel.
2313 */
2314 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2315 ref_setup[5] |= BIT(chan_index);
2316
2317 ref_setup[4] = dev_desc->touch_link;
2318 if (fwnode_property_present(chan_node, "azoteq,use-prox"))
2319 ref_setup[4] -= 2;
2320 } else if (dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row &&
2321 fwnode_property_present(chan_node,
2322 "azoteq,counts-filt-enable")) {
2323 /*
2324 * In the case of IQS7222D, however, the reference mode field
2325 * is partially repurposed as a counts filter enable control.
2326 */
2327 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2328 }
2329
2330 if (fwnode_property_present(chan_node, "azoteq,rx-enable")) {
2331 /*
2332 * Each channel can claim up to 4 CRx pins. The first half of
2333 * the channels can use CRx0-3, while the second half can use
2334 * CRx4-7.
2335 */
2336 unsigned int pins[4];
2337 int count;
2338
2339 count = fwnode_property_count_u32(chan_node,
2340 "azoteq,rx-enable");
2341 if (count < 0) {
2342 dev_err(&client->dev,
2343 "Failed to count %s CRx pins: %d\n",
2344 fwnode_get_name(chan_node), count);
2345 return count;
2346 } else if (count > ARRAY_SIZE(pins)) {
2347 dev_err(&client->dev,
2348 "Invalid number of %s CRx pins\n",
2349 fwnode_get_name(chan_node));
2350 return -EINVAL;
2351 }
2352
2353 error = fwnode_property_read_u32_array(chan_node,
2354 "azoteq,rx-enable",
2355 pins, count);
2356 if (error) {
2357 dev_err(&client->dev,
2358 "Failed to read %s CRx pins: %d\n",
2359 fwnode_get_name(chan_node), error);
2360 return error;
2361 }
2362
2363 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4);
2364
2365 for (i = 0; i < count; i++) {
2366 int min_crx = chan_index < ext_chan / 2 ? 0 : 4;
2367
2368 if (pins[i] < min_crx || pins[i] > min_crx + 3) {
2369 dev_err(&client->dev,
2370 "Invalid %s CRx pin: %u\n",
2371 fwnode_get_name(chan_node), pins[i]);
2372 return -EINVAL;
2373 }
2374
2375 chan_setup[0] |= BIT(pins[i] + 4 - min_crx);
2376 }
2377 }
2378
2379 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) {
2380 const char *event_name = iqs7222_kp_events[i].name;
2381 u16 event_enable = iqs7222_kp_events[i].enable;
2382 struct fwnode_handle *event_node;
2383
2384 event_node = fwnode_get_named_child_node(chan_node, event_name);
2385 if (!event_node)
2386 continue;
2387
2388 error = fwnode_property_read_u32(event_node,
2389 "azoteq,timeout-press-ms",
2390 &val);
2391 if (!error) {
2392 /*
2393 * The IQS7222B employs a global pair of press timeout
2394 * registers as opposed to channel-specific registers.
2395 */
2396 u16 *setup = dev_desc->reg_grps
2397 [IQS7222_REG_GRP_BTN].num_col > 2 ?
2398 &iqs7222->btn_setup[chan_index][2] :
2399 &sys_setup[9];
2400
2401 if (val > U8_MAX * 500) {
2402 dev_err(&client->dev,
2403 "Invalid %s press timeout: %u\n",
2404 fwnode_get_name(event_node), val);
2405 fwnode_handle_put(event_node);
2406 return -EINVAL;
2407 }
2408
2409 *setup &= ~(U8_MAX << i * 8);
2410 *setup |= (val / 500 << i * 8);
2411 } else if (error != -EINVAL) {
2412 dev_err(&client->dev,
2413 "Failed to read %s press timeout: %d\n",
2414 fwnode_get_name(event_node), error);
2415 fwnode_handle_put(event_node);
2416 return error;
2417 }
2418
2419 error = iqs7222_parse_event(iqs7222, event_node, chan_index,
2420 IQS7222_REG_GRP_BTN,
2421 iqs7222_kp_events[i].reg_key,
2422 BIT(chan_index),
2423 dev_desc->touch_link - (i ? 0 : 2),
2424 &iqs7222->kp_type[chan_index][i],
2425 &iqs7222->kp_code[chan_index][i]);
2426 fwnode_handle_put(event_node);
2427 if (error)
2428 return error;
2429
2430 if (!dev_desc->event_offset)
2431 continue;
2432
2433 sys_setup[dev_desc->event_offset] |= event_enable;
2434 }
2435
2436 /*
2437 * The following call handles a special pair of properties that apply
2438 * to a channel node, but reside within the button (event) group.
2439 */
2440 return iqs7222_parse_props(iqs7222, chan_node, chan_index,
2441 IQS7222_REG_GRP_BTN,
2442 IQS7222_REG_KEY_DEBOUNCE);
2443 }
2444
iqs7222_parse_sldr(struct iqs7222_private * iqs7222,struct fwnode_handle * sldr_node,int sldr_index)2445 static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222,
2446 struct fwnode_handle *sldr_node, int sldr_index)
2447 {
2448 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2449 struct i2c_client *client = iqs7222->client;
2450 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2451 int ext_chan = rounddown(num_chan, 10);
2452 int count, error, reg_offset, i;
2453 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2454 u16 *sldr_setup = iqs7222->sldr_setup[sldr_index];
2455 unsigned int chan_sel[4], val;
2456
2457 /*
2458 * Each slider can be spread across 3 to 4 channels. It is possible to
2459 * select only 2 channels, but doing so prevents the slider from using
2460 * the specified resolution.
2461 */
2462 count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select");
2463 if (count < 0) {
2464 dev_err(&client->dev, "Failed to count %s channels: %d\n",
2465 fwnode_get_name(sldr_node), count);
2466 return count;
2467 } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) {
2468 dev_err(&client->dev, "Invalid number of %s channels\n",
2469 fwnode_get_name(sldr_node));
2470 return -EINVAL;
2471 }
2472
2473 error = fwnode_property_read_u32_array(sldr_node,
2474 "azoteq,channel-select",
2475 chan_sel, count);
2476 if (error) {
2477 dev_err(&client->dev, "Failed to read %s channels: %d\n",
2478 fwnode_get_name(sldr_node), error);
2479 return error;
2480 }
2481
2482 /*
2483 * Resolution and top speed, if small enough, are packed into a single
2484 * register. Otherwise, each occupies its own register and the rest of
2485 * the slider-related register addresses are offset by one.
2486 */
2487 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1;
2488
2489 sldr_setup[0] |= count;
2490 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0);
2491
2492 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2493 sldr_setup[5 + reg_offset + i] = 0;
2494 if (i >= count)
2495 continue;
2496
2497 if (chan_sel[i] >= ext_chan) {
2498 dev_err(&client->dev, "Invalid %s channel: %u\n",
2499 fwnode_get_name(sldr_node), chan_sel[i]);
2500 return -EINVAL;
2501 }
2502
2503 /*
2504 * The following fields indicate which channels participate in
2505 * the slider, as well as each channel's relative placement.
2506 */
2507 sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]);
2508 sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080;
2509 }
2510
2511 sldr_setup[4 + reg_offset] = dev_desc->touch_link;
2512 if (fwnode_property_present(sldr_node, "azoteq,use-prox"))
2513 sldr_setup[4 + reg_offset] -= 2;
2514
2515 error = fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val);
2516 if (!error) {
2517 if (val > dev_desc->sldr_res) {
2518 dev_err(&client->dev, "Invalid %s size: %u\n",
2519 fwnode_get_name(sldr_node), val);
2520 return -EINVAL;
2521 }
2522
2523 if (reg_offset) {
2524 sldr_setup[3] = val;
2525 } else {
2526 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK;
2527 sldr_setup[2] |= (val / 16 <<
2528 IQS7222_SLDR_SETUP_2_RES_SHIFT);
2529 }
2530 } else if (error != -EINVAL) {
2531 dev_err(&client->dev, "Failed to read %s size: %d\n",
2532 fwnode_get_name(sldr_node), error);
2533 return error;
2534 }
2535
2536 if (!(reg_offset ? sldr_setup[3]
2537 : sldr_setup[2] & IQS7222_SLDR_SETUP_2_RES_MASK)) {
2538 dev_err(&client->dev, "Undefined %s size\n",
2539 fwnode_get_name(sldr_node));
2540 return -EINVAL;
2541 }
2542
2543 error = fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val);
2544 if (!error) {
2545 if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) {
2546 dev_err(&client->dev, "Invalid %s top speed: %u\n",
2547 fwnode_get_name(sldr_node), val);
2548 return -EINVAL;
2549 }
2550
2551 if (reg_offset) {
2552 sldr_setup[2] = val;
2553 } else {
2554 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK;
2555 sldr_setup[2] |= (val / 4);
2556 }
2557 } else if (error != -EINVAL) {
2558 dev_err(&client->dev, "Failed to read %s top speed: %d\n",
2559 fwnode_get_name(sldr_node), error);
2560 return error;
2561 }
2562
2563 error = fwnode_property_read_u32(sldr_node, "linux,axis", &val);
2564 if (!error) {
2565 u16 sldr_max = sldr_setup[3] - 1;
2566
2567 if (!reg_offset) {
2568 sldr_max = sldr_setup[2];
2569
2570 sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK;
2571 sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT;
2572
2573 sldr_max = sldr_max * 16 - 1;
2574 }
2575
2576 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0);
2577 iqs7222->sl_axis[sldr_index] = val;
2578 } else if (error != -EINVAL) {
2579 dev_err(&client->dev, "Failed to read %s axis: %d\n",
2580 fwnode_get_name(sldr_node), error);
2581 return error;
2582 }
2583
2584 if (dev_desc->wheel_enable) {
2585 sldr_setup[0] &= ~dev_desc->wheel_enable;
2586 if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL)
2587 sldr_setup[0] |= dev_desc->wheel_enable;
2588 }
2589
2590 /*
2591 * The absence of a register offset makes it safe to assume the device
2592 * supports gestures, each of which is first disabled until explicitly
2593 * enabled.
2594 */
2595 if (!reg_offset)
2596 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++)
2597 sldr_setup[9] &= ~iqs7222_sl_events[i].enable;
2598
2599 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) {
2600 const char *event_name = iqs7222_sl_events[i].name;
2601 struct fwnode_handle *event_node;
2602 enum iqs7222_reg_key_id reg_key;
2603
2604 event_node = fwnode_get_named_child_node(sldr_node, event_name);
2605 if (!event_node)
2606 continue;
2607
2608 /*
2609 * Depending on the device, gestures are either offered using
2610 * one of two timing resolutions, or are not supported at all.
2611 */
2612 if (reg_offset)
2613 reg_key = IQS7222_REG_KEY_RESERVED;
2614 else if (dev_desc->legacy_gesture &&
2615 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_TAP)
2616 reg_key = IQS7222_REG_KEY_TAP_LEGACY;
2617 else if (dev_desc->legacy_gesture &&
2618 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_AXIAL)
2619 reg_key = IQS7222_REG_KEY_AXIAL_LEGACY;
2620 else
2621 reg_key = iqs7222_sl_events[i].reg_key;
2622
2623 /*
2624 * The press/release event does not expose a direct GPIO link,
2625 * but one can be emulated by tying each of the participating
2626 * channels to the same GPIO.
2627 */
2628 error = iqs7222_parse_event(iqs7222, event_node, sldr_index,
2629 IQS7222_REG_GRP_SLDR, reg_key,
2630 i ? iqs7222_sl_events[i].enable
2631 : sldr_setup[3 + reg_offset],
2632 i ? 1568 + sldr_index * 30
2633 : sldr_setup[4 + reg_offset],
2634 NULL,
2635 &iqs7222->sl_code[sldr_index][i]);
2636 fwnode_handle_put(event_node);
2637 if (error)
2638 return error;
2639
2640 if (!reg_offset)
2641 sldr_setup[9] |= iqs7222_sl_events[i].enable;
2642
2643 if (!dev_desc->event_offset)
2644 continue;
2645
2646 /*
2647 * The press/release event is determined based on whether the
2648 * coordinate field reports 0xFFFF and solely relies on touch
2649 * or proximity interrupts to be unmasked.
2650 */
2651 if (i && !reg_offset)
2652 *event_mask |= (IQS7222_EVENT_MASK_SLDR << sldr_index);
2653 else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link)
2654 *event_mask |= IQS7222_EVENT_MASK_TOUCH;
2655 else
2656 *event_mask |= IQS7222_EVENT_MASK_PROX;
2657 }
2658
2659 /*
2660 * The following call handles a special pair of properties that shift
2661 * to make room for a wheel enable control in the case of IQS7222C.
2662 */
2663 return iqs7222_parse_props(iqs7222, sldr_node, sldr_index,
2664 IQS7222_REG_GRP_SLDR,
2665 dev_desc->wheel_enable ?
2666 IQS7222_REG_KEY_WHEEL :
2667 IQS7222_REG_KEY_NO_WHEEL);
2668 }
2669
iqs7222_parse_tpad(struct iqs7222_private * iqs7222,struct fwnode_handle * tpad_node,int tpad_index)2670 static int iqs7222_parse_tpad(struct iqs7222_private *iqs7222,
2671 struct fwnode_handle *tpad_node, int tpad_index)
2672 {
2673 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2674 struct touchscreen_properties *prop = &iqs7222->prop;
2675 struct i2c_client *client = iqs7222->client;
2676 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2677 int count, error, i;
2678 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2679 u16 *tpad_setup = iqs7222->tpad_setup;
2680 unsigned int chan_sel[12];
2681
2682 error = iqs7222_parse_props(iqs7222, tpad_node, tpad_index,
2683 IQS7222_REG_GRP_TPAD,
2684 IQS7222_REG_KEY_NONE);
2685 if (error)
2686 return error;
2687
2688 count = fwnode_property_count_u32(tpad_node, "azoteq,channel-select");
2689 if (count < 0) {
2690 dev_err(&client->dev, "Failed to count %s channels: %d\n",
2691 fwnode_get_name(tpad_node), count);
2692 return count;
2693 } else if (!count || count > ARRAY_SIZE(chan_sel)) {
2694 dev_err(&client->dev, "Invalid number of %s channels\n",
2695 fwnode_get_name(tpad_node));
2696 return -EINVAL;
2697 }
2698
2699 error = fwnode_property_read_u32_array(tpad_node,
2700 "azoteq,channel-select",
2701 chan_sel, count);
2702 if (error) {
2703 dev_err(&client->dev, "Failed to read %s channels: %d\n",
2704 fwnode_get_name(tpad_node), error);
2705 return error;
2706 }
2707
2708 tpad_setup[6] &= ~GENMASK(num_chan - 1, 0);
2709
2710 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2711 tpad_setup[8 + i] = 0;
2712 if (i >= count || chan_sel[i] == U8_MAX)
2713 continue;
2714
2715 if (chan_sel[i] >= num_chan) {
2716 dev_err(&client->dev, "Invalid %s channel: %u\n",
2717 fwnode_get_name(tpad_node), chan_sel[i]);
2718 return -EINVAL;
2719 }
2720
2721 /*
2722 * The following fields indicate which channels participate in
2723 * the trackpad, as well as each channel's relative placement.
2724 */
2725 tpad_setup[6] |= BIT(chan_sel[i]);
2726 tpad_setup[8 + i] = chan_sel[i] * 34 + 1072;
2727 }
2728
2729 tpad_setup[7] = dev_desc->touch_link;
2730 if (fwnode_property_present(tpad_node, "azoteq,use-prox"))
2731 tpad_setup[7] -= 2;
2732
2733 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++)
2734 tpad_setup[20] &= ~(iqs7222_tp_events[i].strict |
2735 iqs7222_tp_events[i].enable);
2736
2737 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) {
2738 const char *event_name = iqs7222_tp_events[i].name;
2739 struct fwnode_handle *event_node;
2740
2741 event_node = fwnode_get_named_child_node(tpad_node, event_name);
2742 if (!event_node)
2743 continue;
2744
2745 if (fwnode_property_present(event_node,
2746 "azoteq,gesture-angle-tighten"))
2747 tpad_setup[20] |= iqs7222_tp_events[i].strict;
2748
2749 tpad_setup[20] |= iqs7222_tp_events[i].enable;
2750
2751 error = iqs7222_parse_event(iqs7222, event_node, tpad_index,
2752 IQS7222_REG_GRP_TPAD,
2753 iqs7222_tp_events[i].reg_key,
2754 iqs7222_tp_events[i].link, 1566,
2755 NULL,
2756 &iqs7222->tp_code[i]);
2757 fwnode_handle_put(event_node);
2758 if (error)
2759 return error;
2760
2761 if (!dev_desc->event_offset)
2762 continue;
2763
2764 /*
2765 * The press/release event is determined based on whether the
2766 * coordinate fields report 0xFFFF and solely relies on touch
2767 * or proximity interrupts to be unmasked.
2768 */
2769 if (i)
2770 *event_mask |= IQS7222_EVENT_MASK_TPAD;
2771 else if (tpad_setup[7] == dev_desc->touch_link)
2772 *event_mask |= IQS7222_EVENT_MASK_TOUCH;
2773 else
2774 *event_mask |= IQS7222_EVENT_MASK_PROX;
2775 }
2776
2777 if (!iqs7222->tp_code[0])
2778 return 0;
2779
2780 input_set_abs_params(iqs7222->keypad, ABS_X,
2781 0, (tpad_setup[4] ? : 1) - 1, 0, 0);
2782
2783 input_set_abs_params(iqs7222->keypad, ABS_Y,
2784 0, (tpad_setup[5] ? : 1) - 1, 0, 0);
2785
2786 touchscreen_parse_properties(iqs7222->keypad, false, prop);
2787
2788 if (prop->max_x >= U16_MAX || prop->max_y >= U16_MAX) {
2789 dev_err(&client->dev, "Invalid trackpad size: %u*%u\n",
2790 prop->max_x, prop->max_y);
2791 return -EINVAL;
2792 }
2793
2794 tpad_setup[4] = prop->max_x + 1;
2795 tpad_setup[5] = prop->max_y + 1;
2796
2797 return 0;
2798 }
2799
2800 static int (*iqs7222_parse_extra[IQS7222_NUM_REG_GRPS])
2801 (struct iqs7222_private *iqs7222,
2802 struct fwnode_handle *reg_grp_node,
2803 int reg_grp_index) = {
2804 [IQS7222_REG_GRP_CYCLE] = iqs7222_parse_cycle,
2805 [IQS7222_REG_GRP_CHAN] = iqs7222_parse_chan,
2806 [IQS7222_REG_GRP_SLDR] = iqs7222_parse_sldr,
2807 [IQS7222_REG_GRP_TPAD] = iqs7222_parse_tpad,
2808 };
2809
iqs7222_parse_reg_grp(struct iqs7222_private * iqs7222,enum iqs7222_reg_grp_id reg_grp,int reg_grp_index)2810 static int iqs7222_parse_reg_grp(struct iqs7222_private *iqs7222,
2811 enum iqs7222_reg_grp_id reg_grp,
2812 int reg_grp_index)
2813 {
2814 struct i2c_client *client = iqs7222->client;
2815 struct fwnode_handle *reg_grp_node;
2816 int error;
2817
2818 if (iqs7222_reg_grp_names[reg_grp]) {
2819 char reg_grp_name[16];
2820
2821 snprintf(reg_grp_name, sizeof(reg_grp_name),
2822 iqs7222_reg_grp_names[reg_grp], reg_grp_index);
2823
2824 reg_grp_node = device_get_named_child_node(&client->dev,
2825 reg_grp_name);
2826 } else {
2827 reg_grp_node = fwnode_handle_get(dev_fwnode(&client->dev));
2828 }
2829
2830 if (!reg_grp_node)
2831 return 0;
2832
2833 error = iqs7222_parse_props(iqs7222, reg_grp_node, reg_grp_index,
2834 reg_grp, IQS7222_REG_KEY_NONE);
2835
2836 if (!error && iqs7222_parse_extra[reg_grp])
2837 error = iqs7222_parse_extra[reg_grp](iqs7222, reg_grp_node,
2838 reg_grp_index);
2839
2840 fwnode_handle_put(reg_grp_node);
2841
2842 return error;
2843 }
2844
iqs7222_parse_all(struct iqs7222_private * iqs7222)2845 static int iqs7222_parse_all(struct iqs7222_private *iqs7222)
2846 {
2847 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2848 const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps;
2849 u16 *sys_setup = iqs7222->sys_setup;
2850 int error, i, j;
2851
2852 if (dev_desc->allow_offset)
2853 sys_setup[dev_desc->allow_offset] = U16_MAX;
2854
2855 if (dev_desc->event_offset)
2856 sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI;
2857
2858 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) {
2859 u16 *gpio_setup = iqs7222->gpio_setup[i];
2860
2861 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN;
2862 gpio_setup[1] = 0;
2863 gpio_setup[2] = 0;
2864
2865 if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1)
2866 continue;
2867
2868 /*
2869 * The IQS7222C and IQS7222D expose multiple GPIO and must be
2870 * informed as to which GPIO this group represents.
2871 */
2872 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++)
2873 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]);
2874
2875 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]);
2876 }
2877
2878 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {
2879 u16 *chan_setup = iqs7222->chan_setup[i];
2880
2881 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK;
2882 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN;
2883
2884 chan_setup[5] = 0;
2885 }
2886
2887 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2888 u16 *sldr_setup = iqs7222->sldr_setup[i];
2889
2890 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK;
2891 }
2892
2893 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
2894 for (j = 0; j < reg_grps[i].num_row; j++) {
2895 error = iqs7222_parse_reg_grp(iqs7222, i, j);
2896 if (error)
2897 return error;
2898 }
2899 }
2900
2901 return 0;
2902 }
2903
iqs7222_report(struct iqs7222_private * iqs7222)2904 static int iqs7222_report(struct iqs7222_private *iqs7222)
2905 {
2906 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2907 struct i2c_client *client = iqs7222->client;
2908 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2909 int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col;
2910 int error, i, j;
2911 __le16 status[IQS7222_MAX_COLS_STAT];
2912
2913 error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status,
2914 num_stat * sizeof(*status));
2915 if (error)
2916 return error;
2917
2918 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) {
2919 dev_err(&client->dev, "Unexpected device reset\n");
2920 return iqs7222_dev_init(iqs7222, WRITE);
2921 }
2922
2923 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) {
2924 dev_err(&client->dev, "Unexpected ATI error\n");
2925 return iqs7222_ati_trigger(iqs7222);
2926 }
2927
2928 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE)
2929 return 0;
2930
2931 for (i = 0; i < num_chan; i++) {
2932 u16 *chan_setup = iqs7222->chan_setup[i];
2933
2934 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN))
2935 continue;
2936
2937 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) {
2938 /*
2939 * Proximity state begins at offset 2 and spills into
2940 * offset 3 for devices with more than 16 channels.
2941 *
2942 * Touch state begins at the first offset immediately
2943 * following proximity state.
2944 */
2945 int k = 2 + j * (num_chan > 16 ? 2 : 1);
2946 u16 state = le16_to_cpu(status[k + i / 16]);
2947
2948 if (!iqs7222->kp_type[i][j])
2949 continue;
2950
2951 input_event(iqs7222->keypad,
2952 iqs7222->kp_type[i][j],
2953 iqs7222->kp_code[i][j],
2954 !!(state & BIT(i % 16)));
2955 }
2956 }
2957
2958 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2959 u16 *sldr_setup = iqs7222->sldr_setup[i];
2960 u16 sldr_pos = le16_to_cpu(status[4 + i]);
2961 u16 state = le16_to_cpu(status[6 + i]);
2962
2963 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK))
2964 continue;
2965
2966 if (sldr_pos < dev_desc->sldr_res)
2967 input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i],
2968 sldr_pos);
2969
2970 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0],
2971 sldr_pos < dev_desc->sldr_res);
2972
2973 /*
2974 * A maximum resolution indicates the device does not support
2975 * gestures, in which case the remaining fields are ignored.
2976 */
2977 if (dev_desc->sldr_res == U16_MAX)
2978 continue;
2979
2980 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_SLDR << i))
2981 continue;
2982
2983 /*
2984 * Skip the press/release event, as it does not have separate
2985 * status fields and is handled separately.
2986 */
2987 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) {
2988 u16 mask = iqs7222_sl_events[j].mask;
2989 u16 val = iqs7222_sl_events[j].val;
2990
2991 input_report_key(iqs7222->keypad,
2992 iqs7222->sl_code[i][j],
2993 (state & mask) == val);
2994 }
2995
2996 input_sync(iqs7222->keypad);
2997
2998 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++)
2999 input_report_key(iqs7222->keypad,
3000 iqs7222->sl_code[i][j], 0);
3001 }
3002
3003 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row; i++) {
3004 u16 tpad_pos_x = le16_to_cpu(status[4]);
3005 u16 tpad_pos_y = le16_to_cpu(status[5]);
3006 u16 state = le16_to_cpu(status[6]);
3007
3008 input_report_key(iqs7222->keypad, iqs7222->tp_code[0],
3009 tpad_pos_x < U16_MAX);
3010
3011 if (tpad_pos_x < U16_MAX)
3012 touchscreen_report_pos(iqs7222->keypad, &iqs7222->prop,
3013 tpad_pos_x, tpad_pos_y, false);
3014
3015 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_TPAD))
3016 continue;
3017
3018 /*
3019 * Skip the press/release event, as it does not have separate
3020 * status fields and is handled separately.
3021 */
3022 for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++) {
3023 u16 mask = iqs7222_tp_events[j].mask;
3024 u16 val = iqs7222_tp_events[j].val;
3025
3026 input_report_key(iqs7222->keypad,
3027 iqs7222->tp_code[j],
3028 (state & mask) == val);
3029 }
3030
3031 input_sync(iqs7222->keypad);
3032
3033 for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++)
3034 input_report_key(iqs7222->keypad,
3035 iqs7222->tp_code[j], 0);
3036 }
3037
3038 input_sync(iqs7222->keypad);
3039
3040 return 0;
3041 }
3042
iqs7222_irq(int irq,void * context)3043 static irqreturn_t iqs7222_irq(int irq, void *context)
3044 {
3045 struct iqs7222_private *iqs7222 = context;
3046
3047 return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED;
3048 }
3049
iqs7222_probe(struct i2c_client * client)3050 static int iqs7222_probe(struct i2c_client *client)
3051 {
3052 struct iqs7222_private *iqs7222;
3053 unsigned long irq_flags;
3054 int error, irq;
3055
3056 iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL);
3057 if (!iqs7222)
3058 return -ENOMEM;
3059
3060 i2c_set_clientdata(client, iqs7222);
3061 iqs7222->client = client;
3062
3063 iqs7222->keypad = devm_input_allocate_device(&client->dev);
3064 if (!iqs7222->keypad)
3065 return -ENOMEM;
3066
3067 iqs7222->keypad->name = client->name;
3068 iqs7222->keypad->id.bustype = BUS_I2C;
3069
3070 /*
3071 * The RDY pin behaves as an interrupt, but must also be polled ahead
3072 * of unsolicited I2C communication. As such, it is first opened as a
3073 * GPIO and then passed to gpiod_to_irq() to register the interrupt.
3074 */
3075 iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN);
3076 if (IS_ERR(iqs7222->irq_gpio)) {
3077 error = PTR_ERR(iqs7222->irq_gpio);
3078 dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n",
3079 error);
3080 return error;
3081 }
3082
3083 iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3084 GPIOD_OUT_HIGH);
3085 if (IS_ERR(iqs7222->reset_gpio)) {
3086 error = PTR_ERR(iqs7222->reset_gpio);
3087 dev_err(&client->dev, "Failed to request reset GPIO: %d\n",
3088 error);
3089 return error;
3090 }
3091
3092 error = iqs7222_hard_reset(iqs7222);
3093 if (error)
3094 return error;
3095
3096 error = iqs7222_dev_info(iqs7222);
3097 if (error)
3098 return error;
3099
3100 error = iqs7222_dev_init(iqs7222, READ);
3101 if (error)
3102 return error;
3103
3104 error = iqs7222_parse_all(iqs7222);
3105 if (error)
3106 return error;
3107
3108 error = iqs7222_dev_init(iqs7222, WRITE);
3109 if (error)
3110 return error;
3111
3112 error = iqs7222_report(iqs7222);
3113 if (error)
3114 return error;
3115
3116 error = input_register_device(iqs7222->keypad);
3117 if (error) {
3118 dev_err(&client->dev, "Failed to register device: %d\n", error);
3119 return error;
3120 }
3121
3122 irq = gpiod_to_irq(iqs7222->irq_gpio);
3123 if (irq < 0)
3124 return irq;
3125
3126 irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW
3127 : IRQF_TRIGGER_HIGH;
3128 irq_flags |= IRQF_ONESHOT;
3129
3130 error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq,
3131 irq_flags, client->name, iqs7222);
3132 if (error)
3133 dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
3134
3135 return error;
3136 }
3137
3138 static const struct of_device_id iqs7222_of_match[] = {
3139 { .compatible = "azoteq,iqs7222a" },
3140 { .compatible = "azoteq,iqs7222b" },
3141 { .compatible = "azoteq,iqs7222c" },
3142 { .compatible = "azoteq,iqs7222d" },
3143 { }
3144 };
3145 MODULE_DEVICE_TABLE(of, iqs7222_of_match);
3146
3147 static struct i2c_driver iqs7222_i2c_driver = {
3148 .driver = {
3149 .name = "iqs7222",
3150 .of_match_table = iqs7222_of_match,
3151 },
3152 .probe = iqs7222_probe,
3153 };
3154 module_i2c_driver(iqs7222_i2c_driver);
3155
3156 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
3157 MODULE_DESCRIPTION("Azoteq IQS7222A/B/C/D Capacitive Touch Controller");
3158 MODULE_LICENSE("GPL");
3159