1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sony IMX290 CMOS Image Sensor Driver 4 * 5 * Copyright (C) 2019 FRAMOS GmbH. 6 * 7 * Copyright (C) 2019 Linaro Ltd. 8 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 21 #include <asm/unaligned.h> 22 23 #include <media/media-entity.h> 24 #include <media/v4l2-cci.h> 25 #include <media/v4l2-ctrls.h> 26 #include <media/v4l2-device.h> 27 #include <media/v4l2-event.h> 28 #include <media/v4l2-fwnode.h> 29 #include <media/v4l2-subdev.h> 30 31 #define IMX290_STANDBY CCI_REG8(0x3000) 32 #define IMX290_REGHOLD CCI_REG8(0x3001) 33 #define IMX290_XMSTA CCI_REG8(0x3002) 34 #define IMX290_ADBIT CCI_REG8(0x3005) 35 #define IMX290_ADBIT_10BIT (0 << 0) 36 #define IMX290_ADBIT_12BIT (1 << 0) 37 #define IMX290_CTRL_07 CCI_REG8(0x3007) 38 #define IMX290_VREVERSE BIT(0) 39 #define IMX290_HREVERSE BIT(1) 40 #define IMX290_WINMODE_1080P (0 << 4) 41 #define IMX290_WINMODE_720P (1 << 4) 42 #define IMX290_WINMODE_CROP (4 << 4) 43 #define IMX290_FR_FDG_SEL CCI_REG8(0x3009) 44 #define IMX290_BLKLEVEL CCI_REG16_LE(0x300a) 45 #define IMX290_GAIN CCI_REG8(0x3014) 46 #define IMX290_VMAX CCI_REG24_LE(0x3018) 47 #define IMX290_VMAX_MAX 0x3ffff 48 #define IMX290_HMAX CCI_REG16_LE(0x301c) 49 #define IMX290_HMAX_MAX 0xffff 50 #define IMX290_SHS1 CCI_REG24_LE(0x3020) 51 #define IMX290_WINWV_OB CCI_REG8(0x303a) 52 #define IMX290_WINPV CCI_REG16_LE(0x303c) 53 #define IMX290_WINWV CCI_REG16_LE(0x303e) 54 #define IMX290_WINPH CCI_REG16_LE(0x3040) 55 #define IMX290_WINWH CCI_REG16_LE(0x3042) 56 #define IMX290_OUT_CTRL CCI_REG8(0x3046) 57 #define IMX290_ODBIT_10BIT (0 << 0) 58 #define IMX290_ODBIT_12BIT (1 << 0) 59 #define IMX290_OPORTSEL_PARALLEL (0x0 << 4) 60 #define IMX290_OPORTSEL_LVDS_2CH (0xd << 4) 61 #define IMX290_OPORTSEL_LVDS_4CH (0xe << 4) 62 #define IMX290_OPORTSEL_LVDS_8CH (0xf << 4) 63 #define IMX290_XSOUTSEL CCI_REG8(0x304b) 64 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0) 65 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0) 66 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2) 67 #define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2) 68 #define IMX290_INCKSEL1 CCI_REG8(0x305c) 69 #define IMX290_INCKSEL2 CCI_REG8(0x305d) 70 #define IMX290_INCKSEL3 CCI_REG8(0x305e) 71 #define IMX290_INCKSEL4 CCI_REG8(0x305f) 72 #define IMX290_PGCTRL CCI_REG8(0x308c) 73 #define IMX290_ADBIT1 CCI_REG8(0x3129) 74 #define IMX290_ADBIT1_10BIT 0x1d 75 #define IMX290_ADBIT1_12BIT 0x00 76 #define IMX290_INCKSEL5 CCI_REG8(0x315e) 77 #define IMX290_INCKSEL6 CCI_REG8(0x3164) 78 #define IMX290_ADBIT2 CCI_REG8(0x317c) 79 #define IMX290_ADBIT2_10BIT 0x12 80 #define IMX290_ADBIT2_12BIT 0x00 81 #define IMX290_CHIP_ID CCI_REG16_LE(0x319a) 82 #define IMX290_ADBIT3 CCI_REG8(0x31ec) 83 #define IMX290_ADBIT3_10BIT 0x37 84 #define IMX290_ADBIT3_12BIT 0x0e 85 #define IMX290_REPETITION CCI_REG8(0x3405) 86 #define IMX290_PHY_LANE_NUM CCI_REG8(0x3407) 87 #define IMX290_OPB_SIZE_V CCI_REG8(0x3414) 88 #define IMX290_Y_OUT_SIZE CCI_REG16_LE(0x3418) 89 #define IMX290_CSI_DT_FMT CCI_REG16_LE(0x3441) 90 #define IMX290_CSI_DT_FMT_RAW10 0x0a0a 91 #define IMX290_CSI_DT_FMT_RAW12 0x0c0c 92 #define IMX290_CSI_LANE_MODE CCI_REG8(0x3443) 93 #define IMX290_EXTCK_FREQ CCI_REG16_LE(0x3444) 94 #define IMX290_TCLKPOST CCI_REG16_LE(0x3446) 95 #define IMX290_THSZERO CCI_REG16_LE(0x3448) 96 #define IMX290_THSPREPARE CCI_REG16_LE(0x344a) 97 #define IMX290_TCLKTRAIL CCI_REG16_LE(0x344c) 98 #define IMX290_THSTRAIL CCI_REG16_LE(0x344e) 99 #define IMX290_TCLKZERO CCI_REG16_LE(0x3450) 100 #define IMX290_TCLKPREPARE CCI_REG16_LE(0x3452) 101 #define IMX290_TLPX CCI_REG16_LE(0x3454) 102 #define IMX290_X_OUT_SIZE CCI_REG16_LE(0x3472) 103 #define IMX290_INCKSEL7 CCI_REG8(0x3480) 104 105 #define IMX290_PGCTRL_REGEN BIT(0) 106 #define IMX290_PGCTRL_THRU BIT(1) 107 #define IMX290_PGCTRL_MODE(n) ((n) << 4) 108 109 /* Number of lines by which exposure must be less than VMAX */ 110 #define IMX290_EXPOSURE_OFFSET 2 111 112 #define IMX290_PIXEL_RATE 148500000 113 114 /* 115 * The IMX290 pixel array is organized as follows: 116 * 117 * +------------------------------------+ 118 * | Optical Black | } Vertical effective optical black (10) 119 * +---+------------------------------------+---+ 120 * | | | | } Effective top margin (8) 121 * | | +----------------------------+ | | \ 122 * | | | | | | | 123 * | | | | | | | 124 * | | | | | | | 125 * | | | Recording Pixel Area | | | | Recommended height (1080) 126 * | | | | | | | 127 * | | | | | | | 128 * | | | | | | | 129 * | | +----------------------------+ | | / 130 * | | | | } Effective bottom margin (9) 131 * +---+------------------------------------+---+ 132 * <-> <-> <--------------------------> <-> <-> 133 * \---- Ignored right margin (4) 134 * \-------- Effective right margin (9) 135 * \------------------------- Recommended width (1920) 136 * \----------------------------------------- Effective left margin (8) 137 * \--------------------------------------------- Ignored left margin (4) 138 * 139 * The optical black lines are output over CSI-2 with a separate data type. 140 * 141 * The pixel array is meant to have 1920x1080 usable pixels after image 142 * processing in an ISP. It has 8 (9) extra active pixels usable for color 143 * processing in the ISP on the top and left (bottom and right) sides of the 144 * image. In addition, 4 additional pixels are present on the left and right 145 * sides of the image, documented as "ignored area". 146 * 147 * As far as is understood, all pixels of the pixel array (ignored area, color 148 * processing margins and recording area) can be output by the sensor. 149 */ 150 151 #define IMX290_PIXEL_ARRAY_WIDTH 1945 152 #define IMX290_PIXEL_ARRAY_HEIGHT 1097 153 #define IMX290_PIXEL_ARRAY_MARGIN_LEFT 12 154 #define IMX290_PIXEL_ARRAY_MARGIN_RIGHT 13 155 #define IMX290_PIXEL_ARRAY_MARGIN_TOP 8 156 #define IMX290_PIXEL_ARRAY_MARGIN_BOTTOM 9 157 #define IMX290_PIXEL_ARRAY_RECORDING_WIDTH 1920 158 #define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT 1080 159 160 /* Equivalent value for 16bpp */ 161 #define IMX290_BLACK_LEVEL_DEFAULT 3840 162 163 #define IMX290_NUM_SUPPLIES 3 164 165 enum imx290_colour_variant { 166 IMX290_VARIANT_COLOUR, 167 IMX290_VARIANT_MONO, 168 IMX290_VARIANT_MAX 169 }; 170 171 enum imx290_model { 172 IMX290_MODEL_IMX290LQR, 173 IMX290_MODEL_IMX290LLR, 174 IMX290_MODEL_IMX327LQR, 175 }; 176 177 struct imx290_model_info { 178 enum imx290_colour_variant colour_variant; 179 const struct cci_reg_sequence *init_regs; 180 size_t init_regs_num; 181 const char *name; 182 }; 183 184 enum imx290_clk_freq { 185 IMX290_CLK_37_125, 186 IMX290_CLK_74_25, 187 IMX290_NUM_CLK 188 }; 189 190 /* 191 * Clock configuration for registers INCKSEL1 to INCKSEL6. 192 */ 193 struct imx290_clk_cfg { 194 u8 incksel1; 195 u8 incksel2; 196 u8 incksel3; 197 u8 incksel4; 198 u8 incksel5; 199 u8 incksel6; 200 }; 201 202 struct imx290_mode { 203 u32 width; 204 u32 height; 205 u32 hmax_min; 206 u32 vmax_min; 207 u8 link_freq_index; 208 u8 ctrl_07; 209 210 const struct cci_reg_sequence *data; 211 u32 data_size; 212 213 const struct imx290_clk_cfg *clk_cfg; 214 }; 215 216 struct imx290_csi_cfg { 217 u16 repetition; 218 u16 tclkpost; 219 u16 thszero; 220 u16 thsprepare; 221 u16 tclktrail; 222 u16 thstrail; 223 u16 tclkzero; 224 u16 tclkprepare; 225 u16 tlpx; 226 }; 227 228 struct imx290 { 229 struct device *dev; 230 struct clk *xclk; 231 struct regmap *regmap; 232 enum imx290_clk_freq xclk_idx; 233 u8 nlanes; 234 const struct imx290_model_info *model; 235 236 struct v4l2_subdev sd; 237 struct media_pad pad; 238 239 const struct imx290_mode *current_mode; 240 241 struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES]; 242 struct gpio_desc *rst_gpio; 243 244 struct v4l2_ctrl_handler ctrls; 245 struct v4l2_ctrl *link_freq; 246 struct v4l2_ctrl *hblank; 247 struct v4l2_ctrl *vblank; 248 struct v4l2_ctrl *exposure; 249 struct { 250 struct v4l2_ctrl *hflip; 251 struct v4l2_ctrl *vflip; 252 }; 253 }; 254 to_imx290(struct v4l2_subdev * _sd)255 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd) 256 { 257 return container_of(_sd, struct imx290, sd); 258 } 259 260 /* ----------------------------------------------------------------------------- 261 * Modes and formats 262 */ 263 264 static const struct cci_reg_sequence imx290_global_init_settings[] = { 265 { IMX290_WINWV_OB, 12 }, 266 { IMX290_WINPH, 0 }, 267 { IMX290_WINPV, 0 }, 268 { IMX290_WINWH, 1948 }, 269 { IMX290_WINWV, 1097 }, 270 { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC | 271 IMX290_XSOUTSEL_XHSOUTSEL_HSYNC }, 272 { CCI_REG8(0x3012), 0x64 }, 273 { CCI_REG8(0x3013), 0x00 }, 274 }; 275 276 static const struct cci_reg_sequence imx290_global_init_settings_290[] = { 277 { CCI_REG8(0x300f), 0x00 }, 278 { CCI_REG8(0x3010), 0x21 }, 279 { CCI_REG8(0x3011), 0x00 }, 280 { CCI_REG8(0x3016), 0x09 }, 281 { CCI_REG8(0x3070), 0x02 }, 282 { CCI_REG8(0x3071), 0x11 }, 283 { CCI_REG8(0x309b), 0x10 }, 284 { CCI_REG8(0x309c), 0x22 }, 285 { CCI_REG8(0x30a2), 0x02 }, 286 { CCI_REG8(0x30a6), 0x20 }, 287 { CCI_REG8(0x30a8), 0x20 }, 288 { CCI_REG8(0x30aa), 0x20 }, 289 { CCI_REG8(0x30ac), 0x20 }, 290 { CCI_REG8(0x30b0), 0x43 }, 291 { CCI_REG8(0x3119), 0x9e }, 292 { CCI_REG8(0x311c), 0x1e }, 293 { CCI_REG8(0x311e), 0x08 }, 294 { CCI_REG8(0x3128), 0x05 }, 295 { CCI_REG8(0x313d), 0x83 }, 296 { CCI_REG8(0x3150), 0x03 }, 297 { CCI_REG8(0x317e), 0x00 }, 298 { CCI_REG8(0x32b8), 0x50 }, 299 { CCI_REG8(0x32b9), 0x10 }, 300 { CCI_REG8(0x32ba), 0x00 }, 301 { CCI_REG8(0x32bb), 0x04 }, 302 { CCI_REG8(0x32c8), 0x50 }, 303 { CCI_REG8(0x32c9), 0x10 }, 304 { CCI_REG8(0x32ca), 0x00 }, 305 { CCI_REG8(0x32cb), 0x04 }, 306 { CCI_REG8(0x332c), 0xd3 }, 307 { CCI_REG8(0x332d), 0x10 }, 308 { CCI_REG8(0x332e), 0x0d }, 309 { CCI_REG8(0x3358), 0x06 }, 310 { CCI_REG8(0x3359), 0xe1 }, 311 { CCI_REG8(0x335a), 0x11 }, 312 { CCI_REG8(0x3360), 0x1e }, 313 { CCI_REG8(0x3361), 0x61 }, 314 { CCI_REG8(0x3362), 0x10 }, 315 { CCI_REG8(0x33b0), 0x50 }, 316 { CCI_REG8(0x33b2), 0x1a }, 317 { CCI_REG8(0x33b3), 0x04 }, 318 }; 319 320 #define IMX290_NUM_CLK_REGS 2 321 static const struct cci_reg_sequence xclk_regs[][IMX290_NUM_CLK_REGS] = { 322 [IMX290_CLK_37_125] = { 323 { IMX290_EXTCK_FREQ, (37125 * 256) / 1000 }, 324 { IMX290_INCKSEL7, 0x49 }, 325 }, 326 [IMX290_CLK_74_25] = { 327 { IMX290_EXTCK_FREQ, (74250 * 256) / 1000 }, 328 { IMX290_INCKSEL7, 0x92 }, 329 }, 330 }; 331 332 static const struct cci_reg_sequence imx290_global_init_settings_327[] = { 333 { CCI_REG8(0x3011), 0x02 }, 334 { CCI_REG8(0x309e), 0x4A }, 335 { CCI_REG8(0x309f), 0x4A }, 336 { CCI_REG8(0x313b), 0x61 }, 337 }; 338 339 static const struct cci_reg_sequence imx290_1080p_settings[] = { 340 /* mode settings */ 341 { IMX290_WINWV_OB, 12 }, 342 { IMX290_OPB_SIZE_V, 10 }, 343 { IMX290_X_OUT_SIZE, 1920 }, 344 { IMX290_Y_OUT_SIZE, 1080 }, 345 }; 346 347 static const struct cci_reg_sequence imx290_720p_settings[] = { 348 /* mode settings */ 349 { IMX290_WINWV_OB, 6 }, 350 { IMX290_OPB_SIZE_V, 4 }, 351 { IMX290_X_OUT_SIZE, 1280 }, 352 { IMX290_Y_OUT_SIZE, 720 }, 353 }; 354 355 static const struct cci_reg_sequence imx290_10bit_settings[] = { 356 { IMX290_ADBIT, IMX290_ADBIT_10BIT }, 357 { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT }, 358 { IMX290_ADBIT1, IMX290_ADBIT1_10BIT }, 359 { IMX290_ADBIT2, IMX290_ADBIT2_10BIT }, 360 { IMX290_ADBIT3, IMX290_ADBIT3_10BIT }, 361 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 }, 362 }; 363 364 static const struct cci_reg_sequence imx290_12bit_settings[] = { 365 { IMX290_ADBIT, IMX290_ADBIT_12BIT }, 366 { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT }, 367 { IMX290_ADBIT1, IMX290_ADBIT1_12BIT }, 368 { IMX290_ADBIT2, IMX290_ADBIT2_12BIT }, 369 { IMX290_ADBIT3, IMX290_ADBIT3_12BIT }, 370 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 }, 371 }; 372 373 static const struct imx290_csi_cfg imx290_csi_222_75mhz = { 374 /* 222.75MHz or 445.5Mbit/s per lane */ 375 .repetition = 0x10, 376 .tclkpost = 87, 377 .thszero = 55, 378 .thsprepare = 31, 379 .tclktrail = 31, 380 .thstrail = 31, 381 .tclkzero = 119, 382 .tclkprepare = 31, 383 .tlpx = 23, 384 }; 385 386 static const struct imx290_csi_cfg imx290_csi_445_5mhz = { 387 /* 445.5MHz or 891Mbit/s per lane */ 388 .repetition = 0x00, 389 .tclkpost = 119, 390 .thszero = 103, 391 .thsprepare = 71, 392 .tclktrail = 55, 393 .thstrail = 63, 394 .tclkzero = 255, 395 .tclkprepare = 63, 396 .tlpx = 55, 397 }; 398 399 static const struct imx290_csi_cfg imx290_csi_148_5mhz = { 400 /* 148.5MHz or 297Mbit/s per lane */ 401 .repetition = 0x10, 402 .tclkpost = 79, 403 .thszero = 47, 404 .thsprepare = 23, 405 .tclktrail = 23, 406 .thstrail = 23, 407 .tclkzero = 87, 408 .tclkprepare = 23, 409 .tlpx = 23, 410 }; 411 412 static const struct imx290_csi_cfg imx290_csi_297mhz = { 413 /* 297MHz or 594Mbit/s per lane */ 414 .repetition = 0x00, 415 .tclkpost = 103, 416 .thszero = 87, 417 .thsprepare = 47, 418 .tclktrail = 39, 419 .thstrail = 47, 420 .tclkzero = 191, 421 .tclkprepare = 47, 422 .tlpx = 39, 423 }; 424 425 /* supported link frequencies */ 426 #define FREQ_INDEX_1080P 0 427 #define FREQ_INDEX_720P 1 428 static const s64 imx290_link_freq_2lanes[] = { 429 [FREQ_INDEX_1080P] = 445500000, 430 [FREQ_INDEX_720P] = 297000000, 431 }; 432 433 static const s64 imx290_link_freq_4lanes[] = { 434 [FREQ_INDEX_1080P] = 222750000, 435 [FREQ_INDEX_720P] = 148500000, 436 }; 437 438 /* 439 * In this function and in the similar ones below We rely on imx290_probe() 440 * to ensure that nlanes is either 2 or 4. 441 */ imx290_link_freqs_ptr(const struct imx290 * imx290)442 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290) 443 { 444 if (imx290->nlanes == 2) 445 return imx290_link_freq_2lanes; 446 else 447 return imx290_link_freq_4lanes; 448 } 449 imx290_link_freqs_num(const struct imx290 * imx290)450 static inline int imx290_link_freqs_num(const struct imx290 *imx290) 451 { 452 if (imx290->nlanes == 2) 453 return ARRAY_SIZE(imx290_link_freq_2lanes); 454 else 455 return ARRAY_SIZE(imx290_link_freq_4lanes); 456 } 457 458 static const struct imx290_clk_cfg imx290_1080p_clock_config[] = { 459 [IMX290_CLK_37_125] = { 460 /* 37.125MHz clock config */ 461 .incksel1 = 0x18, 462 .incksel2 = 0x03, 463 .incksel3 = 0x20, 464 .incksel4 = 0x01, 465 .incksel5 = 0x1a, 466 .incksel6 = 0x1a, 467 }, 468 [IMX290_CLK_74_25] = { 469 /* 74.25MHz clock config */ 470 .incksel1 = 0x0c, 471 .incksel2 = 0x03, 472 .incksel3 = 0x10, 473 .incksel4 = 0x01, 474 .incksel5 = 0x1b, 475 .incksel6 = 0x1b, 476 }, 477 }; 478 479 static const struct imx290_clk_cfg imx290_720p_clock_config[] = { 480 [IMX290_CLK_37_125] = { 481 /* 37.125MHz clock config */ 482 .incksel1 = 0x20, 483 .incksel2 = 0x00, 484 .incksel3 = 0x20, 485 .incksel4 = 0x01, 486 .incksel5 = 0x1a, 487 .incksel6 = 0x1a, 488 }, 489 [IMX290_CLK_74_25] = { 490 /* 74.25MHz clock config */ 491 .incksel1 = 0x10, 492 .incksel2 = 0x00, 493 .incksel3 = 0x10, 494 .incksel4 = 0x01, 495 .incksel5 = 0x1b, 496 .incksel6 = 0x1b, 497 }, 498 }; 499 500 /* Mode configs */ 501 static const struct imx290_mode imx290_modes_2lanes[] = { 502 { 503 .width = 1920, 504 .height = 1080, 505 .hmax_min = 2200, 506 .vmax_min = 1125, 507 .link_freq_index = FREQ_INDEX_1080P, 508 .ctrl_07 = IMX290_WINMODE_1080P, 509 .data = imx290_1080p_settings, 510 .data_size = ARRAY_SIZE(imx290_1080p_settings), 511 .clk_cfg = imx290_1080p_clock_config, 512 }, 513 { 514 .width = 1280, 515 .height = 720, 516 .hmax_min = 3300, 517 .vmax_min = 750, 518 .link_freq_index = FREQ_INDEX_720P, 519 .ctrl_07 = IMX290_WINMODE_720P, 520 .data = imx290_720p_settings, 521 .data_size = ARRAY_SIZE(imx290_720p_settings), 522 .clk_cfg = imx290_720p_clock_config, 523 }, 524 }; 525 526 static const struct imx290_mode imx290_modes_4lanes[] = { 527 { 528 .width = 1920, 529 .height = 1080, 530 .hmax_min = 2200, 531 .vmax_min = 1125, 532 .link_freq_index = FREQ_INDEX_1080P, 533 .ctrl_07 = IMX290_WINMODE_1080P, 534 .data = imx290_1080p_settings, 535 .data_size = ARRAY_SIZE(imx290_1080p_settings), 536 .clk_cfg = imx290_1080p_clock_config, 537 }, 538 { 539 .width = 1280, 540 .height = 720, 541 .hmax_min = 3300, 542 .vmax_min = 750, 543 .link_freq_index = FREQ_INDEX_720P, 544 .ctrl_07 = IMX290_WINMODE_720P, 545 .data = imx290_720p_settings, 546 .data_size = ARRAY_SIZE(imx290_720p_settings), 547 .clk_cfg = imx290_720p_clock_config, 548 }, 549 }; 550 imx290_modes_ptr(const struct imx290 * imx290)551 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290) 552 { 553 if (imx290->nlanes == 2) 554 return imx290_modes_2lanes; 555 else 556 return imx290_modes_4lanes; 557 } 558 imx290_modes_num(const struct imx290 * imx290)559 static inline int imx290_modes_num(const struct imx290 *imx290) 560 { 561 if (imx290->nlanes == 2) 562 return ARRAY_SIZE(imx290_modes_2lanes); 563 else 564 return ARRAY_SIZE(imx290_modes_4lanes); 565 } 566 567 struct imx290_format_info { 568 u32 code[IMX290_VARIANT_MAX]; 569 u8 bpp; 570 const struct cci_reg_sequence *regs; 571 unsigned int num_regs; 572 }; 573 574 static const struct imx290_format_info imx290_formats[] = { 575 { 576 .code = { 577 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB10_1X10, 578 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y10_1X10 579 }, 580 .bpp = 10, 581 .regs = imx290_10bit_settings, 582 .num_regs = ARRAY_SIZE(imx290_10bit_settings), 583 }, { 584 .code = { 585 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB12_1X12, 586 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y12_1X12 587 }, 588 .bpp = 12, 589 .regs = imx290_12bit_settings, 590 .num_regs = ARRAY_SIZE(imx290_12bit_settings), 591 } 592 }; 593 594 static const struct imx290_format_info * imx290_format_info(const struct imx290 * imx290,u32 code)595 imx290_format_info(const struct imx290 *imx290, u32 code) 596 { 597 unsigned int i; 598 599 for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) { 600 const struct imx290_format_info *info = &imx290_formats[i]; 601 602 if (info->code[imx290->model->colour_variant] == code) 603 return info; 604 } 605 606 return NULL; 607 } 608 imx290_set_register_array(struct imx290 * imx290,const struct cci_reg_sequence * settings,unsigned int num_settings)609 static int imx290_set_register_array(struct imx290 *imx290, 610 const struct cci_reg_sequence *settings, 611 unsigned int num_settings) 612 { 613 int ret; 614 615 ret = cci_multi_reg_write(imx290->regmap, settings, num_settings, NULL); 616 if (ret < 0) 617 return ret; 618 619 /* Provide 10ms settle time */ 620 usleep_range(10000, 11000); 621 622 return 0; 623 } 624 imx290_set_clock(struct imx290 * imx290)625 static int imx290_set_clock(struct imx290 *imx290) 626 { 627 const struct imx290_mode *mode = imx290->current_mode; 628 enum imx290_clk_freq clk_idx = imx290->xclk_idx; 629 const struct imx290_clk_cfg *clk_cfg = &mode->clk_cfg[clk_idx]; 630 int ret; 631 632 ret = imx290_set_register_array(imx290, xclk_regs[clk_idx], 633 IMX290_NUM_CLK_REGS); 634 635 cci_write(imx290->regmap, IMX290_INCKSEL1, clk_cfg->incksel1, &ret); 636 cci_write(imx290->regmap, IMX290_INCKSEL2, clk_cfg->incksel2, &ret); 637 cci_write(imx290->regmap, IMX290_INCKSEL3, clk_cfg->incksel3, &ret); 638 cci_write(imx290->regmap, IMX290_INCKSEL4, clk_cfg->incksel4, &ret); 639 cci_write(imx290->regmap, IMX290_INCKSEL5, clk_cfg->incksel5, &ret); 640 cci_write(imx290->regmap, IMX290_INCKSEL6, clk_cfg->incksel6, &ret); 641 642 return ret; 643 } 644 imx290_set_data_lanes(struct imx290 * imx290)645 static int imx290_set_data_lanes(struct imx290 *imx290) 646 { 647 int ret = 0; 648 649 cci_write(imx290->regmap, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, 650 &ret); 651 cci_write(imx290->regmap, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, 652 &ret); 653 cci_write(imx290->regmap, IMX290_FR_FDG_SEL, 0x01, &ret); 654 655 return ret; 656 } 657 imx290_set_black_level(struct imx290 * imx290,const struct v4l2_mbus_framefmt * format,unsigned int black_level,int * err)658 static int imx290_set_black_level(struct imx290 *imx290, 659 const struct v4l2_mbus_framefmt *format, 660 unsigned int black_level, int *err) 661 { 662 unsigned int bpp = imx290_format_info(imx290, format->code)->bpp; 663 664 return cci_write(imx290->regmap, IMX290_BLKLEVEL, 665 black_level >> (16 - bpp), err); 666 } 667 imx290_set_csi_config(struct imx290 * imx290)668 static int imx290_set_csi_config(struct imx290 *imx290) 669 { 670 const s64 *link_freqs = imx290_link_freqs_ptr(imx290); 671 const struct imx290_csi_cfg *csi_cfg; 672 int ret = 0; 673 674 switch (link_freqs[imx290->current_mode->link_freq_index]) { 675 case 445500000: 676 csi_cfg = &imx290_csi_445_5mhz; 677 break; 678 case 297000000: 679 csi_cfg = &imx290_csi_297mhz; 680 break; 681 case 222750000: 682 csi_cfg = &imx290_csi_222_75mhz; 683 break; 684 case 148500000: 685 csi_cfg = &imx290_csi_148_5mhz; 686 break; 687 default: 688 return -EINVAL; 689 } 690 691 cci_write(imx290->regmap, IMX290_REPETITION, csi_cfg->repetition, &ret); 692 cci_write(imx290->regmap, IMX290_TCLKPOST, csi_cfg->tclkpost, &ret); 693 cci_write(imx290->regmap, IMX290_THSZERO, csi_cfg->thszero, &ret); 694 cci_write(imx290->regmap, IMX290_THSPREPARE, csi_cfg->thsprepare, &ret); 695 cci_write(imx290->regmap, IMX290_TCLKTRAIL, csi_cfg->tclktrail, &ret); 696 cci_write(imx290->regmap, IMX290_THSTRAIL, csi_cfg->thstrail, &ret); 697 cci_write(imx290->regmap, IMX290_TCLKZERO, csi_cfg->tclkzero, &ret); 698 cci_write(imx290->regmap, IMX290_TCLKPREPARE, csi_cfg->tclkprepare, 699 &ret); 700 cci_write(imx290->regmap, IMX290_TLPX, csi_cfg->tlpx, &ret); 701 702 return ret; 703 } 704 imx290_setup_format(struct imx290 * imx290,const struct v4l2_mbus_framefmt * format)705 static int imx290_setup_format(struct imx290 *imx290, 706 const struct v4l2_mbus_framefmt *format) 707 { 708 const struct imx290_format_info *info; 709 int ret; 710 711 info = imx290_format_info(imx290, format->code); 712 713 ret = imx290_set_register_array(imx290, info->regs, info->num_regs); 714 if (ret < 0) { 715 dev_err(imx290->dev, "Could not set format registers\n"); 716 return ret; 717 } 718 719 return imx290_set_black_level(imx290, format, 720 IMX290_BLACK_LEVEL_DEFAULT, &ret); 721 } 722 723 /* ---------------------------------------------------------------------------- 724 * Controls 725 */ imx290_exposure_update(struct imx290 * imx290,const struct imx290_mode * mode)726 static void imx290_exposure_update(struct imx290 *imx290, 727 const struct imx290_mode *mode) 728 { 729 unsigned int exposure_max; 730 731 exposure_max = imx290->vblank->val + mode->height - 732 IMX290_EXPOSURE_OFFSET; 733 __v4l2_ctrl_modify_range(imx290->exposure, 1, exposure_max, 1, 734 exposure_max); 735 } 736 imx290_set_ctrl(struct v4l2_ctrl * ctrl)737 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl) 738 { 739 struct imx290 *imx290 = container_of(ctrl->handler, 740 struct imx290, ctrls); 741 const struct v4l2_mbus_framefmt *format; 742 struct v4l2_subdev_state *state; 743 int ret = 0, vmax; 744 745 /* 746 * Return immediately for controls that don't need to be applied to the 747 * device. 748 */ 749 if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY) 750 return 0; 751 752 if (ctrl->id == V4L2_CID_VBLANK) { 753 /* Changing vblank changes the allowed range for exposure. */ 754 imx290_exposure_update(imx290, imx290->current_mode); 755 } 756 757 /* V4L2 controls values will be applied only when power is already up */ 758 if (!pm_runtime_get_if_in_use(imx290->dev)) 759 return 0; 760 761 state = v4l2_subdev_get_locked_active_state(&imx290->sd); 762 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 763 764 switch (ctrl->id) { 765 case V4L2_CID_ANALOGUE_GAIN: 766 ret = cci_write(imx290->regmap, IMX290_GAIN, ctrl->val, NULL); 767 break; 768 769 case V4L2_CID_VBLANK: 770 ret = cci_write(imx290->regmap, IMX290_VMAX, 771 ctrl->val + imx290->current_mode->height, NULL); 772 /* 773 * Due to the way that exposure is programmed in this sensor in 774 * relation to VMAX, we have to reprogramme it whenever VMAX is 775 * changed. 776 * Update ctrl so that the V4L2_CID_EXPOSURE case can refer to 777 * it. 778 */ 779 ctrl = imx290->exposure; 780 fallthrough; 781 case V4L2_CID_EXPOSURE: 782 vmax = imx290->vblank->val + imx290->current_mode->height; 783 ret = cci_write(imx290->regmap, IMX290_SHS1, 784 vmax - ctrl->val - 1, NULL); 785 break; 786 787 case V4L2_CID_TEST_PATTERN: 788 if (ctrl->val) { 789 imx290_set_black_level(imx290, format, 0, &ret); 790 usleep_range(10000, 11000); 791 cci_write(imx290->regmap, IMX290_PGCTRL, 792 (u8)(IMX290_PGCTRL_REGEN | 793 IMX290_PGCTRL_THRU | 794 IMX290_PGCTRL_MODE(ctrl->val)), &ret); 795 } else { 796 cci_write(imx290->regmap, IMX290_PGCTRL, 0x00, &ret); 797 usleep_range(10000, 11000); 798 imx290_set_black_level(imx290, format, 799 IMX290_BLACK_LEVEL_DEFAULT, &ret); 800 } 801 break; 802 803 case V4L2_CID_HBLANK: 804 ret = cci_write(imx290->regmap, IMX290_HMAX, 805 ctrl->val + imx290->current_mode->width, NULL); 806 break; 807 808 case V4L2_CID_HFLIP: 809 case V4L2_CID_VFLIP: 810 { 811 u32 reg; 812 813 reg = imx290->current_mode->ctrl_07; 814 if (imx290->hflip->val) 815 reg |= IMX290_HREVERSE; 816 if (imx290->vflip->val) 817 reg |= IMX290_VREVERSE; 818 ret = cci_write(imx290->regmap, IMX290_CTRL_07, reg, NULL); 819 break; 820 } 821 822 default: 823 ret = -EINVAL; 824 break; 825 } 826 827 pm_runtime_mark_last_busy(imx290->dev); 828 pm_runtime_put_autosuspend(imx290->dev); 829 830 return ret; 831 } 832 833 static const struct v4l2_ctrl_ops imx290_ctrl_ops = { 834 .s_ctrl = imx290_set_ctrl, 835 }; 836 837 static const char * const imx290_test_pattern_menu[] = { 838 "Disabled", 839 "Sequence Pattern 1", 840 "Horizontal Color-bar Chart", 841 "Vertical Color-bar Chart", 842 "Sequence Pattern 2", 843 "Gradation Pattern 1", 844 "Gradation Pattern 2", 845 "000/555h Toggle Pattern", 846 }; 847 imx290_ctrl_update(struct imx290 * imx290,const struct imx290_mode * mode)848 static void imx290_ctrl_update(struct imx290 *imx290, 849 const struct imx290_mode *mode) 850 { 851 unsigned int hblank_min = mode->hmax_min - mode->width; 852 unsigned int hblank_max = IMX290_HMAX_MAX - mode->width; 853 unsigned int vblank_min = mode->vmax_min - mode->height; 854 unsigned int vblank_max = IMX290_VMAX_MAX - mode->height; 855 856 __v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index); 857 858 __v4l2_ctrl_modify_range(imx290->hblank, hblank_min, hblank_max, 1, 859 hblank_min); 860 __v4l2_ctrl_modify_range(imx290->vblank, vblank_min, vblank_max, 1, 861 vblank_min); 862 } 863 imx290_ctrl_init(struct imx290 * imx290)864 static int imx290_ctrl_init(struct imx290 *imx290) 865 { 866 struct v4l2_fwnode_device_properties props; 867 int ret; 868 869 ret = v4l2_fwnode_device_parse(imx290->dev, &props); 870 if (ret < 0) 871 return ret; 872 873 v4l2_ctrl_handler_init(&imx290->ctrls, 11); 874 875 /* 876 * The sensor has an analog gain and a digital gain, both controlled 877 * through a single gain value, expressed in 0.3dB increments. Values 878 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values 879 * up to 72.0dB (240) add further digital gain. Limit the range to 880 * analog gain only, support for digital gain can be added separately 881 * if needed. 882 * 883 * The IMX327 and IMX462 are largely compatible with the IMX290, but 884 * have an analog gain range of 0.0dB to 29.4dB and 42dB of digital 885 * gain. When support for those sensors gets added to the driver, the 886 * gain control should be adjusted accordingly. 887 */ 888 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 889 V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0); 890 891 /* 892 * Correct range will be determined through imx290_ctrl_update setting 893 * V4L2_CID_VBLANK. 894 */ 895 imx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 896 V4L2_CID_EXPOSURE, 1, 65535, 1, 897 65535); 898 899 /* 900 * Set the link frequency, pixel rate, horizontal blanking and vertical 901 * blanking to hardcoded values, they will be updated by 902 * imx290_ctrl_update(). 903 */ 904 imx290->link_freq = 905 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops, 906 V4L2_CID_LINK_FREQ, 907 imx290_link_freqs_num(imx290) - 1, 0, 908 imx290_link_freqs_ptr(imx290)); 909 if (imx290->link_freq) 910 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 911 912 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, V4L2_CID_PIXEL_RATE, 913 IMX290_PIXEL_RATE, IMX290_PIXEL_RATE, 1, 914 IMX290_PIXEL_RATE); 915 916 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops, 917 V4L2_CID_TEST_PATTERN, 918 ARRAY_SIZE(imx290_test_pattern_menu) - 1, 919 0, 0, imx290_test_pattern_menu); 920 921 /* 922 * Actual range will be set from imx290_ctrl_update later in the probe. 923 */ 924 imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 925 V4L2_CID_HBLANK, 1, 1, 1, 1); 926 927 imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 928 V4L2_CID_VBLANK, 1, 1, 1, 1); 929 930 imx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 931 V4L2_CID_HFLIP, 0, 1, 1, 0); 932 imx290->vflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 933 V4L2_CID_VFLIP, 0, 1, 1, 0); 934 v4l2_ctrl_cluster(2, &imx290->hflip); 935 936 v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops, 937 &props); 938 939 imx290->sd.ctrl_handler = &imx290->ctrls; 940 941 if (imx290->ctrls.error) { 942 ret = imx290->ctrls.error; 943 v4l2_ctrl_handler_free(&imx290->ctrls); 944 return ret; 945 } 946 947 return 0; 948 } 949 950 /* ---------------------------------------------------------------------------- 951 * Subdev operations 952 */ 953 954 /* Start streaming */ imx290_start_streaming(struct imx290 * imx290,struct v4l2_subdev_state * state)955 static int imx290_start_streaming(struct imx290 *imx290, 956 struct v4l2_subdev_state *state) 957 { 958 const struct v4l2_mbus_framefmt *format; 959 int ret; 960 961 /* Set init register settings */ 962 ret = imx290_set_register_array(imx290, imx290_global_init_settings, 963 ARRAY_SIZE(imx290_global_init_settings)); 964 if (ret < 0) { 965 dev_err(imx290->dev, "Could not set init registers\n"); 966 return ret; 967 } 968 969 /* Set mdel specific init register settings */ 970 ret = imx290_set_register_array(imx290, imx290->model->init_regs, 971 imx290->model->init_regs_num); 972 if (ret < 0) { 973 dev_err(imx290->dev, "Could not set model specific init registers\n"); 974 return ret; 975 } 976 977 /* Set clock parameters based on mode and xclk */ 978 ret = imx290_set_clock(imx290); 979 if (ret < 0) { 980 dev_err(imx290->dev, "Could not set clocks - %d\n", ret); 981 return ret; 982 } 983 984 /* Set data lane count */ 985 ret = imx290_set_data_lanes(imx290); 986 if (ret < 0) { 987 dev_err(imx290->dev, "Could not set data lanes - %d\n", ret); 988 return ret; 989 } 990 991 ret = imx290_set_csi_config(imx290); 992 if (ret < 0) { 993 dev_err(imx290->dev, "Could not set csi cfg - %d\n", ret); 994 return ret; 995 } 996 997 /* Apply the register values related to current frame format */ 998 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 999 ret = imx290_setup_format(imx290, format); 1000 if (ret < 0) { 1001 dev_err(imx290->dev, "Could not set frame format - %d\n", ret); 1002 return ret; 1003 } 1004 1005 /* Apply default values of current mode */ 1006 ret = imx290_set_register_array(imx290, imx290->current_mode->data, 1007 imx290->current_mode->data_size); 1008 if (ret < 0) { 1009 dev_err(imx290->dev, "Could not set current mode - %d\n", ret); 1010 return ret; 1011 } 1012 1013 /* Apply customized values from user */ 1014 ret = __v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler); 1015 if (ret) { 1016 dev_err(imx290->dev, "Could not sync v4l2 controls - %d\n", ret); 1017 return ret; 1018 } 1019 1020 cci_write(imx290->regmap, IMX290_STANDBY, 0x00, &ret); 1021 1022 msleep(30); 1023 1024 /* Start streaming */ 1025 return cci_write(imx290->regmap, IMX290_XMSTA, 0x00, &ret); 1026 } 1027 1028 /* Stop streaming */ imx290_stop_streaming(struct imx290 * imx290)1029 static int imx290_stop_streaming(struct imx290 *imx290) 1030 { 1031 int ret = 0; 1032 1033 cci_write(imx290->regmap, IMX290_STANDBY, 0x01, &ret); 1034 1035 msleep(30); 1036 1037 return cci_write(imx290->regmap, IMX290_XMSTA, 0x01, &ret); 1038 } 1039 imx290_set_stream(struct v4l2_subdev * sd,int enable)1040 static int imx290_set_stream(struct v4l2_subdev *sd, int enable) 1041 { 1042 struct imx290 *imx290 = to_imx290(sd); 1043 struct v4l2_subdev_state *state; 1044 int ret = 0; 1045 1046 state = v4l2_subdev_lock_and_get_active_state(sd); 1047 1048 if (enable) { 1049 ret = pm_runtime_resume_and_get(imx290->dev); 1050 if (ret < 0) 1051 goto unlock; 1052 1053 ret = imx290_start_streaming(imx290, state); 1054 if (ret) { 1055 dev_err(imx290->dev, "Start stream failed\n"); 1056 pm_runtime_put_sync(imx290->dev); 1057 goto unlock; 1058 } 1059 } else { 1060 imx290_stop_streaming(imx290); 1061 pm_runtime_mark_last_busy(imx290->dev); 1062 pm_runtime_put_autosuspend(imx290->dev); 1063 } 1064 1065 /* 1066 * vflip and hflip should not be changed during streaming as the sensor 1067 * will produce an invalid frame. 1068 */ 1069 __v4l2_ctrl_grab(imx290->vflip, enable); 1070 __v4l2_ctrl_grab(imx290->hflip, enable); 1071 1072 unlock: 1073 v4l2_subdev_unlock_state(state); 1074 return ret; 1075 } 1076 imx290_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1077 static int imx290_enum_mbus_code(struct v4l2_subdev *sd, 1078 struct v4l2_subdev_state *sd_state, 1079 struct v4l2_subdev_mbus_code_enum *code) 1080 { 1081 const struct imx290 *imx290 = to_imx290(sd); 1082 1083 if (code->index >= ARRAY_SIZE(imx290_formats)) 1084 return -EINVAL; 1085 1086 code->code = imx290_formats[code->index].code[imx290->model->colour_variant]; 1087 1088 return 0; 1089 } 1090 imx290_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1091 static int imx290_enum_frame_size(struct v4l2_subdev *sd, 1092 struct v4l2_subdev_state *sd_state, 1093 struct v4l2_subdev_frame_size_enum *fse) 1094 { 1095 const struct imx290 *imx290 = to_imx290(sd); 1096 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290); 1097 1098 if (!imx290_format_info(imx290, fse->code)) 1099 return -EINVAL; 1100 1101 if (fse->index >= imx290_modes_num(imx290)) 1102 return -EINVAL; 1103 1104 fse->min_width = imx290_modes[fse->index].width; 1105 fse->max_width = imx290_modes[fse->index].width; 1106 fse->min_height = imx290_modes[fse->index].height; 1107 fse->max_height = imx290_modes[fse->index].height; 1108 1109 return 0; 1110 } 1111 imx290_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1112 static int imx290_set_fmt(struct v4l2_subdev *sd, 1113 struct v4l2_subdev_state *sd_state, 1114 struct v4l2_subdev_format *fmt) 1115 { 1116 struct imx290 *imx290 = to_imx290(sd); 1117 const struct imx290_mode *mode; 1118 struct v4l2_mbus_framefmt *format; 1119 1120 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290), 1121 imx290_modes_num(imx290), width, height, 1122 fmt->format.width, fmt->format.height); 1123 1124 fmt->format.width = mode->width; 1125 fmt->format.height = mode->height; 1126 1127 if (!imx290_format_info(imx290, fmt->format.code)) 1128 fmt->format.code = imx290_formats[0].code[imx290->model->colour_variant]; 1129 1130 fmt->format.field = V4L2_FIELD_NONE; 1131 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 1132 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 1133 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 1134 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 1135 1136 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 1137 1138 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1139 imx290->current_mode = mode; 1140 1141 imx290_ctrl_update(imx290, mode); 1142 imx290_exposure_update(imx290, mode); 1143 } 1144 1145 *format = fmt->format; 1146 1147 return 0; 1148 } 1149 imx290_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)1150 static int imx290_get_selection(struct v4l2_subdev *sd, 1151 struct v4l2_subdev_state *sd_state, 1152 struct v4l2_subdev_selection *sel) 1153 { 1154 struct imx290 *imx290 = to_imx290(sd); 1155 struct v4l2_mbus_framefmt *format; 1156 1157 switch (sel->target) { 1158 case V4L2_SEL_TGT_CROP: { 1159 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 1160 1161 /* 1162 * The sensor moves the readout by 1 pixel based on flips to 1163 * keep the Bayer order the same. 1164 */ 1165 sel->r.top = IMX290_PIXEL_ARRAY_MARGIN_TOP 1166 + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2 1167 + imx290->vflip->val; 1168 sel->r.left = IMX290_PIXEL_ARRAY_MARGIN_LEFT 1169 + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2 1170 + imx290->hflip->val; 1171 sel->r.width = format->width; 1172 sel->r.height = format->height; 1173 1174 return 0; 1175 } 1176 1177 case V4L2_SEL_TGT_NATIVE_SIZE: 1178 case V4L2_SEL_TGT_CROP_BOUNDS: 1179 sel->r.top = 0; 1180 sel->r.left = 0; 1181 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH; 1182 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT; 1183 1184 return 0; 1185 1186 case V4L2_SEL_TGT_CROP_DEFAULT: 1187 sel->r.top = IMX290_PIXEL_ARRAY_MARGIN_TOP; 1188 sel->r.left = IMX290_PIXEL_ARRAY_MARGIN_LEFT; 1189 sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH; 1190 sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT; 1191 1192 return 0; 1193 1194 default: 1195 return -EINVAL; 1196 } 1197 } 1198 imx290_entity_init_cfg(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state)1199 static int imx290_entity_init_cfg(struct v4l2_subdev *subdev, 1200 struct v4l2_subdev_state *sd_state) 1201 { 1202 struct v4l2_subdev_format fmt = { 1203 .which = V4L2_SUBDEV_FORMAT_TRY, 1204 .format = { 1205 .width = 1920, 1206 .height = 1080, 1207 }, 1208 }; 1209 1210 imx290_set_fmt(subdev, sd_state, &fmt); 1211 1212 return 0; 1213 } 1214 1215 static const struct v4l2_subdev_core_ops imx290_core_ops = { 1216 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1217 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1218 }; 1219 1220 static const struct v4l2_subdev_video_ops imx290_video_ops = { 1221 .s_stream = imx290_set_stream, 1222 }; 1223 1224 static const struct v4l2_subdev_pad_ops imx290_pad_ops = { 1225 .init_cfg = imx290_entity_init_cfg, 1226 .enum_mbus_code = imx290_enum_mbus_code, 1227 .enum_frame_size = imx290_enum_frame_size, 1228 .get_fmt = v4l2_subdev_get_fmt, 1229 .set_fmt = imx290_set_fmt, 1230 .get_selection = imx290_get_selection, 1231 }; 1232 1233 static const struct v4l2_subdev_ops imx290_subdev_ops = { 1234 .core = &imx290_core_ops, 1235 .video = &imx290_video_ops, 1236 .pad = &imx290_pad_ops, 1237 }; 1238 1239 static const struct media_entity_operations imx290_subdev_entity_ops = { 1240 .link_validate = v4l2_subdev_link_validate, 1241 }; 1242 imx290_subdev_init(struct imx290 * imx290)1243 static int imx290_subdev_init(struct imx290 *imx290) 1244 { 1245 struct i2c_client *client = to_i2c_client(imx290->dev); 1246 struct v4l2_subdev_state *state; 1247 int ret; 1248 1249 imx290->current_mode = &imx290_modes_ptr(imx290)[0]; 1250 1251 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops); 1252 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1253 V4L2_SUBDEV_FL_HAS_EVENTS; 1254 imx290->sd.dev = imx290->dev; 1255 imx290->sd.entity.ops = &imx290_subdev_entity_ops; 1256 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1257 1258 imx290->pad.flags = MEDIA_PAD_FL_SOURCE; 1259 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad); 1260 if (ret < 0) { 1261 dev_err(imx290->dev, "Could not register media entity\n"); 1262 return ret; 1263 } 1264 1265 ret = imx290_ctrl_init(imx290); 1266 if (ret < 0) { 1267 dev_err(imx290->dev, "Control initialization error %d\n", ret); 1268 goto err_media; 1269 } 1270 1271 imx290->sd.state_lock = imx290->ctrls.lock; 1272 1273 ret = v4l2_subdev_init_finalize(&imx290->sd); 1274 if (ret < 0) { 1275 dev_err(imx290->dev, "subdev initialization error %d\n", ret); 1276 goto err_ctrls; 1277 } 1278 1279 state = v4l2_subdev_lock_and_get_active_state(&imx290->sd); 1280 imx290_ctrl_update(imx290, imx290->current_mode); 1281 v4l2_subdev_unlock_state(state); 1282 1283 return 0; 1284 1285 err_ctrls: 1286 v4l2_ctrl_handler_free(&imx290->ctrls); 1287 err_media: 1288 media_entity_cleanup(&imx290->sd.entity); 1289 return ret; 1290 } 1291 imx290_subdev_cleanup(struct imx290 * imx290)1292 static void imx290_subdev_cleanup(struct imx290 *imx290) 1293 { 1294 v4l2_subdev_cleanup(&imx290->sd); 1295 media_entity_cleanup(&imx290->sd.entity); 1296 v4l2_ctrl_handler_free(&imx290->ctrls); 1297 } 1298 1299 /* ---------------------------------------------------------------------------- 1300 * Power management 1301 */ 1302 imx290_power_on(struct imx290 * imx290)1303 static int imx290_power_on(struct imx290 *imx290) 1304 { 1305 int ret; 1306 1307 ret = clk_prepare_enable(imx290->xclk); 1308 if (ret) { 1309 dev_err(imx290->dev, "Failed to enable clock\n"); 1310 return ret; 1311 } 1312 1313 ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies), 1314 imx290->supplies); 1315 if (ret) { 1316 dev_err(imx290->dev, "Failed to enable regulators\n"); 1317 clk_disable_unprepare(imx290->xclk); 1318 return ret; 1319 } 1320 1321 usleep_range(1, 2); 1322 gpiod_set_value_cansleep(imx290->rst_gpio, 0); 1323 usleep_range(30000, 31000); 1324 1325 return 0; 1326 } 1327 imx290_power_off(struct imx290 * imx290)1328 static void imx290_power_off(struct imx290 *imx290) 1329 { 1330 clk_disable_unprepare(imx290->xclk); 1331 gpiod_set_value_cansleep(imx290->rst_gpio, 1); 1332 regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies); 1333 } 1334 imx290_runtime_resume(struct device * dev)1335 static int imx290_runtime_resume(struct device *dev) 1336 { 1337 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1338 struct imx290 *imx290 = to_imx290(sd); 1339 1340 return imx290_power_on(imx290); 1341 } 1342 imx290_runtime_suspend(struct device * dev)1343 static int imx290_runtime_suspend(struct device *dev) 1344 { 1345 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1346 struct imx290 *imx290 = to_imx290(sd); 1347 1348 imx290_power_off(imx290); 1349 1350 return 0; 1351 } 1352 1353 static const struct dev_pm_ops imx290_pm_ops = { 1354 RUNTIME_PM_OPS(imx290_runtime_suspend, imx290_runtime_resume, NULL) 1355 }; 1356 1357 /* ---------------------------------------------------------------------------- 1358 * Probe & remove 1359 */ 1360 1361 static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = { 1362 "vdda", 1363 "vddd", 1364 "vdddo", 1365 }; 1366 imx290_get_regulators(struct device * dev,struct imx290 * imx290)1367 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290) 1368 { 1369 unsigned int i; 1370 1371 for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++) 1372 imx290->supplies[i].supply = imx290_supply_name[i]; 1373 1374 return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies), 1375 imx290->supplies); 1376 } 1377 imx290_init_clk(struct imx290 * imx290)1378 static int imx290_init_clk(struct imx290 *imx290) 1379 { 1380 u32 xclk_freq; 1381 int ret; 1382 1383 ret = device_property_read_u32(imx290->dev, "clock-frequency", 1384 &xclk_freq); 1385 if (ret) { 1386 dev_err(imx290->dev, "Could not get xclk frequency\n"); 1387 return ret; 1388 } 1389 1390 /* external clock must be 37.125 MHz or 74.25MHz */ 1391 switch (xclk_freq) { 1392 case 37125000: 1393 imx290->xclk_idx = IMX290_CLK_37_125; 1394 break; 1395 case 74250000: 1396 imx290->xclk_idx = IMX290_CLK_74_25; 1397 break; 1398 default: 1399 dev_err(imx290->dev, "External clock frequency %u is not supported\n", 1400 xclk_freq); 1401 return -EINVAL; 1402 } 1403 1404 ret = clk_set_rate(imx290->xclk, xclk_freq); 1405 if (ret) { 1406 dev_err(imx290->dev, "Could not set xclk frequency\n"); 1407 return ret; 1408 } 1409 1410 return 0; 1411 } 1412 1413 /* 1414 * Returns 0 if all link frequencies used by the driver for the given number 1415 * of MIPI data lanes are mentioned in the device tree, or the value of the 1416 * first missing frequency otherwise. 1417 */ imx290_check_link_freqs(const struct imx290 * imx290,const struct v4l2_fwnode_endpoint * ep)1418 static s64 imx290_check_link_freqs(const struct imx290 *imx290, 1419 const struct v4l2_fwnode_endpoint *ep) 1420 { 1421 int i, j; 1422 const s64 *freqs = imx290_link_freqs_ptr(imx290); 1423 int freqs_count = imx290_link_freqs_num(imx290); 1424 1425 for (i = 0; i < freqs_count; i++) { 1426 for (j = 0; j < ep->nr_of_link_frequencies; j++) 1427 if (freqs[i] == ep->link_frequencies[j]) 1428 break; 1429 if (j == ep->nr_of_link_frequencies) 1430 return freqs[i]; 1431 } 1432 return 0; 1433 } 1434 1435 static const struct imx290_model_info imx290_models[] = { 1436 [IMX290_MODEL_IMX290LQR] = { 1437 .colour_variant = IMX290_VARIANT_COLOUR, 1438 .init_regs = imx290_global_init_settings_290, 1439 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1440 .name = "imx290", 1441 }, 1442 [IMX290_MODEL_IMX290LLR] = { 1443 .colour_variant = IMX290_VARIANT_MONO, 1444 .init_regs = imx290_global_init_settings_290, 1445 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1446 .name = "imx290", 1447 }, 1448 [IMX290_MODEL_IMX327LQR] = { 1449 .colour_variant = IMX290_VARIANT_COLOUR, 1450 .init_regs = imx290_global_init_settings_327, 1451 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_327), 1452 .name = "imx327", 1453 }, 1454 }; 1455 imx290_parse_dt(struct imx290 * imx290)1456 static int imx290_parse_dt(struct imx290 *imx290) 1457 { 1458 /* Only CSI2 is supported for now: */ 1459 struct v4l2_fwnode_endpoint ep = { 1460 .bus_type = V4L2_MBUS_CSI2_DPHY 1461 }; 1462 struct fwnode_handle *endpoint; 1463 int ret; 1464 s64 fq; 1465 1466 imx290->model = of_device_get_match_data(imx290->dev); 1467 1468 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx290->dev), NULL); 1469 if (!endpoint) { 1470 dev_err(imx290->dev, "Endpoint node not found\n"); 1471 return -EINVAL; 1472 } 1473 1474 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep); 1475 fwnode_handle_put(endpoint); 1476 if (ret == -ENXIO) { 1477 dev_err(imx290->dev, "Unsupported bus type, should be CSI2\n"); 1478 goto done; 1479 } else if (ret) { 1480 dev_err(imx290->dev, "Parsing endpoint node failed\n"); 1481 goto done; 1482 } 1483 1484 /* Get number of data lanes */ 1485 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes; 1486 if (imx290->nlanes != 2 && imx290->nlanes != 4) { 1487 dev_err(imx290->dev, "Invalid data lanes: %d\n", imx290->nlanes); 1488 ret = -EINVAL; 1489 goto done; 1490 } 1491 1492 dev_dbg(imx290->dev, "Using %u data lanes\n", imx290->nlanes); 1493 1494 if (!ep.nr_of_link_frequencies) { 1495 dev_err(imx290->dev, "link-frequency property not found in DT\n"); 1496 ret = -EINVAL; 1497 goto done; 1498 } 1499 1500 /* Check that link frequences for all the modes are in device tree */ 1501 fq = imx290_check_link_freqs(imx290, &ep); 1502 if (fq) { 1503 dev_err(imx290->dev, "Link frequency of %lld is not supported\n", 1504 fq); 1505 ret = -EINVAL; 1506 goto done; 1507 } 1508 1509 ret = 0; 1510 1511 done: 1512 v4l2_fwnode_endpoint_free(&ep); 1513 return ret; 1514 } 1515 imx290_probe(struct i2c_client * client)1516 static int imx290_probe(struct i2c_client *client) 1517 { 1518 struct device *dev = &client->dev; 1519 struct imx290 *imx290; 1520 int ret; 1521 1522 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL); 1523 if (!imx290) 1524 return -ENOMEM; 1525 1526 imx290->dev = dev; 1527 imx290->regmap = devm_cci_regmap_init_i2c(client, 16); 1528 if (IS_ERR(imx290->regmap)) { 1529 dev_err(dev, "Unable to initialize I2C\n"); 1530 return -ENODEV; 1531 } 1532 1533 ret = imx290_parse_dt(imx290); 1534 if (ret) 1535 return ret; 1536 1537 /* Acquire resources. */ 1538 imx290->xclk = devm_clk_get(dev, "xclk"); 1539 if (IS_ERR(imx290->xclk)) 1540 return dev_err_probe(dev, PTR_ERR(imx290->xclk), 1541 "Could not get xclk\n"); 1542 1543 ret = imx290_get_regulators(dev, imx290); 1544 if (ret < 0) 1545 return dev_err_probe(dev, ret, "Cannot get regulators\n"); 1546 1547 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset", 1548 GPIOD_OUT_HIGH); 1549 if (IS_ERR(imx290->rst_gpio)) 1550 return dev_err_probe(dev, PTR_ERR(imx290->rst_gpio), 1551 "Cannot get reset gpio\n"); 1552 1553 /* Initialize external clock frequency. */ 1554 ret = imx290_init_clk(imx290); 1555 if (ret) 1556 return ret; 1557 1558 /* 1559 * Enable power management. The driver supports runtime PM, but needs to 1560 * work when runtime PM is disabled in the kernel. To that end, power 1561 * the sensor on manually here. 1562 */ 1563 ret = imx290_power_on(imx290); 1564 if (ret < 0) { 1565 dev_err(dev, "Could not power on the device\n"); 1566 return ret; 1567 } 1568 1569 /* 1570 * Enable runtime PM with autosuspend. As the device has been powered 1571 * manually, mark it as active, and increase the usage count without 1572 * resuming the device. 1573 */ 1574 pm_runtime_set_active(dev); 1575 pm_runtime_get_noresume(dev); 1576 pm_runtime_enable(dev); 1577 pm_runtime_set_autosuspend_delay(dev, 1000); 1578 pm_runtime_use_autosuspend(dev); 1579 1580 /* Initialize the V4L2 subdev. */ 1581 ret = imx290_subdev_init(imx290); 1582 if (ret) 1583 goto err_pm; 1584 1585 v4l2_i2c_subdev_set_name(&imx290->sd, client, 1586 imx290->model->name, NULL); 1587 1588 /* 1589 * Finally, register the V4L2 subdev. This must be done after 1590 * initializing everything as the subdev can be used immediately after 1591 * being registered. 1592 */ 1593 ret = v4l2_async_register_subdev(&imx290->sd); 1594 if (ret < 0) { 1595 dev_err(dev, "Could not register v4l2 device\n"); 1596 goto err_subdev; 1597 } 1598 1599 /* 1600 * Decrease the PM usage count. The device will get suspended after the 1601 * autosuspend delay, turning the power off. 1602 */ 1603 pm_runtime_mark_last_busy(dev); 1604 pm_runtime_put_autosuspend(dev); 1605 1606 return 0; 1607 1608 err_subdev: 1609 imx290_subdev_cleanup(imx290); 1610 err_pm: 1611 pm_runtime_disable(dev); 1612 pm_runtime_put_noidle(dev); 1613 imx290_power_off(imx290); 1614 return ret; 1615 } 1616 imx290_remove(struct i2c_client * client)1617 static void imx290_remove(struct i2c_client *client) 1618 { 1619 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1620 struct imx290 *imx290 = to_imx290(sd); 1621 1622 v4l2_async_unregister_subdev(sd); 1623 imx290_subdev_cleanup(imx290); 1624 1625 /* 1626 * Disable runtime PM. In case runtime PM is disabled in the kernel, 1627 * make sure to turn power off manually. 1628 */ 1629 pm_runtime_disable(imx290->dev); 1630 if (!pm_runtime_status_suspended(imx290->dev)) 1631 imx290_power_off(imx290); 1632 pm_runtime_set_suspended(imx290->dev); 1633 } 1634 1635 static const struct of_device_id imx290_of_match[] = { 1636 { 1637 /* Deprecated - synonym for "sony,imx290lqr" */ 1638 .compatible = "sony,imx290", 1639 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1640 }, { 1641 .compatible = "sony,imx290lqr", 1642 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1643 }, { 1644 .compatible = "sony,imx290llr", 1645 .data = &imx290_models[IMX290_MODEL_IMX290LLR], 1646 }, { 1647 .compatible = "sony,imx327lqr", 1648 .data = &imx290_models[IMX290_MODEL_IMX327LQR], 1649 }, 1650 { /* sentinel */ }, 1651 }; 1652 MODULE_DEVICE_TABLE(of, imx290_of_match); 1653 1654 static struct i2c_driver imx290_i2c_driver = { 1655 .probe = imx290_probe, 1656 .remove = imx290_remove, 1657 .driver = { 1658 .name = "imx290", 1659 .pm = pm_ptr(&imx290_pm_ops), 1660 .of_match_table = imx290_of_match, 1661 }, 1662 }; 1663 1664 module_i2c_driver(imx290_i2c_driver); 1665 1666 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver"); 1667 MODULE_AUTHOR("FRAMOS GmbH"); 1668 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1669 MODULE_LICENSE("GPL v2"); 1670